TimeQuest Timing Analyzer report for atari800core
Sat Jul 13 22:15:51 2019
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. Parallel Compilation
  4. SDC File List
  5. Clocks
  6. Slow 1200mV 85C Model Fmax Summary
  7. Timing Closure Recommendations
  8. Slow 1200mV 85C Model Setup Summary
  9. Slow 1200mV 85C Model Hold Summary
 10. Slow 1200mV 85C Model Recovery Summary
 11. Slow 1200mV 85C Model Removal Summary
 12. Slow 1200mV 85C Model Minimum Pulse Width Summary
 13. Slow 1200mV 85C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 14. Slow 1200mV 85C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 15. Slow 1200mV 85C Model Setup: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 16. Slow 1200mV 85C Model Setup: 'FPGA_CLK'
 17. Slow 1200mV 85C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 18. Slow 1200mV 85C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
 19. Slow 1200mV 85C Model Hold: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 20. Slow 1200mV 85C Model Hold: 'FPGA_CLK'
 21. Slow 1200mV 85C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 22. Slow 1200mV 85C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 23. Slow 1200mV 85C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
 24. Slow 1200mV 85C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 25. Slow 1200mV 85C Model Recovery: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 26. Slow 1200mV 85C Model Recovery: 'FPGA_CLK'
 27. Slow 1200mV 85C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 28. Slow 1200mV 85C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 29. Slow 1200mV 85C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
 30. Slow 1200mV 85C Model Removal: 'FPGA_CLK'
 31. Slow 1200mV 85C Model Removal: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 32. Slow 1200mV 85C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 33. Slow 1200mV 85C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 34. Slow 1200mV 85C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
 35. Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 36. Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 37. Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
 38. Slow 1200mV 85C Model Minimum Pulse Width: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 39. Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 40. Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'
 41. Slow 1200mV 85C Model Minimum Pulse Width: 'FPGA_CLK'
 42. Setup Times
 43. Hold Times
 44. Clock to Output Times
 45. Minimum Clock to Output Times
 46. Output Enable Times
 47. Minimum Output Enable Times
 48. Output Disable Times
 49. Minimum Output Disable Times
 50. Slow 1200mV 85C Model Metastability Report
 51. Slow 1200mV 0C Model Fmax Summary
 52. Slow 1200mV 0C Model Setup Summary
 53. Slow 1200mV 0C Model Hold Summary
 54. Slow 1200mV 0C Model Recovery Summary
 55. Slow 1200mV 0C Model Removal Summary
 56. Slow 1200mV 0C Model Minimum Pulse Width Summary
 57. Slow 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 58. Slow 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 59. Slow 1200mV 0C Model Setup: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 60. Slow 1200mV 0C Model Setup: 'FPGA_CLK'
 61. Slow 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 62. Slow 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
 63. Slow 1200mV 0C Model Hold: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 64. Slow 1200mV 0C Model Hold: 'FPGA_CLK'
 65. Slow 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 66. Slow 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 67. Slow 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
 68. Slow 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 69. Slow 1200mV 0C Model Recovery: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 70. Slow 1200mV 0C Model Recovery: 'FPGA_CLK'
 71. Slow 1200mV 0C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 72. Slow 1200mV 0C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 73. Slow 1200mV 0C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
 74. Slow 1200mV 0C Model Removal: 'FPGA_CLK'
 75. Slow 1200mV 0C Model Removal: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 76. Slow 1200mV 0C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 77. Slow 1200mV 0C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 78. Slow 1200mV 0C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
 79. Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 80. Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 81. Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
 82. Slow 1200mV 0C Model Minimum Pulse Width: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 83. Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 84. Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'
 85. Slow 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'
 86. Setup Times
 87. Hold Times
 88. Clock to Output Times
 89. Minimum Clock to Output Times
 90. Output Enable Times
 91. Minimum Output Enable Times
 92. Output Disable Times
 93. Minimum Output Disable Times
 94. Slow 1200mV 0C Model Metastability Report
 95. Fast 1200mV 0C Model Setup Summary
 96. Fast 1200mV 0C Model Hold Summary
 97. Fast 1200mV 0C Model Recovery Summary
 98. Fast 1200mV 0C Model Removal Summary
 99. Fast 1200mV 0C Model Minimum Pulse Width Summary
100. Fast 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
101. Fast 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
102. Fast 1200mV 0C Model Setup: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
103. Fast 1200mV 0C Model Setup: 'FPGA_CLK'
104. Fast 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
105. Fast 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
106. Fast 1200mV 0C Model Hold: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
107. Fast 1200mV 0C Model Hold: 'FPGA_CLK'
108. Fast 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
109. Fast 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
110. Fast 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
111. Fast 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
112. Fast 1200mV 0C Model Recovery: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
113. Fast 1200mV 0C Model Recovery: 'FPGA_CLK'
114. Fast 1200mV 0C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
115. Fast 1200mV 0C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
116. Fast 1200mV 0C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
117. Fast 1200mV 0C Model Removal: 'FPGA_CLK'
118. Fast 1200mV 0C Model Removal: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
119. Fast 1200mV 0C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
120. Fast 1200mV 0C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
121. Fast 1200mV 0C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
122. Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
123. Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
124. Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
125. Fast 1200mV 0C Model Minimum Pulse Width: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
126. Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
127. Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'
128. Fast 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'
129. Setup Times
130. Hold Times
131. Clock to Output Times
132. Minimum Clock to Output Times
133. Output Enable Times
134. Minimum Output Enable Times
135. Output Disable Times
136. Minimum Output Disable Times
137. Fast 1200mV 0C Model Metastability Report
138. Multicorner Timing Analysis Summary
139. Setup Times
140. Hold Times
141. Clock to Output Times
142. Minimum Clock to Output Times
143. Board Trace Model Assignments
144. Input Transition Times
145. Signal Integrity Metrics (Slow 1200mv 0c Model)
146. Signal Integrity Metrics (Slow 1200mv 85c Model)
147. Signal Integrity Metrics (Fast 1200mv 0c Model)
148. Setup Transfers
149. Hold Transfers
150. Recovery Transfers
151. Removal Transfers
152. Report TCCS
153. Report RSKM
154. Unconstrained Paths
155. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                                      ;
+--------------------+-------------------------------------------------------------------+
; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition ;
; Revision Name      ; atari800core                                                      ;
; Device Family      ; Cyclone IV E                                                      ;
; Device Name        ; EP4CE15E22C7                                                      ;
; Timing Models      ; Final                                                             ;
; Delay Model        ; Combined                                                          ;
; Rise/Fall Delays   ; Enabled                                                           ;
+--------------------+-------------------------------------------------------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 12          ;
; Maximum allowed            ; 6           ;
;                            ;             ;
; Average used               ; 1.11        ;
; Maximum used               ; 6           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processor 2            ;  11.1%      ;
;     Processors 3-6         ; < 0.1%      ;
;     Processors 7-12        ;   0.0%      ;
+----------------------------+-------------+


+------------------------------------------------------+
; SDC File List                                        ;
+------------------+--------+--------------------------+
; SDC File Path    ; Status ; Read at                  ;
+------------------+--------+--------------------------+
; atari800core.sdc ; OK     ; Sat Jul 13 22:15:43 2019 ;
+------------------+--------+--------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
+-------------------------------------------------------------------------------------+-----------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------+
; Clock Name                                                                          ; Type      ; Period  ; Frequency ; Rise  ; Fall    ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master                                                                             ; Source                                                                                ; Targets                                                                                 ;
+-------------------------------------------------------------------------------------+-----------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------+
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Generated ; 11.747  ; 85.13 MHz ; 0.000 ; 5.873   ; 50.00      ; 1         ; 3           ;       ;        ;           ;            ; false    ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] } ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Generated ; 35.242  ; 28.38 MHz ; 0.000 ; 17.621  ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] } ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Generated ; 11.747  ; 85.13 MHz ; 7.341 ; 13.214  ; 50.00      ; 1         ; 3           ; 225.0 ;        ;           ;            ; false    ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] } ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Generated ; 17.621  ; 56.75 MHz ; 0.000 ; 8.810   ; 50.00      ; 1         ; 2           ;       ;        ;           ;            ; false    ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] } ;
; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; Generated ; 35.242  ; 28.38 MHz ; 0.000 ; 17.621  ; 50.00      ; 40        ; 227         ;       ;        ;           ;            ; false    ; FPGA_CLK                                                                           ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]  ; { \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] }  ;
; FPGA_CLK                                                                            ; Base      ; 200.000 ; 5.0 MHz   ; 0.000 ; 100.000 ;            ;           ;             ;       ;        ;           ;            ;          ;                                                                                    ;                                                                                       ; { FPGA_CLK }                                                                            ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; Generated ; 20.833  ; 48.0 MHz  ; 0.000 ; 10.416  ; 50.00      ; 5         ; 48          ;       ;        ;           ;            ; false    ; FPGA_CLK                                                                           ; usb_pll|altpll_component|auto_generated|pll1|inclk[0]                                 ; { usb_pll|altpll_component|auto_generated|pll1|clk[0] }                                 ;
+-------------------------------------------------------------------------------------+-----------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Fmax Summary                                                                                                                                  ;
+------------+-----------------+-------------------------------------------------------------------------------------+------------------------------------------------+
; Fmax       ; Restricted Fmax ; Clock Name                                                                          ; Note                                           ;
+------------+-----------------+-------------------------------------------------------------------------------------+------------------------------------------------+
; 33.92 MHz  ; 33.92 MHz       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;                                                ;
; 84.31 MHz  ; 84.31 MHz       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;                                                ;
; 97.36 MHz  ; 97.36 MHz       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;                                                ;
; 122.8 MHz  ; 122.8 MHz       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;                                                ;
; 208.38 MHz ; 40.0 MHz        ; FPGA_CLK                                                                            ; limit due to minimum period restriction (tmin) ;
+------------+-----------------+-------------------------------------------------------------------------------------+------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


----------------------------------
; Timing Closure Recommendations ;
----------------------------------
HTML report is unavailable in plain text report export.


+--------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup Summary                                                                          ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; -3.665 ; -275.360      ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -1.765 ; -1.765        ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; -0.274 ; -11.588       ;
; FPGA_CLK                                                                            ; 0.140  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.949  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 2.079  ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold Summary                                                                           ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; -1.833 ; -130.585      ;
; FPGA_CLK                                                                            ; -0.735 ; -0.735        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.343  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.413  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.414  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 12.748 ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery Summary                                                                       ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; -2.348 ; -21.132       ;
; FPGA_CLK                                                                            ; -0.299 ; -7.592        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 7.512  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 7.659  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 12.988 ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal Summary                                                                        ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; FPGA_CLK                                                                            ; -0.360 ; -9.143        ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 0.482  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 1.744  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 2.565  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 3.656  ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width Summary                                                            ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.595  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 5.720  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 8.534  ; 0.000         ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 9.381  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.258 ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; 17.595 ; 0.000         ;
; FPGA_CLK                                                                            ; 89.530 ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                          ; To Node                                                                                                                                                                                            ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; -3.665 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[4]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[4]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.415     ; 1.219      ;
; -3.636 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[8]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[8]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.415     ; 1.190      ;
; -3.621 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[2]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[2]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.417     ; 1.173      ;
; -3.499 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[7]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[7]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.415     ; 1.053      ;
; -3.296 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[15]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[15]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.036     ; 1.229      ;
; -3.261 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CRCError                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[0]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.417     ; 0.813      ;
; -3.260 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|bitStuffError                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[1]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.417     ; 0.812      ;
; -3.260 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[1]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[1]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.417     ; 0.812      ;
; -3.259 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reset_n_reg                                                                                                                                             ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[2]                                                                                                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.439     ; 0.789      ;
; -3.248 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.427     ; 0.790      ;
; -3.248 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.427     ; 0.790      ;
; -3.248 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInExtend[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInSTB[2]           ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.426     ; 0.791      ;
; -3.247 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.426     ; 0.790      ;
; -3.246 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.427     ; 0.788      ;
; -3.236 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|ACKRxed                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[6]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.417     ; 0.788      ;
; -3.183 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[1]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[1]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.023     ; 1.129      ;
; -3.171 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[13]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.982     ; 1.158      ;
; -3.126 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[9]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.036     ; 1.059      ;
; -3.120 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[13]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.067     ; 1.022      ;
; -3.100 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[11]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[11]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.067     ; 1.002      ;
; -3.095 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[14]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[14]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.036     ; 1.028      ;
; -3.093 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[8]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[8]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.036     ; 1.026      ;
; -3.089 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.061     ; 0.997      ;
; -3.083 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.053     ; 0.999      ;
; -3.079 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[8]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[8]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.067     ; 0.981      ;
; -3.068 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.061     ; 0.976      ;
; -3.062 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[12]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[12]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.038     ; 0.993      ;
; -3.061 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.053     ; 0.977      ;
; -3.059 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[3]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[3]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.053     ; 0.975      ;
; -3.055 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[2]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[2]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.053     ; 0.971      ;
; -3.053 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[0]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[0]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.053     ; 0.969      ;
; -3.052 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[5]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[5]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.023     ; 0.998      ;
; -3.046 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[5]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[5]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.017     ; 0.998      ;
; -3.040 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[8]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[8]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.018     ; 0.991      ;
; -3.037 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[3]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[3]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.023     ; 0.983      ;
; -3.035 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[1]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[1]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.053     ; 0.951      ;
; -3.031 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[3]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[3]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.018     ; 0.982      ;
; -3.028 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[9]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[9]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.023     ; 0.974      ;
; -3.027 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[0]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[0]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.023     ; 0.973      ;
; -3.027 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[0]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[0]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.017     ; 0.979      ;
; -3.020 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[2]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[2]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.023     ; 0.966      ;
; -3.020 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXTimeOut                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[3]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.026     ; 0.963      ;
; -3.013 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[7]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[7]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.018     ; 0.964      ;
; -3.013 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.013     ; 0.969      ;
; -3.012 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.013     ; 0.968      ;
; -3.009 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[12]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[12]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.982     ; 0.996      ;
; -3.008 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[10]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[10]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.982     ; 0.995      ;
; -3.007 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[9]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[9]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.018     ; 0.958      ;
; -2.981 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[11]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[11]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.982     ; 0.968      ;
; -2.928 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.061     ; 0.836      ;
; -2.927 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.061     ; 0.835      ;
; -2.926 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.061     ; 0.834      ;
; -2.920 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.053     ; 0.836      ;
; -2.919 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.053     ; 0.835      ;
; -2.915 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[0] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.049     ; 0.835      ;
; -2.911 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[0] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.067     ; 0.813      ;
; -2.911 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[1] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.067     ; 0.813      ;
; -2.909 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.053     ; 0.825      ;
; -2.906 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.061     ; 0.814      ;
; -2.905 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.061     ; 0.813      ;
; -2.904 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[9]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.038     ; 0.835      ;
; -2.903 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXOverflow                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[2]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.055     ; 0.817      ;
; -2.902 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXOverflow                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[2]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.055     ; 0.816      ;
; -2.901 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|ACKRxed                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[6]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.055     ; 0.815      ;
; -2.899 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|NAKRxed                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[4]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.055     ; 0.813      ;
; -2.899 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|stallRxed                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[5]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.055     ; 0.813      ;
; -2.898 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.053     ; 0.814      ;
; -2.898 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|NAKRxed                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[4]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.055     ; 0.812      ;
; -2.898 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|stallRxed                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[5]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.055     ; 0.812      ;
; -2.897 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.053     ; 0.813      ;
; -2.896 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_enable_reg                                                                                                                                          ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[2]                                                                                                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.074     ; 0.791      ;
; -2.894 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CRCError                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[0]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.050     ; 0.813      ;
; -2.893 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|bitStuffError                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[1]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.050     ; 0.812      ;
; -2.892 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[1] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.049     ; 0.812      ;
; -2.892 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXTimeOut                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[3]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.050     ; 0.811      ;
; -2.883 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[6]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[6]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.017     ; 0.835      ;
; -2.882 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[14]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[14]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.038     ; 0.813      ;
; -2.882 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[10]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[10]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.038     ; 0.813      ;
; -2.881 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[15]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[15]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.038     ; 0.812      ;
; -2.881 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[10]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[10]    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.023     ; 0.827      ;
; -2.876 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInExtend[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInSTB[2]           ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.054     ; 0.791      ;
; -2.875 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|dataSequence                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[7]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.052     ; 0.792      ;
; -2.873 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[10]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[10]    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.017     ; 0.825      ;
; -2.870 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|dataSequence                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[7]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.050     ; 0.789      ;
; -2.867 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[6]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[6]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.023     ; 0.813      ;
; -2.860 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[4]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[4]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.017     ; 0.812      ;
; -2.843 ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                                                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|synchronizer:tick_toggle_synchronizer|ff_reg[2]                                                                                                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.023     ; 0.789      ;
; -2.804 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[1]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[1]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.983     ; 0.790      ;
; -2.803 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[3]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[3]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.983     ; 0.789      ;
; -2.802 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[2]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[2]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.983     ; 0.788      ;
; -2.802 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[0]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[0]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.983     ; 0.788      ;
; 1.873  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|pmg_dma_state_reg[2]                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 9.623      ;
; 2.017  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Dreg                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 9.464      ;
; 2.128  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Vreg                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.170     ; 9.358      ;
; 2.184  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[6]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 9.315      ;
; 2.184  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[0]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 9.315      ;
; 2.235  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Ireg                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 9.245      ;
; 2.307  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[0]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 9.191      ;
; 2.308  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[7]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 9.190      ;
; 2.313  ; ram_do_reg[6]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.173     ; 9.170      ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                                                            ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                 ; To Node                                                                                                                                             ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; -1.765 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 1.467        ; -1.756     ; 1.256      ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                                                                           ; To Node                                                                                                                                                                                           ; Launch Clock                                                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -0.274 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.228      ; 1.399      ;
; -0.242 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]                                                                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.231      ; 1.370      ;
; -0.231 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.228      ; 1.356      ;
; -0.228 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.228      ; 1.353      ;
; -0.226 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.228      ; 1.351      ;
; -0.223 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.231      ; 1.351      ;
; -0.210 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.219      ; 1.326      ;
; -0.199 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.241      ; 1.337      ;
; -0.198 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.232      ; 1.327      ;
; -0.196 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.231      ; 1.324      ;
; -0.194 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1]                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.231      ; 1.322      ;
; -0.191 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.219      ; 1.307      ;
; -0.189 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.231      ; 1.317      ;
; -0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.314      ;
; -0.184 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.219      ; 1.300      ;
; -0.183 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB                                                                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.310      ;
; -0.183 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.231      ; 1.311      ;
; -0.183 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.231      ; 1.311      ;
; -0.181 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.231      ; 1.309      ;
; -0.180 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB                                                                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.231      ; 1.308      ;
; -0.180 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.232      ; 1.309      ;
; -0.180 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.232      ; 1.309      ;
; -0.178 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.231      ; 1.306      ;
; -0.178 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.219      ; 1.294      ;
; -0.178 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB                                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg_reg1      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.231      ; 1.306      ;
; -0.178 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.231      ; 1.306      ;
; -0.177 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.241      ; 1.315      ;
; -0.177 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.231      ; 1.305      ;
; -0.177 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.231      ; 1.305      ;
; -0.175 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.219      ; 1.291      ;
; -0.175 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.231      ; 1.303      ;
; -0.175 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.231      ; 1.303      ;
; -0.175 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.241      ; 1.313      ;
; -0.175 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.231      ; 1.303      ;
; -0.174 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.301      ;
; -0.174 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]                                                                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.231      ; 1.302      ;
; -0.174 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.231      ; 1.302      ;
; -0.171 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.231      ; 1.299      ;
; -0.170 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.231      ; 1.298      ;
; -0.169 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.241      ; 1.307      ;
; -0.168 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn_reg1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.295      ;
; -0.168 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.231      ; 1.296      ;
; -0.168 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB                                                                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.231      ; 1.296      ;
; -0.167 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.231      ; 1.295      ;
; -0.166 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.293      ;
; -0.165 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate_reg1       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.292      ;
; -0.164 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate_reg1       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.231      ; 1.292      ;
; -0.164 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.231      ; 1.292      ;
; -0.163 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.231      ; 1.291      ;
; -0.160 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol_reg1        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.287      ;
; -0.160 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.231      ; 1.288      ;
; -0.160 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.231      ; 1.288      ;
; -0.160 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.231      ; 1.288      ;
; -0.159 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.231      ; 1.287      ;
; -0.159 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1]                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.231      ; 1.287      ;
; -0.159 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.231      ; 1.287      ;
; -0.158 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB                                                                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.231      ; 1.286      ;
; -0.157 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.241      ; 1.295      ;
; -0.147 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.231      ; 1.275      ;
; -0.144 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.231      ; 1.272      ;
; -0.136 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.231      ; 1.264      ;
; -0.132 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[0]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.231      ; 1.260      ;
; -0.101 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.231      ; 1.229      ;
; -0.093 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.241      ; 1.231      ;
; -0.066 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.241      ; 1.204      ;
; -0.047 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.228      ; 1.172      ;
; -0.043 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.228      ; 1.168      ;
; -0.039 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.166      ;
; -0.036 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol_reg1        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.231      ; 1.164      ;
; -0.022 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn_reg1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.231      ; 1.150      ;
; -0.022 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.149      ;
; -0.012 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB                                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg_reg1      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.139      ;
; -0.011 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.138      ;
; -0.008 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.135      ;
; -0.006 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.133      ;
; -0.006 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.133      ;
; 0.021  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.231      ; 1.107      ;
; 0.027  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.100      ;
; 0.029  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.231      ; 1.099      ;
; 0.034  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[0]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.093      ;
; 0.135  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.228      ; 0.990      ;
; 4.486  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|altsyncram:altsyncram4|altsyncram_i0m3:auto_generated|ram_block1a0~porta_address_reg0                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.686     ; 7.436      ;
; 4.962  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|altsyncram:altsyncram4|altsyncram_nsl3:auto_generated|ram_block1a0~porta_address_reg0 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.689     ; 6.957      ;
; 6.415  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C1_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.332     ; 5.861      ;
; 6.491  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C0_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.336     ; 5.781      ;
; 6.571  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C1_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.336     ; 5.701      ;
; 6.591  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C0_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.332     ; 5.685      ;
; 6.955  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_post_state                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 3.635      ; 7.095      ;
; 6.990  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_post_state ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 3.635      ; 7.060      ;
; 7.033  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C4_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.336     ; 5.239      ;
; 7.037  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C2_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.336     ; 5.235      ;
; 7.065  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C3_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.332     ; 5.211      ;
; 7.205  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr14|cntr_qfo:auto_generated|counter_reg_bit[3]                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.336     ; 5.067      ;
; 7.211  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|idle_state                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 3.635      ; 6.839      ;
; 7.253  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr14|cntr_qfo:auto_generated|counter_reg_bit[4]                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.335     ; 5.020      ;
; 7.279  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C4_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.332     ; 4.997      ;
; 7.281  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_wait_state                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 3.635      ; 6.769      ;
; 7.321  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C3_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.336     ; 4.951      ;
; 7.326  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_wait_state ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 3.636      ; 6.725      ;
; 7.331  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|idle_state          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 3.636      ; 6.720      ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'FPGA_CLK'                                                                                                                                                                                                                                                                                              ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack   ; From Node                                                                             ; To Node                                                                               ; Launch Clock                                                                        ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; 0.140   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[131]                                       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.292      ; 3.916      ;
; 195.201 ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; 0.197      ; 4.994      ;
; 195.420 ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8           ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.307     ; 1.472      ;
; 196.731 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 3.195      ;
; 196.750 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 3.176      ;
; 196.858 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 3.068      ;
; 196.863 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 3.063      ;
; 196.864 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 3.062      ;
; 196.882 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 3.044      ;
; 196.883 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 3.043      ;
; 196.949 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.977      ;
; 196.986 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.940      ;
; 196.990 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.936      ;
; 196.995 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.931      ;
; 196.995 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.931      ;
; 196.996 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.930      ;
; 197.014 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.912      ;
; 197.014 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.912      ;
; 197.015 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.911      ;
; 197.081 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.845      ;
; 197.083 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.843      ;
; 197.103 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.823      ;
; 197.118 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.808      ;
; 197.122 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.804      ;
; 197.126 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.800      ;
; 197.127 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.799      ;
; 197.127 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.799      ;
; 197.128 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.798      ;
; 197.145 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.781      ;
; 197.146 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.780      ;
; 197.146 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.780      ;
; 197.147 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.779      ;
; 197.205 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.721      ;
; 197.213 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.713      ;
; 197.215 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.711      ;
; 197.235 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.691      ;
; 197.250 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.676      ;
; 197.254 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.672      ;
; 197.255 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.671      ;
; 197.258 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.668      ;
; 197.259 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.667      ;
; 197.259 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.667      ;
; 197.260 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.666      ;
; 197.261 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.665      ;
; 197.277 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.649      ;
; 197.278 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.648      ;
; 197.278 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.648      ;
; 197.279 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.647      ;
; 197.280 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.646      ;
; 197.337 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.589      ;
; 197.345 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.581      ;
; 197.345 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.581      ;
; 197.347 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.579      ;
; 197.367 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.559      ;
; 197.382 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.544      ;
; 197.386 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.540      ;
; 197.387 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.539      ;
; 197.388 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.538      ;
; 197.390 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.536      ;
; 197.391 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.535      ;
; 197.391 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.535      ;
; 197.392 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.534      ;
; 197.392 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.534      ;
; 197.393 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.533      ;
; 197.409 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.517      ;
; 197.410 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.516      ;
; 197.410 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.516      ;
; 197.411 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.515      ;
; 197.411 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.515      ;
; 197.412 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.514      ;
; 197.469 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.457      ;
; 197.477 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.449      ;
; 197.477 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.449      ;
; 197.478 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.448      ;
; 197.479 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.447      ;
; 197.499 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.427      ;
; 197.514 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.412      ;
; 197.518 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.408      ;
; 197.519 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.407      ;
; 197.520 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.406      ;
; 197.521 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.405      ;
; 197.522 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.404      ;
; 197.523 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.403      ;
; 197.524 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.402      ;
; 197.524 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.402      ;
; 197.525 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.403      ;
; 197.525 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.401      ;
; 197.529 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.400      ;
; 197.541 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.385      ;
; 197.542 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.384      ;
; 197.542 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.384      ;
; 197.543 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.383      ;
; 197.543 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.383      ;
; 197.544 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.382      ;
; 197.548 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.381      ;
; 197.601 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.325      ;
; 197.609 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.317      ;
; 197.609 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.317      ;
; 197.609 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.317      ;
; 197.610 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.072     ; 2.316      ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                           ;
+-------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                 ; To Node                                                                                                                                             ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.949 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[4]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.177     ; 4.540      ;
; 1.042 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[4]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.177     ; 4.447      ;
; 1.235 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[10]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.168     ; 4.263      ;
; 1.288 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[9]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.178     ; 4.200      ;
; 1.288 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[11]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.178     ; 4.200      ;
; 1.328 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[10]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.168     ; 4.170      ;
; 1.345 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_ras_n                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.166     ; 4.155      ;
; 1.381 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[9]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.178     ; 4.107      ;
; 1.381 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[11]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.178     ; 4.107      ;
; 1.418 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[5]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.177     ; 4.071      ;
; 1.418 ; SDRAM_ADDR[18]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[7]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.187     ; 4.061      ;
; 1.453 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_ras_n                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.166     ; 4.047      ;
; 1.511 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[5]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.177     ; 3.978      ;
; 1.535 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[6]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.179     ; 3.952      ;
; 1.539 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[7]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.180     ; 3.947      ;
; 1.539 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[8]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.180     ; 3.947      ;
; 1.628 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[6]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.179     ; 3.859      ;
; 1.632 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[7]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.180     ; 3.854      ;
; 1.632 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[8]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.180     ; 3.854      ;
; 1.662 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[4]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.164     ; 3.955      ;
; 1.662 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[13]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.164     ; 3.955      ;
; 1.677 ; SDRAM_ADDR[8]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[7]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.195     ; 3.794      ;
; 1.731 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[7]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.164     ; 3.886      ;
; 1.732 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[3]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.164     ; 3.885      ;
; 1.857 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[0]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.158     ; 3.766      ;
; 1.860 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[1]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.158     ; 3.763      ;
; 1.862 ; SDRAM_ADDR[21]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[10]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.175     ; 3.629      ;
; 1.863 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[2]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.158     ; 3.760      ;
; 1.894 ; SDRAM_ADDR[17]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[6]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.186     ; 3.586      ;
; 1.925 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_ba[0]                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.168     ; 3.573      ;
; 1.925 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_ba[1]                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.168     ; 3.573      ;
; 1.983 ; SDRAM_ADDR[5]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[4]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.177     ; 3.506      ;
; 2.033 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_ba[0]                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.168     ; 3.465      ;
; 2.033 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_ba[1]                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.168     ; 3.465      ;
; 2.066 ; SDRAM_ADDR[16]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.184     ; 3.416      ;
; 2.092 ; SDRAM_ADDR[7]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[6]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.179     ; 3.395      ;
; 2.146 ; SDRAM_ADDR[15]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.177     ; 3.343      ;
; 2.162 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[4]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.166     ; 3.453      ;
; 2.162 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[13]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.166     ; 3.453      ;
; 2.167 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[14]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.164     ; 3.450      ;
; 2.168 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[15]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.164     ; 3.449      ;
; 2.171 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[6]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.164     ; 3.446      ;
; 2.231 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[7]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.166     ; 3.384      ;
; 2.232 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[3]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.166     ; 3.383      ;
; 2.281 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[2]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.153     ; 3.347      ;
; 2.287 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[8]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.162     ; 3.332      ;
; 2.287 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[10]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.162     ; 3.332      ;
; 2.288 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_bena_reg[1]                                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.162     ; 3.331      ;
; 2.290 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[11]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.162     ; 3.329      ;
; 2.290 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[12]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.162     ; 3.329      ;
; 2.290 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_bena_reg[0]                                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.162     ; 3.329      ;
; 2.292 ; SDRAM_ADDR[20]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[9]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.185     ; 3.189      ;
; 2.327 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[5]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.158     ; 3.296      ;
; 2.356 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[9]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.162     ; 3.263      ;
; 2.357 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[0]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.160     ; 3.264      ;
; 2.360 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[1]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.160     ; 3.261      ;
; 2.363 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[2]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.160     ; 3.258      ;
; 2.372 ; SDRAM_ADDR[19]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[8]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.187     ; 3.107      ;
; 2.390 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[2]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.165     ; 3.111      ;
; 2.390 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[3]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.165     ; 3.111      ;
; 2.465 ; SDRAM_ADDR[22]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[11]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.179     ; 3.022      ;
; 2.498 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[2]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.165     ; 3.003      ;
; 2.498 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[3]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.165     ; 3.003      ;
; 2.512 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[0]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.156     ; 3.113      ;
; 2.512 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[5]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.156     ; 3.113      ;
; 2.512 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[4]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.156     ; 3.113      ;
; 2.512 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[13]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.156     ; 3.113      ;
; 2.512 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[12]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.156     ; 3.113      ;
; 2.512 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[10]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.156     ; 3.113      ;
; 2.512 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[9]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.156     ; 3.113      ;
; 2.512 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[8]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.156     ; 3.113      ;
; 2.522 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[0]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.168     ; 2.976      ;
; 2.522 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[1]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.168     ; 2.976      ;
; 2.546 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.153     ; 3.082      ;
; 2.555 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_do_reg[15]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.154     ; 3.072      ;
; 2.583 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[6]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.164     ; 3.034      ;
; 2.594 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_do_reg[3]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.154     ; 3.033      ;
; 2.606 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_do_reg[11]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.154     ; 3.021      ;
; 2.630 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[0]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.168     ; 2.868      ;
; 2.630 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[1]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.168     ; 2.868      ;
; 2.639 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.153     ; 2.989      ;
; 2.640 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[3]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.156     ; 2.985      ;
; 2.640 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[15]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.156     ; 2.985      ;
; 2.640 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[14]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.156     ; 2.985      ;
; 2.640 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[11]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.156     ; 2.985      ;
; 2.641 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:0:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -1.755     ; 1.257      ;
; 2.667 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[14]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.166     ; 2.948      ;
; 2.668 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[15]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.166     ; 2.947      ;
; 2.671 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[6]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.166     ; 2.944      ;
; 2.674 ; SDRAM_ADDR[14]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[3]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.165     ; 2.827      ;
; 2.685 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_do_reg[2]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.151     ; 2.945      ;
; 2.689 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[10]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.164     ; 2.928      ;
; 2.691 ; SDRAM_WRITE_ENABLE                                                                        ; ram_bena_reg[1]                                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.164     ; 2.926      ;
; 2.693 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[12]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.164     ; 2.924      ;
; 2.694 ; SDRAM_WRITE_ENABLE                                                                        ; ram_bena_reg[0]                                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.164     ; 2.923      ;
; 2.713 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[8]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.164     ; 2.904      ;
; 2.714 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[9]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.164     ; 2.903      ;
; 2.717 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[11]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.164     ; 2.900      ;
; 2.731 ; SDRAM_ADDR[6]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[5]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.177     ; 2.758      ;
; 2.741 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_do_reg[14]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.154     ; 2.886      ;
+-------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                                                                                                                                                      ;
+--------+-----------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                           ; To Node                                                                                                                                             ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 2.079  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 15.264     ;
; 2.171  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 15.172     ;
; 2.191  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 15.152     ;
; 2.211  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 15.132     ;
; 2.221  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 15.122     ;
; 2.266  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 15.077     ;
; 2.283  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 15.060     ;
; 2.313  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 15.030     ;
; 2.323  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 15.020     ;
; 2.353  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 14.990     ;
; 2.358  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 14.985     ;
; 2.363  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 14.980     ;
; 2.378  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 14.965     ;
; 2.398  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 14.945     ;
; 2.455  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 14.888     ;
; 2.490  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 14.853     ;
; 2.495  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 14.848     ;
; 2.520  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 14.823     ;
; 2.565  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 14.778     ;
; 2.662  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 14.681     ;
; 2.673  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.195     ; 14.661     ;
; 2.765  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.195     ; 14.569     ;
; 2.805  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.195     ; 14.529     ;
; 2.875  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.189     ; 14.465     ;
; 2.967  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.189     ; 14.373     ;
; 2.972  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.195     ; 14.362     ;
; 2.974  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 14.369     ;
; 3.007  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.189     ; 14.333     ;
; 3.086  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 14.257     ;
; 3.116  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 14.227     ;
; 3.161  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 14.182     ;
; 3.174  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.189     ; 14.166     ;
; 3.258  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 14.085     ;
; 3.549  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 13.794     ;
; 3.568  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.195     ; 13.766     ;
; 3.661  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 13.682     ;
; 3.691  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 13.652     ;
; 3.736  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 13.607     ;
; 3.770  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.189     ; 13.570     ;
; 3.833  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 13.510     ;
; 4.143  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.195     ; 13.191     ;
; 4.345  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.189     ; 12.995     ;
; 4.489  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 12.854     ;
; 4.601  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 12.742     ;
; 4.631  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 12.712     ;
; 4.676  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 12.667     ;
; 4.773  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 12.570     ;
; 5.083  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.195     ; 12.251     ;
; 5.285  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.189     ; 12.055     ;
; 5.305  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0]           ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 8.810        ; -1.755     ; 1.530      ;
; 6.024  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 11.319     ;
; 6.136  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 11.207     ;
; 6.166  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 11.177     ;
; 6.211  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 11.132     ;
; 6.308  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 11.035     ;
; 6.618  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.195     ; 10.716     ;
; 6.820  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.189     ; 10.520     ;
; 7.350  ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.073     ; 10.106     ;
; 7.365  ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.073     ; 10.091     ;
; 7.442  ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.073     ; 10.014     ;
; 7.457  ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.073     ; 9.999      ;
; 7.457  ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.073     ; 9.999      ;
; 7.482  ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.073     ; 9.974      ;
; 7.497  ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.073     ; 9.959      ;
; 7.546  ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.073     ; 9.910      ;
; 7.549  ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.073     ; 9.907      ;
; 7.589  ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.073     ; 9.867      ;
; 7.638  ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.073     ; 9.818      ;
; 7.649  ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.073     ; 9.807      ;
; 7.664  ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.073     ; 9.792      ;
; 7.678  ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.073     ; 9.778      ;
; 7.756  ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.073     ; 9.700      ;
; 7.845  ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.073     ; 9.611      ;
; 8.245  ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.073     ; 9.211      ;
; 8.245  ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.073     ; 9.211      ;
; 8.260  ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.073     ; 9.196      ;
; 8.337  ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.073     ; 9.119      ;
; 8.352  ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.073     ; 9.104      ;
; 8.377  ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.073     ; 9.079      ;
; 8.441  ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.073     ; 9.015      ;
; 8.548  ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.073     ; 8.908      ;
; 8.820  ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.073     ; 8.636      ;
; 8.835  ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.073     ; 8.621      ;
; 8.927  ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.073     ; 8.529      ;
; 9.016  ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.073     ; 8.440      ;
; 9.144  ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.073     ; 8.312      ;
; 9.719  ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.073     ; 7.737      ;
; 9.760  ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.073     ; 7.696      ;
; 9.775  ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.073     ; 7.681      ;
; 9.867  ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.073     ; 7.589      ;
; 9.956  ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.073     ; 7.500      ;
; 10.655 ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.073     ; 6.801      ;
; 11.171 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg        ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.189     ; 6.169      ;
; 11.295 ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.073     ; 6.161      ;
; 11.310 ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.073     ; 6.146      ;
; 11.402 ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.073     ; 6.054      ;
; 11.491 ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.073     ; 5.965      ;
; 11.559 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2]    ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.189     ; 5.781      ;
; 11.582 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0]    ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.208     ; 5.739      ;
; 11.664 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg        ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.189     ; 5.676      ;
+--------+-----------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                              ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                     ; To Node                                                                                                                                                                                                                                          ; Launch Clock                                                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -1.833 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 0.887      ;
; -1.785 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.425      ; 0.934      ;
; -1.782 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 0.938      ;
; -1.739 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.427      ; 0.982      ;
; -1.739 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 0.981      ;
; -1.735 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[0]                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.427      ; 0.986      ;
; -1.727 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 0.993      ;
; -1.705 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn_reg1                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.015      ;
; -1.698 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg_reg1                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.427      ; 1.023      ;
; -1.690 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.427      ; 1.031      ;
; -1.684 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol_reg1                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.036      ;
; -1.680 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.427      ; 1.041      ;
; -1.679 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.427      ; 1.042      ;
; -1.673 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.427      ; 1.048      ;
; -1.672 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.427      ; 1.049      ;
; -1.653 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.438      ; 1.079      ;
; -1.649 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.438      ; 1.083      ;
; -1.649 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.427      ; 1.072      ;
; -1.647 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.427      ; 1.074      ;
; -1.646 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.427      ; 1.075      ;
; -1.646 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.074      ;
; -1.645 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.438      ; 1.087      ;
; -1.645 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate_reg1                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.075      ;
; -1.645 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.075      ;
; -1.644 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.427      ; 1.077      ;
; -1.644 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.427      ; 1.077      ;
; -1.644 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.427      ; 1.077      ;
; -1.643 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.077      ;
; -1.641 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.079      ;
; -1.640 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.427      ; 1.081      ;
; -1.640 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.080      ;
; -1.638 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.082      ;
; -1.638 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.082      ;
; -1.637 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.083      ;
; -1.635 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.415      ; 1.074      ;
; -1.635 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.085      ;
; -1.631 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.089      ;
; -1.630 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.438      ; 1.102      ;
; -1.629 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.091      ;
; -1.627 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.427      ; 1.094      ;
; -1.626 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.427      ; 1.095      ;
; -1.626 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.094      ;
; -1.626 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[0]                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.094      ;
; -1.624 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.427      ; 1.097      ;
; -1.624 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.096      ;
; -1.620 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.100      ;
; -1.620 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.427      ; 1.101      ;
; -1.619 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.101      ;
; -1.617 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.427      ; 1.104      ;
; -1.616 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.438      ; 1.116      ;
; -1.605 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                                                           ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.115      ;
; -1.603 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate_reg1                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.427      ; 1.118      ;
; -1.599 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn_reg1                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.427      ; 1.122      ;
; -1.599 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.121      ;
; -1.597 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol_reg1                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.427      ; 1.124      ;
; -1.596 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.427      ; 1.125      ;
; -1.596 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.427      ; 1.125      ;
; -1.595 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.427      ; 1.126      ;
; -1.594 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.126      ;
; -1.593 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg_reg1                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.427      ; 1.128      ;
; -1.590 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.415      ; 1.119      ;
; -1.586 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[3]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.415      ; 1.123      ;
; -1.582 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.438      ; 1.150      ;
; -1.581 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[2]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.415      ; 1.128      ;
; -1.576 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.144      ;
; -1.515 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.205      ;
; -1.512 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[2]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.208      ;
; -1.511 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.209      ;
; -1.510 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.210      ;
; -1.509 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.211      ;
; -1.505 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.427      ; 1.216      ;
; -1.502 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.427      ; 1.219      ;
; -1.494 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.438      ; 1.238      ;
; -1.491 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.414      ; 1.217      ;
; -1.485 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[3]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.235      ;
; -1.465 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.255      ;
; -1.441 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.279      ;
; -1.434 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.427      ; 1.287      ;
; -1.433 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.425      ; 1.286      ;
; -1.429 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.425      ; 1.290      ;
; -1.397 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.323      ;
; 0.350  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[0]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.435      ; 1.007      ;
; 0.353  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[1]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.435      ; 1.010      ;
; 0.356  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[4]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.435      ; 1.013      ;
; 0.360  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[5]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.435      ; 1.017      ;
; 0.365  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[3]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.431      ; 1.018      ;
; 0.368  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[0]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.431      ; 1.021      ;
; 0.371  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[6]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.435      ; 1.028      ;
; 0.375  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[4]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.431      ; 1.028      ;
; 0.375  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[3]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.435      ; 1.032      ;
; 0.377  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[2]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.435      ; 1.034      ;
; 0.383  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[7]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.435      ; 1.040      ;
; 0.388  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[6]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.431      ; 1.041      ;
; 0.389  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_address_reg0 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.426      ; 1.037      ;
; 0.390  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[2]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.431      ; 1.043      ;
; 0.400  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[5]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.431      ; 1.053      ;
; 0.404  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[7]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.431      ; 1.057      ;
; 0.408  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[1]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.431      ; 1.061      ;
; 0.410  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_address_reg0 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.426      ; 1.058      ;
; 0.410  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_address_reg0 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.426      ; 1.058      ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'FPGA_CLK'                                                                                                                                                                                                                                                                                        ;
+--------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                       ; To Node                                                                               ; Launch Clock                                                                        ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.735 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[131]                                 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.112      ; 3.729      ;
; 0.438  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2] ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1]       ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.694      ;
; 0.442  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1] ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.698      ;
; 0.453  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 0.708      ;
; 0.484  ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8     ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; -0.197     ; 1.420      ;
; 0.652  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.908      ;
; 0.652  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.908      ;
; 0.652  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.908      ;
; 0.652  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.908      ;
; 0.653  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.909      ;
; 0.653  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.909      ;
; 0.653  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 0.908      ;
; 0.654  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.910      ;
; 0.654  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.910      ;
; 0.654  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.910      ;
; 0.654  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 0.909      ;
; 0.654  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 0.909      ;
; 0.654  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 0.909      ;
; 0.655  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 0.910      ;
; 0.655  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 0.910      ;
; 0.656  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 0.911      ;
; 0.656  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 0.911      ;
; 0.657  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 0.912      ;
; 0.658  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.914      ;
; 0.659  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 0.914      ;
; 0.660  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 0.915      ;
; 0.671  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.927      ;
; 0.671  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 0.926      ;
; 0.680  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.936      ;
; 0.969  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.225      ;
; 0.970  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.226      ;
; 0.970  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.225      ;
; 0.970  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.226      ;
; 0.971  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.227      ;
; 0.971  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.227      ;
; 0.971  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.226      ;
; 0.971  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.227      ;
; 0.972  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.227      ;
; 0.972  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.227      ;
; 0.974  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.229      ;
; 0.979  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.235      ;
; 0.980  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.236      ;
; 0.981  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.237      ;
; 0.981  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.236      ;
; 0.982  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.237      ;
; 0.982  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.067      ; 1.235      ;
; 0.983  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.238      ;
; 0.983  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.238      ;
; 0.984  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.240      ;
; 0.985  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.241      ;
; 0.985  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.241      ;
; 0.986  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.241      ;
; 0.986  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.242      ;
; 0.986  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.241      ;
; 0.987  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.242      ;
; 0.987  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.067      ; 1.240      ;
; 0.987  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.242      ;
; 0.988  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.243      ;
; 0.988  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.243      ;
; 0.990  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.246      ;
; 0.991  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.246      ;
; 0.992  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.247      ;
; 0.998  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.254      ;
; 1.003  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.259      ;
; 1.091  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.347      ;
; 1.091  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.346      ;
; 1.091  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.347      ;
; 1.092  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.348      ;
; 1.092  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.348      ;
; 1.092  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.347      ;
; 1.092  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.348      ;
; 1.093  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.348      ;
; 1.093  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.067      ; 1.346      ;
; 1.093  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.348      ;
; 1.095  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.350      ;
; 1.096  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.352      ;
; 1.096  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.351      ;
; 1.096  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.352      ;
; 1.097  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.353      ;
; 1.097  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.353      ;
; 1.097  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.352      ;
; 1.097  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.353      ;
; 1.098  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.067      ; 1.351      ;
; 1.098  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.353      ;
; 1.098  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.353      ;
; 1.106  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.362      ;
; 1.107  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.363      ;
; 1.107  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.362      ;
; 1.108  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.067      ; 1.361      ;
; 1.108  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.067      ; 1.361      ;
; 1.108  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.363      ;
; 1.109  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.364      ;
; 1.109  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.364      ;
; 1.111  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.367      ;
; 1.111  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.367      ;
; 1.112  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.368      ;
; 1.112  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.367      ;
; 1.112  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.367      ;
; 1.113  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.368      ;
; 1.113  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.067      ; 1.366      ;
+--------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                           ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                   ; To Node                                                                                                                                                                                                                                          ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.343 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_address_reg0 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.449      ; 1.014      ;
; 0.353 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp0_snap_reg[5]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.432      ; 1.007      ;
; 0.366 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_address_reg0 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.449      ; 1.037      ;
; 0.370 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|cntr_1ab:wr_ptr|counter_reg_bit[1] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|altsyncram_pe81:FIFOram|ram_block1a0~porta_address_reg0                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.425      ; 1.017      ;
; 0.375 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|cntr_1ab:wr_ptr|counter_reg_bit[7] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|altsyncram_pe81:FIFOram|ram_block1a0~porta_address_reg0                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.425      ; 1.022      ;
; 0.377 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[0]                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|altsyncram_lh81:FIFOram|ram_block1a0~porta_datain_reg0                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.432      ; 1.031      ;
; 0.381 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|cntr_1ab:wr_ptr|counter_reg_bit[0] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|altsyncram_pe81:FIFOram|ram_block1a0~porta_address_reg0                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.425      ; 1.028      ;
; 0.381 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|cntr_1ab:wr_ptr|counter_reg_bit[6] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|altsyncram_pe81:FIFOram|ram_block1a0~porta_address_reg0                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.425      ; 1.028      ;
; 0.384 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|cntr_1ab:wr_ptr|counter_reg_bit[5] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|altsyncram_pe81:FIFOram|ram_block1a0~porta_address_reg0                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.425      ; 1.031      ;
; 0.385 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[3]                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|altsyncram_lh81:FIFOram|ram_block1a0~porta_datain_reg0                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.432      ; 1.039      ;
; 0.388 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_address_reg0 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.449      ; 1.059      ;
; 0.390 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[2]                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|altsyncram_lh81:FIFOram|ram_block1a0~porta_datain_reg0                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.432      ; 1.044      ;
; 0.390 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|cntr_1ab:wr_ptr|counter_reg_bit[4] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|altsyncram_pe81:FIFOram|ram_block1a0~porta_address_reg0                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.425      ; 1.037      ;
; 0.397 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInt                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInt                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 0.669      ;
; 0.397 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeInt                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeInt                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 0.669      ;
; 0.399 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp0_snap_reg[2]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.425      ; 1.046      ;
; 0.404 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp3_snap_reg[4]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.426      ; 1.052      ;
; 0.408 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[5]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.426      ; 1.056      ;
; 0.410 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[1]                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|altsyncram_lh81:FIFOram|ram_block1a0~porta_datain_reg0                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.432      ; 1.064      ;
; 0.411 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|cntr_1ab:wr_ptr|counter_reg_bit[3] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|altsyncram_pe81:FIFOram|ram_block1a0~porta_address_reg0                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.425      ; 1.058      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg                                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[4]                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[4]                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[6]                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[6]                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|cfg_enable                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|cfg_enable                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[22]                                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[22]                                                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|full_dff                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|full_dff                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|usedw_is_0_dff                       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|usedw_is_0_dff                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[23]                                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[23]                                                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[16]                                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[16]                                                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[17]                                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[17]                                                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|latch_delay_line:stimer_delay|data_in_reg                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|latch_delay_line:stimer_delay|data_in_reg                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serial_out_reg                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serial_out_reg                                                                                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[0]                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[0]                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf1_reg[6]                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf1_reg[6]                                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf1_reg[1]                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf1_reg[1]                                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf1_reg[2]                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf1_reg[2]                                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf1_reg[3]                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf1_reg[3]                                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf1_reg[4]                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf1_reg[4]                                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf1_reg[5]                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf1_reg[5]                                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer1|delay_line:underflow0_delay|shift_reg[0]                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer1|delay_line:underflow0_delay|shift_reg[0]                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|serial_out_reg                                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|serial_out_reg                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[7]                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[7]                                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[0]                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[0]                                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[1]                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[1]                                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[2]                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[2]                                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[3]                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[3]                                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[4]                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[4]                                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[5]                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[5]                                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[6]                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[6]                                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[0]                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[0]                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[7]                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[7]                                                                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|count_reg[1]                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|count_reg[1]                                                                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[0]                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[0]                                                                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pl_reg[2]                                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pl_reg[2]                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|shift_reg[6]                                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|shift_reg[6]                                                                                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|shift_reg[7]                                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|shift_reg[7]                                                                                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pl_reg[1]                                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pl_reg[1]                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player3|shift_reg[0]                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player3|shift_reg[0]                                                                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pf_reg[0]                                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pf_reg[0]                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p2pf_reg[0]                                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p2pf_reg[0]                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pf_reg[0]                                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pf_reg[0]                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pf_reg[0]                                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pf_reg[0]                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pf_reg[2]                                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pf_reg[2]                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pf_reg[2]                                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pf_reg[2]                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pl_reg[2]                                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pl_reg[2]                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pf_reg[2]                                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pf_reg[2]                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pf_reg[2]                                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pf_reg[2]                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pf_reg[3]                                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pf_reg[3]                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pf_reg[3]                                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pf_reg[3]                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pl_reg[3]                                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pl_reg[3]                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pl_reg[3]                                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pl_reg[3]                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pf_reg[3]                                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pf_reg[3]                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pl_reg[1]                                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pl_reg[1]                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pf_reg[1]                                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pf_reg[1]                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pf_reg[1]                                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pf_reg[1]                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p2pf_reg[1]                                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p2pf_reg[1]                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pf_reg[1]                                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pf_reg[1]                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pf_reg[1]                                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pf_reg[1]                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pf_reg[1]                                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pf_reg[1]                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pl_reg[1]                                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pl_reg[1]                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_noise_filter:pokey_noise_filter1|out_reg                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_noise_filter:pokey_noise_filter1|out_reg                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|highpass1_reg                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|highpass1_reg                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|highpass0_reg                                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|highpass0_reg                                                                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_noise_filter:pokey_noise_filter2|out_reg                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_noise_filter:pokey_noise_filter2|out_reg                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.413 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_load_sp2                                                                                                                                     ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_load_sp2                                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_store_sp2                                                                                                                                    ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_store_sp2                                                                                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_add_sp2                                                                                                                                      ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_add_sp2                                                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]                                                                                                                                                           ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]                                                                                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                                                                                                                                          ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                                                                                                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[8]                                                                                                                                                           ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[8]                                                                                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; sdram_reset_n_reg                                                                                                                                                                                           ; sdram_reset_n_reg                                                                                                                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[4]                                                                                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[4]                                                                                                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[26]                                                                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[26]                                                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[0]                                                                                                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[0]                                                                                                                                                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[31]                                                                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[31]                                                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[10]                                                                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[10]                                                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[24]                                                                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[24]                                                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[25]                                                                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[25]                                                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[28]                                                                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[28]                                                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                  ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                 ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.413 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; sdram_ctrl:sdram_controller|sdram_rdy                     ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; sdram_request_reg                                         ; sdram_request_reg                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.414 ; sdram_ctrl:sdram_controller|r_refr_act                    ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; sdram_ctrl:sdram_controller|r_rd_act                      ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; sdram_ctrl:sdram_controller|r_wr_act                      ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.418 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.674      ;
; 0.471 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.727      ;
; 0.474 ; seq_reg[11]                                               ; seq_reg[0]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.730      ;
; 0.574 ; sdram_ctrl:sdram_controller|r_rd_act                      ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.829      ;
; 0.613 ; seq_reg[9]                                                ; seq_reg[10]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.869      ;
; 0.634 ; seq_reg[2]                                                ; seq_reg[3]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.890      ;
; 0.646 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.902      ;
; 0.646 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.902      ;
; 0.646 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.902      ;
; 0.647 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.903      ;
; 0.647 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.903      ;
; 0.649 ; seq_reg[3]                                                ; seq_reg[4]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.905      ;
; 0.650 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.906      ;
; 0.650 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.906      ;
; 0.650 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.905      ;
; 0.650 ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.905      ;
; 0.655 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.910      ;
; 0.661 ; seq_reg[0]                                                ; seq_reg[1]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.917      ;
; 0.663 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.919      ;
; 0.663 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.919      ;
; 0.666 ; seq_reg[4]                                                ; seq_reg[5]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.922      ;
; 0.708 ; sdram_ctrl:sdram_controller|r_rd_act                      ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.963      ;
; 0.719 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.975      ;
; 0.726 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.982      ;
; 0.727 ; seq_reg[10]                                               ; seq_reg[11]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.983      ;
; 0.735 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.991      ;
; 0.764 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.020      ;
; 0.784 ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.040      ;
; 0.799 ; seq_reg[8]                                                ; seq_reg[9]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.055      ;
; 0.807 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.063      ;
; 0.817 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.073      ;
; 0.825 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.081      ;
; 0.938 ; seq_reg[4]                                                ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.194      ;
; 0.945 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.073      ; 1.204      ;
; 0.963 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.219      ;
; 0.964 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.220      ;
; 0.964 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.220      ;
; 0.973 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.229      ;
; 0.973 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.229      ;
; 0.976 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.232      ;
; 0.977 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.233      ;
; 0.977 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.233      ;
; 0.978 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.234      ;
; 0.978 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.234      ;
; 0.981 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.237      ;
; 0.982 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.238      ;
; 0.982 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.238      ;
; 0.992 ; sdram_ctrl:sdram_controller|r_refr_act                    ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.083      ; 1.261      ;
; 0.998 ; sdram_ctrl:sdram_controller|r_refr_act                    ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.083      ; 1.267      ;
; 1.080 ; seq_reg[7]                                                ; seq_reg[8]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.336      ;
; 1.085 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.341      ;
; 1.085 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.341      ;
; 1.090 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.346      ;
; 1.090 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.346      ;
; 1.099 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.355      ;
; 1.102 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.358      ;
; 1.103 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.359      ;
; 1.103 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.359      ;
; 1.104 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.360      ;
; 1.107 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.363      ;
; 1.108 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.364      ;
; 1.108 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.364      ;
; 1.109 ; seq_reg[1]                                                ; seq_reg[2]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.366      ;
; 1.124 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.380      ;
; 1.136 ; seq_reg[1]                                                ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.393      ;
; 1.143 ; sdram_request_reg                                         ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.398      ;
; 1.144 ; sdram_ctrl:sdram_controller|r_rd_reg                      ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.056      ; 1.386      ;
; 1.190 ; seq_reg[0]                                                ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.447      ;
; 1.197 ; sdram_ctrl:sdram_controller|r_wr_reg                      ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.056      ; 1.439      ;
; 1.211 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.467      ;
; 1.212 ; sdram_ctrl:sdram_controller|r_refr_act                    ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.467      ;
; 1.212 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.468      ;
; 1.216 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.472      ;
; 1.225 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.481      ;
; 1.228 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.484      ;
; 1.229 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.485      ;
; 1.230 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.486      ;
; 1.233 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.489      ;
; 1.234 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.490      ;
; 1.240 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.496      ;
; 1.245 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.501      ;
; 1.250 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.506      ;
; 1.268 ; sdram_request_complete_reg                                ; sdram_request_complete_reg                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.523      ;
; 1.276 ; seq_reg[4]                                                ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.532      ;
; 1.314 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.570      ;
; 1.328 ; seq_reg[5]                                                ; seq_reg[6]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.583      ;
; 1.347 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.603      ;
; 1.351 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.607      ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                                     ;
+-------+--------------------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                        ; To Node                               ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.414 ; svideo_gtia:svideo|phase_count_reg[5]                                                            ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; svideo_gtia:svideo|phase_count_reg[6]                                                            ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; svideo_gtia:svideo|phase_count_reg[7]                                                            ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 0.669      ;
; 0.887 ; svideo_gtia:svideo|phase_count_reg[4]                                                            ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 1.142      ;
; 0.991 ; svideo_gtia:svideo|phase_count_reg[4]                                                            ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 1.246      ;
; 1.016 ; svideo_gtia:svideo|phase_count_reg[3]                                                            ; svideo_gtia:svideo|phase_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 1.271      ;
; 1.022 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                              ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.149      ; 1.467      ;
; 1.247 ; svideo_gtia:svideo|phase_count_reg[6]                                                            ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 1.502      ;
; 1.341 ; svideo_gtia:svideo|phase_count_reg[2]                                                            ; svideo_gtia:svideo|phase_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 1.596      ;
; 1.352 ; svideo_gtia:svideo|phase_count_reg[4]                                                            ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 1.607      ;
; 1.410 ; svideo_gtia:svideo|phase_count_reg[5]                                                            ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 1.665      ;
; 1.447 ; svideo_gtia:svideo|phase_count_reg[3]                                                            ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 1.702      ;
; 1.457 ; svideo_gtia:svideo|phase_count_reg[2]                                                            ; svideo_gtia:svideo|phase_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 1.712      ;
; 1.466 ; svideo_gtia:svideo|phase_count_reg[2]                                                            ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 1.721      ;
; 1.486 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                              ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.149      ; 1.931      ;
; 1.499 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                              ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.149      ; 1.944      ;
; 1.501 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                              ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.149      ; 1.946      ;
; 1.522 ; svideo_gtia:svideo|phase_count_reg[5]                                                            ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 1.777      ;
; 1.575 ; svideo_gtia:svideo|phase_count_reg[3]                                                            ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 1.830      ;
; 1.594 ; svideo_gtia:svideo|phase_count_reg[2]                                                            ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 1.849      ;
; 1.640 ; svideo_gtia:svideo|phase_count_reg[4]                                                            ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 1.895      ;
; 1.670 ; svideo_gtia:svideo|phase_count_reg[3]                                                            ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 1.925      ;
; 1.689 ; svideo_gtia:svideo|phase_count_reg[2]                                                            ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 1.944      ;
; 1.696 ; svideo_gtia:svideo|phase_count_reg[3]                                                            ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 1.951      ;
; 1.715 ; svideo_gtia:svideo|phase_count_reg[2]                                                            ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 1.970      ;
; 2.005 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                              ; svideo_gtia:svideo|phase_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.149      ; 2.450      ;
; 2.005 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                              ; svideo_gtia:svideo|phase_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.149      ; 2.450      ;
; 2.111 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 2.562      ;
; 2.152 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.151      ; 2.599      ;
; 2.154 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.151      ; 2.601      ;
; 2.257 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hblank_reg    ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.151      ; 2.704      ;
; 2.276 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hblank_reg    ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.151      ; 2.723      ;
; 2.306 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hblank_reg    ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.151      ; 2.753      ;
; 2.323 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hblank_reg    ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.151      ; 2.770      ;
; 2.334 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 2.785      ;
; 2.390 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|phase_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 2.842      ;
; 2.391 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|phase_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 2.843      ;
; 2.405 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.151      ; 2.852      ;
; 2.421 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hblank_reg    ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.151      ; 2.868      ;
; 2.424 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 2.875      ;
; 2.429 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 2.880      ;
; 2.444 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 2.895      ;
; 2.445 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 2.896      ;
; 2.448 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.133      ; 2.877      ;
; 2.450 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.151      ; 2.897      ;
; 2.459 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.152      ; 2.907      ;
; 2.466 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.133      ; 2.895      ;
; 2.489 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.152      ; 2.937      ;
; 2.505 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.151      ; 2.952      ;
; 2.510 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hblank_reg    ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.151      ; 2.957      ;
; 2.550 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 3.001      ;
; 2.555 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 3.006      ;
; 2.555 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 3.006      ;
; 2.576 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.151      ; 3.023      ;
; 2.577 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 3.028      ;
; 2.598 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hblank_reg    ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.151      ; 3.045      ;
; 2.612 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 3.063      ;
; 2.631 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.151      ; 3.078      ;
; 2.637 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 3.089      ;
; 2.637 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 3.089      ;
; 2.637 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 3.089      ;
; 2.647 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 3.098      ;
; 2.652 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 3.103      ;
; 2.665 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 3.116      ;
; 2.676 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 3.127      ;
; 2.681 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 3.132      ;
; 2.687 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 3.138      ;
; 2.687 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hblank_reg    ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.151      ; 3.134      ;
; 2.694 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.152      ; 3.142      ;
; 2.702 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.151      ; 3.149      ;
; 2.710 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.152      ; 3.158      ;
; 2.714 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 3.165      ;
; 2.719 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 3.170      ;
; 2.720 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 3.171      ;
; 2.721 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.152      ; 3.169      ;
; 2.722 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 3.173      ;
; 2.722 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.151      ; 3.169      ;
; 2.729 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.133      ; 3.158      ;
; 2.739 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.151      ; 3.186      ;
; 2.751 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.152      ; 3.199      ;
; 2.758 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.133      ; 3.187      ;
; 2.763 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 3.214      ;
; 2.776 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 3.227      ;
; 2.781 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.152      ; 3.229      ;
; 2.782 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.133      ; 3.211      ;
; 2.805 ; svideo_gtia:svideo|phase_count_reg[7]                                                            ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.065      ; 3.056      ;
; 2.825 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 3.276      ;
; 2.830 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 3.281      ;
; 2.831 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 3.282      ;
; 2.848 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.151      ; 3.295      ;
; 2.865 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.151      ; 3.312      ;
; 2.868 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 3.320      ;
; 2.882 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 3.333      ;
; 2.891 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.133      ; 3.320      ;
; 2.895 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 3.346      ;
; 2.908 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.133      ; 3.337      ;
; 2.908 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 3.359      ;
; 2.930 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 3.381      ;
; 2.943 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 3.394      ;
; 2.956 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[3] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.151      ; 3.403      ;
+-------+--------------------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                                                             ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                 ; To Node                                                                                                                                             ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 12.748 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -10.281      ; -1.502     ; 1.138      ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                          ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                            ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -2.348 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.214      ; 3.524      ;
; -2.348 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.214      ; 3.524      ;
; -2.348 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.214      ; 3.524      ;
; -2.348 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.214      ; 3.524      ;
; -2.348 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.214      ; 3.524      ;
; -2.348 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.214      ; 3.524      ;
; -2.348 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.214      ; 3.524      ;
; -2.348 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.214      ; 3.524      ;
; -2.348 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.214      ; 3.524      ;
; -2.296 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.215      ; 3.408      ;
; -2.296 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.215      ; 3.408      ;
; -2.296 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.215      ; 3.408      ;
; -2.296 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.215      ; 3.408      ;
; -2.296 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.215      ; 3.408      ;
; -2.296 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.215      ; 3.408      ;
; -2.296 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.215      ; 3.408      ;
; -2.296 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.215      ; 3.408      ;
; -2.296 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.215      ; 3.408      ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: 'FPGA_CLK'                                                                                                                                                                                                                                                                               ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                            ; To Node                                                                     ; Launch Clock                                                                        ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.299 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.286      ; 4.349      ;
; -0.299 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.286      ; 4.349      ;
; -0.299 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.286      ; 4.349      ;
; -0.299 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.286      ; 4.349      ;
; -0.299 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.286      ; 4.349      ;
; -0.299 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.286      ; 4.349      ;
; -0.299 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.286      ; 4.349      ;
; -0.299 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.286      ; 4.349      ;
; -0.299 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.286      ; 4.349      ;
; -0.299 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.286      ; 4.349      ;
; -0.299 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.286      ; 4.349      ;
; -0.299 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.286      ; 4.349      ;
; -0.286 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.285      ; 4.335      ;
; -0.286 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.284      ; 4.334      ;
; -0.286 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.284      ; 4.334      ;
; -0.286 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.284      ; 4.334      ;
; -0.286 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.284      ; 4.334      ;
; -0.286 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.284      ; 4.334      ;
; -0.286 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.284      ; 4.334      ;
; -0.286 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.284      ; 4.334      ;
; -0.286 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.284      ; 4.334      ;
; -0.286 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.284      ; 4.334      ;
; -0.286 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.284      ; 4.334      ;
; -0.286 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.284      ; 4.334      ;
; -0.286 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.284      ; 4.334      ;
; -0.286 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.284      ; 4.334      ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                              ;
+-------+---------------------------------------+-----------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                                                                                       ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+-----------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 7.512 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 3.982      ;
; 7.512 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 3.982      ;
; 7.512 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 3.982      ;
; 7.512 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 3.982      ;
; 7.512 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 3.982      ;
; 7.512 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 3.982      ;
; 7.512 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 3.982      ;
; 7.555 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|scl_ena                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 3.926      ;
; 7.555 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|ack_error                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 3.926      ;
; 7.559 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[2]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.170     ; 3.927      ;
; 7.561 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[14]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 3.935      ;
; 7.561 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[15]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 3.935      ;
; 7.561 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[13]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 3.935      ;
; 7.580 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[21]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 3.914      ;
; 7.580 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[19]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 3.914      ;
; 7.580 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[18]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 3.914      ;
; 7.582 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_select_reg[0]                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.159     ; 3.915      ;
; 7.593 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[6]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 3.903      ;
; 7.593 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[5]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 3.903      ;
; 7.593 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[4]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 3.903      ;
; 7.593 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[2]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 3.903      ;
; 7.595 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 3.897      ;
; 7.595 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[30]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 3.897      ;
; 7.595 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[29]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 3.897      ;
; 7.595 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[31]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 3.897      ;
; 7.595 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[13]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 3.897      ;
; 7.595 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[12]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 3.897      ;
; 7.595 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[24]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 3.897      ;
; 7.595 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[23]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 3.897      ;
; 7.595 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[14]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 3.897      ;
; 7.595 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[28]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 3.897      ;
; 7.942 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[6]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.540      ;
; 7.942 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[4]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.540      ;
; 7.942 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[7]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.540      ;
; 7.942 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[5]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.170     ; 3.544      ;
; 7.942 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[4]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.540      ;
; 7.942 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[0]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.187     ; 3.527      ;
; 7.942 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[8]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 3.539      ;
; 7.942 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[9]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 3.539      ;
; 7.942 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[29]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 3.539      ;
; 7.942 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[29]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.187     ; 3.527      ;
; 7.942 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[29]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.187     ; 3.527      ;
; 7.942 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[0]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.170     ; 3.544      ;
; 7.942 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[8]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.540      ;
; 7.942 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[9]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.540      ;
; 7.942 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[3]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.540      ;
; 7.942 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[0]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.187     ; 3.527      ;
; 7.942 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[21]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.187     ; 3.527      ;
; 7.942 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[21]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.187     ; 3.527      ;
; 7.942 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[16]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 3.539      ;
; 7.942 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[22]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 3.539      ;
; 7.942 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[9]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.540      ;
; 7.942 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[15]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.187     ; 3.527      ;
; 7.942 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[15]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.187     ; 3.527      ;
; 7.942 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[8]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.540      ;
; 7.942 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[3]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.540      ;
; 7.942 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[0]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.186     ; 3.528      ;
; 7.942 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[1]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.186     ; 3.528      ;
; 7.942 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[2]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.186     ; 3.528      ;
; 7.942 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[3]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.186     ; 3.528      ;
; 7.942 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[4]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.186     ; 3.528      ;
; 7.942 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[5]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.186     ; 3.528      ;
; 7.942 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[6]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.186     ; 3.528      ;
; 7.942 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[7]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.186     ; 3.528      ;
; 7.942 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[8]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.186     ; 3.528      ;
; 7.942 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[9]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.186     ; 3.528      ;
; 7.942 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[10]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.186     ; 3.528      ;
; 7.942 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[11]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.186     ; 3.528      ;
; 7.942 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[12]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.186     ; 3.528      ;
; 7.942 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[13]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.186     ; 3.528      ;
; 7.942 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[14]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.186     ; 3.528      ;
; 7.942 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[15]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.186     ; 3.528      ;
; 7.943 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[6]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.173     ; 3.540      ;
; 7.943 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[30]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.185     ; 3.528      ;
; 7.943 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[14]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.185     ; 3.528      ;
; 7.943 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[15]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.185     ; 3.528      ;
; 7.943 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[16]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.539      ;
; 7.943 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[17]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.539      ;
; 7.943 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[15]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.539      ;
; 7.943 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[2]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.539      ;
; 7.943 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[6]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.539      ;
; 7.943 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[21]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.185     ; 3.528      ;
; 7.943 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|bit_cnt[0]                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.187     ; 3.526      ;
; 7.943 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|bit_cnt[2]                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.187     ; 3.526      ;
; 7.943 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[8]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.187     ; 3.526      ;
; 7.943 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[9]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.186     ; 3.527      ;
; 7.943 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|bit_cnt[1]                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.187     ; 3.526      ;
; 7.943 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[2]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.187     ; 3.526      ;
; 7.943 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[3]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.187     ; 3.526      ;
; 7.943 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[1]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.187     ; 3.526      ;
; 7.943 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[0]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.187     ; 3.526      ;
; 7.943 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[5]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.186     ; 3.527      ;
; 7.943 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[6]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.187     ; 3.526      ;
; 7.943 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[7]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.187     ; 3.526      ;
; 7.943 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[4]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.187     ; 3.526      ;
; 7.943 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[13]         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 3.538      ;
; 7.943 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[6]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.539      ;
; 7.943 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[17]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.539      ;
; 7.943 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[13]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.185     ; 3.528      ;
; 7.943 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[16]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.539      ;
+-------+---------------------------------------+-----------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                       ;
+-------+------------------------+-------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                               ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+-------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 7.659 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[7]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.274     ; 3.600      ;
; 7.729 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[4]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.195     ; 3.616      ;
; 7.729 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[5]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.195     ; 3.616      ;
; 7.729 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.196     ; 3.615      ;
; 7.729 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[11]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.196     ; 3.615      ;
; 7.731 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[6]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.197     ; 3.612      ;
; 7.732 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[7]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.198     ; 3.610      ;
; 7.732 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[8]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.198     ; 3.610      ;
; 7.747 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[8]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.333     ; 3.452      ;
; 7.749 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[9]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.340     ; 3.443      ;
; 7.752 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[15]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.334     ; 3.446      ;
; 7.752 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[14]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.334     ; 3.446      ;
; 7.752 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[13]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.334     ; 3.446      ;
; 7.752 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[2]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.183     ; 3.605      ;
; 7.752 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[3]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.183     ; 3.605      ;
; 7.752 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[7]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.184     ; 3.604      ;
; 7.753 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[11]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.336     ; 3.443      ;
; 7.753 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[10]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.336     ; 3.443      ;
; 7.753 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[12]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.336     ; 3.443      ;
; 7.755 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[0]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 3.599      ;
; 7.755 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[1]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 3.599      ;
; 7.755 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[8]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.222     ; 3.565      ;
; 7.755 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[0]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 3.599      ;
; 7.755 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[1]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 3.599      ;
; 7.755 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 3.599      ;
; 7.757 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[9]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.229     ; 3.556      ;
; 7.760 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[13]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.223     ; 3.559      ;
; 7.760 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[14]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.223     ; 3.559      ;
; 7.760 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[15]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.223     ; 3.559      ;
; 7.761 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[10]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.225     ; 3.556      ;
; 7.761 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[11]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.225     ; 3.556      ;
; 7.761 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[12]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.225     ; 3.556      ;
; 7.764 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[5]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.315     ; 3.453      ;
; 7.766 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[3]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.314     ; 3.452      ;
; 7.767 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[6]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.325     ; 3.440      ;
; 7.768 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[4]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.333     ; 3.431      ;
; 7.770 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[2]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.322     ; 3.440      ;
; 7.770 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[0]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.322     ; 3.440      ;
; 7.770 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[1]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.322     ; 3.440      ;
; 7.772 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[5]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.204     ; 3.566      ;
; 7.774 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[3]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.565      ;
; 7.775 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[6]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.214     ; 3.553      ;
; 7.776 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[4]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.222     ; 3.544      ;
; 7.778 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[0]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.211     ; 3.553      ;
; 7.778 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[1]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.211     ; 3.553      ;
; 7.778 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[2]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.211     ; 3.553      ;
; 7.807 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.161     ; 3.687      ;
; 7.877 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.181     ; 3.597      ;
; 7.877 ; sdram_reset_ctrl_n_reg ; ram_di_reg[3]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.184     ; 3.594      ;
; 7.877 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.184     ; 3.594      ;
; 7.877 ; sdram_reset_ctrl_n_reg ; ram_di_reg[6]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.184     ; 3.594      ;
; 7.877 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.184     ; 3.594      ;
; 7.877 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.184     ; 3.594      ;
; 7.877 ; sdram_reset_ctrl_n_reg ; ram_di_reg[14]                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.184     ; 3.594      ;
; 7.877 ; sdram_reset_ctrl_n_reg ; ram_di_reg[15]                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.184     ; 3.594      ;
; 7.882 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.183     ; 3.590      ;
; 7.882 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.183     ; 3.590      ;
; 7.882 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 3.591      ;
; 7.882 ; sdram_reset_ctrl_n_reg ; ram_do_reg[19]                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 3.591      ;
; 7.882 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 3.591      ;
; 7.882 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 3.591      ;
; 7.882 ; sdram_reset_ctrl_n_reg ; ram_do_reg[25]                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 3.591      ;
; 7.882 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 3.591      ;
; 7.882 ; sdram_reset_ctrl_n_reg ; ram_do_reg[20]                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.183     ; 3.590      ;
; 7.882 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.183     ; 3.590      ;
; 7.883 ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 3.594      ;
; 7.888 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.181     ; 3.586      ;
; 7.888 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 3.589      ;
; 7.888 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 3.589      ;
; 7.888 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 3.589      ;
; 7.891 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.183     ; 3.581      ;
; 7.892 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 3.581      ;
; 7.893 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 3.580      ;
; 7.893 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 3.580      ;
; 7.893 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 3.588      ;
; 7.893 ; sdram_reset_ctrl_n_reg ; ram_do_reg[5]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 3.588      ;
; 7.893 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 3.588      ;
; 7.893 ; sdram_reset_ctrl_n_reg ; ram_do_reg[13]                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 3.588      ;
; 7.893 ; sdram_reset_ctrl_n_reg ; ram_do_reg[12]                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 3.588      ;
; 7.893 ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 3.580      ;
; 7.893 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 3.580      ;
; 7.893 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 3.580      ;
; 7.893 ; sdram_reset_ctrl_n_reg ; ram_do_reg[10]                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 3.588      ;
; 7.893 ; sdram_reset_ctrl_n_reg ; ram_do_reg[9]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 3.588      ;
; 7.893 ; sdram_reset_ctrl_n_reg ; ram_do_reg[8]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 3.588      ;
; 7.977 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.195     ; 3.368      ;
; 8.000 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.184     ; 3.356      ;
; 8.000 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.184     ; 3.356      ;
; 8.000 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.184     ; 3.356      ;
; 8.000 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.184     ; 3.356      ;
; 8.000 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.184     ; 3.356      ;
; 8.259 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.165     ; 3.231      ;
; 8.259 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.165     ; 3.231      ;
; 8.259 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.165     ; 3.231      ;
; 8.262 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.180     ; 3.213      ;
; 8.262 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.180     ; 3.213      ;
; 8.262 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.180     ; 3.213      ;
; 8.262 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.180     ; 3.213      ;
; 8.262 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.180     ; 3.213      ;
; 8.262 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.180     ; 3.213      ;
+-------+------------------------+-------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                      ;
+--------+--------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                            ; To Node                               ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 12.988 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.200     ; 4.341      ;
; 12.988 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.200     ; 4.341      ;
; 12.988 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.200     ; 4.341      ;
; 12.988 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.200     ; 4.341      ;
; 12.988 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.200     ; 4.341      ;
; 12.988 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.200     ; 4.341      ;
; 12.988 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.200     ; 4.341      ;
; 12.988 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.200     ; 4.341      ;
; 13.000 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.196     ; 4.333      ;
; 13.000 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.196     ; 4.333      ;
; 13.000 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.196     ; 4.333      ;
; 13.000 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.196     ; 4.333      ;
; 13.000 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.196     ; 4.333      ;
; 13.000 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.196     ; 4.333      ;
+--------+--------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: 'FPGA_CLK'                                                                                                                                                                                                                                                                                ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                            ; To Node                                                                     ; Launch Clock                                                                        ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.360 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.106      ; 4.098      ;
; -0.359 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.104      ; 4.097      ;
; -0.359 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.104      ; 4.097      ;
; -0.359 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.104      ; 4.097      ;
; -0.359 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.104      ; 4.097      ;
; -0.359 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.104      ; 4.097      ;
; -0.359 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.104      ; 4.097      ;
; -0.359 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.104      ; 4.097      ;
; -0.359 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.104      ; 4.097      ;
; -0.359 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.104      ; 4.097      ;
; -0.359 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.104      ; 4.097      ;
; -0.359 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.104      ; 4.097      ;
; -0.359 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.104      ; 4.097      ;
; -0.359 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.104      ; 4.097      ;
; -0.343 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.107      ; 4.116      ;
; -0.343 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.107      ; 4.116      ;
; -0.343 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.107      ; 4.116      ;
; -0.343 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.107      ; 4.116      ;
; -0.343 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.107      ; 4.116      ;
; -0.343 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.107      ; 4.116      ;
; -0.343 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.107      ; 4.116      ;
; -0.343 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.107      ; 4.116      ;
; -0.343 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.107      ; 4.116      ;
; -0.343 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.107      ; 4.116      ;
; -0.343 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.107      ; 4.116      ;
; -0.343 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.107      ; 4.116      ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                          ;
+-------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                            ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; 0.482 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.411      ; 3.187      ;
; 0.482 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.411      ; 3.187      ;
; 0.482 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.411      ; 3.187      ;
; 0.482 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.411      ; 3.187      ;
; 0.482 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.411      ; 3.187      ;
; 0.482 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.411      ; 3.187      ;
; 0.482 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.411      ; 3.187      ;
; 0.482 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.411      ; 3.187      ;
; 0.482 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.411      ; 3.187      ;
; 0.491 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.410      ; 3.312      ;
; 0.491 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.410      ; 3.312      ;
; 0.491 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.410      ; 3.312      ;
; 0.491 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.410      ; 3.312      ;
; 0.491 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.410      ; 3.312      ;
; 0.491 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.410      ; 3.312      ;
; 0.491 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.410      ; 3.312      ;
; 0.491 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.410      ; 3.312      ;
; 0.491 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.410      ; 3.312      ;
+-------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                         ; To Node                                                                                                                                                                                                               ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 1.744 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a47 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.346      ; 2.276      ;
; 1.744 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a46 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.346      ; 2.276      ;
; 1.744 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a45 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.346      ; 2.276      ;
; 1.744 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a44 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.346      ; 2.276      ;
; 1.744 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a43 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.346      ; 2.276      ;
; 1.744 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a42 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.346      ; 2.276      ;
; 1.744 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a41 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.346      ; 2.276      ;
; 1.744 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a40 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.346      ; 2.276      ;
; 1.744 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a35 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.346      ; 2.276      ;
; 1.744 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a34 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.346      ; 2.276      ;
; 1.744 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a33 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.346      ; 2.276      ;
; 1.744 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a32 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.346      ; 2.276      ;
; 1.744 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a15 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.346      ; 2.276      ;
; 1.744 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a14 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.346      ; 2.276      ;
; 1.744 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a13 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.346      ; 2.276      ;
; 1.744 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a12 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.346      ; 2.276      ;
; 1.744 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a11 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.346      ; 2.276      ;
; 1.744 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a10 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.346      ; 2.276      ;
; 1.744 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a9  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.346      ; 2.276      ;
; 1.744 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a8  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.346      ; 2.276      ;
; 1.744 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a7  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.346      ; 2.276      ;
; 1.744 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a6  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.346      ; 2.276      ;
; 1.744 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a5  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.346      ; 2.276      ;
; 1.744 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a4  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.346      ; 2.276      ;
; 1.744 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a3  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.346      ; 2.276      ;
; 1.744 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a2  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.346      ; 2.276      ;
; 1.744 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a1  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.346      ; 2.276      ;
; 1.744 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.346      ; 2.276      ;
; 2.059 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a63 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.590      ;
; 2.059 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a62 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.590      ;
; 2.059 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a61 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.590      ;
; 2.059 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a60 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.590      ;
; 2.059 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a59 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.590      ;
; 2.059 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a58 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.590      ;
; 2.059 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a57 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.590      ;
; 2.059 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a56 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.590      ;
; 2.059 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a55 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.590      ;
; 2.059 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a54 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.590      ;
; 2.059 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a53 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.590      ;
; 2.059 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a52 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.590      ;
; 2.059 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a51 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.590      ;
; 2.059 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a50 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.590      ;
; 2.059 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a49 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.590      ;
; 2.059 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a48 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.590      ;
; 2.059 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a39 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.590      ;
; 2.059 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a38 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.590      ;
; 2.059 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a37 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.590      ;
; 2.059 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a36 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.590      ;
; 2.059 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a31 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.590      ;
; 2.059 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a30 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.590      ;
; 2.059 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a29 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.590      ;
; 2.059 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a28 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.590      ;
; 2.059 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a27 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.590      ;
; 2.059 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a26 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.590      ;
; 2.059 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a25 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.590      ;
; 2.059 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a24 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.590      ;
; 2.059 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a23 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.590      ;
; 2.059 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a22 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.590      ;
; 2.059 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a21 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.590      ;
; 2.059 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a20 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.590      ;
; 2.059 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a19 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.590      ;
; 2.059 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a18 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.590      ;
; 2.059 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a17 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.590      ;
; 2.059 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.590      ;
; 2.414 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[3]                                                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.582      ; 3.182      ;
; 2.414 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[1]                                                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.582      ; 3.182      ;
; 2.429 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[3]                                                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.581      ; 3.307      ;
; 2.429 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[1]                                                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.581      ; 3.307      ;
; 2.806 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[26]                                                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.172      ; 3.164      ;
; 2.806 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[29]                                                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.172      ; 3.164      ;
; 2.806 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[10]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 3.166      ;
; 2.806 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[20]                                                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.172      ; 3.164      ;
; 2.806 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[28]                                                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.172      ; 3.164      ;
; 2.807 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[30]                                                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.172      ; 3.165      ;
; 2.807 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[27]                                                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.173      ; 3.166      ;
; 2.807 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[31]                                                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.173      ; 3.166      ;
; 2.807 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[19]                                                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.173      ; 3.166      ;
; 2.807 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[24]                                                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.173      ; 3.166      ;
; 2.807 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[21]                                                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.172      ; 3.165      ;
; 2.807 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[23]                                                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.172      ; 3.165      ;
; 2.807 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[18]                                                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.172      ; 3.165      ;
; 2.807 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[15]                                                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 3.169      ;
; 2.807 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[22]                                                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.173      ; 3.166      ;
; 2.807 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[17]                                                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 3.169      ;
; 2.807 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[25]                                                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.173      ; 3.166      ;
; 2.807 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[16]                                                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.173      ; 3.166      ;
; 2.809 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[2]                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 3.175      ;
; 2.809 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[0]                                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 3.176      ;
; 2.809 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[1]                                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 3.175      ;
; 2.809 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[6]                                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 3.176      ;
; 2.809 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[7]                                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 3.176      ;
; 2.809 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[10]                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 3.175      ;
; 2.809 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[11]                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 3.175      ;
; 2.809 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[13]                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 3.176      ;
; 2.809 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[27]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 3.175      ;
; 2.809 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[31]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 3.176      ;
; 2.809 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[19]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 3.175      ;
; 2.809 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[19]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 3.175      ;
; 2.809 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[19]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 3.176      ;
; 2.809 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[19]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 3.176      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                            ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 2.565 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.164      ; 3.024      ;
; 2.566 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 3.029      ;
; 2.566 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 3.032      ;
; 2.566 ; sdram_reset_ctrl_n_reg ; ram_do_reg[15]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 3.029      ;
; 2.566 ; sdram_reset_ctrl_n_reg ; ram_do_reg[14]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 3.029      ;
; 2.566 ; sdram_reset_ctrl_n_reg ; ram_do_reg[11]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 3.029      ;
; 2.567 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 3.033      ;
; 2.567 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 3.033      ;
; 2.567 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 3.033      ;
; 2.567 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 3.033      ;
; 2.567 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 3.033      ;
; 2.567 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 3.033      ;
; 2.567 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 3.033      ;
; 2.567 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 3.033      ;
; 2.567 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 3.033      ;
; 2.567 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 3.033      ;
; 2.567 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 3.033      ;
; 2.567 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 3.033      ;
; 2.567 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 3.033      ;
; 2.567 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 3.033      ;
; 2.567 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 3.033      ;
; 2.567 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.160      ; 3.022      ;
; 2.567 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 3.033      ;
; 2.569 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 3.041      ;
; 2.569 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 3.041      ;
; 2.569 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 3.041      ;
; 2.570 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 3.027      ;
; 2.570 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 3.027      ;
; 2.570 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 3.027      ;
; 2.570 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.163      ; 3.028      ;
; 2.570 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.163      ; 3.028      ;
; 2.570 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.163      ; 3.028      ;
; 2.570 ; sdram_reset_ctrl_n_reg ; seq_reg[5]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.163      ; 3.028      ;
; 2.570 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 3.027      ;
; 2.570 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 3.027      ;
; 2.570 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 3.027      ;
; 2.570 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 3.027      ;
; 2.570 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 3.027      ;
; 2.570 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.163      ; 3.028      ;
; 2.570 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.163      ; 3.028      ;
; 2.570 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.163      ; 3.028      ;
; 2.570 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.163      ; 3.028      ;
; 2.570 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.163      ; 3.028      ;
; 2.570 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.163      ; 3.028      ;
; 2.570 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.163      ; 3.028      ;
; 2.570 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.163      ; 3.028      ;
; 2.570 ; sdram_reset_ctrl_n_reg ; ram_di_reg[5]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.163      ; 3.028      ;
; 2.571 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.160      ; 3.026      ;
; 2.571 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.160      ; 3.026      ;
; 2.571 ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.160      ; 3.026      ;
; 2.571 ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.160      ; 3.026      ;
; 2.571 ; sdram_reset_ctrl_n_reg ; ram_di_reg[11]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.160      ; 3.026      ;
; 2.571 ; sdram_reset_ctrl_n_reg ; ram_di_reg[12]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.160      ; 3.026      ;
; 2.571 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[1]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.160      ; 3.026      ;
; 2.571 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[0]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.160      ; 3.026      ;
; 2.820 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.138      ; 3.177      ;
; 2.820 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.138      ; 3.177      ;
; 2.820 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.138      ; 3.177      ;
; 2.820 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.138      ; 3.177      ;
; 2.820 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.138      ; 3.177      ;
; 2.843 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.127      ; 3.189      ;
; 2.932 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 3.395      ;
; 2.932 ; sdram_reset_ctrl_n_reg ; ram_do_reg[5]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 3.395      ;
; 2.932 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 3.395      ;
; 2.932 ; sdram_reset_ctrl_n_reg ; ram_do_reg[13]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 3.395      ;
; 2.932 ; sdram_reset_ctrl_n_reg ; ram_do_reg[12]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 3.395      ;
; 2.932 ; sdram_reset_ctrl_n_reg ; ram_do_reg[10]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 3.395      ;
; 2.932 ; sdram_reset_ctrl_n_reg ; ram_do_reg[9]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 3.395      ;
; 2.932 ; sdram_reset_ctrl_n_reg ; ram_do_reg[8]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 3.395      ;
; 2.934 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 3.388      ;
; 2.934 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 3.388      ;
; 2.934 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 3.388      ;
; 2.934 ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 3.388      ;
; 2.934 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 3.388      ;
; 2.934 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 3.388      ;
; 2.934 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.160      ; 3.389      ;
; 2.938 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.160      ; 3.393      ;
; 2.938 ; sdram_reset_ctrl_n_reg ; ram_do_reg[19]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.160      ; 3.393      ;
; 2.938 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.160      ; 3.393      ;
; 2.938 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.160      ; 3.393      ;
; 2.938 ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.163      ; 3.396      ;
; 2.938 ; sdram_reset_ctrl_n_reg ; ram_do_reg[25]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.160      ; 3.393      ;
; 2.938 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.160      ; 3.393      ;
; 2.938 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.163      ; 3.396      ;
; 2.938 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.163      ; 3.396      ;
; 2.938 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.163      ; 3.396      ;
; 2.939 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 3.392      ;
; 2.939 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 3.392      ;
; 2.939 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.160      ; 3.394      ;
; 2.939 ; sdram_reset_ctrl_n_reg ; ram_do_reg[20]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 3.392      ;
; 2.939 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 3.392      ;
; 2.943 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.161      ; 3.399      ;
; 2.944 ; sdram_reset_ctrl_n_reg ; ram_di_reg[3]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 3.397      ;
; 2.944 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 3.397      ;
; 2.944 ; sdram_reset_ctrl_n_reg ; ram_di_reg[6]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 3.397      ;
; 2.944 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 3.397      ;
; 2.944 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 3.397      ;
; 2.944 ; sdram_reset_ctrl_n_reg ; ram_di_reg[14]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 3.397      ;
; 2.944 ; sdram_reset_ctrl_n_reg ; ram_di_reg[15]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 3.397      ;
; 2.998 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.181      ; 3.474      ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                      ;
+-------+--------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                            ; To Node                               ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 3.656 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.145      ; 4.097      ;
; 3.656 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.145      ; 4.097      ;
; 3.656 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.145      ; 4.097      ;
; 3.656 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.145      ; 4.097      ;
; 3.656 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.145      ; 4.097      ;
; 3.656 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.145      ; 4.097      ;
; 3.673 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.141      ; 4.110      ;
; 3.673 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.141      ; 4.110      ;
; 3.673 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.141      ; 4.110      ;
; 3.673 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.141      ; 4.110      ;
; 3.673 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.141      ; 4.110      ;
; 3.673 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.141      ; 4.110      ;
; 3.673 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.141      ; 4.110      ;
; 3.673 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.141      ; 4.110      ;
+-------+--------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                        ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                               ; Clock Edge ; Target                                                    ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; 5.595 ; 5.815        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[0]                                             ;
; 5.595 ; 5.815        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[13]                                            ;
; 5.595 ; 5.815        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[14]                                            ;
; 5.595 ; 5.815        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[15]                                            ;
; 5.595 ; 5.815        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[1]                                             ;
; 5.595 ; 5.815        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[2]                                             ;
; 5.595 ; 5.815        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[3]                                             ;
; 5.595 ; 5.815        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[4]                                             ;
; 5.595 ; 5.815        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[5]                                             ;
; 5.595 ; 5.815        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[6]                                             ;
; 5.595 ; 5.815        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[7]                                             ;
; 5.595 ; 5.815        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[17]                                            ;
; 5.595 ; 5.815        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ;
; 5.595 ; 5.815        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ;
; 5.595 ; 5.815        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel[0]                     ;
; 5.595 ; 5.815        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ;
; 5.595 ; 5.815        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_act                      ;
; 5.595 ; 5.815        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ;
; 5.595 ; 5.815        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_act                    ;
; 5.595 ; 5.815        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_req                    ;
; 5.595 ; 5.815        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_act                      ;
; 5.595 ; 5.815        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_complete_reg                                ;
; 5.595 ; 5.815        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_reg                                         ;
; 5.595 ; 5.815        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[2]                                                ;
; 5.595 ; 5.815        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[3]                                                ;
; 5.595 ; 5.815        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[4]                                                ;
; 5.595 ; 5.815        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[5]                                                ;
; 5.596 ; 5.816        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[0]                                           ;
; 5.596 ; 5.816        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[1]                                           ;
; 5.596 ; 5.816        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[10]                                            ;
; 5.596 ; 5.816        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[11]                                            ;
; 5.596 ; 5.816        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[12]                                            ;
; 5.596 ; 5.816        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[8]                                             ;
; 5.596 ; 5.816        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[9]                                             ;
; 5.596 ; 5.816        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[0]                                             ;
; 5.596 ; 5.816        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[10]                                            ;
; 5.596 ; 5.816        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[11]                                            ;
; 5.596 ; 5.816        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[12]                                            ;
; 5.596 ; 5.816        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[13]                                            ;
; 5.596 ; 5.816        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[14]                                            ;
; 5.596 ; 5.816        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[15]                                            ;
; 5.596 ; 5.816        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[16]                                            ;
; 5.596 ; 5.816        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[18]                                            ;
; 5.596 ; 5.816        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[19]                                            ;
; 5.596 ; 5.816        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[20]                                            ;
; 5.596 ; 5.816        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[21]                                            ;
; 5.596 ; 5.816        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[22]                                            ;
; 5.596 ; 5.816        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[23]                                            ;
; 5.596 ; 5.816        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[24]                                            ;
; 5.596 ; 5.816        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[25]                                            ;
; 5.596 ; 5.816        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[26]                                            ;
; 5.596 ; 5.816        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[27]                                            ;
; 5.596 ; 5.816        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[28]                                            ;
; 5.596 ; 5.816        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[29]                                            ;
; 5.596 ; 5.816        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[30]                                            ;
; 5.596 ; 5.816        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[31]                                            ;
; 5.596 ; 5.816        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[3]                                             ;
; 5.596 ; 5.816        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[4]                                             ;
; 5.596 ; 5.816        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[5]                                             ;
; 5.596 ; 5.816        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[8]                                             ;
; 5.596 ; 5.816        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[9]                                             ;
; 5.596 ; 5.816        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ;
; 5.596 ; 5.816        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[0]                                                ;
; 5.596 ; 5.816        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[10]                                               ;
; 5.596 ; 5.816        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[11]                                               ;
; 5.596 ; 5.816        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[1]                                                ;
; 5.596 ; 5.816        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[6]                                                ;
; 5.596 ; 5.816        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[7]                                                ;
; 5.596 ; 5.816        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[8]                                                ;
; 5.596 ; 5.816        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[9]                                                ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[1]                                             ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[2]                                             ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|sdram_rdy                     ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[6]                                             ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ;
; 5.601 ; 5.821        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_reg                      ;
; 5.601 ; 5.821        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ;
; 5.601 ; 5.821        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_reg                      ;
; 5.602 ; 5.822        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[7]                                             ;
; 5.652 ; 5.810        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[3]                   ;
; 5.653 ; 5.811        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[5]                   ;
; 5.656 ; 5.814        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[0]                   ;
; 5.656 ; 5.814        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[1]                   ;
; 5.656 ; 5.814        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[2]                   ;
; 5.656 ; 5.814        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[6]                   ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                  ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                               ; Clock Edge ; Target                                                                                                                                              ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; 5.720 ; 5.850        ; 0.130          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 5.785 ; 5.896        ; 0.111          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 5.850 ; 5.850        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 5.896 ; 5.896        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                   ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                               ; Clock Edge ; Target                                                                                                                                              ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; 8.534  ; 8.754        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[2]                                                                                                               ;
; 8.534  ; 8.754        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[3]                                                                                                               ;
; 8.534  ; 8.754        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[4]                                                                                                               ;
; 8.534  ; 8.754        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[5]                                                                                                               ;
; 8.534  ; 8.754        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[6]                                                                                                               ;
; 8.534  ; 8.754        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[7]                                                                                                               ;
; 8.535  ; 8.755        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ;
; 8.535  ; 8.755        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ;
; 8.535  ; 8.755        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ;
; 8.535  ; 8.755        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ;
; 8.535  ; 8.755        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ;
; 8.535  ; 8.755        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ;
; 8.535  ; 8.755        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ;
; 8.535  ; 8.755        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ;
; 8.657  ; 8.787        ; 0.130          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 8.678  ; 8.866        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ;
; 8.678  ; 8.866        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ;
; 8.678  ; 8.866        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ;
; 8.678  ; 8.866        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ;
; 8.678  ; 8.866        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ;
; 8.678  ; 8.866        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ;
; 8.678  ; 8.866        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ;
; 8.678  ; 8.866        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ;
; 8.679  ; 8.867        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[2]                                                                                                               ;
; 8.679  ; 8.867        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[3]                                                                                                               ;
; 8.679  ; 8.867        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[4]                                                                                                               ;
; 8.679  ; 8.867        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[5]                                                                                                               ;
; 8.679  ; 8.867        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[6]                                                                                                               ;
; 8.679  ; 8.867        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[7]                                                                                                               ;
; 8.722  ; 8.833        ; 0.111          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 8.787  ; 8.787        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 8.787  ; 8.787        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|outclk                                                 ;
; 8.789  ; 8.789        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[2]|clk                                                                                                                       ;
; 8.789  ; 8.789        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[3]|clk                                                                                                                       ;
; 8.789  ; 8.789        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[4]|clk                                                                                                                       ;
; 8.789  ; 8.789        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[5]|clk                                                                                                                       ;
; 8.789  ; 8.789        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[6]|clk                                                                                                                       ;
; 8.789  ; 8.789        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[7]|clk                                                                                                                       ;
; 8.790  ; 8.790        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[0]|clk                                                                                                                              ;
; 8.790  ; 8.790        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[1]|clk                                                                                                                              ;
; 8.790  ; 8.790        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[2]|clk                                                                                                                              ;
; 8.790  ; 8.790        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[3]|clk                                                                                                                              ;
; 8.790  ; 8.790        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[4]|clk                                                                                                                              ;
; 8.790  ; 8.790        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[5]|clk                                                                                                                              ;
; 8.790  ; 8.790        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[6]|clk                                                                                                                              ;
; 8.790  ; 8.790        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[7]|clk                                                                                                                              ;
; 8.830  ; 8.830        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[0]|clk                                                                                                                              ;
; 8.830  ; 8.830        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[1]|clk                                                                                                                              ;
; 8.830  ; 8.830        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[2]|clk                                                                                                                              ;
; 8.830  ; 8.830        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[3]|clk                                                                                                                              ;
; 8.830  ; 8.830        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[4]|clk                                                                                                                              ;
; 8.830  ; 8.830        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[5]|clk                                                                                                                              ;
; 8.830  ; 8.830        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[6]|clk                                                                                                                              ;
; 8.830  ; 8.830        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[7]|clk                                                                                                                              ;
; 8.831  ; 8.831        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[2]|clk                                                                                                                       ;
; 8.831  ; 8.831        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[3]|clk                                                                                                                       ;
; 8.831  ; 8.831        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[4]|clk                                                                                                                       ;
; 8.831  ; 8.831        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[5]|clk                                                                                                                       ;
; 8.831  ; 8.831        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[6]|clk                                                                                                                       ;
; 8.831  ; 8.831        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[7]|clk                                                                                                                       ;
; 8.833  ; 8.833        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 8.833  ; 8.833        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|outclk                                                 ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[2]                                                                                                               ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[3]                                                                                                               ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[4]                                                                                                               ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[5]                                                                                                               ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[6]                                                                                                               ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[7]                                                                                                               ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                               ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                               ; Clock Edge ; Target                                                                                                                                                                                                          ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 9.381  ; 10.411       ; 1.030          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                     ;
; 9.391  ; 10.421       ; 1.030          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                     ;
; 10.139 ; 10.359       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[0]                                            ;
; 10.139 ; 10.359       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[1]                                            ;
; 10.139 ; 10.359       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[2]                                            ;
; 10.139 ; 10.359       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[3]                                            ;
; 10.139 ; 10.359       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[4]                                            ;
; 10.139 ; 10.359       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[5]                                            ;
; 10.139 ; 10.359       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[7]                                            ;
; 10.139 ; 10.359       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[0]                                    ;
; 10.139 ; 10.359       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[1]                                    ;
; 10.140 ; 10.360       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[3]                                                                ;
; 10.140 ; 10.360       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[4]                                                                ;
; 10.140 ; 10.360       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[5]                                                                ;
; 10.140 ; 10.360       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[6]                                                                ;
; 10.140 ; 10.360       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[7]                                                                ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[4]                                         ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[6]                                         ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[0]                                         ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[1]                                         ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[2]                                         ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[3]                                         ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[4]                                         ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[5]                                         ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[6]                                         ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[7]                                         ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[0]                                      ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[1]                                      ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[2]                                      ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[3]                                      ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[4]                                      ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[5]                                      ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[6]                                      ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[7]                                      ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|rxStatusMonitor:u_rxStatusMonitor|connectionEventOut                       ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|rxStatusMonitor:u_rxStatusMonitor|oldConnectState[0]                       ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|rxStatusMonitor:u_rxStatusMonitor|oldConnectState[1]                       ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[0]               ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[1]               ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[2]               ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]               ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[4]               ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[5]               ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[6]               ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[7]               ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[0]              ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[1]              ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010000 ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010111 ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011111 ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101111 ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireCtrl            ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireWEn             ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg2     ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireEdgeDetect     ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[0]    ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[1]    ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[0]       ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[1]       ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[2]       ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[3]       ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[4]       ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[5]       ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[6]       ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[7]       ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                              ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.110                              ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[0]                                             ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[1]                                             ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[2]                                             ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[3]                                             ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[4]                                             ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[5]                                             ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[6]                                             ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[7]                                             ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                             ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync                                ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg[1]                           ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg[2]                           ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg[3]                           ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]                      ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]                      ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[2]                      ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[3]                      ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00100                             ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00111                             ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01010                             ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01011                             ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10001                             ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10010                             ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[0]       ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[1]       ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[2]       ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[3]       ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[4]       ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[5]       ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[6]       ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[7]       ;
; 10.143 ; 10.363       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[0]                                            ;
; 10.143 ; 10.363       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[1]                                            ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                  ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                               ; Clock Edge ; Target                                                                                                                                                                                             ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 17.258 ; 17.609       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[0]                                          ;
; 17.258 ; 17.609       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[1]                                          ;
; 17.258 ; 17.609       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[2]                                          ;
; 17.258 ; 17.609       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[3]                                          ;
; 17.258 ; 17.609       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[4]                                          ;
; 17.258 ; 17.609       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[10]                                               ;
; 17.258 ; 17.609       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[11]                                               ;
; 17.258 ; 17.609       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[12]                                               ;
; 17.258 ; 17.609       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[13]                                               ;
; 17.258 ; 17.609       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[14]                                               ;
; 17.258 ; 17.609       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[15]                                               ;
; 17.258 ; 17.609       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[16]                                               ;
; 17.258 ; 17.609       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[17]                                               ;
; 17.258 ; 17.609       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[18]                                               ;
; 17.258 ; 17.609       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[19]                                               ;
; 17.258 ; 17.609       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[20]                                               ;
; 17.258 ; 17.609       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[5]                                                ;
; 17.258 ; 17.609       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[6]                                                ;
; 17.258 ; 17.609       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[7]                                                ;
; 17.258 ; 17.609       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[8]                                                ;
; 17.258 ; 17.609       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[9]                                                ;
; 17.262 ; 17.613       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[0]                                          ;
; 17.262 ; 17.613       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[1]                                          ;
; 17.262 ; 17.613       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[2]                                          ;
; 17.262 ; 17.613       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[3]                                          ;
; 17.262 ; 17.613       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[4]                                          ;
; 17.262 ; 17.613       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[10]                                               ;
; 17.262 ; 17.613       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[11]                                               ;
; 17.262 ; 17.613       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[12]                                               ;
; 17.262 ; 17.613       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[13]                                               ;
; 17.262 ; 17.613       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[14]                                               ;
; 17.262 ; 17.613       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[15]                                               ;
; 17.262 ; 17.613       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[16]                                               ;
; 17.262 ; 17.613       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[17]                                               ;
; 17.262 ; 17.613       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[18]                                               ;
; 17.262 ; 17.613       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[19]                                               ;
; 17.262 ; 17.613       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[20]                                               ;
; 17.262 ; 17.613       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[5]                                                ;
; 17.262 ; 17.613       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[6]                                                ;
; 17.262 ; 17.613       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[7]                                                ;
; 17.262 ; 17.613       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[8]                                                ;
; 17.262 ; 17.613       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[9]                                                ;
; 17.337 ; 17.557       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[2]                                                                                                          ;
; 17.342 ; 17.562       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                  ;
; 17.342 ; 17.562       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                  ;
; 17.342 ; 17.562       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                  ;
; 17.342 ; 17.562       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                  ;
; 17.342 ; 17.562       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                  ;
; 17.342 ; 17.562       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                  ;
; 17.342 ; 17.562       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                  ;
; 17.342 ; 17.562       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[8]            ;
; 17.342 ; 17.562       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[9]            ;
; 17.342 ; 17.562       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[14]      ;
; 17.342 ; 17.562       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[15]      ;
; 17.342 ; 17.562       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[8]       ;
; 17.342 ; 17.562       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[9]       ;
; 17.342 ; 17.562       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB[0]      ;
; 17.342 ; 17.562       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB[1]      ;
; 17.342 ; 17.562       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[0] ;
; 17.342 ; 17.562       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[1] ;
; 17.343 ; 17.563       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[13]           ;
; 17.343 ; 17.563       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[8]            ;
; 17.343 ; 17.563       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[11]      ;
; 17.343 ; 17.563       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[13]      ;
; 17.343 ; 17.563       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[8]       ;
; 17.343 ; 17.563       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB[0]      ;
; 17.343 ; 17.563       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[0] ;
; 17.343 ; 17.563       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[1] ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Nreg                                                                                   ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[0]                                                                                   ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[4]                                                                                   ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Y[0]                                                                                   ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Y[4]                                                                                   ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Zreg                                                                                   ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|VOLUME_OUT_L_REG[12]                                                                      ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|VOLUME_OUT_L_REG[13]                                                                      ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|VOLUME_OUT_L_REG[14]                                                                      ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|VOLUME_OUT_L_REG[7]                                                                       ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|VOLUME_OUT_L_REG[9]                                                                       ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|simple_low_pass_filter:filter_left|accum2_reg[10]                                         ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|simple_low_pass_filter:filter_left|accum2_reg[11]                                         ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|simple_low_pass_filter:filter_left|accum2_reg[12]                                         ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|simple_low_pass_filter:filter_left|accum2_reg[13]                                         ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|simple_low_pass_filter:filter_left|accum2_reg[14]                                         ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|simple_low_pass_filter:filter_left|accum2_reg[15]                                         ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|simple_low_pass_filter:filter_left|accum2_reg[16]                                         ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|simple_low_pass_filter:filter_left|accum2_reg[17]                                         ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|simple_low_pass_filter:filter_left|accum2_reg[18]                                         ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|simple_low_pass_filter:filter_left|accum2_reg[19]                                         ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|simple_low_pass_filter:filter_left|accum2_reg[20]                                         ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|simple_low_pass_filter:filter_left|accum_reg[10]                                          ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|simple_low_pass_filter:filter_left|accum_reg[11]                                          ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|simple_low_pass_filter:filter_left|accum_reg[12]                                          ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|simple_low_pass_filter:filter_left|accum_reg[13]                                          ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|simple_low_pass_filter:filter_left|accum_reg[14]                                          ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|simple_low_pass_filter:filter_left|accum_reg[15]                                          ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|simple_low_pass_filter:filter_left|accum_reg[16]                                          ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|simple_low_pass_filter:filter_left|accum_reg[17]                                          ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|simple_low_pass_filter:filter_left|accum_reg[18]                                          ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|simple_low_pass_filter:filter_left|accum_reg[19]                                          ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                        ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                              ; Clock Edge ; Target                                                                                                   ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------+
; 17.595 ; 17.595       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.595 ; 17.595       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.595 ; 17.595       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.595 ; 17.595       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]                      ;
; 17.595 ; 17.595       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 17.599 ; 17.599       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.599 ; 17.599       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.604 ; 17.604       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.638 ; 17.638       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.642 ; 17.642       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.642 ; 17.642       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.646 ; 17.646       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.646 ; 17.646       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.646 ; 17.646       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.646 ; 17.646       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]                      ;
; 17.646 ; 17.646       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'FPGA_CLK'                                                                                                                             ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------------+
; Slack   ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                                                       ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------------+
; 89.530  ; 99.833       ; 10.303         ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout        ;
; 89.864  ; 100.167      ; 10.303         ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout        ;
; 99.680  ; 99.868       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                                   ;
; 99.680  ; 99.868       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                                  ;
; 99.680  ; 99.868       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                                  ;
; 99.680  ; 99.868       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                                  ;
; 99.680  ; 99.868       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                                  ;
; 99.680  ; 99.868       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                                  ;
; 99.680  ; 99.868       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                                  ;
; 99.680  ; 99.868       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                                  ;
; 99.680  ; 99.868       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                                  ;
; 99.680  ; 99.868       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                                  ;
; 99.680  ; 99.868       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                                  ;
; 99.680  ; 99.868       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                                   ;
; 99.680  ; 99.868       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                                  ;
; 99.680  ; 99.868       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                                  ;
; 99.680  ; 99.868       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                                  ;
; 99.680  ; 99.868       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                                  ;
; 99.680  ; 99.868       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                                  ;
; 99.680  ; 99.868       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                                   ;
; 99.680  ; 99.868       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                                   ;
; 99.680  ; 99.868       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                                   ;
; 99.680  ; 99.868       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                                   ;
; 99.680  ; 99.868       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                                   ;
; 99.680  ; 99.868       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                                   ;
; 99.680  ; 99.868       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                                   ;
; 99.680  ; 99.868       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                                   ;
; 99.680  ; 99.868       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8                  ;
; 99.680  ; 99.868       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]              ;
; 99.680  ; 99.868       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1]              ;
; 99.680  ; 99.868       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]              ;
; 99.796  ; 99.796       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 99.796  ; 99.796       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 99.798  ; 99.798       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                          ;
; 99.798  ; 99.798       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|observablevcoout                                ;
; 99.818  ; 99.818       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                             ;
; 99.833  ; 99.833       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[0]|clk                                        ;
; 99.833  ; 99.833       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[1]|clk                                        ;
; 99.833  ; 99.833       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[2]|clk                                        ;
; 99.833  ; 99.833       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[0]|clk                                                ;
; 99.833  ; 99.833       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[10]|clk                                               ;
; 99.833  ; 99.833       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[11]|clk                                               ;
; 99.833  ; 99.833       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[12]|clk                                               ;
; 99.833  ; 99.833       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[13]|clk                                               ;
; 99.833  ; 99.833       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[14]|clk                                               ;
; 99.833  ; 99.833       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[15]|clk                                               ;
; 99.833  ; 99.833       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[16]|clk                                               ;
; 99.833  ; 99.833       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[17]|clk                                               ;
; 99.833  ; 99.833       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[18]|clk                                               ;
; 99.833  ; 99.833       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[19]|clk                                               ;
; 99.833  ; 99.833       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[1]|clk                                                ;
; 99.833  ; 99.833       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[20]|clk                                               ;
; 99.833  ; 99.833       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[21]|clk                                               ;
; 99.833  ; 99.833       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[22]|clk                                               ;
; 99.833  ; 99.833       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[23]|clk                                               ;
; 99.833  ; 99.833       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[24]|clk                                               ;
; 99.833  ; 99.833       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[2]|clk                                                ;
; 99.833  ; 99.833       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[3]|clk                                                ;
; 99.833  ; 99.833       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[4]|clk                                                ;
; 99.833  ; 99.833       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[5]|clk                                                ;
; 99.833  ; 99.833       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[6]|clk                                                ;
; 99.833  ; 99.833       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[7]|clk                                                ;
; 99.833  ; 99.833       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[8]|clk                                                ;
; 99.833  ; 99.833       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[9]|clk                                                ;
; 99.833  ; 99.833       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|remote|dffe8|clk                                                         ;
; 99.833  ; 99.833       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|remote|sd4|clk                                                           ;
; 99.834  ; 99.834       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~inputclkctrl|inclk[0]                                                               ;
; 99.834  ; 99.834       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~inputclkctrl|outclk                                                                 ;
; 99.850  ; 99.850       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 99.852  ; 99.852       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|inclk[0]                                        ;
; 99.910  ; 100.130      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                                  ;
; 99.910  ; 100.130      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                                  ;
; 99.910  ; 100.130      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                                  ;
; 99.910  ; 100.130      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                                  ;
; 99.910  ; 100.130      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                                  ;
; 99.910  ; 100.130      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                                  ;
; 99.910  ; 100.130      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                                  ;
; 99.910  ; 100.130      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                                  ;
; 99.910  ; 100.130      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                                  ;
; 99.910  ; 100.130      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                                  ;
; 99.910  ; 100.130      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                                  ;
; 99.910  ; 100.130      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                                  ;
; 99.910  ; 100.130      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                                  ;
; 99.911  ; 100.131      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                                   ;
; 99.911  ; 100.131      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                                  ;
; 99.911  ; 100.131      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                                  ;
; 99.911  ; 100.131      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                                   ;
; 99.911  ; 100.131      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                                   ;
; 99.911  ; 100.131      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                                   ;
; 99.911  ; 100.131      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                                   ;
; 99.911  ; 100.131      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                                   ;
; 99.911  ; 100.131      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                                   ;
; 99.911  ; 100.131      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                                   ;
; 99.911  ; 100.131      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                                   ;
; 99.911  ; 100.131      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                                   ;
; 99.911  ; 100.131      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8                  ;
; 99.911  ; 100.131      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]              ;
; 99.911  ; 100.131      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1]              ;
; 99.911  ; 100.131      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]              ;
; 100.000 ; 100.000      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                             ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                                   ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.771 ; 2.950 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.753 ; 2.932 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.753 ; 2.932 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.753 ; 2.932 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.745 ; 2.924 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.764 ; 2.943 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.746 ; 2.925 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.756 ; 2.935 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.704 ; 2.882 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.764 ; 2.943 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.771 ; 2.950 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.767 ; 2.946 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.767 ; 2.946 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.767 ; 2.946 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.765 ; 2.944 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.765 ; 2.944 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.765 ; 2.944 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_DAT0       ; FPGA_CLK   ; 3.641 ; 3.845 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 0.790 ; 0.969 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 0.796 ; 0.975 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 0.799 ; 0.978 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 0.793 ; 0.972 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                      ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; -1.833 ; -2.011 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; -1.877 ; -2.056 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; -1.877 ; -2.056 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; -1.877 ; -2.056 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; -1.869 ; -2.048 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; -1.889 ; -2.068 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; -1.870 ; -2.049 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; -1.880 ; -2.059 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; -1.833 ; -2.011 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; -1.889 ; -2.068 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; -1.896 ; -2.075 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; -1.891 ; -2.070 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; -1.891 ; -2.070 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; -1.891 ; -2.070 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; -1.890 ; -2.069 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; -1.890 ; -2.069 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; -1.890 ; -2.069 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_DAT0       ; FPGA_CLK   ; -2.674 ; -2.867 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; -0.173 ; -0.352 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; -0.179 ; -0.358 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; -0.182 ; -0.361 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; -0.176 ; -0.355 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                           ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; SDRAM_A[*]    ; FPGA_CLK   ; 5.639  ; 5.886  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; FPGA_CLK   ; 3.034  ; 2.821  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; FPGA_CLK   ; 3.034  ; 2.821  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; FPGA_CLK   ; 3.037  ; 2.824  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; FPGA_CLK   ; 3.037  ; 2.824  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; FPGA_CLK   ; 3.025  ; 2.812  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; FPGA_CLK   ; 3.025  ; 2.812  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; FPGA_CLK   ; 3.023  ; 2.810  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; FPGA_CLK   ; 2.202  ; 2.128  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; FPGA_CLK   ; 5.639  ; 5.886  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; FPGA_CLK   ; 3.024  ; 2.811  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; FPGA_CLK   ; 3.034  ; 2.821  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; FPGA_CLK   ; 3.024  ; 2.811  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; FPGA_CLK   ; 5.651  ; 5.898  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; FPGA_CLK   ; 5.651  ; 5.898  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; FPGA_CLK   ; 2.214  ; 2.140  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N   ; FPGA_CLK   ; 2.216  ; 2.142  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N    ; FPGA_CLK   ; 3.036  ; 2.823  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; FPGA_CLK   ; 4.986  ; 5.410  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.406  ; 3.261  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.406  ; 3.261  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.406  ; 3.261  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 4.986  ; 5.410  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 4.966  ; 5.390  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.372  ; 2.351  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.223  ; 3.069  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.036  ; 2.823  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.394  ; 3.249  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 4.959  ; 5.383  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.392  ; 3.247  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.392  ; 3.247  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.392  ; 3.247  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 4.965  ; 5.389  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 3.393  ; 3.248  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 3.393  ; 3.248  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH_n  ; FPGA_CLK   ; 3.025  ; 2.812  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML_n  ; FPGA_CLK   ; 3.036  ; 2.823  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N   ; FPGA_CLK   ; 3.036  ; 2.823  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N    ; FPGA_CLK   ; 5.653  ; 5.900  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L       ; FPGA_CLK   ; 7.539  ; 7.874  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R       ; FPGA_CLK   ; 4.250  ; 4.188  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK        ; FPGA_CLK   ; 4.033  ; 4.003  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD        ; FPGA_CLK   ; 3.775  ; 3.752  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3       ; FPGA_CLK   ; 4.784  ; 4.870  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]      ; FPGA_CLK   ; 8.440  ; 8.771  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; FPGA_CLK   ; 5.757  ; 5.651  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; FPGA_CLK   ; 8.440  ; 8.771  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; FPGA_CLK   ; 6.106  ; 6.015  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; FPGA_CLK   ; 5.534  ; 5.389  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; FPGA_CLK   ; 8.646  ; 8.951  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; FPGA_CLK   ; 6.240  ; 6.108  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; FPGA_CLK   ; 6.396  ; 6.231  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; FPGA_CLK   ; 6.164  ; 6.021  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; FPGA_CLK   ; 8.646  ; 8.951  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; FPGA_CLK   ; 11.844 ;        ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; FPGA_CLK   ;        ; 12.193 ; Fall       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]      ; FPGA_CLK   ; 7.007  ; 7.392  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]     ; FPGA_CLK   ; 3.962  ; 3.906  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]     ; FPGA_CLK   ; 7.007  ; 7.392  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]     ; FPGA_CLK   ; 4.303  ; 4.277  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]     ; FPGA_CLK   ; 4.129  ; 4.015  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]      ; FPGA_CLK   ; 7.286  ; 7.629  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]     ; FPGA_CLK   ; 4.823  ; 4.736  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]     ; FPGA_CLK   ; 4.988  ; 4.868  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]     ; FPGA_CLK   ; 4.818  ; 4.717  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]     ; FPGA_CLK   ; 7.286  ; 7.629  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; dminus1       ; FPGA_CLK   ; 4.249  ; 4.237  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 4.063  ; 4.042  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 6.673  ; 7.097  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 4.066  ; 4.045  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                                   ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; SDRAM_A[*]    ; FPGA_CLK   ; 1.476  ; 1.402  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; FPGA_CLK   ; 2.276  ; 2.068  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; FPGA_CLK   ; 2.276  ; 2.068  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; FPGA_CLK   ; 2.279  ; 2.071  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; FPGA_CLK   ; 2.279  ; 2.071  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; FPGA_CLK   ; 2.267  ; 2.059  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; FPGA_CLK   ; 2.267  ; 2.059  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; FPGA_CLK   ; 2.265  ; 2.057  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; FPGA_CLK   ; 1.476  ; 1.402  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; FPGA_CLK   ; 4.881  ; 5.133  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; FPGA_CLK   ; 2.266  ; 2.058  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; FPGA_CLK   ; 2.276  ; 2.068  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; FPGA_CLK   ; 2.266  ; 2.058  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; FPGA_CLK   ; 1.488  ; 1.414  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; FPGA_CLK   ; 4.893  ; 5.145  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; FPGA_CLK   ; 1.488  ; 1.414  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N   ; FPGA_CLK   ; 1.490  ; 1.416  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N    ; FPGA_CLK   ; 2.278  ; 2.070  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.646  ; 1.626  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.646  ; 2.508  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.646  ; 2.508  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.646  ; 2.508  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 4.260  ; 4.685  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 4.241  ; 4.666  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 1.646  ; 1.626  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.463  ; 2.316  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.278  ; 2.070  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.635  ; 2.497  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 4.234  ; 4.659  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.632  ; 2.494  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.632  ; 2.494  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.632  ; 2.494  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 4.240  ; 4.665  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.634  ; 2.496  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.634  ; 2.496  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH_n  ; FPGA_CLK   ; 2.267  ; 2.059  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML_n  ; FPGA_CLK   ; 2.278  ; 2.070  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N   ; FPGA_CLK   ; 2.278  ; 2.070  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N    ; FPGA_CLK   ; 4.895  ; 5.147  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L       ; FPGA_CLK   ; 6.621  ; 6.959  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R       ; FPGA_CLK   ; 3.359  ; 3.296  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK        ; FPGA_CLK   ; 3.150  ; 3.118  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD        ; FPGA_CLK   ; 2.903  ; 2.878  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3       ; FPGA_CLK   ; 3.868  ; 3.954  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]      ; FPGA_CLK   ; 4.471  ; 4.343  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; FPGA_CLK   ; 4.721  ; 4.609  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; FPGA_CLK   ; 7.321  ; 7.644  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; FPGA_CLK   ; 4.961  ; 4.871  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; FPGA_CLK   ; 4.471  ; 4.343  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; FPGA_CLK   ; 5.076  ; 4.950  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; FPGA_CLK   ; 5.148  ; 5.032  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; FPGA_CLK   ; 5.299  ; 5.152  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; FPGA_CLK   ; 5.076  ; 4.950  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; FPGA_CLK   ; 7.562  ; 7.885  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; FPGA_CLK   ; 11.057 ;        ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; FPGA_CLK   ;        ; 11.407 ; Fall       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]      ; FPGA_CLK   ; 3.083  ; 3.025  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]     ; FPGA_CLK   ; 3.083  ; 3.025  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]     ; FPGA_CLK   ; 6.109  ; 6.494  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]     ; FPGA_CLK   ; 3.408  ; 3.380  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]     ; FPGA_CLK   ; 3.243  ; 3.130  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]      ; FPGA_CLK   ; 3.904  ; 3.803  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]     ; FPGA_CLK   ; 3.910  ; 3.821  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]     ; FPGA_CLK   ; 4.068  ; 3.949  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]     ; FPGA_CLK   ; 3.904  ; 3.803  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]     ; FPGA_CLK   ; 6.378  ; 6.722  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; dminus1       ; FPGA_CLK   ; 3.782  ; 3.771  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 3.596  ; 3.576  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 6.206  ; 6.631  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 3.599  ; 3.579  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                                           ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 3.108 ; 3.032 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.108 ; 3.032 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.108 ; 3.032 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.108 ; 3.032 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 5.868 ; 6.229 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 6.939 ; 7.300 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 4.027 ; 3.941 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 4.345 ; 4.259 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.728 ; 3.580 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 4.412 ; 4.336 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 6.519 ; 6.880 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.765 ; 3.689 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.765 ; 3.689 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.765 ; 3.689 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 6.193 ; 6.554 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 3.763 ; 3.687 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 3.763 ; 3.687 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 4.624 ; 4.476 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 6.174 ; 6.098 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 7.389 ; 7.303 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 8.957 ; 9.318 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 7.079 ; 6.993 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                                   ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.278 ; 2.202 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.278 ; 2.202 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.278 ; 2.202 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.278 ; 2.202 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 5.026 ; 5.387 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 6.054 ; 6.415 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.153 ; 3.067 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.459 ; 3.373 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.830 ; 2.682 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.530 ; 3.454 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 5.650 ; 6.011 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.909 ; 2.833 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.909 ; 2.833 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.909 ; 2.833 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 5.338 ; 5.699 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.908 ; 2.832 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.908 ; 2.832 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 3.692 ; 3.544 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 5.550 ; 5.474 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 6.709 ; 6.623 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 8.318 ; 8.679 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 6.411 ; 6.325 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                                  ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 3.075     ; 3.151     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.075     ; 3.151     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.075     ; 3.151     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.075     ; 3.151     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 6.267     ; 5.906     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 7.310     ; 6.949     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.960     ; 4.046     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 4.255     ; 4.341     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.619     ; 3.767     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 4.359     ; 4.435     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 6.912     ; 6.551     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.726     ; 3.802     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.726     ; 3.802     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.726     ; 3.802     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 6.576     ; 6.215     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 3.709     ; 3.785     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 3.709     ; 3.785     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 4.488     ; 4.636     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 6.093     ; 6.169     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 7.341     ; 7.427     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 9.308     ; 8.947     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 7.039     ; 7.125     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                                          ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.243     ; 2.319     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.243     ; 2.319     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.243     ; 2.319     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.243     ; 2.319     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 5.423     ; 5.062     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 6.424     ; 6.063     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.086     ; 3.172     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.369     ; 3.455     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.720     ; 2.868     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.476     ; 3.552     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 6.042     ; 5.681     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.868     ; 2.944     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.868     ; 2.944     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.868     ; 2.944     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 5.719     ; 5.358     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.853     ; 2.929     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.853     ; 2.929     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 3.555     ; 3.703     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 5.468     ; 5.544     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 6.659     ; 6.745     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 8.669     ; 8.308     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 6.370     ; 6.456     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+


----------------------------------------------
; Slow 1200mV 85C Model Metastability Report ;
----------------------------------------------
No synchronizer chains to report.


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Fmax Summary                                                                                                                                   ;
+------------+-----------------+-------------------------------------------------------------------------------------+------------------------------------------------+
; Fmax       ; Restricted Fmax ; Clock Name                                                                          ; Note                                           ;
+------------+-----------------+-------------------------------------------------------------------------------------+------------------------------------------------+
; 37.51 MHz  ; 37.51 MHz       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;                                                ;
; 91.35 MHz  ; 91.35 MHz       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;                                                ;
; 108.05 MHz ; 108.05 MHz      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;                                                ;
; 133.24 MHz ; 133.24 MHz      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;                                                ;
; 212.72 MHz ; 40.0 MHz        ; FPGA_CLK                                                                            ; limit due to minimum period restriction (tmin) ;
+------------+-----------------+-------------------------------------------------------------------------------------+------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+--------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup Summary                                                                           ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; -3.260 ; -243.956      ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -1.459 ; -1.459        ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; -0.278 ; -11.678       ;
; FPGA_CLK                                                                            ; 0.011  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1.416  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 3.650  ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold Summary                                                                            ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; -1.616 ; -113.847      ;
; FPGA_CLK                                                                            ; -0.594 ; -0.594        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.344  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.362  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.363  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 12.480 ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery Summary                                                                        ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; -2.135 ; -19.215       ;
; FPGA_CLK                                                                            ; -0.304 ; -7.751        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 7.912  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.066  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 13.404 ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal Summary                                                                         ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; FPGA_CLK                                                                            ; -0.281 ; -7.174        ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 0.438  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 1.577  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 2.293  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 3.253  ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width Summary                                                             ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.595  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 5.733  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 8.533  ; 0.000         ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 9.380  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.284 ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; 17.589 ; 0.000         ;
; FPGA_CLK                                                                            ; 89.643 ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                          ; To Node                                                                                                                                                                                            ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; -3.260 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[4]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[4]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.139     ; 1.091      ;
; -3.236 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[8]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[8]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.139     ; 1.067      ;
; -3.221 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[2]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[2]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.140     ; 1.051      ;
; -3.109 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[7]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[7]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.139     ; 0.940      ;
; -2.920 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[15]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[15]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.790     ; 1.100      ;
; -2.901 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CRCError                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[0]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.139     ; 0.732      ;
; -2.901 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[1]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[1]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.140     ; 0.731      ;
; -2.900 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|bitStuffError                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[1]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.139     ; 0.731      ;
; -2.898 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reset_n_reg                                                                                                                                             ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[2]                                                                                                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.157     ; 0.711      ;
; -2.889 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.148     ; 0.711      ;
; -2.889 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.148     ; 0.711      ;
; -2.889 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInExtend[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInSTB[2]           ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.147     ; 0.712      ;
; -2.888 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.147     ; 0.711      ;
; -2.887 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.148     ; 0.709      ;
; -2.878 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|ACKRxed                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[6]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.139     ; 0.709      ;
; -2.822 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[1]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[1]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.776     ; 1.016      ;
; -2.806 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[13]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.736     ; 1.040      ;
; -2.765 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[9]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.790     ; 0.945      ;
; -2.760 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[13]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.816     ; 0.914      ;
; -2.740 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[11]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[11]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.816     ; 0.894      ;
; -2.738 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[14]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[14]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.790     ; 0.918      ;
; -2.737 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.806     ; 0.901      ;
; -2.736 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.807     ; 0.899      ;
; -2.736 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[8]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[8]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.790     ; 0.916      ;
; -2.726 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[8]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[8]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.816     ; 0.880      ;
; -2.718 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.807     ; 0.881      ;
; -2.717 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.806     ; 0.881      ;
; -2.713 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[12]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[12]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.788     ; 0.895      ;
; -2.708 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[3]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[3]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.805     ; 0.873      ;
; -2.707 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[5]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[5]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.777     ; 0.900      ;
; -2.703 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[2]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[2]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.805     ; 0.868      ;
; -2.702 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[0]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[0]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.805     ; 0.867      ;
; -2.699 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[5]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[5]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.769     ; 0.900      ;
; -2.688 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[3]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[3]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.776     ; 0.882      ;
; -2.687 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[8]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[8]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.769     ; 0.888      ;
; -2.686 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[9]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[9]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.777     ; 0.879      ;
; -2.685 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[0]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[0]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.777     ; 0.878      ;
; -2.683 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[1]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[1]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.805     ; 0.848      ;
; -2.682 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[0]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[0]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.769     ; 0.883      ;
; -2.680 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[3]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[3]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.769     ; 0.881      ;
; -2.674 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[2]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[2]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.776     ; 0.868      ;
; -2.669 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXTimeOut                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[3]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.777     ; 0.862      ;
; -2.663 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[12]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[12]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.736     ; 0.897      ;
; -2.663 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.766     ; 0.867      ;
; -2.662 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[7]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[7]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.769     ; 0.863      ;
; -2.662 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[10]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[10]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.736     ; 0.896      ;
; -2.662 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.766     ; 0.866      ;
; -2.659 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[9]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[9]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.769     ; 0.860      ;
; -2.636 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[11]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[11]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.736     ; 0.870      ;
; -2.589 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.807     ; 0.752      ;
; -2.588 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.807     ; 0.751      ;
; -2.588 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.807     ; 0.751      ;
; -2.588 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.806     ; 0.752      ;
; -2.587 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.806     ; 0.751      ;
; -2.582 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[0] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.801     ; 0.751      ;
; -2.579 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[1] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.817     ; 0.732      ;
; -2.578 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[0] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.817     ; 0.731      ;
; -2.577 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.806     ; 0.741      ;
; -2.571 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXOverflow                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[2]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.806     ; 0.735      ;
; -2.570 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.807     ; 0.733      ;
; -2.570 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXOverflow                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[2]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.805     ; 0.735      ;
; -2.570 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[9]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.788     ; 0.752      ;
; -2.569 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.806     ; 0.733      ;
; -2.569 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|ACKRxed                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[6]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.806     ; 0.733      ;
; -2.568 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.807     ; 0.731      ;
; -2.568 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.806     ; 0.732      ;
; -2.567 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|NAKRxed                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[4]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.806     ; 0.731      ;
; -2.567 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|NAKRxed                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[4]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.805     ; 0.732      ;
; -2.567 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|stallRxed                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[5]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.806     ; 0.731      ;
; -2.566 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|stallRxed                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[5]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.805     ; 0.731      ;
; -2.566 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CRCError                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[0]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.804     ; 0.732      ;
; -2.565 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|bitStuffError                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[1]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.804     ; 0.731      ;
; -2.564 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXTimeOut                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[3]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.804     ; 0.730      ;
; -2.562 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[1] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.801     ; 0.731      ;
; -2.562 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_enable_reg                                                                                                                                          ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[2]                                                                                                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.820     ; 0.712      ;
; -2.551 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[10]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[10]    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.777     ; 0.744      ;
; -2.550 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[6]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[6]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.769     ; 0.751      ;
; -2.550 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[14]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[14]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.788     ; 0.732      ;
; -2.550 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[10]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[10]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.788     ; 0.732      ;
; -2.549 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[15]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[15]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.788     ; 0.731      ;
; -2.548 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInExtend[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInSTB[2]           ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.806     ; 0.712      ;
; -2.545 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|dataSequence                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[7]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.802     ; 0.713      ;
; -2.544 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|dataSequence                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[7]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.804     ; 0.710      ;
; -2.540 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[10]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[10]    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.769     ; 0.741      ;
; -2.539 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[6]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[6]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.777     ; 0.732      ;
; -2.530 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[4]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[4]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.769     ; 0.731      ;
; -2.518 ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                                                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|synchronizer:tick_toggle_synchronizer|ff_reg[2]                                                                                                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.778     ; 0.710      ;
; -2.477 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[1]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[1]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.736     ; 0.711      ;
; -2.477 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[3]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[3]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.736     ; 0.711      ;
; -2.476 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[0]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[0]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.736     ; 0.710      ;
; -2.475 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[2]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[2]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.736     ; 0.709      ;
; 2.725  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|pmg_dma_state_reg[2]                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.141     ; 8.791      ;
; 2.789  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Dreg                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.155     ; 8.713      ;
; 2.885  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Vreg                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.151     ; 8.621      ;
; 3.028  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Ireg                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 8.473      ;
; 3.080  ; ram_do_reg[6]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.155     ; 8.422      ;
; 3.094  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[6]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.139     ; 8.424      ;
; 3.095  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[0]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.139     ; 8.423      ;
; 3.168  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[7]                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 8.333      ;
; 3.203  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[7]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.140     ; 8.314      ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                                                             ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                 ; To Node                                                                                                                                             ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; -1.459 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 1.467        ; -1.564     ; 1.158      ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                                                                           ; To Node                                                                                                                                                                                           ; Launch Clock                                                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -0.278 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.093      ; 1.269      ;
; -0.243 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]                                                                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.237      ;
; -0.242 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.094      ; 1.234      ;
; -0.240 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.094      ; 1.232      ;
; -0.235 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.093      ; 1.226      ;
; -0.225 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.219      ;
; -0.209 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.085      ; 1.192      ;
; -0.209 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.203      ;
; -0.202 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.106      ; 1.206      ;
; -0.200 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.194      ;
; -0.197 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1]                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.191      ;
; -0.191 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.097      ; 1.186      ;
; -0.186 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.180      ;
; -0.185 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.179      ;
; -0.184 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.178      ;
; -0.182 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.085      ; 1.165      ;
; -0.182 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.176      ;
; -0.181 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.175      ;
; -0.179 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.173      ;
; -0.177 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.085      ; 1.160      ;
; -0.177 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.171      ;
; -0.175 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB                                                                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.169      ;
; -0.175 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB                                                                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.169      ;
; -0.174 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.106      ; 1.178      ;
; -0.174 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.168      ;
; -0.172 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.166      ;
; -0.171 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.165      ;
; -0.171 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.085      ; 1.154      ;
; -0.170 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.164      ;
; -0.170 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB                                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg_reg1      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.164      ;
; -0.170 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.164      ;
; -0.170 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.164      ;
; -0.169 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]                                                                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.163      ;
; -0.168 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.095      ; 1.161      ;
; -0.168 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.162      ;
; -0.167 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.086      ; 1.151      ;
; -0.167 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.106      ; 1.171      ;
; -0.164 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.158      ;
; -0.163 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.157      ;
; -0.162 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.106      ; 1.166      ;
; -0.162 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.156      ;
; -0.161 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn_reg1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.095      ; 1.154      ;
; -0.161 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.095      ; 1.154      ;
; -0.161 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.155      ;
; -0.161 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB                                                                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.097      ; 1.156      ;
; -0.159 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate_reg1       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.095      ; 1.152      ;
; -0.158 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate_reg1       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.152      ;
; -0.157 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.151      ;
; -0.157 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.151      ;
; -0.156 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol_reg1        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.095      ; 1.149      ;
; -0.156 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.150      ;
; -0.155 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.149      ;
; -0.155 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.149      ;
; -0.155 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.149      ;
; -0.155 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.149      ;
; -0.154 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1]                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.148      ;
; -0.154 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB                                                                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.148      ;
; -0.151 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.106      ; 1.155      ;
; -0.144 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.138      ;
; -0.141 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.135      ;
; -0.136 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.130      ;
; -0.133 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[0]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.127      ;
; -0.119 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.113      ;
; -0.116 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.106      ; 1.120      ;
; -0.087 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.106      ; 1.091      ;
; -0.061 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.093      ; 1.052      ;
; -0.058 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.052      ;
; -0.055 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.094      ; 1.047      ;
; -0.052 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol_reg1        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.046      ;
; -0.038 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn_reg1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.032      ;
; -0.037 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.031      ;
; -0.033 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.027      ;
; -0.032 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.026      ;
; -0.031 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.025      ;
; -0.030 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.024      ;
; -0.023 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB                                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg_reg1      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.017      ;
; 0.003  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 0.991      ;
; 0.008  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 0.986      ;
; 0.009  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 0.985      ;
; 0.014  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[0]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.095      ; 0.979      ;
; 0.088  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.093      ; 0.903      ;
; 4.943  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|altsyncram:altsyncram4|altsyncram_i0m3:auto_generated|ram_block1a0~porta_address_reg0                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.630     ; 6.870      ;
; 5.399  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|altsyncram:altsyncram4|altsyncram_nsl3:auto_generated|ram_block1a0~porta_address_reg0 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.633     ; 6.411      ;
; 6.805  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C1_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.313     ; 5.325      ;
; 6.834  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C0_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.316     ; 5.293      ;
; 6.865  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C1_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.316     ; 5.262      ;
; 6.936  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C0_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.313     ; 5.194      ;
; 7.211  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_post_state                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 3.217      ; 6.422      ;
; 7.242  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_post_state ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 3.217      ; 6.391      ;
; 7.334  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C2_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.316     ; 4.793      ;
; 7.343  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C4_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.316     ; 4.784      ;
; 7.412  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C3_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.313     ; 4.718      ;
; 7.439  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|idle_state                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 3.217      ; 6.194      ;
; 7.514  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_wait_state                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 3.217      ; 6.119      ;
; 7.541  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr14|cntr_qfo:auto_generated|counter_reg_bit[3]                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.316     ; 4.586      ;
; 7.561  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|idle_state          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 3.218      ; 6.073      ;
; 7.563  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_wait_state ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 3.218      ; 6.071      ;
; 7.597  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C4_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.313     ; 4.533      ;
; 7.598  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr14|cntr_qfo:auto_generated|counter_reg_bit[4]                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.316     ; 4.529      ;
; 7.614  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C3_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.316     ; 4.513      ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'FPGA_CLK'                                                                                                                                                                                                                                                                                               ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack   ; From Node                                                                             ; To Node                                                                               ; Launch Clock                                                                        ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; 0.011   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[131]                                       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.891      ; 3.645      ;
; 195.299 ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; 0.176      ; 4.876      ;
; 195.574 ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8           ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.275     ; 1.377      ;
; 197.096 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.839      ;
; 197.125 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.810      ;
; 197.199 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.736      ;
; 197.212 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.723      ;
; 197.213 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.722      ;
; 197.241 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.694      ;
; 197.242 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.693      ;
; 197.286 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.649      ;
; 197.311 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.624      ;
; 197.315 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.620      ;
; 197.328 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.607      ;
; 197.328 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.607      ;
; 197.329 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.606      ;
; 197.357 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.578      ;
; 197.357 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.578      ;
; 197.358 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.577      ;
; 197.402 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.533      ;
; 197.406 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.529      ;
; 197.413 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.522      ;
; 197.427 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.508      ;
; 197.431 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.504      ;
; 197.443 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.492      ;
; 197.444 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.491      ;
; 197.444 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.491      ;
; 197.445 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.490      ;
; 197.472 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.463      ;
; 197.473 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.462      ;
; 197.473 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.462      ;
; 197.474 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.461      ;
; 197.512 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.423      ;
; 197.518 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.417      ;
; 197.522 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.413      ;
; 197.529 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.406      ;
; 197.543 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.392      ;
; 197.547 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.388      ;
; 197.548 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.387      ;
; 197.559 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.376      ;
; 197.560 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.375      ;
; 197.560 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.375      ;
; 197.561 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.374      ;
; 197.562 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.373      ;
; 197.588 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.347      ;
; 197.589 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.346      ;
; 197.589 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.346      ;
; 197.590 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.345      ;
; 197.591 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.344      ;
; 197.628 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.307      ;
; 197.634 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.301      ;
; 197.635 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.300      ;
; 197.638 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.297      ;
; 197.645 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.290      ;
; 197.659 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.276      ;
; 197.663 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.272      ;
; 197.664 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.271      ;
; 197.665 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.270      ;
; 197.675 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.260      ;
; 197.676 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.259      ;
; 197.676 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.259      ;
; 197.677 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.258      ;
; 197.677 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.258      ;
; 197.678 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.257      ;
; 197.704 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.231      ;
; 197.705 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.230      ;
; 197.705 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.230      ;
; 197.706 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.229      ;
; 197.706 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.229      ;
; 197.707 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.228      ;
; 197.744 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.191      ;
; 197.750 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.185      ;
; 197.751 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.184      ;
; 197.752 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.183      ;
; 197.754 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.181      ;
; 197.761 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.174      ;
; 197.775 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.160      ;
; 197.779 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.156      ;
; 197.780 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.155      ;
; 197.781 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.154      ;
; 197.781 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.154      ;
; 197.791 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.144      ;
; 197.792 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.143      ;
; 197.793 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.142      ;
; 197.793 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.142      ;
; 197.794 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.062     ; 2.143      ;
; 197.794 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.141      ;
; 197.797 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.062     ; 2.140      ;
; 197.820 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.115      ;
; 197.821 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.114      ;
; 197.821 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.114      ;
; 197.822 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.113      ;
; 197.822 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.113      ;
; 197.823 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.112      ;
; 197.826 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.062     ; 2.111      ;
; 197.860 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.075      ;
; 197.865 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.070      ;
; 197.866 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.069      ;
; 197.867 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.068      ;
; 197.868 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.064     ; 2.067      ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                            ;
+-------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                 ; To Node                                                                                                                                             ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 1.416 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[4]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.145     ; 4.109      ;
; 1.505 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[4]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.145     ; 4.020      ;
; 1.639 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[10]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.138     ; 3.893      ;
; 1.655 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[9]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.147     ; 3.868      ;
; 1.655 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[11]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.147     ; 3.868      ;
; 1.728 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[10]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.138     ; 3.804      ;
; 1.730 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_ras_n                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.135     ; 3.805      ;
; 1.755 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[9]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.147     ; 3.768      ;
; 1.755 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[11]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.147     ; 3.768      ;
; 1.814 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[5]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.146     ; 3.710      ;
; 1.823 ; SDRAM_ADDR[18]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[7]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.154     ; 3.693      ;
; 1.830 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_ras_n                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.135     ; 3.705      ;
; 1.909 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[6]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.147     ; 3.614      ;
; 1.911 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[7]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.148     ; 3.611      ;
; 1.911 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[8]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.148     ; 3.611      ;
; 1.914 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[5]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.146     ; 3.610      ;
; 2.003 ; SDRAM_ADDR[8]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[7]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.163     ; 3.504      ;
; 2.009 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[6]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.147     ; 3.514      ;
; 2.011 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[7]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.148     ; 3.511      ;
; 2.011 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[8]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.148     ; 3.511      ;
; 2.062 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[4]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.133     ; 3.587      ;
; 2.062 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[13]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.133     ; 3.587      ;
; 2.113 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[7]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.133     ; 3.536      ;
; 2.114 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[3]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.133     ; 3.535      ;
; 2.164 ; SDRAM_ADDR[21]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[10]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.144     ; 3.362      ;
; 2.217 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[0]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.128     ; 3.437      ;
; 2.220 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[1]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.128     ; 3.434      ;
; 2.222 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[2]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.128     ; 3.432      ;
; 2.256 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_ba[0]                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.138     ; 3.276      ;
; 2.256 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_ba[1]                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.138     ; 3.276      ;
; 2.272 ; SDRAM_ADDR[17]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[6]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.153     ; 3.245      ;
; 2.356 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_ba[0]                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.138     ; 3.176      ;
; 2.356 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_ba[1]                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.138     ; 3.176      ;
; 2.366 ; SDRAM_ADDR[5]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[4]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.146     ; 3.158      ;
; 2.399 ; SDRAM_ADDR[16]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.152     ; 3.119      ;
; 2.413 ; SDRAM_ADDR[7]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[6]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.148     ; 3.109      ;
; 2.483 ; SDRAM_ADDR[15]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.146     ; 3.041      ;
; 2.488 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[13]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.135     ; 3.159      ;
; 2.489 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[4]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.135     ; 3.158      ;
; 2.503 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[14]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.133     ; 3.146      ;
; 2.503 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[15]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.133     ; 3.146      ;
; 2.506 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[6]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.133     ; 3.143      ;
; 2.518 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[7]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.135     ; 3.129      ;
; 2.519 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[3]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.135     ; 3.128      ;
; 2.544 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[2]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.123     ; 3.115      ;
; 2.590 ; SDRAM_ADDR[20]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[9]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.153     ; 2.927      ;
; 2.625 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[8]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.131     ; 3.026      ;
; 2.625 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[10]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.131     ; 3.026      ;
; 2.627 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_bena_reg[1]                                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.131     ; 3.024      ;
; 2.628 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[11]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.131     ; 3.023      ;
; 2.628 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[12]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.131     ; 3.023      ;
; 2.628 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_bena_reg[0]                                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.131     ; 3.023      ;
; 2.628 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[0]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.130     ; 3.024      ;
; 2.631 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[1]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.130     ; 3.021      ;
; 2.631 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[2]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.130     ; 3.021      ;
; 2.650 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[5]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.128     ; 3.004      ;
; 2.672 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[2]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.134     ; 2.864      ;
; 2.672 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[3]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.134     ; 2.864      ;
; 2.674 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[9]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.131     ; 2.977      ;
; 2.696 ; SDRAM_ADDR[19]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[8]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.154     ; 2.820      ;
; 2.772 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[2]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.134     ; 2.764      ;
; 2.772 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[3]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.134     ; 2.764      ;
; 2.780 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[0]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 2.877      ;
; 2.780 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[5]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 2.877      ;
; 2.780 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[4]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 2.877      ;
; 2.780 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[13]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 2.877      ;
; 2.780 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[12]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 2.877      ;
; 2.780 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[10]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 2.877      ;
; 2.780 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[9]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 2.877      ;
; 2.780 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[8]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 2.877      ;
; 2.780 ; SDRAM_ADDR[22]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[11]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.148     ; 2.742      ;
; 2.808 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[0]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.138     ; 2.724      ;
; 2.808 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[1]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.138     ; 2.724      ;
; 2.826 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[6]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.131     ; 2.825      ;
; 2.841 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.123     ; 2.818      ;
; 2.877 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_do_reg[15]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.123     ; 2.782      ;
; 2.879 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_do_reg[11]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.123     ; 2.780      ;
; 2.880 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[3]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 2.777      ;
; 2.880 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[15]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 2.777      ;
; 2.880 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[14]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 2.777      ;
; 2.880 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[11]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 2.777      ;
; 2.908 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[0]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.138     ; 2.624      ;
; 2.908 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[1]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.138     ; 2.624      ;
; 2.917 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_do_reg[3]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.123     ; 2.742      ;
; 2.930 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.123     ; 2.729      ;
; 2.932 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[14]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.135     ; 2.715      ;
; 2.933 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[15]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.135     ; 2.714      ;
; 2.935 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[6]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.135     ; 2.712      ;
; 2.939 ; SDRAM_ADDR[14]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[3]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.135     ; 2.596      ;
; 2.946 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:0:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -1.564     ; 1.159      ;
; 2.990 ; SDRAM_WRITE_ENABLE                                                                        ; ram_bena_reg[1]                                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.133     ; 2.659      ;
; 2.992 ; SDRAM_WRITE_ENABLE                                                                        ; ram_bena_reg[0]                                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.133     ; 2.657      ;
; 3.000 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_do_reg[2]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.121     ; 2.661      ;
; 3.001 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[8]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.133     ; 2.648      ;
; 3.002 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[9]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.133     ; 2.647      ;
; 3.004 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[11]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.133     ; 2.645      ;
; 3.010 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[10]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.133     ; 2.639      ;
; 3.013 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[12]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.133     ; 2.636      ;
; 3.038 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_do_reg[14]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.123     ; 2.621      ;
; 3.045 ; SDRAM_ADDR[6]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[5]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.147     ; 2.478      ;
+-------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                                                                                                                                                       ;
+--------+-----------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                           ; To Node                                                                                                                                             ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 3.650  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.163     ; 13.717     ;
; 3.717  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.163     ; 13.650     ;
; 3.748  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.163     ; 13.619     ;
; 3.766  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.163     ; 13.601     ;
; 3.768  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.163     ; 13.599     ;
; 3.773  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.163     ; 13.594     ;
; 3.815  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.163     ; 13.552     ;
; 3.835  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.163     ; 13.532     ;
; 3.840  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.163     ; 13.527     ;
; 3.840  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.163     ; 13.527     ;
; 3.861  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.163     ; 13.506     ;
; 3.864  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.163     ; 13.503     ;
; 3.884  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.163     ; 13.483     ;
; 3.889  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.163     ; 13.478     ;
; 3.928  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.163     ; 13.439     ;
; 3.938  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.163     ; 13.429     ;
; 3.958  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.163     ; 13.409     ;
; 3.963  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.163     ; 13.404     ;
; 3.977  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.163     ; 13.390     ;
; 4.051  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.163     ; 13.316     ;
; 4.180  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.172     ; 13.178     ;
; 4.247  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.172     ; 13.111     ;
; 4.260  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.169     ; 13.101     ;
; 4.296  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.172     ; 13.062     ;
; 4.327  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.169     ; 13.034     ;
; 4.360  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.163     ; 13.007     ;
; 4.370  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.172     ; 12.988     ;
; 4.376  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.169     ; 12.985     ;
; 4.450  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.169     ; 12.911     ;
; 4.458  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.163     ; 12.909     ;
; 4.478  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.163     ; 12.889     ;
; 4.483  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.163     ; 12.884     ;
; 4.571  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.163     ; 12.796     ;
; 4.890  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.172     ; 12.468     ;
; 4.923  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.163     ; 12.444     ;
; 4.970  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.169     ; 12.391     ;
; 5.021  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.163     ; 12.346     ;
; 5.041  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.163     ; 12.326     ;
; 5.046  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.163     ; 12.321     ;
; 5.134  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.163     ; 12.233     ;
; 5.453  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.172     ; 11.905     ;
; 5.533  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.169     ; 11.828     ;
; 5.634  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0]           ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 8.810        ; -1.563     ; 1.409      ;
; 5.767  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.163     ; 11.600     ;
; 5.865  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.163     ; 11.502     ;
; 5.885  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.163     ; 11.482     ;
; 5.890  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.163     ; 11.477     ;
; 5.978  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.163     ; 11.389     ;
; 6.297  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.172     ; 11.061     ;
; 6.377  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.169     ; 10.984     ;
; 7.092  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.163     ; 10.275     ;
; 7.190  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.163     ; 10.177     ;
; 7.210  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.163     ; 10.157     ;
; 7.215  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.163     ; 10.152     ;
; 7.303  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.163     ; 10.064     ;
; 7.622  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.172     ; 9.736      ;
; 7.702  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.169     ; 9.659      ;
; 8.366  ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.065     ; 9.099      ;
; 8.378  ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.065     ; 9.087      ;
; 8.433  ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.065     ; 9.032      ;
; 8.445  ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.065     ; 9.020      ;
; 8.458  ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.065     ; 9.007      ;
; 8.482  ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.065     ; 8.983      ;
; 8.494  ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.065     ; 8.971      ;
; 8.525  ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.065     ; 8.940      ;
; 8.540  ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.065     ; 8.925      ;
; 8.556  ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.065     ; 8.909      ;
; 8.568  ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.065     ; 8.897      ;
; 8.574  ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.065     ; 8.891      ;
; 8.607  ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.065     ; 8.858      ;
; 8.648  ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.065     ; 8.817      ;
; 8.656  ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.065     ; 8.809      ;
; 8.730  ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.065     ; 8.735      ;
; 9.076  ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.065     ; 8.389      ;
; 9.088  ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.065     ; 8.377      ;
; 9.122  ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.065     ; 8.343      ;
; 9.168  ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.065     ; 8.297      ;
; 9.189  ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.065     ; 8.276      ;
; 9.238  ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.065     ; 8.227      ;
; 9.250  ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.065     ; 8.215      ;
; 9.312  ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.065     ; 8.153      ;
; 9.639  ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.065     ; 7.826      ;
; 9.651  ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.065     ; 7.814      ;
; 9.731  ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.065     ; 7.734      ;
; 9.813  ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.065     ; 7.652      ;
; 9.832  ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.065     ; 7.633      ;
; 10.395 ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.065     ; 7.070      ;
; 10.483 ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.065     ; 6.982      ;
; 10.495 ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.065     ; 6.970      ;
; 10.575 ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.065     ; 6.890      ;
; 10.657 ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.065     ; 6.808      ;
; 11.239 ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.065     ; 6.226      ;
; 11.691 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg        ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.169     ; 5.670      ;
; 11.808 ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.065     ; 5.657      ;
; 11.820 ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.065     ; 5.645      ;
; 11.900 ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.065     ; 5.565      ;
; 11.982 ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.065     ; 5.483      ;
; 12.107 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2]    ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.169     ; 5.254      ;
; 12.122 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0]    ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.184     ; 5.224      ;
; 12.206 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg        ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.169     ; 5.155      ;
+--------+-----------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                       ; To Node                                                                                                                                                                                                                                         ; Launch Clock                                                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -1.616 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.147      ; 0.810      ;
; -1.572 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.147      ; 0.854      ;
; -1.569 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.147      ; 0.857      ;
; -1.518 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 0.909      ;
; -1.516 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.147      ; 0.910      ;
; -1.512 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[0]                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 0.915      ;
; -1.508 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 0.919      ;
; -1.487 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn_reg1                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 0.940      ;
; -1.479 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg_reg1                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 0.948      ;
; -1.471 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 0.956      ;
; -1.470 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol_reg1                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 0.957      ;
; -1.468 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 0.959      ;
; -1.466 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 0.961      ;
; -1.459 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 0.968      ;
; -1.457 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 0.970      ;
; -1.441 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.158      ; 0.996      ;
; -1.436 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.158      ; 1.001      ;
; -1.436 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.149      ; 0.992      ;
; -1.435 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.149      ; 0.993      ;
; -1.435 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 0.992      ;
; -1.434 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.149      ; 0.994      ;
; -1.434 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate_reg1                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 0.993      ;
; -1.434 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 0.993      ;
; -1.433 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.158      ; 1.004      ;
; -1.433 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.149      ; 0.995      ;
; -1.433 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.149      ; 0.995      ;
; -1.432 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 0.995      ;
; -1.431 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]                                                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 0.996      ;
; -1.431 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 0.996      ;
; -1.429 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.149      ; 0.999      ;
; -1.429 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 0.998      ;
; -1.429 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[0]                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 0.998      ;
; -1.428 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 0.999      ;
; -1.426 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 1.001      ;
; -1.426 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 1.001      ;
; -1.425 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.138      ; 0.992      ;
; -1.425 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 1.002      ;
; -1.424 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 1.003      ;
; -1.422 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.158      ; 1.015      ;
; -1.421 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 1.006      ;
; -1.421 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 1.006      ;
; -1.420 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 1.007      ;
; -1.417 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.158      ; 1.020      ;
; -1.416 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 1.011      ;
; -1.416 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 1.011      ;
; -1.413 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 1.014      ;
; -1.412 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 1.015      ;
; -1.411 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.149      ; 1.017      ;
; -1.410 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 1.017      ;
; -1.407 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 1.020      ;
; -1.401 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                                                                             ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 1.026      ;
; -1.398 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.158      ; 1.039      ;
; -1.395 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate_reg1                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 1.032      ;
; -1.392 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn_reg1                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 1.035      ;
; -1.390 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol_reg1                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 1.037      ;
; -1.390 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.147      ; 1.036      ;
; -1.388 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 1.039      ;
; -1.388 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 1.039      ;
; -1.388 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 1.039      ;
; -1.388 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 1.039      ;
; -1.386 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg_reg1                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 1.041      ;
; -1.385 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.138      ; 1.032      ;
; -1.379 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[3]                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.138      ; 1.038      ;
; -1.376 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[2]                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.138      ; 1.041      ;
; -1.372 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 1.055      ;
; -1.320 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 1.107      ;
; -1.319 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 1.108      ;
; -1.317 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 1.110      ;
; -1.316 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[2]                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 1.111      ;
; -1.315 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 1.112      ;
; -1.307 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.149      ; 1.121      ;
; -1.305 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.149      ; 1.123      ;
; -1.303 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.158      ; 1.134      ;
; -1.302 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[3]                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 1.125      ;
; -1.292 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.137      ; 1.124      ;
; -1.282 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 1.145      ;
; -1.248 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.147      ; 1.178      ;
; -1.247 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.147      ; 1.179      ;
; -1.243 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.147      ; 1.183      ;
; -1.234 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]                                                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.149      ; 1.194      ;
; -1.208 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.147      ; 1.218      ;
; 0.348  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[0]                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.389      ; 0.938      ;
; 0.353  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[4]                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.389      ; 0.943      ;
; 0.357  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[5]                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.389      ; 0.947      ;
; 0.359  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[3]                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.386      ; 0.946      ;
; 0.360  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[1]                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.389      ; 0.950      ;
; 0.362  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutCtrl[0]       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutCtrl[0]                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10110   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10110                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10111   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10111                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11000   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11000                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11001   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11001                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11011   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11011                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11100   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11100                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireWEn               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireWEn                                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireCtrl              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireCtrl                                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0001 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0001                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.011                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.011                                                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFTimerClr                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFTimerClr                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.101                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.101                                                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|clearTXReq                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|clearTXReq                                                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'FPGA_CLK'                                                                                                                                                                                                                                                                                         ;
+--------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                       ; To Node                                                                               ; Launch Clock                                                                        ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.594 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[131]                                 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.613      ; 3.356      ;
; 0.330  ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8     ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; -0.176     ; 1.276      ;
; 0.404  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2] ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1]       ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.063      ; 0.638      ;
; 0.407  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1] ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.063      ; 0.641      ;
; 0.410  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.643      ;
; 0.595  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.828      ;
; 0.595  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.828      ;
; 0.596  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.829      ;
; 0.597  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.830      ;
; 0.597  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.830      ;
; 0.597  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.830      ;
; 0.597  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.830      ;
; 0.597  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.830      ;
; 0.597  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.830      ;
; 0.598  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.831      ;
; 0.598  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.831      ;
; 0.598  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.831      ;
; 0.598  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.831      ;
; 0.599  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.832      ;
; 0.599  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.832      ;
; 0.599  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.832      ;
; 0.599  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.832      ;
; 0.601  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.834      ;
; 0.602  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.835      ;
; 0.602  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.835      ;
; 0.602  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.835      ;
; 0.614  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.847      ;
; 0.614  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.847      ;
; 0.622  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.855      ;
; 0.883  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.116      ;
; 0.883  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.116      ;
; 0.884  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.117      ;
; 0.884  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.117      ;
; 0.884  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.117      ;
; 0.884  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.117      ;
; 0.885  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.118      ;
; 0.885  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.118      ;
; 0.885  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.118      ;
; 0.885  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.118      ;
; 0.885  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.060      ; 1.116      ;
; 0.885  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.118      ;
; 0.886  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.119      ;
; 0.886  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.119      ;
; 0.886  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.119      ;
; 0.886  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.119      ;
; 0.886  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.119      ;
; 0.887  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.120      ;
; 0.888  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.121      ;
; 0.890  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.123      ;
; 0.890  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.123      ;
; 0.890  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.123      ;
; 0.894  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.127      ;
; 0.895  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.128      ;
; 0.896  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.129      ;
; 0.896  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.060      ; 1.127      ;
; 0.896  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.129      ;
; 0.896  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.129      ;
; 0.898  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.131      ;
; 0.901  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.134      ;
; 0.901  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.134      ;
; 0.901  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.134      ;
; 0.901  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.134      ;
; 0.902  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.135      ;
; 0.913  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.146      ;
; 0.982  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.215      ;
; 0.983  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.216      ;
; 0.983  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.216      ;
; 0.984  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.217      ;
; 0.984  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.217      ;
; 0.985  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.218      ;
; 0.985  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.218      ;
; 0.985  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.218      ;
; 0.985  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.060      ; 1.216      ;
; 0.985  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.218      ;
; 0.987  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.220      ;
; 0.993  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.226      ;
; 0.994  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.227      ;
; 0.994  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.227      ;
; 0.994  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.227      ;
; 0.995  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.228      ;
; 0.995  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.228      ;
; 0.995  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.228      ;
; 0.995  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.060      ; 1.226      ;
; 0.995  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.228      ;
; 0.995  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.228      ;
; 0.995  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.060      ; 1.226      ;
; 0.996  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.229      ;
; 0.996  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.229      ;
; 0.996  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.060      ; 1.227      ;
; 0.996  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.229      ;
; 0.996  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.229      ;
; 0.997  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.230      ;
; 1.000  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.233      ;
; 1.000  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.233      ;
; 1.000  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.233      ;
; 1.000  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.233      ;
; 1.005  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.238      ;
; 1.006  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.239      ;
; 1.006  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.060      ; 1.237      ;
; 1.006  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.239      ;
+--------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                              ; To Node                                                                                                                                                                                                                                          ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.344 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_address_reg0 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.402      ; 0.947      ;
; 0.347 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInt  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInt                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 0.597      ;
; 0.347 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeInt     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeInt                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 0.597      ;
; 0.359 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp0_snap_reg[5]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.386      ; 0.946      ;
; 0.362 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]                                                                                                                                      ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]                                                                                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                                                                                                                     ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                                                                                                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[8]                                                                                                                                      ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[8]                                                                                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; sdram_reset_n_reg                                                                                                                                                                      ; sdram_reset_n_reg                                                                                                                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[4]                                                                                                                                          ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[4]                                                                                                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[31]                                                                                                                                       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[31]                                                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[25]                                                                                                                                       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[25]                                                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[17]                                                                                                                                       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[17]                                                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[23]                                                                                                                                       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[23]                                                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[18]                                                                                                                                       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[18]                                                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[20]                                                                                                                                       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[20]                                                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[27]                                                                                                                                       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[27]                                                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[35]                                                                                                                                         ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[35]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[52]                                                                                                                                         ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[52]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[28]                                                                                                                                         ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[28]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|b_r[31]                                                                                                                          ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|b_r[31]                                                                                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[19]                                                                                                                                       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[19]                                                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[61]                                                                                                                                         ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[61]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[11]                                                                                                                                       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[11]                                                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[4]                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[4]                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[6]                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[6]                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|cpu_fetch_real_reg                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|cpu_fetch_real_reg                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[29]                                                                                                                                         ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[29]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[76]                                                                                                                                         ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[76]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[82]                                                                                                                                         ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[82]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[273]                                                                                                                                        ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[273]                                                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[93]                                                                                                                                         ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[93]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[21]                                                                                                                                         ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[21]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[51]                                                                                                                                         ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[51]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[45]                                                                                                                                         ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[45]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[68]                                                                                                                                         ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[68]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[65]                                                                                                                                         ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[65]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[75]                                                                                                                                         ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[75]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[59]                                                                                                                                         ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[59]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[77]                                                                                                                                         ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[77]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[60]                                                                                                                                         ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[60]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[5]                                                                                                                                          ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[5]                                                                                                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[73]                                                                                                                                         ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[73]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[49]                                                                                                                                         ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[49]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[36]                                                                                                                                         ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[36]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[53]                                                                                                                                         ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[53]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[69]                                                                                                                                         ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[69]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[12]                                                                                                                                         ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[12]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[44]                                                                                                                                         ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[44]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[67]                                                                                                                                         ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[67]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[88]                                                                                                                                         ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[88]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[2]                                                                                                                             ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[2]                                                                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[3]                                                                                                                             ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[3]                                                                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; paddle_mode_reg                                                                                                                                                                        ; paddle_mode_reg                                                                                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[369]                                                                                                                                        ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[369]                                                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[11]                                                                                                                                     ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[11]                                                                                                                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[20]                                                                                                                                         ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[20]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[119]                                                                                                                                        ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[119]                                                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[7]                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[7]                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[22]                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[22]                                                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[370]                                                                                                                                        ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[370]                                                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|full_dff        ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|full_dff                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|usedw_is_0_dff  ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|usedw_is_0_dff                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|low_addressa[7] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|low_addressa[7]                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|low_addressa[6] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|low_addressa[6]                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|low_addressa[5] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|low_addressa[5]                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|low_addressa[4] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|low_addressa[4]                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|low_addressa[3] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|low_addressa[3]                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|low_addressa[2] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|low_addressa[2]                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|low_addressa[1] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|low_addressa[1]                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|low_addressa[0] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|low_addressa[0]                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[373]                                                                                                                                        ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[373]                                                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[12]                                                                                                                                       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[12]                                                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[37]                                                                                                                                         ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[37]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[16]                                                                                                                          ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[16]                                                                                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[18]                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[18]                                                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[19]                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[19]                                                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[20]                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[20]                                                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[23]                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[23]                                                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|idim_r                                                                                                                           ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|idim_r                                                                                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[7]                                                                                                                                          ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[7]                                                                                                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[363]                                                                                                                                        ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[363]                                                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[120]                                                                                                                                        ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[120]                                                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[372]                                                                                                                                        ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[372]                                                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|s2p_framing_error_reg                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|s2p_framing_error_reg                                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                                                         ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[16]                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[16]                                                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[17]                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[17]                                                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[16]                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[16]                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[17]                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[17]                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[18]                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[18]                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[19]                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[19]                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[20]                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[20]                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[21]                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[21]                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[23]                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[23]                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[24]                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[24]                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[27]                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[27]                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[28]                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[28]                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[12]                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[12]                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[13]                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[13]                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                   ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                 ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.362 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; sdram_ctrl:sdram_controller|sdram_rdy                     ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.363 ; sdram_ctrl:sdram_controller|r_refr_act                    ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; sdram_request_reg                                         ; sdram_request_reg                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; sdram_ctrl:sdram_controller|r_rd_act                      ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; sdram_ctrl:sdram_controller|r_wr_act                      ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.373 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.608      ;
; 0.424 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.659      ;
; 0.436 ; seq_reg[11]                                               ; seq_reg[0]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.670      ;
; 0.526 ; sdram_ctrl:sdram_controller|r_rd_act                      ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.760      ;
; 0.564 ; seq_reg[9]                                                ; seq_reg[10]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.798      ;
; 0.578 ; seq_reg[2]                                                ; seq_reg[3]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.813      ;
; 0.588 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.823      ;
; 0.588 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.823      ;
; 0.590 ; seq_reg[3]                                                ; seq_reg[4]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.825      ;
; 0.590 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.825      ;
; 0.591 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.826      ;
; 0.591 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.826      ;
; 0.592 ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.826      ;
; 0.593 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.828      ;
; 0.593 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.828      ;
; 0.593 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.827      ;
; 0.597 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.831      ;
; 0.603 ; seq_reg[0]                                                ; seq_reg[1]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.837      ;
; 0.606 ; seq_reg[4]                                                ; seq_reg[5]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.841      ;
; 0.607 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.842      ;
; 0.608 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.843      ;
; 0.640 ; sdram_ctrl:sdram_controller|r_rd_act                      ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.874      ;
; 0.655 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.890      ;
; 0.663 ; seq_reg[10]                                               ; seq_reg[11]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.897      ;
; 0.666 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.901      ;
; 0.671 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.906      ;
; 0.696 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.931      ;
; 0.711 ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.945      ;
; 0.741 ; seq_reg[8]                                                ; seq_reg[9]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.975      ;
; 0.750 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.985      ;
; 0.752 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.987      ;
; 0.754 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.988      ;
; 0.841 ; seq_reg[4]                                                ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.076      ;
; 0.861 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.066      ; 1.098      ;
; 0.876 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.111      ;
; 0.876 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.111      ;
; 0.877 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.112      ;
; 0.878 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.113      ;
; 0.878 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.113      ;
; 0.880 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.115      ;
; 0.881 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.116      ;
; 0.881 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.116      ;
; 0.887 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.122      ;
; 0.887 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.122      ;
; 0.891 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.126      ;
; 0.892 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.127      ;
; 0.892 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.127      ;
; 0.917 ; sdram_ctrl:sdram_controller|r_refr_act                    ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 1.163      ;
; 0.923 ; sdram_ctrl:sdram_controller|r_refr_act                    ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 1.169      ;
; 0.977 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.212      ;
; 0.977 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.212      ;
; 0.986 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.221      ;
; 0.988 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.223      ;
; 0.988 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.223      ;
; 0.990 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.225      ;
; 0.991 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.226      ;
; 0.991 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.226      ;
; 0.997 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.232      ;
; 1.001 ; seq_reg[7]                                                ; seq_reg[8]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.235      ;
; 1.001 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.236      ;
; 1.002 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.237      ;
; 1.002 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.237      ;
; 1.014 ; sdram_request_reg                                         ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.248      ;
; 1.029 ; seq_reg[1]                                                ; seq_reg[2]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.264      ;
; 1.037 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.272      ;
; 1.052 ; seq_reg[1]                                                ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.287      ;
; 1.061 ; sdram_ctrl:sdram_controller|r_rd_reg                      ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.051      ; 1.283      ;
; 1.087 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.322      ;
; 1.096 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.331      ;
; 1.098 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.333      ;
; 1.100 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.335      ;
; 1.101 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.336      ;
; 1.106 ; seq_reg[0]                                                ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.341      ;
; 1.107 ; sdram_ctrl:sdram_controller|r_wr_reg                      ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.051      ; 1.329      ;
; 1.107 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.342      ;
; 1.109 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.344      ;
; 1.111 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.346      ;
; 1.112 ; sdram_ctrl:sdram_controller|r_refr_act                    ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.346      ;
; 1.112 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.347      ;
; 1.122 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.357      ;
; 1.147 ; seq_reg[4]                                                ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.382      ;
; 1.147 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.382      ;
; 1.147 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.382      ;
; 1.151 ; sdram_request_complete_reg                                ; sdram_request_complete_reg                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.385      ;
; 1.206 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.441      ;
; 1.210 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.445      ;
; 1.215 ; seq_reg[5]                                                ; seq_reg[6]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.449      ;
; 1.216 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.451      ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                                      ;
+-------+--------------------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                        ; To Node                               ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.363 ; svideo_gtia:svideo|phase_count_reg[5]                                                            ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; svideo_gtia:svideo|phase_count_reg[6]                                                            ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; svideo_gtia:svideo|phase_count_reg[7]                                                            ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.063      ; 0.597      ;
; 0.824 ; svideo_gtia:svideo|phase_count_reg[4]                                                            ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.063      ; 1.058      ;
; 0.904 ; svideo_gtia:svideo|phase_count_reg[4]                                                            ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.063      ; 1.138      ;
; 0.930 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                              ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.132      ; 1.343      ;
; 0.932 ; svideo_gtia:svideo|phase_count_reg[3]                                                            ; svideo_gtia:svideo|phase_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.063      ; 1.166      ;
; 1.141 ; svideo_gtia:svideo|phase_count_reg[6]                                                            ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.063      ; 1.375      ;
; 1.208 ; svideo_gtia:svideo|phase_count_reg[2]                                                            ; svideo_gtia:svideo|phase_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.063      ; 1.442      ;
; 1.252 ; svideo_gtia:svideo|phase_count_reg[4]                                                            ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.063      ; 1.486      ;
; 1.301 ; svideo_gtia:svideo|phase_count_reg[5]                                                            ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.063      ; 1.535      ;
; 1.303 ; svideo_gtia:svideo|phase_count_reg[3]                                                            ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.063      ; 1.537      ;
; 1.311 ; svideo_gtia:svideo|phase_count_reg[2]                                                            ; svideo_gtia:svideo|phase_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.063      ; 1.545      ;
; 1.318 ; svideo_gtia:svideo|phase_count_reg[2]                                                            ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.063      ; 1.552      ;
; 1.368 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                              ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.132      ; 1.781      ;
; 1.387 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                              ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.132      ; 1.800      ;
; 1.389 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                              ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.132      ; 1.802      ;
; 1.413 ; svideo_gtia:svideo|phase_count_reg[5]                                                            ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.063      ; 1.647      ;
; 1.415 ; svideo_gtia:svideo|phase_count_reg[3]                                                            ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.063      ; 1.649      ;
; 1.430 ; svideo_gtia:svideo|phase_count_reg[2]                                                            ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.063      ; 1.664      ;
; 1.519 ; svideo_gtia:svideo|phase_count_reg[4]                                                            ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.063      ; 1.753      ;
; 1.520 ; svideo_gtia:svideo|phase_count_reg[3]                                                            ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.063      ; 1.754      ;
; 1.535 ; svideo_gtia:svideo|phase_count_reg[2]                                                            ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.063      ; 1.769      ;
; 1.543 ; svideo_gtia:svideo|phase_count_reg[3]                                                            ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.063      ; 1.777      ;
; 1.558 ; svideo_gtia:svideo|phase_count_reg[2]                                                            ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.063      ; 1.792      ;
; 1.823 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                              ; svideo_gtia:svideo|phase_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.132      ; 2.236      ;
; 1.823 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                              ; svideo_gtia:svideo|phase_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.132      ; 2.236      ;
; 1.886 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.139      ; 2.306      ;
; 1.939 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.133      ; 2.353      ;
; 1.940 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.133      ; 2.354      ;
; 2.055 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hblank_reg    ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.133      ; 2.469      ;
; 2.078 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hblank_reg    ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.133      ; 2.492      ;
; 2.102 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.139      ; 2.522      ;
; 2.103 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hblank_reg    ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.133      ; 2.517      ;
; 2.119 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hblank_reg    ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.133      ; 2.533      ;
; 2.150 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.139      ; 2.570      ;
; 2.193 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|phase_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.135      ; 2.609      ;
; 2.195 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|phase_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.135      ; 2.611      ;
; 2.196 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.139      ; 2.616      ;
; 2.198 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hblank_reg    ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.133      ; 2.612      ;
; 2.198 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.133      ; 2.612      ;
; 2.211 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.133      ; 2.625      ;
; 2.223 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.139      ; 2.643      ;
; 2.228 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.119      ; 2.628      ;
; 2.249 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.139      ; 2.669      ;
; 2.254 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.119      ; 2.654      ;
; 2.254 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.133      ; 2.668      ;
; 2.260 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.139      ; 2.680      ;
; 2.279 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.133      ; 2.693      ;
; 2.283 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hblank_reg    ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.133      ; 2.697      ;
; 2.300 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.133      ; 2.714      ;
; 2.317 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.139      ; 2.737      ;
; 2.321 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.133      ; 2.735      ;
; 2.342 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.139      ; 2.762      ;
; 2.359 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.139      ; 2.779      ;
; 2.360 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.139      ; 2.780      ;
; 2.367 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hblank_reg    ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.133      ; 2.781      ;
; 2.370 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.139      ; 2.790      ;
; 2.393 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.139      ; 2.813      ;
; 2.410 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.133      ; 2.824      ;
; 2.410 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.139      ; 2.830      ;
; 2.420 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.135      ; 2.836      ;
; 2.420 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.135      ; 2.836      ;
; 2.420 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.135      ; 2.836      ;
; 2.431 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.133      ; 2.845      ;
; 2.433 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.119      ; 2.833      ;
; 2.434 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hblank_reg    ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.133      ; 2.848      ;
; 2.436 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.139      ; 2.856      ;
; 2.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.139      ; 2.874      ;
; 2.459 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.133      ; 2.873      ;
; 2.461 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.139      ; 2.881      ;
; 2.469 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.133      ; 2.883      ;
; 2.469 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.139      ; 2.889      ;
; 2.475 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.119      ; 2.875      ;
; 2.476 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.139      ; 2.896      ;
; 2.478 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.139      ; 2.898      ;
; 2.479 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.139      ; 2.899      ;
; 2.483 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.133      ; 2.897      ;
; 2.486 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.133      ; 2.900      ;
; 2.514 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.139      ; 2.934      ;
; 2.520 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.133      ; 2.934      ;
; 2.527 ; svideo_gtia:svideo|phase_count_reg[7]                                                            ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.061      ; 2.759      ;
; 2.530 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.133      ; 2.944      ;
; 2.543 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.133      ; 2.957      ;
; 2.558 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.139      ; 2.978      ;
; 2.560 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.119      ; 2.960      ;
; 2.579 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.133      ; 2.993      ;
; 2.597 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.139      ; 3.017      ;
; 2.599 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.139      ; 3.019      ;
; 2.600 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.139      ; 3.020      ;
; 2.604 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.135      ; 3.020      ;
; 2.609 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.119      ; 3.009      ;
; 2.624 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.139      ; 3.044      ;
; 2.633 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.139      ; 3.053      ;
; 2.640 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.133      ; 3.054      ;
; 2.651 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.139      ; 3.071      ;
; 2.670 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.119      ; 3.070      ;
; 2.681 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.139      ; 3.101      ;
; 2.689 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[3] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.133      ; 3.103      ;
; 2.689 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.133      ; 3.103      ;
+-------+--------------------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                                                              ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                 ; To Node                                                                                                                                             ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 12.480 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -10.281      ; -1.341     ; 1.024      ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                           ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                            ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -2.135 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.080      ; 3.178      ;
; -2.135 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.080      ; 3.178      ;
; -2.135 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.080      ; 3.178      ;
; -2.135 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.080      ; 3.178      ;
; -2.135 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.080      ; 3.178      ;
; -2.135 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.080      ; 3.178      ;
; -2.135 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.080      ; 3.178      ;
; -2.135 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.080      ; 3.178      ;
; -2.135 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.080      ; 3.178      ;
; -2.091 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.080      ; 3.069      ;
; -2.091 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.080      ; 3.069      ;
; -2.091 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.080      ; 3.069      ;
; -2.091 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.080      ; 3.069      ;
; -2.091 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.080      ; 3.069      ;
; -2.091 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.080      ; 3.069      ;
; -2.091 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.080      ; 3.069      ;
; -2.091 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.080      ; 3.069      ;
; -2.091 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.080      ; 3.069      ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: 'FPGA_CLK'                                                                                                                                                                                                                                                                                ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                            ; To Node                                                                     ; Launch Clock                                                                        ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.304 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.885      ; 3.954      ;
; -0.304 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.885      ; 3.954      ;
; -0.304 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.885      ; 3.954      ;
; -0.304 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.885      ; 3.954      ;
; -0.304 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.885      ; 3.954      ;
; -0.304 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.885      ; 3.954      ;
; -0.304 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.885      ; 3.954      ;
; -0.304 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.885      ; 3.954      ;
; -0.304 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.885      ; 3.954      ;
; -0.304 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.885      ; 3.954      ;
; -0.304 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.885      ; 3.954      ;
; -0.304 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.885      ; 3.954      ;
; -0.294 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.883      ; 3.942      ;
; -0.293 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.883      ; 3.941      ;
; -0.293 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.883      ; 3.941      ;
; -0.293 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.883      ; 3.941      ;
; -0.293 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.883      ; 3.941      ;
; -0.293 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.883      ; 3.941      ;
; -0.293 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.883      ; 3.941      ;
; -0.293 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.883      ; 3.941      ;
; -0.293 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.883      ; 3.941      ;
; -0.293 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.883      ; 3.941      ;
; -0.293 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.883      ; 3.941      ;
; -0.293 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.883      ; 3.941      ;
; -0.293 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.883      ; 3.941      ;
; -0.293 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.883      ; 3.941      ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                    ;
+-------+---------------------------------------+----------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                                                                                            ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+----------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 7.912 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[0]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.143     ; 3.602      ;
; 7.912 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[1]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.143     ; 3.602      ;
; 7.912 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[2]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.143     ; 3.602      ;
; 7.912 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[3]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.143     ; 3.602      ;
; 7.912 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[4]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.143     ; 3.602      ;
; 7.912 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[5]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.143     ; 3.602      ;
; 7.912 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[6]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.143     ; 3.602      ;
; 7.954 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[2]                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.149     ; 3.554      ;
; 7.955 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|scl_ena                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 3.546      ;
; 7.955 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|ack_error                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 3.546      ;
; 7.959 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[14]                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.141     ; 3.557      ;
; 7.959 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[15]                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.141     ; 3.557      ;
; 7.959 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[13]                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.141     ; 3.557      ;
; 7.974 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[21]                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.143     ; 3.540      ;
; 7.974 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[19]                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.143     ; 3.540      ;
; 7.974 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[18]                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.143     ; 3.540      ;
; 7.978 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_select_reg[0]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.140     ; 3.539      ;
; 7.989 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.146     ; 3.522      ;
; 7.989 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[30]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.146     ; 3.522      ;
; 7.989 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[29]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.146     ; 3.522      ;
; 7.989 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[31]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.146     ; 3.522      ;
; 7.989 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[13]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.146     ; 3.522      ;
; 7.989 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[12]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.146     ; 3.522      ;
; 7.989 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[24]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.146     ; 3.522      ;
; 7.989 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[23]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.146     ; 3.522      ;
; 7.989 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[14]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.146     ; 3.522      ;
; 7.989 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[28]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.146     ; 3.522      ;
; 7.990 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[6]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.141     ; 3.526      ;
; 7.990 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[5]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.141     ; 3.526      ;
; 7.990 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[4]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.141     ; 3.526      ;
; 7.990 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[2]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.141     ; 3.526      ;
; 8.312 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[5]                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.149     ; 3.196      ;
; 8.312 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[8]                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.154     ; 3.191      ;
; 8.312 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[9]                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.154     ; 3.191      ;
; 8.312 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[29]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.154     ; 3.191      ;
; 8.312 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[0]                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.149     ; 3.196      ;
; 8.312 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.153     ; 3.192      ;
; 8.312 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.153     ; 3.192      ;
; 8.312 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[3]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.153     ; 3.192      ;
; 8.312 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.153     ; 3.192      ;
; 8.312 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[6]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.153     ; 3.192      ;
; 8.312 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.153     ; 3.192      ;
; 8.312 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[7]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.153     ; 3.192      ;
; 8.312 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.153     ; 3.192      ;
; 8.312 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[0]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.153     ; 3.192      ;
; 8.312 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.153     ; 3.192      ;
; 8.312 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[1]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.153     ; 3.192      ;
; 8.312 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.153     ; 3.192      ;
; 8.312 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.153     ; 3.192      ;
; 8.312 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[5]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.153     ; 3.192      ;
; 8.312 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[4]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.153     ; 3.192      ;
; 8.312 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[16]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.154     ; 3.191      ;
; 8.312 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rd[7]                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 3.180      ;
; 8.312 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rd[7]                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 3.180      ;
; 8.312 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[11]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 3.181      ;
; 8.312 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[10]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 3.181      ;
; 8.312 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[9]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 3.181      ;
; 8.312 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[8]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 3.181      ;
; 8.312 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rd[6]                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 3.180      ;
; 8.312 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[22]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.154     ; 3.191      ;
; 8.312 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rd[4]                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 3.180      ;
; 8.312 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rd[4]                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 3.181      ;
; 8.312 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rd[5]                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 3.180      ;
; 8.312 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rd[2]                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 3.181      ;
; 8.312 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rd[2]                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 3.180      ;
; 8.312 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rd[0]                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 3.180      ;
; 8.312 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rd[0]                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 3.180      ;
; 8.312 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rd[1]                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 3.180      ;
; 8.312 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rd[1]                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 3.180      ;
; 8.312 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rd[3]                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 3.180      ;
; 8.312 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rd[3]                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 3.180      ;
; 8.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[6]                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.152     ; 3.192      ;
; 8.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[4]                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.152     ; 3.192      ;
; 8.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[7]                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.152     ; 3.192      ;
; 8.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[6]                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.152     ; 3.192      ;
; 8.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[4]                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.152     ; 3.192      ;
; 8.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[0]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.163     ; 3.181      ;
; 8.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[30]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 3.182      ;
; 8.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[14]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 3.182      ;
; 8.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[15]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 3.182      ;
; 8.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[29]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.163     ; 3.181      ;
; 8.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[29]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.163     ; 3.181      ;
; 8.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[16]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.153     ; 3.191      ;
; 8.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[17]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.153     ; 3.191      ;
; 8.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[8]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.153     ; 3.191      ;
; 8.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[9]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.153     ; 3.191      ;
; 8.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[15]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.153     ; 3.191      ;
; 8.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[2]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.153     ; 3.191      ;
; 8.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[3]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.153     ; 3.191      ;
; 8.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[6]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.153     ; 3.191      ;
; 8.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[2]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.152     ; 3.192      ;
; 8.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|transmit_divisor_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.152     ; 3.192      ;
; 8.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|transmit_divisor_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.152     ; 3.192      ;
; 8.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|transmit_divisor_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.152     ; 3.192      ;
; 8.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|transmit_divisor_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.152     ; 3.192      ;
; 8.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|transmit_divisor_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.152     ; 3.192      ;
; 8.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|transmit_divisor_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.152     ; 3.192      ;
; 8.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|transmit_divisor_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.152     ; 3.192      ;
; 8.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|transmit_divisor_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.152     ; 3.192      ;
; 8.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[0]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.163     ; 3.181      ;
+-------+---------------------------------------+----------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                               ;
+-------+------------------------+----------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                      ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+----------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 8.066 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[7]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.249     ; 3.224      ;
; 8.129 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.177     ; 3.238      ;
; 8.129 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[11] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.177     ; 3.238      ;
; 8.130 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 3.239      ;
; 8.130 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 3.238      ;
; 8.130 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.177     ; 3.237      ;
; 8.130 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 3.236      ;
; 8.130 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 3.236      ;
; 8.139 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[8]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.305     ; 3.093      ;
; 8.139 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[9]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.312     ; 3.086      ;
; 8.143 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[15]     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.306     ; 3.088      ;
; 8.143 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[14]     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.306     ; 3.088      ;
; 8.143 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[13]     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.306     ; 3.088      ;
; 8.144 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[11]     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.307     ; 3.086      ;
; 8.144 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[10]     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.307     ; 3.086      ;
; 8.144 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[12]     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.307     ; 3.086      ;
; 8.149 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[0]    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.168     ; 3.227      ;
; 8.149 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[1]    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.168     ; 3.227      ;
; 8.150 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[0]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.168     ; 3.226      ;
; 8.150 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.168     ; 3.226      ;
; 8.150 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.168     ; 3.226      ;
; 8.151 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.164     ; 3.229      ;
; 8.151 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.164     ; 3.229      ;
; 8.153 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[7]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.164     ; 3.227      ;
; 8.155 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[5]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.289     ; 3.093      ;
; 8.155 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[8]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.198     ; 3.193      ;
; 8.155 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[9]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.205     ; 3.186      ;
; 8.156 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[4]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.306     ; 3.075      ;
; 8.159 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[2]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.294     ; 3.084      ;
; 8.159 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[0]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.294     ; 3.084      ;
; 8.159 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[1]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.294     ; 3.084      ;
; 8.159 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[13] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.199     ; 3.188      ;
; 8.159 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[14] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.199     ; 3.188      ;
; 8.159 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[15] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.199     ; 3.188      ;
; 8.160 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[6]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.296     ; 3.081      ;
; 8.160 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[10] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.200     ; 3.186      ;
; 8.160 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[11] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.200     ; 3.186      ;
; 8.160 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[12] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.200     ; 3.186      ;
; 8.161 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[3]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.287     ; 3.089      ;
; 8.171 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[5]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 3.193      ;
; 8.172 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[4]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.199     ; 3.175      ;
; 8.175 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[0]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.187     ; 3.184      ;
; 8.175 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[1]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.187     ; 3.184      ;
; 8.175 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[2]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.187     ; 3.184      ;
; 8.176 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[6]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 3.181      ;
; 8.177 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[3]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.180     ; 3.189      ;
; 8.189 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.144     ; 3.323      ;
; 8.246 ; sdram_reset_ctrl_n_reg ; ram_di_reg[3]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.165     ; 3.245      ;
; 8.246 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.165     ; 3.245      ;
; 8.246 ; sdram_reset_ctrl_n_reg ; ram_di_reg[6]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.165     ; 3.245      ;
; 8.246 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.165     ; 3.245      ;
; 8.246 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.165     ; 3.245      ;
; 8.246 ; sdram_reset_ctrl_n_reg ; ram_di_reg[14]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.165     ; 3.245      ;
; 8.246 ; sdram_reset_ctrl_n_reg ; ram_di_reg[15]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.165     ; 3.245      ;
; 8.251 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.162     ; 3.243      ;
; 8.254 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.165     ; 3.237      ;
; 8.254 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.165     ; 3.237      ;
; 8.254 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.163     ; 3.239      ;
; 8.254 ; sdram_reset_ctrl_n_reg ; ram_do_reg[19]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.163     ; 3.239      ;
; 8.254 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.163     ; 3.239      ;
; 8.254 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.163     ; 3.239      ;
; 8.254 ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.160     ; 3.242      ;
; 8.254 ; sdram_reset_ctrl_n_reg ; ram_do_reg[25]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.163     ; 3.239      ;
; 8.254 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.163     ; 3.239      ;
; 8.254 ; sdram_reset_ctrl_n_reg ; ram_do_reg[20]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.165     ; 3.237      ;
; 8.254 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.165     ; 3.237      ;
; 8.255 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.160     ; 3.241      ;
; 8.255 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.160     ; 3.241      ;
; 8.255 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.160     ; 3.241      ;
; 8.256 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.162     ; 3.238      ;
; 8.259 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.164     ; 3.233      ;
; 8.259 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.164     ; 3.233      ;
; 8.259 ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.164     ; 3.233      ;
; 8.259 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.164     ; 3.233      ;
; 8.259 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.164     ; 3.233      ;
; 8.259 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.161     ; 3.236      ;
; 8.260 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.163     ; 3.233      ;
; 8.261 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.155     ; 3.240      ;
; 8.261 ; sdram_reset_ctrl_n_reg ; ram_do_reg[5]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.155     ; 3.240      ;
; 8.261 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.155     ; 3.240      ;
; 8.261 ; sdram_reset_ctrl_n_reg ; ram_do_reg[13]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.155     ; 3.240      ;
; 8.261 ; sdram_reset_ctrl_n_reg ; ram_do_reg[12]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.155     ; 3.240      ;
; 8.261 ; sdram_reset_ctrl_n_reg ; ram_do_reg[10]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.155     ; 3.240      ;
; 8.261 ; sdram_reset_ctrl_n_reg ; ram_do_reg[9]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.155     ; 3.240      ;
; 8.261 ; sdram_reset_ctrl_n_reg ; ram_do_reg[8]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.155     ; 3.240      ;
; 8.321 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 3.047      ;
; 8.344 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.165     ; 3.035      ;
; 8.344 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.165     ; 3.035      ;
; 8.344 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.165     ; 3.035      ;
; 8.345 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.164     ; 3.035      ;
; 8.345 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.164     ; 3.035      ;
; 8.608 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.153     ; 2.895      ;
; 8.608 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.153     ; 2.895      ;
; 8.608 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.153     ; 2.895      ;
; 8.608 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.153     ; 2.895      ;
; 8.608 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.153     ; 2.895      ;
; 8.608 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_bctr[0]     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.163     ; 2.885      ;
; 8.608 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.163     ; 2.885      ;
; 8.608 ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.163     ; 2.885      ;
; 8.608 ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.163     ; 2.885      ;
+-------+------------------------+----------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                       ;
+--------+--------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                            ; To Node                               ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 13.404 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.178     ; 3.948      ;
; 13.404 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.178     ; 3.948      ;
; 13.404 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.178     ; 3.948      ;
; 13.404 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.178     ; 3.948      ;
; 13.404 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.178     ; 3.948      ;
; 13.404 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.178     ; 3.948      ;
; 13.404 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.178     ; 3.948      ;
; 13.404 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.178     ; 3.948      ;
; 13.414 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.176     ; 3.940      ;
; 13.414 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.176     ; 3.940      ;
; 13.414 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.176     ; 3.940      ;
; 13.414 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.176     ; 3.940      ;
; 13.414 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.176     ; 3.940      ;
; 13.414 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.176     ; 3.940      ;
+--------+--------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: 'FPGA_CLK'                                                                                                                                                                                                                                                                                 ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                            ; To Node                                                                     ; Launch Clock                                                                        ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.281 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.606      ; 3.662      ;
; -0.281 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.605      ; 3.661      ;
; -0.281 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.605      ; 3.661      ;
; -0.281 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.605      ; 3.661      ;
; -0.281 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.605      ; 3.661      ;
; -0.281 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.605      ; 3.661      ;
; -0.281 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.605      ; 3.661      ;
; -0.281 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.605      ; 3.661      ;
; -0.281 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.605      ; 3.661      ;
; -0.281 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.605      ; 3.661      ;
; -0.281 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.605      ; 3.661      ;
; -0.281 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.605      ; 3.661      ;
; -0.281 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.605      ; 3.661      ;
; -0.281 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.605      ; 3.661      ;
; -0.270 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.607      ; 3.674      ;
; -0.270 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.607      ; 3.674      ;
; -0.270 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.607      ; 3.674      ;
; -0.270 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.607      ; 3.674      ;
; -0.270 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.607      ; 3.674      ;
; -0.270 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.607      ; 3.674      ;
; -0.270 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.607      ; 3.674      ;
; -0.270 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.607      ; 3.674      ;
; -0.270 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.607      ; 3.674      ;
; -0.270 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.607      ; 3.674      ;
; -0.270 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.607      ; 3.674      ;
; -0.270 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.607      ; 3.674      ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                           ;
+-------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                            ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; 0.438 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.133      ; 2.967      ;
; 0.438 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.133      ; 2.967      ;
; 0.438 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.133      ; 2.967      ;
; 0.438 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.133      ; 2.967      ;
; 0.438 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.133      ; 2.967      ;
; 0.438 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.133      ; 2.967      ;
; 0.438 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.133      ; 2.967      ;
; 0.438 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.133      ; 2.967      ;
; 0.438 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.133      ; 2.967      ;
; 0.442 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.133      ; 2.854      ;
; 0.442 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.133      ; 2.854      ;
; 0.442 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.133      ; 2.854      ;
; 0.442 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.133      ; 2.854      ;
; 0.442 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.133      ; 2.854      ;
; 0.442 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.133      ; 2.854      ;
; 0.442 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.133      ; 2.854      ;
; 0.442 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.133      ; 2.854      ;
; 0.442 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.133      ; 2.854      ;
+-------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                         ; To Node                                                                                                                                                                                                               ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 1.577 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a47 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.305      ; 2.050      ;
; 1.577 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a46 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.305      ; 2.050      ;
; 1.577 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a45 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.305      ; 2.050      ;
; 1.577 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a44 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.305      ; 2.050      ;
; 1.577 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a43 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.305      ; 2.050      ;
; 1.577 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a42 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.305      ; 2.050      ;
; 1.577 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a41 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.305      ; 2.050      ;
; 1.577 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a40 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.305      ; 2.050      ;
; 1.577 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a35 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.305      ; 2.050      ;
; 1.577 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a34 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.305      ; 2.050      ;
; 1.577 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a33 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.305      ; 2.050      ;
; 1.577 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a32 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.305      ; 2.050      ;
; 1.577 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a15 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.305      ; 2.050      ;
; 1.577 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a14 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.305      ; 2.050      ;
; 1.577 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a13 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.305      ; 2.050      ;
; 1.577 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a12 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.305      ; 2.050      ;
; 1.577 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a11 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.305      ; 2.050      ;
; 1.577 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a10 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.305      ; 2.050      ;
; 1.577 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a9  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.305      ; 2.050      ;
; 1.577 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a8  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.305      ; 2.050      ;
; 1.577 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a7  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.305      ; 2.050      ;
; 1.577 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a6  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.305      ; 2.050      ;
; 1.577 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a5  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.305      ; 2.050      ;
; 1.577 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a4  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.305      ; 2.050      ;
; 1.577 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a3  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.305      ; 2.050      ;
; 1.577 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a2  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.305      ; 2.050      ;
; 1.577 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a1  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.305      ; 2.050      ;
; 1.577 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.305      ; 2.050      ;
; 1.859 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a63 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.304      ; 2.331      ;
; 1.859 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a62 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.304      ; 2.331      ;
; 1.859 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a61 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.304      ; 2.331      ;
; 1.859 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a60 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.304      ; 2.331      ;
; 1.859 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a59 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.304      ; 2.331      ;
; 1.859 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a58 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.304      ; 2.331      ;
; 1.859 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a57 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.304      ; 2.331      ;
; 1.859 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a56 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.304      ; 2.331      ;
; 1.859 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a55 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.304      ; 2.331      ;
; 1.859 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a54 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.304      ; 2.331      ;
; 1.859 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a53 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.304      ; 2.331      ;
; 1.859 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a52 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.304      ; 2.331      ;
; 1.859 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a51 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.304      ; 2.331      ;
; 1.859 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a50 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.304      ; 2.331      ;
; 1.859 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a49 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.304      ; 2.331      ;
; 1.859 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a48 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.304      ; 2.331      ;
; 1.859 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a39 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.304      ; 2.331      ;
; 1.859 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a38 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.304      ; 2.331      ;
; 1.859 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a37 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.304      ; 2.331      ;
; 1.859 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a36 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.304      ; 2.331      ;
; 1.859 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a31 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.304      ; 2.331      ;
; 1.859 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a30 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.304      ; 2.331      ;
; 1.859 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a29 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.304      ; 2.331      ;
; 1.859 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a28 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.304      ; 2.331      ;
; 1.859 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a27 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.304      ; 2.331      ;
; 1.859 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a26 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.304      ; 2.331      ;
; 1.859 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a25 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.304      ; 2.331      ;
; 1.859 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a24 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.304      ; 2.331      ;
; 1.859 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a23 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.304      ; 2.331      ;
; 1.859 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a22 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.304      ; 2.331      ;
; 1.859 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a21 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.304      ; 2.331      ;
; 1.859 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a20 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.304      ; 2.331      ;
; 1.859 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a19 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.304      ; 2.331      ;
; 1.859 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a18 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.304      ; 2.331      ;
; 1.859 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a17 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.304      ; 2.331      ;
; 1.859 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.304      ; 2.331      ;
; 2.152 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[3]                                                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.532      ; 2.855      ;
; 2.152 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[1]                                                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.532      ; 2.855      ;
; 2.154 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[3]                                                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.532      ; 2.968      ;
; 2.154 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[1]                                                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.532      ; 2.968      ;
; 2.516 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[26]                                                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.150      ; 2.837      ;
; 2.516 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[30]                                                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.151      ; 2.838      ;
; 2.516 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[27]                                                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.152      ; 2.839      ;
; 2.516 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[29]                                                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.150      ; 2.837      ;
; 2.516 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[31]                                                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.152      ; 2.839      ;
; 2.516 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[19]                                                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.152      ; 2.839      ;
; 2.516 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[24]                                                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.152      ; 2.839      ;
; 2.516 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[21]                                                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.151      ; 2.838      ;
; 2.516 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[23]                                                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.151      ; 2.838      ;
; 2.516 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[18]                                                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.151      ; 2.838      ;
; 2.516 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[15]                                                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.155      ; 2.842      ;
; 2.516 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[22]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.164      ; 2.851      ;
; 2.516 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[22]                                                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.152      ; 2.839      ;
; 2.516 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[4]                                                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.163      ; 2.850      ;
; 2.516 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[17]                                                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.155      ; 2.842      ;
; 2.516 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[5]                                                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.163      ; 2.850      ;
; 2.516 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[25]                                                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.152      ; 2.839      ;
; 2.516 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[16]                                                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.152      ; 2.839      ;
; 2.516 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[2]                                                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.163      ; 2.850      ;
; 2.516 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[20]                                                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.150      ; 2.837      ;
; 2.516 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[28]                                                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.150      ; 2.837      ;
; 2.516 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[3]                                                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.163      ; 2.850      ;
; 2.517 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]                                                                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.163      ; 2.851      ;
; 2.517 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                                                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.163      ; 2.851      ;
; 2.517 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[8]                                                                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.163      ; 2.851      ;
; 2.517 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[19]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.159      ; 2.847      ;
; 2.517 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[19]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.159      ; 2.847      ;
; 2.517 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[10]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.152      ; 2.840      ;
; 2.517 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[11]                                                                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.163      ; 2.851      ;
; 2.517 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[18]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.159      ; 2.847      ;
; 2.517 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[18]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.159      ; 2.847      ;
; 2.517 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[20]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.159      ; 2.847      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                             ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 2.293 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.144      ; 2.717      ;
; 2.294 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.148      ; 2.722      ;
; 2.294 ; sdram_reset_ctrl_n_reg ; ram_do_reg[15]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.148      ; 2.722      ;
; 2.294 ; sdram_reset_ctrl_n_reg ; ram_do_reg[14]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.148      ; 2.722      ;
; 2.294 ; sdram_reset_ctrl_n_reg ; ram_do_reg[11]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.148      ; 2.722      ;
; 2.295 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.151      ; 2.726      ;
; 2.296 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.142      ; 2.718      ;
; 2.297 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.143      ; 2.720      ;
; 2.297 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.143      ; 2.720      ;
; 2.297 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.143      ; 2.720      ;
; 2.297 ; sdram_reset_ctrl_n_reg ; seq_reg[5]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.143      ; 2.720      ;
; 2.297 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.151      ; 2.728      ;
; 2.297 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.151      ; 2.728      ;
; 2.297 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.151      ; 2.728      ;
; 2.297 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.151      ; 2.728      ;
; 2.297 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.151      ; 2.728      ;
; 2.297 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.151      ; 2.728      ;
; 2.297 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.151      ; 2.728      ;
; 2.297 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.151      ; 2.728      ;
; 2.297 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.151      ; 2.728      ;
; 2.297 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.151      ; 2.728      ;
; 2.297 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.151      ; 2.728      ;
; 2.297 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.151      ; 2.728      ;
; 2.297 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.151      ; 2.728      ;
; 2.297 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.151      ; 2.728      ;
; 2.297 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.151      ; 2.728      ;
; 2.297 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.151      ; 2.728      ;
; 2.298 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.142      ; 2.720      ;
; 2.298 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.142      ; 2.720      ;
; 2.298 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.142      ; 2.720      ;
; 2.298 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.142      ; 2.720      ;
; 2.298 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.142      ; 2.720      ;
; 2.298 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.142      ; 2.720      ;
; 2.298 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.142      ; 2.720      ;
; 2.298 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.142      ; 2.720      ;
; 2.298 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.143      ; 2.721      ;
; 2.298 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.143      ; 2.721      ;
; 2.298 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.143      ; 2.721      ;
; 2.298 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.143      ; 2.721      ;
; 2.298 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.143      ; 2.721      ;
; 2.298 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.143      ; 2.721      ;
; 2.298 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.143      ; 2.721      ;
; 2.298 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.143      ; 2.721      ;
; 2.298 ; sdram_reset_ctrl_n_reg ; ram_di_reg[5]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.143      ; 2.721      ;
; 2.299 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.140      ; 2.719      ;
; 2.299 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.140      ; 2.719      ;
; 2.299 ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.140      ; 2.719      ;
; 2.299 ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.140      ; 2.719      ;
; 2.299 ; sdram_reset_ctrl_n_reg ; ram_di_reg[11]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.140      ; 2.719      ;
; 2.299 ; sdram_reset_ctrl_n_reg ; ram_di_reg[12]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.140      ; 2.719      ;
; 2.299 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[1]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.140      ; 2.719      ;
; 2.299 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[0]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.140      ; 2.719      ;
; 2.300 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 2.735      ;
; 2.300 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 2.735      ;
; 2.300 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 2.735      ;
; 2.523 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.120      ; 2.849      ;
; 2.523 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.120      ; 2.849      ;
; 2.523 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.120      ; 2.849      ;
; 2.524 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.120      ; 2.850      ;
; 2.524 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.120      ; 2.850      ;
; 2.546 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.109      ; 2.861      ;
; 2.609 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.148      ; 3.037      ;
; 2.609 ; sdram_reset_ctrl_n_reg ; ram_do_reg[5]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.148      ; 3.037      ;
; 2.609 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.148      ; 3.037      ;
; 2.609 ; sdram_reset_ctrl_n_reg ; ram_do_reg[13]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.148      ; 3.037      ;
; 2.609 ; sdram_reset_ctrl_n_reg ; ram_do_reg[12]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.148      ; 3.037      ;
; 2.609 ; sdram_reset_ctrl_n_reg ; ram_do_reg[10]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.148      ; 3.037      ;
; 2.609 ; sdram_reset_ctrl_n_reg ; ram_do_reg[9]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.148      ; 3.037      ;
; 2.609 ; sdram_reset_ctrl_n_reg ; ram_do_reg[8]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.148      ; 3.037      ;
; 2.610 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.139      ; 3.029      ;
; 2.610 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.139      ; 3.029      ;
; 2.610 ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.139      ; 3.029      ;
; 2.610 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.139      ; 3.029      ;
; 2.610 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.139      ; 3.029      ;
; 2.612 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.140      ; 3.032      ;
; 2.612 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.142      ; 3.034      ;
; 2.614 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.144      ; 3.038      ;
; 2.614 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.144      ; 3.038      ;
; 2.614 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.144      ; 3.038      ;
; 2.615 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.141      ; 3.036      ;
; 2.618 ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.144      ; 3.042      ;
; 2.619 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.138      ; 3.037      ;
; 2.619 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.138      ; 3.037      ;
; 2.619 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.140      ; 3.039      ;
; 2.619 ; sdram_reset_ctrl_n_reg ; ram_do_reg[19]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.140      ; 3.039      ;
; 2.619 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.140      ; 3.039      ;
; 2.619 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.140      ; 3.039      ;
; 2.619 ; sdram_reset_ctrl_n_reg ; ram_do_reg[25]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.140      ; 3.039      ;
; 2.619 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.140      ; 3.039      ;
; 2.619 ; sdram_reset_ctrl_n_reg ; ram_do_reg[20]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.138      ; 3.037      ;
; 2.619 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.138      ; 3.037      ;
; 2.624 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.141      ; 3.045      ;
; 2.624 ; sdram_reset_ctrl_n_reg ; ram_di_reg[3]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.138      ; 3.042      ;
; 2.624 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.138      ; 3.042      ;
; 2.624 ; sdram_reset_ctrl_n_reg ; ram_di_reg[6]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.138      ; 3.042      ;
; 2.624 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.138      ; 3.042      ;
; 2.624 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.138      ; 3.042      ;
; 2.624 ; sdram_reset_ctrl_n_reg ; ram_di_reg[14]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.138      ; 3.042      ;
; 2.624 ; sdram_reset_ctrl_n_reg ; ram_di_reg[15]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.138      ; 3.042      ;
; 2.677 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.160      ; 3.117      ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                       ;
+-------+--------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                            ; To Node                               ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 3.253 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.127      ; 3.661      ;
; 3.253 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.127      ; 3.661      ;
; 3.253 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.127      ; 3.661      ;
; 3.253 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.127      ; 3.661      ;
; 3.253 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.127      ; 3.661      ;
; 3.253 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.127      ; 3.661      ;
; 3.263 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.125      ; 3.669      ;
; 3.263 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.125      ; 3.669      ;
; 3.263 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.125      ; 3.669      ;
; 3.263 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.125      ; 3.669      ;
; 3.263 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.125      ; 3.669      ;
; 3.263 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.125      ; 3.669      ;
; 3.263 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.125      ; 3.669      ;
; 3.263 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.125      ; 3.669      ;
+-------+--------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                         ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                               ; Clock Edge ; Target                                                    ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; 5.595 ; 5.813        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[0]                                             ;
; 5.595 ; 5.813        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[1]                                             ;
; 5.595 ; 5.813        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[2]                                             ;
; 5.595 ; 5.813        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[17]                                            ;
; 5.595 ; 5.813        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[2]                                             ;
; 5.595 ; 5.813        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ;
; 5.595 ; 5.813        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ;
; 5.595 ; 5.813        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ;
; 5.595 ; 5.813        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ;
; 5.595 ; 5.813        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ;
; 5.595 ; 5.813        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ;
; 5.595 ; 5.813        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ;
; 5.595 ; 5.813        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ;
; 5.595 ; 5.813        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ;
; 5.595 ; 5.813        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ;
; 5.595 ; 5.813        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ;
; 5.595 ; 5.813        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ;
; 5.595 ; 5.813        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ;
; 5.595 ; 5.813        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ;
; 5.595 ; 5.813        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ;
; 5.595 ; 5.813        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|sdram_rdy                     ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[0]                                           ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[1]                                           ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[10]                                            ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[11]                                            ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[12]                                            ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[13]                                            ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[14]                                            ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[15]                                            ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[3]                                             ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[4]                                             ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[5]                                             ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[6]                                             ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[7]                                             ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[8]                                             ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[9]                                             ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[16]                                            ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[18]                                            ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[19]                                            ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[21]                                            ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[22]                                            ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[23]                                            ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[24]                                            ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[25]                                            ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[27]                                            ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[30]                                            ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[31]                                            ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[6]                                             ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel[0]                     ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_act                      ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_act                    ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_req                    ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_act                      ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_complete_reg                                ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_reg                                         ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[0]                                                ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[10]                                               ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[11]                                               ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[1]                                                ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[2]                                                ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[3]                                                ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[4]                                                ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[5]                                                ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[6]                                                ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[7]                                                ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[8]                                                ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[9]                                                ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[0]                                             ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[10]                                            ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[11]                                            ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[12]                                            ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[13]                                            ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[14]                                            ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[15]                                            ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[20]                                            ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[26]                                            ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[28]                                            ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[29]                                            ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[3]                                             ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[4]                                             ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[5]                                             ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[8]                                             ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[9]                                             ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[1]                                             ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[7]                                             ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_reg                      ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_reg                      ;
; 5.669 ; 5.825        ; 0.156          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[3]                   ;
; 5.669 ; 5.825        ; 0.156          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[5]                   ;
; 5.670 ; 5.826        ; 0.156          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[0]                   ;
; 5.670 ; 5.826        ; 0.156          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[10]                  ;
; 5.670 ; 5.826        ; 0.156          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[11]                  ;
; 5.670 ; 5.826        ; 0.156          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[12]                  ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                   ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                               ; Clock Edge ; Target                                                                                                                                              ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; 5.733 ; 5.848        ; 0.115          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 5.801 ; 5.897        ; 0.096          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 5.848 ; 5.848        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 5.897 ; 5.897        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                    ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                               ; Clock Edge ; Target                                                                                                                                              ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; 8.533  ; 8.751        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ;
; 8.533  ; 8.751        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ;
; 8.533  ; 8.751        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ;
; 8.533  ; 8.751        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ;
; 8.533  ; 8.751        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ;
; 8.533  ; 8.751        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ;
; 8.533  ; 8.751        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ;
; 8.533  ; 8.751        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ;
; 8.535  ; 8.753        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[2]                                                                                                               ;
; 8.535  ; 8.753        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[3]                                                                                                               ;
; 8.535  ; 8.753        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[4]                                                                                                               ;
; 8.535  ; 8.753        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[5]                                                                                                               ;
; 8.535  ; 8.753        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[6]                                                                                                               ;
; 8.535  ; 8.753        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[7]                                                                                                               ;
; 8.670  ; 8.785        ; 0.115          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 8.678  ; 8.864        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[2]                                                                                                               ;
; 8.678  ; 8.864        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[3]                                                                                                               ;
; 8.678  ; 8.864        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[4]                                                                                                               ;
; 8.678  ; 8.864        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[5]                                                                                                               ;
; 8.678  ; 8.864        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[6]                                                                                                               ;
; 8.678  ; 8.864        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[7]                                                                                                               ;
; 8.680  ; 8.866        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ;
; 8.680  ; 8.866        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ;
; 8.680  ; 8.866        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ;
; 8.680  ; 8.866        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ;
; 8.680  ; 8.866        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ;
; 8.680  ; 8.866        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ;
; 8.680  ; 8.866        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ;
; 8.680  ; 8.866        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ;
; 8.738  ; 8.834        ; 0.096          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 8.785  ; 8.785        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 8.785  ; 8.785        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|outclk                                                 ;
; 8.791  ; 8.791        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[0]|clk                                                                                                                              ;
; 8.791  ; 8.791        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[1]|clk                                                                                                                              ;
; 8.791  ; 8.791        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[2]|clk                                                                                                                              ;
; 8.791  ; 8.791        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[3]|clk                                                                                                                              ;
; 8.791  ; 8.791        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[4]|clk                                                                                                                              ;
; 8.791  ; 8.791        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[5]|clk                                                                                                                              ;
; 8.791  ; 8.791        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[6]|clk                                                                                                                              ;
; 8.791  ; 8.791        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[7]|clk                                                                                                                              ;
; 8.793  ; 8.793        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[2]|clk                                                                                                                       ;
; 8.793  ; 8.793        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[3]|clk                                                                                                                       ;
; 8.793  ; 8.793        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[4]|clk                                                                                                                       ;
; 8.793  ; 8.793        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[5]|clk                                                                                                                       ;
; 8.793  ; 8.793        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[6]|clk                                                                                                                       ;
; 8.793  ; 8.793        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[7]|clk                                                                                                                       ;
; 8.826  ; 8.826        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[2]|clk                                                                                                                       ;
; 8.826  ; 8.826        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[3]|clk                                                                                                                       ;
; 8.826  ; 8.826        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[4]|clk                                                                                                                       ;
; 8.826  ; 8.826        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[5]|clk                                                                                                                       ;
; 8.826  ; 8.826        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[6]|clk                                                                                                                       ;
; 8.826  ; 8.826        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[7]|clk                                                                                                                       ;
; 8.828  ; 8.828        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[0]|clk                                                                                                                              ;
; 8.828  ; 8.828        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[1]|clk                                                                                                                              ;
; 8.828  ; 8.828        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[2]|clk                                                                                                                              ;
; 8.828  ; 8.828        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[3]|clk                                                                                                                              ;
; 8.828  ; 8.828        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[4]|clk                                                                                                                              ;
; 8.828  ; 8.828        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[5]|clk                                                                                                                              ;
; 8.828  ; 8.828        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[6]|clk                                                                                                                              ;
; 8.828  ; 8.828        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[7]|clk                                                                                                                              ;
; 8.834  ; 8.834        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 8.834  ; 8.834        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|outclk                                                 ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[2]                                                                                                               ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[3]                                                                                                               ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[4]                                                                                                               ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[5]                                                                                                               ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[6]                                                                                                               ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[7]                                                                                                               ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                             ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                               ; Clock Edge ; Target                                                                                                                                                                                                       ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 9.380  ; 10.400       ; 1.020          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                  ;
; 9.412  ; 10.432       ; 1.020          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                  ;
; 10.118 ; 10.336       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[4]                                      ;
; 10.118 ; 10.336       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[6]                                      ;
; 10.119 ; 10.337       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[0]                                         ;
; 10.119 ; 10.337       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[1]                                         ;
; 10.119 ; 10.337       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[2]                                         ;
; 10.119 ; 10.337       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[3]                                         ;
; 10.119 ; 10.337       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[4]                                         ;
; 10.119 ; 10.337       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[5]                                         ;
; 10.119 ; 10.337       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[7]                                         ;
; 10.119 ; 10.337       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[0]                                 ;
; 10.119 ; 10.337       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[1]                                 ;
; 10.124 ; 10.342       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[3]                                                             ;
; 10.124 ; 10.342       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[4]                                                             ;
; 10.124 ; 10.342       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[5]                                                             ;
; 10.124 ; 10.342       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[6]                                                             ;
; 10.124 ; 10.342       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[7]                                                             ;
; 10.127 ; 10.345       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]                               ;
; 10.127 ; 10.345       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1]                               ;
; 10.129 ; 10.347       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]                               ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg   ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg   ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[0]                                      ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[1]                                      ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[2]                                      ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[3]                                      ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[4]                                      ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[5]                                      ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[6]                                      ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[7]                                      ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[0]                                   ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[1]                                   ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[2]                                   ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[3]                                   ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[4]                                   ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[5]                                   ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[6]                                   ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[7]                                   ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0000       ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0000    ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0011    ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg2  ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireEdgeDetect  ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferInIndex[0]  ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferInIndex[1]  ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|incBufferCnt      ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|noActivityTimeOut ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[0]    ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[1]    ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[2]    ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[3]    ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[4]    ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[5]    ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[6]    ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[7]    ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[0]     ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[10]    ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[11]    ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[12]    ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[13]    ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[14]    ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[15]    ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[1]     ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[2]     ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[3]     ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[4]     ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[5]     ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[6]     ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[7]     ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[8]     ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[9]     ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00011                            ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00100                            ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00110                            ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00111                            ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01000                            ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01001                            ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[4]                                   ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[6]                                   ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[0]    ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[1]    ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[2]    ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[3]    ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[4]    ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[5]    ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[6]    ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[7]    ;
; 10.142 ; 10.360       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                   ;
; 10.142 ; 10.360       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[1]                                   ;
; 10.142 ; 10.360       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                           ;
; 10.142 ; 10.360       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                           ;
; 10.142 ; 10.360       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                           ;
; 10.142 ; 10.360       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                           ;
; 10.142 ; 10.360       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                           ;
; 10.142 ; 10.360       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                           ;
; 10.142 ; 10.360       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoFull                                                               ;
; 10.142 ; 10.360       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[0]                                                             ;
; 10.142 ; 10.360       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[1]                                                             ;
; 10.142 ; 10.360       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[2]                                                             ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                   ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                               ; Clock Edge ; Target                                                                                                                                                                                             ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 17.284 ; 17.614       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[0]                                          ;
; 17.284 ; 17.614       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[1]                                          ;
; 17.284 ; 17.614       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[2]                                          ;
; 17.284 ; 17.614       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[3]                                          ;
; 17.284 ; 17.614       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[4]                                          ;
; 17.284 ; 17.614       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[10]                                               ;
; 17.284 ; 17.614       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[11]                                               ;
; 17.284 ; 17.614       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[12]                                               ;
; 17.284 ; 17.614       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[13]                                               ;
; 17.284 ; 17.614       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[14]                                               ;
; 17.284 ; 17.614       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[15]                                               ;
; 17.284 ; 17.614       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[16]                                               ;
; 17.284 ; 17.614       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[17]                                               ;
; 17.284 ; 17.614       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[18]                                               ;
; 17.284 ; 17.614       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[19]                                               ;
; 17.284 ; 17.614       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[20]                                               ;
; 17.284 ; 17.614       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[5]                                                ;
; 17.284 ; 17.614       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[6]                                                ;
; 17.284 ; 17.614       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[7]                                                ;
; 17.284 ; 17.614       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[8]                                                ;
; 17.284 ; 17.614       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[9]                                                ;
; 17.285 ; 17.615       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[0]                                          ;
; 17.285 ; 17.615       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[1]                                          ;
; 17.285 ; 17.615       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[2]                                          ;
; 17.285 ; 17.615       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[3]                                          ;
; 17.285 ; 17.615       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[4]                                          ;
; 17.285 ; 17.615       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[10]                                               ;
; 17.285 ; 17.615       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[11]                                               ;
; 17.285 ; 17.615       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[12]                                               ;
; 17.285 ; 17.615       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[13]                                               ;
; 17.285 ; 17.615       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[14]                                               ;
; 17.285 ; 17.615       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[15]                                               ;
; 17.285 ; 17.615       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[16]                                               ;
; 17.285 ; 17.615       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[17]                                               ;
; 17.285 ; 17.615       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[18]                                               ;
; 17.285 ; 17.615       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[19]                                               ;
; 17.285 ; 17.615       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[20]                                               ;
; 17.285 ; 17.615       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[5]                                                ;
; 17.285 ; 17.615       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[6]                                                ;
; 17.285 ; 17.615       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[7]                                                ;
; 17.285 ; 17.615       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[8]                                                ;
; 17.285 ; 17.615       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[9]                                                ;
; 17.317 ; 17.535       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                  ;
; 17.317 ; 17.535       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                  ;
; 17.317 ; 17.535       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                  ;
; 17.317 ; 17.535       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                  ;
; 17.317 ; 17.535       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                  ;
; 17.317 ; 17.535       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                  ;
; 17.317 ; 17.535       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                  ;
; 17.321 ; 17.539       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[2]                                                                                                          ;
; 17.323 ; 17.541       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[8]            ;
; 17.323 ; 17.541       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[9]            ;
; 17.323 ; 17.541       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[14]      ;
; 17.323 ; 17.541       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[15]      ;
; 17.323 ; 17.541       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[8]       ;
; 17.323 ; 17.541       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[9]       ;
; 17.323 ; 17.541       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB[0]      ;
; 17.323 ; 17.541       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB[1]      ;
; 17.323 ; 17.541       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[0] ;
; 17.323 ; 17.541       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[1] ;
; 17.323 ; 17.541       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[7]       ;
; 17.323 ; 17.541       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[7]  ;
; 17.325 ; 17.543       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[4]       ;
; 17.325 ; 17.543       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[5]       ;
; 17.325 ; 17.543       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[6]       ;
; 17.325 ; 17.543       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[2]  ;
; 17.325 ; 17.543       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[4]  ;
; 17.325 ; 17.543       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[5]  ;
; 17.325 ; 17.543       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[6]  ;
; 17.325 ; 17.543       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[13]           ;
; 17.325 ; 17.543       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[4]          ;
; 17.325 ; 17.543       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[5]          ;
; 17.326 ; 17.544       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[1]       ;
; 17.326 ; 17.544       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[7]       ;
; 17.326 ; 17.544       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[0]  ;
; 17.326 ; 17.544       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[1]  ;
; 17.326 ; 17.544       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[3]  ;
; 17.326 ; 17.544       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[7]  ;
; 17.326 ; 17.544       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[4]       ;
; 17.326 ; 17.544       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[5]       ;
; 17.326 ; 17.544       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[2]  ;
; 17.326 ; 17.544       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[4]  ;
; 17.326 ; 17.544       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[5]  ;
; 17.327 ; 17.545       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[0]             ;
; 17.327 ; 17.545       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[1]             ;
; 17.327 ; 17.545       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[2]             ;
; 17.327 ; 17.545       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[0]        ;
; 17.327 ; 17.545       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[1]        ;
; 17.327 ; 17.545       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[2]        ;
; 17.327 ; 17.545       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[3]        ;
; 17.327 ; 17.545       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInSTB[2]           ;
; 17.327 ; 17.545       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[13]           ;
; 17.327 ; 17.545       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[8]            ;
; 17.327 ; 17.545       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[11]      ;
; 17.327 ; 17.545       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[13]      ;
; 17.327 ; 17.545       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[8]       ;
; 17.327 ; 17.545       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB[0]      ;
; 17.327 ; 17.545       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[0] ;
; 17.327 ; 17.545       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[1] ;
; 17.328 ; 17.546       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[1]             ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                         ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                              ; Clock Edge ; Target                                                                                                   ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------+
; 17.589 ; 17.589       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.589 ; 17.589       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.589 ; 17.589       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.589 ; 17.589       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]                      ;
; 17.589 ; 17.589       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 17.596 ; 17.596       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.596 ; 17.596       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.605 ; 17.605       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.637 ; 17.637       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.645 ; 17.645       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.645 ; 17.645       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.652 ; 17.652       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.652 ; 17.652       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.652 ; 17.652       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.652 ; 17.652       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]                      ;
; 17.652 ; 17.652       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'                                                                                                                              ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------------+
; Slack   ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                                                       ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------------+
; 89.643  ; 99.844       ; 10.201         ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout        ;
; 89.954  ; 100.155      ; 10.201         ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout        ;
; 99.682  ; 99.868       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                                   ;
; 99.682  ; 99.868       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                                  ;
; 99.682  ; 99.868       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                                  ;
; 99.682  ; 99.868       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                                   ;
; 99.682  ; 99.868       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                                   ;
; 99.682  ; 99.868       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                                   ;
; 99.682  ; 99.868       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                                   ;
; 99.682  ; 99.868       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                                   ;
; 99.682  ; 99.868       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                                   ;
; 99.682  ; 99.868       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                                   ;
; 99.682  ; 99.868       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                                   ;
; 99.682  ; 99.868       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                                   ;
; 99.682  ; 99.868       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8                  ;
; 99.682  ; 99.868       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]              ;
; 99.682  ; 99.868       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1]              ;
; 99.682  ; 99.868       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]              ;
; 99.683  ; 99.869       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                                  ;
; 99.683  ; 99.869       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                                  ;
; 99.683  ; 99.869       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                                  ;
; 99.683  ; 99.869       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                                  ;
; 99.683  ; 99.869       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                                  ;
; 99.683  ; 99.869       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                                  ;
; 99.683  ; 99.869       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                                  ;
; 99.683  ; 99.869       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                                  ;
; 99.683  ; 99.869       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                                  ;
; 99.683  ; 99.869       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                                  ;
; 99.683  ; 99.869       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                                  ;
; 99.683  ; 99.869       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                                  ;
; 99.683  ; 99.869       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                                  ;
; 99.778  ; 99.778       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                          ;
; 99.778  ; 99.778       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|observablevcoout                                ;
; 99.779  ; 99.779       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 99.779  ; 99.779       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 99.828  ; 99.828       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                             ;
; 99.830  ; 99.830       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[0]|clk                                        ;
; 99.830  ; 99.830       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[1]|clk                                        ;
; 99.830  ; 99.830       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[2]|clk                                        ;
; 99.830  ; 99.830       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[0]|clk                                                ;
; 99.830  ; 99.830       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[10]|clk                                               ;
; 99.830  ; 99.830       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[11]|clk                                               ;
; 99.830  ; 99.830       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[12]|clk                                               ;
; 99.830  ; 99.830       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[13]|clk                                               ;
; 99.830  ; 99.830       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[14]|clk                                               ;
; 99.830  ; 99.830       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[15]|clk                                               ;
; 99.830  ; 99.830       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[16]|clk                                               ;
; 99.830  ; 99.830       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[17]|clk                                               ;
; 99.830  ; 99.830       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[18]|clk                                               ;
; 99.830  ; 99.830       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[19]|clk                                               ;
; 99.830  ; 99.830       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[1]|clk                                                ;
; 99.830  ; 99.830       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[20]|clk                                               ;
; 99.830  ; 99.830       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[21]|clk                                               ;
; 99.830  ; 99.830       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[22]|clk                                               ;
; 99.830  ; 99.830       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[23]|clk                                               ;
; 99.830  ; 99.830       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[24]|clk                                               ;
; 99.830  ; 99.830       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[2]|clk                                                ;
; 99.830  ; 99.830       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[3]|clk                                                ;
; 99.830  ; 99.830       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[4]|clk                                                ;
; 99.830  ; 99.830       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[5]|clk                                                ;
; 99.830  ; 99.830       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[6]|clk                                                ;
; 99.830  ; 99.830       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[7]|clk                                                ;
; 99.830  ; 99.830       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[8]|clk                                                ;
; 99.830  ; 99.830       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[9]|clk                                                ;
; 99.830  ; 99.830       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|remote|dffe8|clk                                                         ;
; 99.835  ; 99.835       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~inputclkctrl|inclk[0]                                                               ;
; 99.835  ; 99.835       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~inputclkctrl|outclk                                                                 ;
; 99.844  ; 99.844       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|remote|sd4|clk                                                           ;
; 99.856  ; 99.856       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|inclk[0]                                        ;
; 99.857  ; 99.857       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 99.912  ; 100.130      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                                   ;
; 99.912  ; 100.130      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                                  ;
; 99.912  ; 100.130      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                                  ;
; 99.912  ; 100.130      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                                  ;
; 99.912  ; 100.130      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                                  ;
; 99.912  ; 100.130      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                                  ;
; 99.912  ; 100.130      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                                  ;
; 99.912  ; 100.130      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                                  ;
; 99.912  ; 100.130      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                                  ;
; 99.912  ; 100.130      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                                  ;
; 99.912  ; 100.130      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                                  ;
; 99.912  ; 100.130      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                                   ;
; 99.912  ; 100.130      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                                  ;
; 99.912  ; 100.130      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                                  ;
; 99.912  ; 100.130      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                                  ;
; 99.912  ; 100.130      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                                  ;
; 99.912  ; 100.130      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                                  ;
; 99.912  ; 100.130      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                                   ;
; 99.912  ; 100.130      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                                   ;
; 99.912  ; 100.130      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                                   ;
; 99.912  ; 100.130      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                                   ;
; 99.912  ; 100.130      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                                   ;
; 99.912  ; 100.130      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                                   ;
; 99.912  ; 100.130      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                                   ;
; 99.912  ; 100.130      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                                   ;
; 99.912  ; 100.130      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8                  ;
; 99.912  ; 100.130      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]              ;
; 99.912  ; 100.130      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1]              ;
; 99.912  ; 100.130      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]              ;
; 100.000 ; 100.000      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                             ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                                   ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.441 ; 2.612 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.423 ; 2.594 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.423 ; 2.594 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.423 ; 2.594 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.416 ; 2.587 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.435 ; 2.606 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.418 ; 2.589 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.425 ; 2.596 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.375 ; 2.545 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.434 ; 2.605 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.441 ; 2.612 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.436 ; 2.607 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.436 ; 2.607 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.436 ; 2.607 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.435 ; 2.606 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.435 ; 2.606 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.435 ; 2.606 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_DAT0       ; FPGA_CLK   ; 3.205 ; 3.432 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 0.683 ; 0.854 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 0.688 ; 0.859 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 0.691 ; 0.862 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 0.686 ; 0.857 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                      ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; -1.604 ; -1.774 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; -1.646 ; -1.817 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; -1.646 ; -1.817 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; -1.646 ; -1.817 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; -1.639 ; -1.810 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; -1.658 ; -1.829 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; -1.641 ; -1.812 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; -1.649 ; -1.820 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; -1.604 ; -1.774 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; -1.657 ; -1.828 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; -1.664 ; -1.835 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; -1.660 ; -1.831 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; -1.660 ; -1.831 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; -1.660 ; -1.831 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; -1.658 ; -1.829 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; -1.658 ; -1.829 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; -1.658 ; -1.829 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_DAT0       ; FPGA_CLK   ; -2.348 ; -2.566 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; -0.132 ; -0.303 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; -0.138 ; -0.309 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; -0.141 ; -0.312 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; -0.136 ; -0.307 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                           ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; SDRAM_A[*]    ; FPGA_CLK   ; 4.914  ; 5.089  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; FPGA_CLK   ; 2.707  ; 2.557  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; FPGA_CLK   ; 2.707  ; 2.557  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; FPGA_CLK   ; 2.711  ; 2.561  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; FPGA_CLK   ; 2.711  ; 2.561  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; FPGA_CLK   ; 2.699  ; 2.549  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; FPGA_CLK   ; 2.699  ; 2.549  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; FPGA_CLK   ; 2.697  ; 2.547  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; FPGA_CLK   ; 2.006  ; 1.949  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; FPGA_CLK   ; 4.914  ; 5.089  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; FPGA_CLK   ; 2.698  ; 2.548  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; FPGA_CLK   ; 2.707  ; 2.557  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; FPGA_CLK   ; 2.698  ; 2.548  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; FPGA_CLK   ; 4.925  ; 5.100  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; FPGA_CLK   ; 4.925  ; 5.100  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; FPGA_CLK   ; 2.017  ; 1.960  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N   ; FPGA_CLK   ; 2.020  ; 1.963  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N    ; FPGA_CLK   ; 2.710  ; 2.560  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; FPGA_CLK   ; 4.365  ; 4.698  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.018  ; 2.955  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.018  ; 2.955  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.018  ; 2.955  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 4.365  ; 4.698  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 4.346  ; 4.679  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.173  ; 2.136  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.887  ; 2.766  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.710  ; 2.560  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.007  ; 2.944  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 4.340  ; 4.673  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.004  ; 2.941  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.004  ; 2.941  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.004  ; 2.941  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 4.346  ; 4.679  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 3.006  ; 2.943  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 3.006  ; 2.943  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH_n  ; FPGA_CLK   ; 2.699  ; 2.549  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML_n  ; FPGA_CLK   ; 2.710  ; 2.560  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N   ; FPGA_CLK   ; 2.710  ; 2.560  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N    ; FPGA_CLK   ; 4.928  ; 5.103  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L       ; FPGA_CLK   ; 6.784  ; 6.905  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R       ; FPGA_CLK   ; 3.965  ; 3.813  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK        ; FPGA_CLK   ; 3.745  ; 3.643  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD        ; FPGA_CLK   ; 3.498  ; 3.421  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3       ; FPGA_CLK   ; 4.349  ; 4.537  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]      ; FPGA_CLK   ; 7.556  ; 7.780  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; FPGA_CLK   ; 5.325  ; 5.175  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; FPGA_CLK   ; 7.556  ; 7.780  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; FPGA_CLK   ; 5.604  ; 5.472  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; FPGA_CLK   ; 5.088  ; 4.959  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; FPGA_CLK   ; 7.791  ; 7.922  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; FPGA_CLK   ; 5.743  ; 5.599  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; FPGA_CLK   ; 5.905  ; 5.710  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; FPGA_CLK   ; 5.684  ; 5.525  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; FPGA_CLK   ; 7.791  ; 7.922  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; FPGA_CLK   ; 11.310 ;        ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; FPGA_CLK   ;        ; 11.508 ; Fall       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]      ; FPGA_CLK   ; 6.300  ; 6.469  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]     ; FPGA_CLK   ; 3.678  ; 3.548  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]     ; FPGA_CLK   ; 6.300  ; 6.469  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]     ; FPGA_CLK   ; 3.981  ; 3.899  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]     ; FPGA_CLK   ; 3.835  ; 3.653  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]      ; FPGA_CLK   ; 6.575  ; 6.660  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]     ; FPGA_CLK   ; 4.481  ; 4.295  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]     ; FPGA_CLK   ; 4.647  ; 4.413  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]     ; FPGA_CLK   ; 4.479  ; 4.277  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]     ; FPGA_CLK   ; 6.575  ; 6.660  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; dminus1       ; FPGA_CLK   ; 3.810  ; 3.831  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 3.676  ; 3.639  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 5.863  ; 6.196  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 3.678  ; 3.641  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                                   ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; SDRAM_A[*]    ; FPGA_CLK   ; 1.369  ; 1.312  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; FPGA_CLK   ; 2.042  ; 1.895  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; FPGA_CLK   ; 2.042  ; 1.895  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; FPGA_CLK   ; 2.046  ; 1.899  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; FPGA_CLK   ; 2.046  ; 1.899  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; FPGA_CLK   ; 2.035  ; 1.888  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; FPGA_CLK   ; 2.034  ; 1.887  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; FPGA_CLK   ; 2.033  ; 1.886  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; FPGA_CLK   ; 1.369  ; 1.312  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; FPGA_CLK   ; 4.250  ; 4.428  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; FPGA_CLK   ; 2.033  ; 1.886  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; FPGA_CLK   ; 2.042  ; 1.895  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; FPGA_CLK   ; 2.033  ; 1.886  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; FPGA_CLK   ; 1.379  ; 1.322  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; FPGA_CLK   ; 4.260  ; 4.438  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; FPGA_CLK   ; 1.379  ; 1.322  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N   ; FPGA_CLK   ; 1.382  ; 1.325  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N    ; FPGA_CLK   ; 2.045  ; 1.898  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.535  ; 1.497  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.352  ; 2.291  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.352  ; 2.291  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.352  ; 2.291  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.727  ; 4.059  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 3.708  ; 4.040  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 1.535  ; 1.497  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.222  ; 2.103  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.046  ; 1.899  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.341  ; 2.280  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.702  ; 4.034  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.339  ; 2.278  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.339  ; 2.278  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.339  ; 2.278  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 3.708  ; 4.040  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.340  ; 2.279  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.340  ; 2.279  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH_n  ; FPGA_CLK   ; 2.034  ; 1.887  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML_n  ; FPGA_CLK   ; 2.046  ; 1.899  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N   ; FPGA_CLK   ; 2.045  ; 1.898  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N    ; FPGA_CLK   ; 4.264  ; 4.442  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L       ; FPGA_CLK   ; 5.953  ; 6.080  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R       ; FPGA_CLK   ; 3.158  ; 3.009  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK        ; FPGA_CLK   ; 2.946  ; 2.845  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD        ; FPGA_CLK   ; 2.710  ; 2.634  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3       ; FPGA_CLK   ; 3.524  ; 3.707  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]      ; FPGA_CLK   ; 4.161  ; 4.010  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; FPGA_CLK   ; 4.384  ; 4.207  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; FPGA_CLK   ; 6.611  ; 6.758  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; FPGA_CLK   ; 4.563  ; 4.423  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; FPGA_CLK   ; 4.161  ; 4.010  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; FPGA_CLK   ; 4.734  ; 4.554  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; FPGA_CLK   ; 4.789  ; 4.624  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; FPGA_CLK   ; 4.947  ; 4.732  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; FPGA_CLK   ; 4.734  ; 4.554  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; FPGA_CLK   ; 6.845  ; 6.956  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; FPGA_CLK   ; 10.601 ;        ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; FPGA_CLK   ;        ; 10.801 ; Fall       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]      ; FPGA_CLK   ; 2.883  ; 2.753  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]     ; FPGA_CLK   ; 2.883  ; 2.753  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]     ; FPGA_CLK   ; 5.486  ; 5.659  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]     ; FPGA_CLK   ; 3.171  ; 3.091  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]     ; FPGA_CLK   ; 3.034  ; 2.855  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]      ; FPGA_CLK   ; 3.651  ; 3.454  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]     ; FPGA_CLK   ; 3.654  ; 3.471  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]     ; FPGA_CLK   ; 3.814  ; 3.584  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]     ; FPGA_CLK   ; 3.651  ; 3.454  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]     ; FPGA_CLK   ; 5.753  ; 5.843  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; dminus1       ; FPGA_CLK   ; 3.398  ; 3.418  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 3.265  ; 3.227  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 5.452  ; 5.784  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 3.267  ; 3.229  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                                           ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.810 ; 2.761 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.810 ; 2.761 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.810 ; 2.761 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.810 ; 2.761 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 5.179 ; 5.442 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 6.187 ; 6.450 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.722 ; 3.612 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 4.021 ; 3.911 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.435 ; 3.307 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 4.028 ; 3.979 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 5.787 ; 6.050 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.423 ; 3.374 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.423 ; 3.374 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.423 ; 3.374 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 5.482 ; 5.745 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 3.421 ; 3.372 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 3.421 ; 3.372 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 4.291 ; 4.163 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 5.595 ; 5.546 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 6.800 ; 6.690 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 7.985 ; 8.248 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 6.513 ; 6.403 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                                   ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.079 ; 2.030 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.079 ; 2.030 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.079 ; 2.030 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.079 ; 2.030 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 4.435 ; 4.698 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 5.403 ; 5.666 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.949 ; 2.839 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.236 ; 3.126 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.633 ; 2.505 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.248 ; 3.199 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 5.019 ; 5.282 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.667 ; 2.618 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.667 ; 2.618 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.667 ; 2.618 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 4.726 ; 4.989 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.665 ; 2.616 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.665 ; 2.616 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 3.454 ; 3.326 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 5.039 ; 4.990 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 6.191 ; 6.081 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 7.416 ; 7.679 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 5.916 ; 5.806 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                                  ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.783     ; 2.832     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.783     ; 2.832     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.783     ; 2.832     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.783     ; 2.832     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 5.450     ; 5.187     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 6.380     ; 6.117     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.557     ; 3.667     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.820     ; 3.930     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.279     ; 3.407     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.944     ; 3.993     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 6.034     ; 5.771     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.372     ; 3.421     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.372     ; 3.421     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.372     ; 3.421     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 5.730     ; 5.467     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 3.358     ; 3.407     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 3.358     ; 3.407     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 4.061     ; 4.189     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 5.482     ; 5.531     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 6.580     ; 6.690     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 8.171     ; 7.908     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 6.308     ; 6.418     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                                          ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.051     ; 2.100     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.051     ; 2.100     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.051     ; 2.100     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.051     ; 2.100     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 4.706     ; 4.443     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 5.599     ; 5.336     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.786     ; 2.896     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.038     ; 3.148     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.478     ; 2.606     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.166     ; 3.215     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 5.267     ; 5.004     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.617     ; 2.666     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.617     ; 2.666     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.617     ; 2.666     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 4.975     ; 4.712     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.602     ; 2.651     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.602     ; 2.651     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 3.229     ; 3.357     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 4.929     ; 4.978     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 5.976     ; 6.086     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 7.604     ; 7.341     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 5.715     ; 5.825     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+


---------------------------------------------
; Slow 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+--------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup Summary                                                                           ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; -1.898 ; -144.257      ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -0.230 ; -0.230        ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; -0.146 ; -7.463        ;
; FPGA_CLK                                                                            ; 0.343  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 3.238  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 6.985  ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold Summary                                                                            ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; -1.063 ; -77.853       ;
; FPGA_CLK                                                                            ; -0.632 ; -0.632        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.134  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.186  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.187  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 11.482 ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery Summary                                                                        ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; -1.187 ; -10.683       ;
; FPGA_CLK                                                                            ; 0.196  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 9.573  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 9.603  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 15.130 ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal Summary                                                                         ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; FPGA_CLK                                                                            ; -0.387 ; -9.978        ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 0.100  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.851  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1.236  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 1.756  ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width Summary                                                             ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.655  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 5.801  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 8.592  ; 0.000         ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 9.376  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.369 ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; 17.601 ; 0.000         ;
; FPGA_CLK                                                                            ; 89.338 ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                          ; To Node                                                                                                                                                                                            ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; -1.898 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[4]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[4]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.263     ; 0.593      ;
; -1.882 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[8]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[8]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.263     ; 0.577      ;
; -1.870 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[2]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[2]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.263     ; 0.565      ;
; -1.821 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[7]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[7]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.263     ; 0.516      ;
; -1.725 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[15]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[15]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.084     ; 0.599      ;
; -1.691 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CRCError                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[0]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.263     ; 0.386      ;
; -1.691 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reset_n_reg                                                                                                                                             ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[2]                                                                                                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.276     ; 0.373      ;
; -1.689 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|bitStuffError                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[1]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.263     ; 0.384      ;
; -1.689 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[1]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[1]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.263     ; 0.384      ;
; -1.686 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInExtend[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInSTB[2]           ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.269     ; 0.375      ;
; -1.685 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.269     ; 0.374      ;
; -1.685 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.269     ; 0.374      ;
; -1.684 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.269     ; 0.373      ;
; -1.684 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.269     ; 0.373      ;
; -1.678 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|ACKRxed                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[6]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.263     ; 0.373      ;
; -1.664 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[1]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[1]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.081     ; 0.541      ;
; -1.661 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[13]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.063     ; 0.556      ;
; -1.645 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[9]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.084     ; 0.519      ;
; -1.640 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[13]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.101     ; 0.497      ;
; -1.629 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[11]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[11]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.101     ; 0.486      ;
; -1.628 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[14]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[14]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.084     ; 0.502      ;
; -1.628 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[8]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[8]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.084     ; 0.502      ;
; -1.618 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[8]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[8]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.101     ; 0.475      ;
; -1.611 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[12]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[12]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.088     ; 0.481      ;
; -1.609 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[3]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[3]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.093     ; 0.474      ;
; -1.608 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.097     ; 0.469      ;
; -1.606 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.093     ; 0.471      ;
; -1.605 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[2]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[2]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.093     ; 0.470      ;
; -1.603 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[0]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[0]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.093     ; 0.468      ;
; -1.600 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[3]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[3]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.081     ; 0.477      ;
; -1.599 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[8]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[8]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.076     ; 0.481      ;
; -1.597 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.097     ; 0.458      ;
; -1.595 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[5]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[5]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.082     ; 0.471      ;
; -1.595 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[1]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[1]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.093     ; 0.460      ;
; -1.594 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.093     ; 0.459      ;
; -1.594 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[3]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[3]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.076     ; 0.476      ;
; -1.590 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[2]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[2]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.081     ; 0.467      ;
; -1.588 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[12]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[12]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.063     ; 0.483      ;
; -1.588 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[5]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[5]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.076     ; 0.470      ;
; -1.587 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[10]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[10]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.063     ; 0.482      ;
; -1.587 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXTimeOut                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[3]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.081     ; 0.464      ;
; -1.586 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[7]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[7]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.076     ; 0.468      ;
; -1.585 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.074     ; 0.469      ;
; -1.583 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.074     ; 0.467      ;
; -1.582 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[9]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[9]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.082     ; 0.458      ;
; -1.582 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[9]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[9]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.076     ; 0.464      ;
; -1.581 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[0]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[0]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.082     ; 0.457      ;
; -1.579 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[0]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[0]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.076     ; 0.461      ;
; -1.573 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[11]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[11]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.063     ; 0.468      ;
; -1.536 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.097     ; 0.397      ;
; -1.535 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.097     ; 0.396      ;
; -1.535 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.097     ; 0.396      ;
; -1.533 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.093     ; 0.398      ;
; -1.531 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.093     ; 0.396      ;
; -1.529 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[1] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.101     ; 0.386      ;
; -1.528 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[0] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.090     ; 0.396      ;
; -1.527 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[0] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.101     ; 0.384      ;
; -1.527 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[9]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.088     ; 0.397      ;
; -1.526 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.093     ; 0.391      ;
; -1.525 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.097     ; 0.386      ;
; -1.525 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXOverflow                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[2]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.094     ; 0.389      ;
; -1.524 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.097     ; 0.385      ;
; -1.523 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXOverflow                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[2]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.093     ; 0.388      ;
; -1.522 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.093     ; 0.387      ;
; -1.522 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|ACKRxed                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[6]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.093     ; 0.387      ;
; -1.522 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|NAKRxed                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[4]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.094     ; 0.386      ;
; -1.522 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_enable_reg                                                                                                                                          ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[2]                                                                                                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.105     ; 0.375      ;
; -1.521 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|stallRxed                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[5]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.094     ; 0.385      ;
; -1.520 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.093     ; 0.385      ;
; -1.519 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|NAKRxed                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[4]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.093     ; 0.384      ;
; -1.519 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|stallRxed                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[5]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.093     ; 0.384      ;
; -1.519 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CRCError                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[0]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.092     ; 0.385      ;
; -1.518 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[10]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[10]    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.082     ; 0.394      ;
; -1.518 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|bitStuffError                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[1]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.092     ; 0.384      ;
; -1.518 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXTimeOut                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[3]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.092     ; 0.384      ;
; -1.517 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[10]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[10]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.088     ; 0.387      ;
; -1.516 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[15]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[15]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.088     ; 0.386      ;
; -1.516 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[14]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[14]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.088     ; 0.386      ;
; -1.516 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[1] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.090     ; 0.384      ;
; -1.514 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[6]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[6]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.076     ; 0.396      ;
; -1.511 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInExtend[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInSTB[2]           ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.094     ; 0.375      ;
; -1.509 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|dataSequence                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[7]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.091     ; 0.376      ;
; -1.509 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[6]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[6]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.082     ; 0.385      ;
; -1.509 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[10]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[10]    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.076     ; 0.391      ;
; -1.506 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|dataSequence                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[7]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.092     ; 0.372      ;
; -1.502 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[4]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[4]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.076     ; 0.384      ;
; -1.495 ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                                                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|synchronizer:tick_toggle_synchronizer|ff_reg[2]                                                                                                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.081     ; 0.372      ;
; -1.479 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[2]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[2]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.064     ; 0.373      ;
; -1.479 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[1]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[1]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.064     ; 0.373      ;
; -1.479 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[3]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[3]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.064     ; 0.373      ;
; -1.478 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[0]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[0]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.064     ; 0.372      ;
; 6.551  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|pmg_dma_state_reg[2]                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.082     ; 5.012      ;
; 6.570  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Dreg                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 4.981      ;
; 6.634  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Vreg                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 4.922      ;
; 6.685  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Ireg                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.091     ; 4.869      ;
; 6.758  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[7]                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.092     ; 4.795      ;
; 6.811  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Y[4]                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.099     ; 4.735      ;
; 6.811  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Y[0]                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.099     ; 4.735      ;
; 6.823  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[6]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.080     ; 4.742      ;
; 6.824  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[0]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.080     ; 4.741      ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                                                             ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                 ; To Node                                                                                                                                             ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; -0.230 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 1.467        ; -0.916     ; 0.619      ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                                                                           ; To Node                                                                                                                                                                                           ; Launch Clock                                                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -0.146 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.632      ; 0.664      ;
; -0.138 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.658      ;
; -0.133 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.627      ; 0.646      ;
; -0.129 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.632      ; 0.647      ;
; -0.129 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]                                                                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.649      ;
; -0.126 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.646      ;
; -0.125 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.641      ; 0.652      ;
; -0.125 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.633      ; 0.644      ;
; -0.125 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.635      ; 0.646      ;
; -0.124 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1]                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.644      ;
; -0.123 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.633      ; 0.642      ;
; -0.121 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.641      ;
; -0.119 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.628      ; 0.633      ;
; -0.117 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.637      ;
; -0.117 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.637      ;
; -0.116 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.628      ; 0.630      ;
; -0.116 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.636      ;
; -0.116 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.635      ; 0.637      ;
; -0.116 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.635      ; 0.637      ;
; -0.115 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.641      ; 0.642      ;
; -0.115 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.635      ;
; -0.115 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.635      ; 0.636      ;
; -0.114 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]                                                                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.635      ; 0.635      ;
; -0.114 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.634      ;
; -0.113 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.633      ;
; -0.113 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB                                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg_reg1      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.633      ;
; -0.113 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.633      ;
; -0.112 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB                                                                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.632      ;
; -0.112 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB                                                                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.632      ;
; -0.112 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.635      ; 0.633      ;
; -0.112 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.632      ;
; -0.112 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.632      ;
; -0.111 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.628      ; 0.625      ;
; -0.111 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.631      ;
; -0.110 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.627      ; 0.623      ;
; -0.109 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.641      ; 0.636      ;
; -0.109 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.635      ; 0.630      ;
; -0.108 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.628      ;
; -0.108 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB                                                                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.628      ;
; -0.107 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.635      ; 0.628      ;
; -0.106 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.641      ; 0.633      ;
; -0.106 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.626      ;
; -0.106 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.626      ;
; -0.106 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.626      ;
; -0.105 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn_reg1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.635      ; 0.626      ;
; -0.105 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.635      ; 0.626      ;
; -0.105 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.635      ; 0.626      ;
; -0.105 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.635      ; 0.626      ;
; -0.105 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1]                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.625      ;
; -0.104 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol_reg1        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.635      ; 0.625      ;
; -0.104 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.635      ; 0.625      ;
; -0.104 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate_reg1       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.635      ; 0.625      ;
; -0.103 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate_reg1       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.635      ; 0.624      ;
; -0.103 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.641      ; 0.630      ;
; -0.103 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB                                                                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.635      ; 0.624      ;
; -0.103 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.635      ; 0.624      ;
; -0.102 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.635      ; 0.623      ;
; -0.102 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.622      ;
; -0.097 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.635      ; 0.618      ;
; -0.093 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.613      ;
; -0.088 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.635      ; 0.609      ;
; -0.086 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[0]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.635      ; 0.607      ;
; -0.077 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.641      ; 0.604      ;
; -0.066 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.586      ;
; -0.064 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.641      ; 0.591      ;
; -0.046 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.632      ; 0.564      ;
; -0.043 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol_reg1        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.635      ; 0.564      ;
; -0.040 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.633      ; 0.559      ;
; -0.037 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn_reg1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.635      ; 0.558      ;
; -0.035 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.555      ;
; -0.027 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB                                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg_reg1      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.635      ; 0.548      ;
; -0.026 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.546      ;
; -0.011 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.531      ;
; -0.009 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.529      ;
; -0.009 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.529      ;
; -0.007 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.527      ;
; -0.007 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.527      ;
; -0.006 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.526      ;
; -0.005 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.635      ; 0.526      ;
; -0.001 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[0]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.635      ; 0.522      ;
; 0.069  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.632      ; 0.449      ;
; 7.705  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|altsyncram:altsyncram4|altsyncram_i0m3:auto_generated|ram_block1a0~porta_address_reg0                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.317     ; 3.580      ;
; 7.944  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|altsyncram:altsyncram4|altsyncram_nsl3:auto_generated|ram_block1a0~porta_address_reg0 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.319     ; 3.339      ;
; 8.503  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C1_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.135     ; 2.964      ;
; 8.576  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C0_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.139     ; 2.887      ;
; 8.588  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C0_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.135     ; 2.879      ;
; 8.620  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C1_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.139     ; 2.843      ;
; 8.628  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_post_state                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 1.916      ; 3.692      ;
; 8.652  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_post_state ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 1.916      ; 3.668      ;
; 8.757  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|idle_state                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 1.916      ; 3.563      ;
; 8.782  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_wait_state                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 1.916      ; 3.538      ;
; 8.798  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C3_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.135     ; 2.669      ;
; 8.810  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_wait_state ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 1.918      ; 3.512      ;
; 8.811  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|idle_state          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 1.918      ; 3.511      ;
; 8.821  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C4_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.139     ; 2.642      ;
; 8.825  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C2_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.139     ; 2.638      ;
; 8.842  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr14|cntr_qfo:auto_generated|counter_reg_bit[3]                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.139     ; 2.621      ;
; 8.878  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr14|cntr_qfo:auto_generated|counter_reg_bit[4]                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.137     ; 2.587      ;
; 8.917  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C4_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.135     ; 2.550      ;
; 8.952  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr14|cntr_qfo:auto_generated|counter_reg_bit[3]                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.137     ; 2.513      ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'FPGA_CLK'                                                                                                                                                                                                                                                                                               ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack   ; From Node                                                                             ; To Node                                                                               ; Launch Clock                                                                        ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; 0.343   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[131]                                       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.731      ; 2.141      ;
; 197.864 ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; 0.103      ; 2.226      ;
; 197.959 ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8           ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.158     ; 0.752      ;
; 198.367 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.582      ;
; 198.371 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.578      ;
; 198.435 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.514      ;
; 198.439 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.510      ;
; 198.439 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.510      ;
; 198.443 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.506      ;
; 198.451 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.498      ;
; 198.489 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.460      ;
; 198.503 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.446      ;
; 198.504 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.445      ;
; 198.507 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.442      ;
; 198.507 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.442      ;
; 198.508 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.441      ;
; 198.511 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.438      ;
; 198.519 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.430      ;
; 198.519 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.430      ;
; 198.555 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.394      ;
; 198.557 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.392      ;
; 198.571 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.378      ;
; 198.572 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.377      ;
; 198.572 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.377      ;
; 198.575 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.374      ;
; 198.575 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.374      ;
; 198.576 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.373      ;
; 198.576 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.373      ;
; 198.579 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.370      ;
; 198.580 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.369      ;
; 198.587 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.362      ;
; 198.587 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.362      ;
; 198.618 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.331      ;
; 198.623 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.326      ;
; 198.625 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.324      ;
; 198.639 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.310      ;
; 198.640 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.309      ;
; 198.640 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.309      ;
; 198.641 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.308      ;
; 198.643 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.306      ;
; 198.643 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.306      ;
; 198.644 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.305      ;
; 198.644 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.305      ;
; 198.645 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.304      ;
; 198.647 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.302      ;
; 198.648 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.301      ;
; 198.655 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.294      ;
; 198.655 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.294      ;
; 198.655 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.294      ;
; 198.686 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.263      ;
; 198.691 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.258      ;
; 198.693 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.256      ;
; 198.693 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.256      ;
; 198.707 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.242      ;
; 198.708 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.241      ;
; 198.708 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.241      ;
; 198.708 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.241      ;
; 198.709 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.240      ;
; 198.711 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.238      ;
; 198.711 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.238      ;
; 198.712 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.237      ;
; 198.712 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.237      ;
; 198.712 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.237      ;
; 198.713 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.236      ;
; 198.715 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.234      ;
; 198.716 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.233      ;
; 198.723 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.226      ;
; 198.723 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.226      ;
; 198.723 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.226      ;
; 198.724 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.225      ;
; 198.754 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.195      ;
; 198.759 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.190      ;
; 198.760 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.189      ;
; 198.761 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.188      ;
; 198.761 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.188      ;
; 198.775 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.174      ;
; 198.776 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.173      ;
; 198.776 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.173      ;
; 198.776 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.173      ;
; 198.777 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.172      ;
; 198.779 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.170      ;
; 198.780 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.172      ;
; 198.780 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.169      ;
; 198.780 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.169      ;
; 198.780 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.169      ;
; 198.781 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.168      ;
; 198.782 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.170      ;
; 198.783 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.166      ;
; 198.784 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.168      ;
; 198.784 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.165      ;
; 198.791 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.158      ;
; 198.791 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.158      ;
; 198.791 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.158      ;
; 198.792 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.157      ;
; 198.792 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.157      ;
; 198.822 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.127      ;
; 198.827 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.122      ;
; 198.828 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.121      ;
; 198.828 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.121      ;
; 198.829 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.038     ; 1.120      ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                            ;
+-------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                 ; To Node                                                                                                                                             ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 3.238 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[4]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 2.359      ;
; 3.273 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[4]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 2.324      ;
; 3.438 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[9]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.126     ; 2.158      ;
; 3.438 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[11]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.126     ; 2.158      ;
; 3.473 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[9]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.126     ; 2.123      ;
; 3.473 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[11]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.126     ; 2.123      ;
; 3.481 ; SDRAM_ADDR[18]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[7]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.131     ; 2.110      ;
; 3.505 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[5]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 2.092      ;
; 3.540 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[5]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 2.057      ;
; 3.545 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[10]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.121     ; 2.056      ;
; 3.576 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_ras_n                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.119     ; 2.027      ;
; 3.580 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[6]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.127     ; 2.015      ;
; 3.580 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[10]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.121     ; 2.021      ;
; 3.582 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[7]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.127     ; 2.013      ;
; 3.582 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[8]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.127     ; 2.013      ;
; 3.584 ; SDRAM_ADDR[8]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[7]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.139     ; 1.999      ;
; 3.615 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[6]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.127     ; 1.980      ;
; 3.617 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[7]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.127     ; 1.978      ;
; 3.617 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[8]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.127     ; 1.978      ;
; 3.623 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_ras_n                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.119     ; 1.980      ;
; 3.730 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[4]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.118     ; 1.922      ;
; 3.730 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[13]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.118     ; 1.922      ;
; 3.741 ; SDRAM_ADDR[17]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[6]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.131     ; 1.850      ;
; 3.761 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[3]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.118     ; 1.891      ;
; 3.761 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[7]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.118     ; 1.891      ;
; 3.785 ; SDRAM_ADDR[5]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[4]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 1.812      ;
; 3.788 ; SDRAM_ADDR[21]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[10]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 1.809      ;
; 3.791 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[0]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.112     ; 1.867      ;
; 3.794 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[1]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.112     ; 1.864      ;
; 3.796 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[2]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.112     ; 1.862      ;
; 3.840 ; SDRAM_ADDR[16]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.129     ; 1.753      ;
; 3.849 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_ba[0]                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.121     ; 1.752      ;
; 3.849 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_ba[1]                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.121     ; 1.752      ;
; 3.856 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[4]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.121     ; 1.793      ;
; 3.856 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[13]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.121     ; 1.793      ;
; 3.857 ; SDRAM_ADDR[15]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 1.740      ;
; 3.861 ; SDRAM_ADDR[7]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[6]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.127     ; 1.734      ;
; 3.884 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_ba[0]                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.121     ; 1.717      ;
; 3.884 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_ba[1]                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.121     ; 1.717      ;
; 3.887 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[3]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.121     ; 1.762      ;
; 3.887 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[7]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.121     ; 1.762      ;
; 3.917 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[0]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.115     ; 1.738      ;
; 3.920 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[1]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.115     ; 1.735      ;
; 3.922 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[2]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.115     ; 1.733      ;
; 3.928 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[2]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.108     ; 1.734      ;
; 3.938 ; SDRAM_ADDR[20]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[9]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.130     ; 1.654      ;
; 3.973 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[14]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.118     ; 1.679      ;
; 3.973 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[15]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.118     ; 1.679      ;
; 3.976 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[6]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.118     ; 1.676      ;
; 3.985 ; SDRAM_ADDR[19]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[8]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.131     ; 1.606      ;
; 4.011 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_do_reg[15]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.107     ; 1.652      ;
; 4.025 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[8]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.116     ; 1.629      ;
; 4.025 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[10]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.116     ; 1.629      ;
; 4.027 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_bena_reg[1]                                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.116     ; 1.627      ;
; 4.028 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[11]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.116     ; 1.626      ;
; 4.028 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[12]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.116     ; 1.626      ;
; 4.029 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_bena_reg[0]                                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.116     ; 1.625      ;
; 4.031 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_do_reg[3]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.107     ; 1.632      ;
; 4.042 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_do_reg[11]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.107     ; 1.621      ;
; 4.043 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[0]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.110     ; 1.617      ;
; 4.043 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[5]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.110     ; 1.617      ;
; 4.043 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[4]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.110     ; 1.617      ;
; 4.043 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[13]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.110     ; 1.617      ;
; 4.043 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[12]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.110     ; 1.617      ;
; 4.043 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[10]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.110     ; 1.617      ;
; 4.043 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[9]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.110     ; 1.617      ;
; 4.043 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[8]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.110     ; 1.617      ;
; 4.052 ; SDRAM_ADDR[22]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[11]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.126     ; 1.544      ;
; 4.057 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[5]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.113     ; 1.600      ;
; 4.064 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[9]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.116     ; 1.590      ;
; 4.089 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[2]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.118     ; 1.515      ;
; 4.089 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[3]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.118     ; 1.515      ;
; 4.090 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[6]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.113     ; 1.567      ;
; 4.104 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_do_reg[2]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.105     ; 1.561      ;
; 4.112 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[14]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.121     ; 1.537      ;
; 4.112 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[15]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.121     ; 1.537      ;
; 4.113 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_do_reg[14]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.107     ; 1.550      ;
; 4.115 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[6]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.121     ; 1.534      ;
; 4.124 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[2]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.118     ; 1.480      ;
; 4.124 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[3]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.118     ; 1.480      ;
; 4.126 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[10]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.119     ; 1.525      ;
; 4.128 ; SDRAM_WRITE_ENABLE                                                                        ; ram_bena_reg[1]                                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.119     ; 1.523      ;
; 4.130 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[12]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.119     ; 1.521      ;
; 4.131 ; SDRAM_WRITE_ENABLE                                                                        ; ram_bena_reg[0]                                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.119     ; 1.520      ;
; 4.138 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[0]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.121     ; 1.463      ;
; 4.138 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[1]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.121     ; 1.463      ;
; 4.138 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[8]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.119     ; 1.513      ;
; 4.138 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[9]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.119     ; 1.513      ;
; 4.141 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[11]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.119     ; 1.510      ;
; 4.155 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[3]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.110     ; 1.505      ;
; 4.155 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[15]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.110     ; 1.505      ;
; 4.155 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[14]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.110     ; 1.505      ;
; 4.155 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[11]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.110     ; 1.505      ;
; 4.173 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[0]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.121     ; 1.428      ;
; 4.173 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[1]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.121     ; 1.428      ;
; 4.175 ; SDRAM_ADDR[14]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[3]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.118     ; 1.429      ;
; 4.176 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:0:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.915     ; 0.620      ;
; 4.199 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.108     ; 1.463      ;
; 4.209 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_do_reg[6]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.110     ; 1.451      ;
; 4.212 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[5]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.116     ; 1.442      ;
+-------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                                                                                                                                                       ;
+--------+-----------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                           ; To Node                                                                                                                                             ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 6.985  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0]           ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 8.810        ; -0.915     ; 0.748      ;
; 9.945  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 7.474      ;
; 9.958  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 7.461      ;
; 9.999  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 7.420      ;
; 10.012 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 7.407      ;
; 10.014 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 7.405      ;
; 10.025 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 7.394      ;
; 10.038 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 7.381      ;
; 10.058 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 7.361      ;
; 10.068 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 7.351      ;
; 10.071 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 7.348      ;
; 10.094 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 7.325      ;
; 10.124 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 7.295      ;
; 10.127 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 7.292      ;
; 10.137 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 7.282      ;
; 10.192 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 7.227      ;
; 10.193 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 7.226      ;
; 10.220 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.103     ; 7.195      ;
; 10.230 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.105     ; 7.183      ;
; 10.233 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.103     ; 7.182      ;
; 10.243 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.105     ; 7.170      ;
; 10.246 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 7.173      ;
; 10.272 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 7.147      ;
; 10.289 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.103     ; 7.126      ;
; 10.299 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.105     ; 7.114      ;
; 10.305 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 7.114      ;
; 10.371 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 7.048      ;
; 10.467 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.103     ; 6.948      ;
; 10.469 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 6.950      ;
; 10.477 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.105     ; 6.936      ;
; 10.523 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 6.896      ;
; 10.549 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 6.870      ;
; 10.582 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 6.837      ;
; 10.648 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 6.771      ;
; 10.691 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 6.728      ;
; 10.744 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.103     ; 6.671      ;
; 10.745 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 6.674      ;
; 10.754 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.105     ; 6.659      ;
; 10.771 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 6.648      ;
; 10.804 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 6.615      ;
; 10.870 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 6.549      ;
; 10.966 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.103     ; 6.449      ;
; 10.976 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.105     ; 6.437      ;
; 11.055 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 6.364      ;
; 11.109 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 6.310      ;
; 11.135 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 6.284      ;
; 11.168 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 6.251      ;
; 11.234 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 6.185      ;
; 11.330 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.103     ; 6.085      ;
; 11.340 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.105     ; 6.073      ;
; 11.797 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 5.622      ;
; 11.851 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 5.568      ;
; 11.877 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 5.542      ;
; 11.910 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 5.509      ;
; 11.976 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 5.443      ;
; 12.072 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.103     ; 5.343      ;
; 12.082 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.105     ; 5.331      ;
; 12.562 ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.039     ; 4.917      ;
; 12.572 ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.039     ; 4.907      ;
; 12.575 ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.039     ; 4.904      ;
; 12.585 ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.039     ; 4.894      ;
; 12.614 ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.039     ; 4.865      ;
; 12.627 ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.039     ; 4.852      ;
; 12.631 ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.039     ; 4.848      ;
; 12.641 ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.039     ; 4.838      ;
; 12.661 ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.039     ; 4.818      ;
; 12.674 ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.039     ; 4.805      ;
; 12.683 ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.039     ; 4.796      ;
; 12.730 ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.039     ; 4.749      ;
; 12.809 ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.039     ; 4.670      ;
; 12.819 ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.039     ; 4.660      ;
; 12.861 ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.039     ; 4.618      ;
; 12.908 ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.039     ; 4.571      ;
; 12.989 ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.039     ; 4.490      ;
; 13.002 ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.039     ; 4.477      ;
; 13.058 ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.039     ; 4.421      ;
; 13.086 ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.039     ; 4.393      ;
; 13.096 ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.039     ; 4.383      ;
; 13.138 ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.039     ; 4.341      ;
; 13.185 ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.039     ; 4.294      ;
; 13.236 ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.039     ; 4.243      ;
; 13.308 ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.039     ; 4.171      ;
; 13.318 ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.039     ; 4.161      ;
; 13.360 ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.039     ; 4.119      ;
; 13.407 ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.039     ; 4.072      ;
; 13.513 ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.039     ; 3.966      ;
; 13.672 ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.039     ; 3.807      ;
; 13.682 ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.039     ; 3.797      ;
; 13.724 ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.039     ; 3.755      ;
; 13.735 ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.039     ; 3.744      ;
; 13.771 ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.039     ; 3.708      ;
; 14.099 ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.039     ; 3.380      ;
; 14.267 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg        ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.103     ; 3.148      ;
; 14.414 ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.039     ; 3.065      ;
; 14.424 ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.039     ; 3.055      ;
; 14.466 ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.039     ; 3.013      ;
; 14.485 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg        ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.103     ; 2.930      ;
; 14.513 ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.039     ; 2.966      ;
; 14.595 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2]    ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.103     ; 2.820      ;
; 14.601 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg        ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.103     ; 2.814      ;
+--------+-----------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                     ; To Node                                                                                                                                                                                                                                          ; Launch Clock                                                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -1.063 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.268      ; 0.397      ;
; -1.029 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.268      ; 0.431      ;
; -1.026 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.268      ; 0.434      ;
; -1.021 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.440      ;
; -1.020 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[0]                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.441      ;
; -1.020 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.441      ;
; -1.015 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.446      ;
; -1.003 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg_reg1                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.458      ;
; -0.999 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.462      ;
; -0.998 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.463      ;
; -0.998 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.463      ;
; -0.998 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.463      ;
; -0.997 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn_reg1                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.464      ;
; -0.995 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.466      ;
; -0.989 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol_reg1                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.472      ;
; -0.987 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.474      ;
; -0.977 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.276      ; 0.491      ;
; -0.977 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.484      ;
; -0.976 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.276      ; 0.492      ;
; -0.975 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.486      ;
; -0.975 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.486      ;
; -0.974 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.276      ; 0.494      ;
; -0.974 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.487      ;
; -0.974 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate_reg1                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.487      ;
; -0.974 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.268      ; 0.486      ;
; -0.973 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.268      ; 0.487      ;
; -0.973 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.488      ;
; -0.972 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.489      ;
; -0.972 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.489      ;
; -0.972 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.268      ; 0.488      ;
; -0.969 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.276      ; 0.499      ;
; -0.969 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.492      ;
; -0.969 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.492      ;
; -0.969 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[0]                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.492      ;
; -0.968 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.262      ; 0.486      ;
; -0.968 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.493      ;
; -0.968 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.493      ;
; -0.968 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.493      ;
; -0.968 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.493      ;
; -0.967 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.494      ;
; -0.967 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.494      ;
; -0.967 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.494      ;
; -0.966 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.276      ; 0.502      ;
; -0.965 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.496      ;
; -0.965 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.496      ;
; -0.964 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.497      ;
; -0.962 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.499      ;
; -0.962 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.499      ;
; -0.961 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.500      ;
; -0.960 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.276      ; 0.508      ;
; -0.957 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.504      ;
; -0.955 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                                                           ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.506      ;
; -0.953 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate_reg1                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.508      ;
; -0.952 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn_reg1                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.509      ;
; -0.952 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol_reg1                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.509      ;
; -0.951 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.510      ;
; -0.951 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.510      ;
; -0.951 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.510      ;
; -0.950 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.268      ; 0.510      ;
; -0.949 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.512      ;
; -0.947 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.508      ;
; -0.947 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg_reg1                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.514      ;
; -0.943 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[3]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.512      ;
; -0.942 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.268      ; 0.518      ;
; -0.941 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[2]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.514      ;
; -0.921 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.540      ;
; -0.920 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.541      ;
; -0.918 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[2]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.268      ; 0.542      ;
; -0.918 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.543      ;
; -0.916 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.268      ; 0.544      ;
; -0.914 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.268      ; 0.546      ;
; -0.914 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.276      ; 0.554      ;
; -0.912 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.268      ; 0.548      ;
; -0.909 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.546      ;
; -0.909 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[3]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.268      ; 0.551      ;
; -0.901 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.560      ;
; -0.894 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.268      ; 0.566      ;
; -0.891 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.268      ; 0.569      ;
; -0.890 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.268      ; 0.570      ;
; -0.890 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.571      ;
; -0.877 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.268      ; 0.583      ;
; 0.141  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[0]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.223      ; 0.468      ;
; 0.145  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[4]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.223      ; 0.472      ;
; 0.146  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[1]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.223      ; 0.473      ;
; 0.149  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[3]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.221      ; 0.474      ;
; 0.149  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[5]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.223      ; 0.476      ;
; 0.149  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[6]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.223      ; 0.476      ;
; 0.151  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[3]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.223      ; 0.478      ;
; 0.152  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[0]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.221      ; 0.477      ;
; 0.152  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[4]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.221      ; 0.477      ;
; 0.154  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[2]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.223      ; 0.481      ;
; 0.157  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[6]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.221      ; 0.482      ;
; 0.157  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[7]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.223      ; 0.484      ;
; 0.158  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[2]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.221      ; 0.483      ;
; 0.163  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[7]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.221      ; 0.488      ;
; 0.165  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[1]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.221      ; 0.490      ;
; 0.166  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[5]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.221      ; 0.491      ;
; 0.166  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_address_reg0 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.219      ; 0.489      ;
; 0.177  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_address_reg0 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.219      ; 0.500      ;
; 0.178  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_address_reg0 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.219      ; 0.501      ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'FPGA_CLK'                                                                                                                                                                                                                                                                                         ;
+--------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                       ; To Node                                                                               ; Launch Clock                                                                        ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.632 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[131]                                 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.166      ; 1.784      ;
; 0.141  ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8     ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; -0.103     ; 0.644      ;
; 0.194  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2] ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1]       ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.313      ;
; 0.197  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1] ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.316      ;
; 0.206  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.325      ;
; 0.298  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.417      ;
; 0.298  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.417      ;
; 0.298  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.417      ;
; 0.299  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.418      ;
; 0.299  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.418      ;
; 0.299  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.418      ;
; 0.299  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.418      ;
; 0.299  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.418      ;
; 0.300  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.419      ;
; 0.300  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.419      ;
; 0.300  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.419      ;
; 0.300  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.419      ;
; 0.300  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.419      ;
; 0.300  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.419      ;
; 0.300  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.419      ;
; 0.300  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.419      ;
; 0.301  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.420      ;
; 0.301  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.420      ;
; 0.301  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.420      ;
; 0.301  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.420      ;
; 0.302  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.421      ;
; 0.307  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.426      ;
; 0.308  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.427      ;
; 0.313  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.432      ;
; 0.447  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.566      ;
; 0.447  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.566      ;
; 0.448  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.567      ;
; 0.448  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.567      ;
; 0.448  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.567      ;
; 0.448  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.567      ;
; 0.449  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.568      ;
; 0.449  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.568      ;
; 0.449  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.568      ;
; 0.450  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.569      ;
; 0.450  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.569      ;
; 0.456  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.575      ;
; 0.457  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.576      ;
; 0.458  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.577      ;
; 0.458  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.577      ;
; 0.458  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.577      ;
; 0.458  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.577      ;
; 0.458  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.577      ;
; 0.459  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.578      ;
; 0.459  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.032      ; 0.575      ;
; 0.459  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.578      ;
; 0.459  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.578      ;
; 0.460  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.579      ;
; 0.460  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.579      ;
; 0.461  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.580      ;
; 0.461  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.580      ;
; 0.461  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.580      ;
; 0.461  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.580      ;
; 0.461  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.580      ;
; 0.462  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.032      ; 0.578      ;
; 0.462  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.581      ;
; 0.462  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.581      ;
; 0.463  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.582      ;
; 0.466  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.585      ;
; 0.469  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.588      ;
; 0.510  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.629      ;
; 0.511  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.630      ;
; 0.511  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.630      ;
; 0.511  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.630      ;
; 0.511  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.630      ;
; 0.512  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.631      ;
; 0.512  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.631      ;
; 0.512  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.631      ;
; 0.513  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.632      ;
; 0.513  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.632      ;
; 0.513  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.032      ; 0.629      ;
; 0.513  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.632      ;
; 0.514  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.633      ;
; 0.514  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.633      ;
; 0.514  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.633      ;
; 0.514  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.633      ;
; 0.515  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.634      ;
; 0.515  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.634      ;
; 0.515  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.634      ;
; 0.516  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.635      ;
; 0.516  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.032      ; 0.632      ;
; 0.519  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.638      ;
; 0.522  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.641      ;
; 0.524  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.643      ;
; 0.524  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.643      ;
; 0.524  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.643      ;
; 0.524  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.643      ;
; 0.524  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.643      ;
; 0.525  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.032      ; 0.641      ;
; 0.525  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.644      ;
; 0.525  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.644      ;
; 0.526  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.645      ;
; 0.526  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.032      ; 0.642      ;
; 0.527  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.646      ;
; 0.527  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.646      ;
; 0.527  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.646      ;
+--------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                   ; To Node                                                                                                                                                                                                                                          ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.134 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_address_reg0 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.234      ; 0.472      ;
; 0.144 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp0_snap_reg[5]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.469      ;
; 0.145 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_address_reg0 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.234      ; 0.483      ;
; 0.154 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_address_reg0 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.234      ; 0.492      ;
; 0.156 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|cntr_1ab:wr_ptr|counter_reg_bit[1] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|altsyncram_pe81:FIFOram|ram_block1a0~porta_address_reg0                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.479      ;
; 0.157 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[0]                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|altsyncram_lh81:FIFOram|ram_block1a0~porta_datain_reg0                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.482      ;
; 0.158 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|cntr_1ab:wr_ptr|counter_reg_bit[7] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|altsyncram_pe81:FIFOram|ram_block1a0~porta_address_reg0                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.481      ;
; 0.161 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[3]                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|altsyncram_lh81:FIFOram|ram_block1a0~porta_datain_reg0                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.486      ;
; 0.161 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|cntr_1ab:wr_ptr|counter_reg_bit[6] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|altsyncram_pe81:FIFOram|ram_block1a0~porta_address_reg0                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.484      ;
; 0.162 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[2]                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|altsyncram_lh81:FIFOram|ram_block1a0~porta_datain_reg0                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.487      ;
; 0.162 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|cntr_1ab:wr_ptr|counter_reg_bit[0] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|altsyncram_pe81:FIFOram|ram_block1a0~porta_address_reg0                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.485      ;
; 0.163 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|cntr_1ab:wr_ptr|counter_reg_bit[5] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|altsyncram_pe81:FIFOram|ram_block1a0~porta_address_reg0                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.486      ;
; 0.165 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|cntr_1ab:wr_ptr|counter_reg_bit[4] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|altsyncram_pe81:FIFOram|ram_block1a0~porta_address_reg0                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.488      ;
; 0.168 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[1]                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|altsyncram_lh81:FIFOram|ram_block1a0~porta_datain_reg0                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.493      ;
; 0.171 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[5]                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|altsyncram_lh81:FIFOram|ram_block1a0~porta_datain_reg0                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.496      ;
; 0.172 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp0_snap_reg[2]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.495      ;
; 0.173 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp3_snap_reg[4]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.496      ;
; 0.173 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|cntr_1ab:wr_ptr|counter_reg_bit[3] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|altsyncram_pe81:FIFOram|ram_block1a0~porta_address_reg0                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.496      ;
; 0.175 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[5]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.498      ;
; 0.177 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|cntr_1ab:wr_ptr|counter_reg_bit[2] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|altsyncram_pe81:FIFOram|ram_block1a0~porta_address_reg0                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.500      ;
; 0.178 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp0_snap_reg[1]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.501      ;
; 0.178 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[5]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.501      ;
; 0.179 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[4]                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|altsyncram_lh81:FIFOram|ram_block1a0~porta_datain_reg0                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.504      ;
; 0.179 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[6]                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|altsyncram_lh81:FIFOram|ram_block1a0~porta_datain_reg0                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.504      ;
; 0.180 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInt                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInt                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.043      ; 0.307      ;
; 0.180 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeInt                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeInt                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.043      ; 0.307      ;
; 0.181 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[0]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.505      ;
; 0.182 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp0_snap_reg[3]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.506      ;
; 0.182 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp3_snap_reg[1]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.506      ;
; 0.183 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[5]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.506      ;
; 0.184 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp0_snap_reg[6]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.507      ;
; 0.184 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp3_snap_reg[2]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.507      ;
; 0.185 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp3_snap_reg[6]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.508      ;
; 0.185 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[13]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[13]                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.313      ;
; 0.185 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[8]              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[8]                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.045      ; 0.314      ;
; 0.185 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[9]              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[9]                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.045      ; 0.314      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vblank_reg                                                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vblank_reg                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[5]                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[5]                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_ready_reg                                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_ready_reg                                                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[4]                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[4]                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[0]                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[0]                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[1]                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[1]                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[6]                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[6]                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|latch_delay_line:stimer_delay|data_in_reg                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|latch_delay_line:stimer_delay|data_in_reg                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[4]                                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[4]                                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[0]                                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[0]                                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[2]                                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[2]                                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[3]                                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[3]                                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[6]                                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[6]                                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[5]                                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[5]                                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf2_reg[1]                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf2_reg[1]                                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf2_reg[2]                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf2_reg[2]                                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf2_reg[3]                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf2_reg[3]                                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf2_reg[5]                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf2_reg[5]                                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf2_reg[4]                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf2_reg[4]                                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf2_reg[7]                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf2_reg[7]                                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|irqst_reg[5]                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|irqst_reg[5]                                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serial_out_reg                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serial_out_reg                                                                                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf1_reg[6]                                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf1_reg[6]                                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf1_reg[0]                                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf1_reg[0]                                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf1_reg[2]                                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf1_reg[2]                                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf1_reg[3]                                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf1_reg[3]                                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf1_reg[4]                                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf1_reg[4]                                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf1_reg[5]                                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf1_reg[5]                                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[2]                                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[2]                                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[0]                                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[0]                                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[4]                                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[4]                                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[5]                                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[5]                                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[6]                                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[6]                                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[0]                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[0]                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[0]                                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[0]                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[2]                                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[2]                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[1]                                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[1]                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[2]                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[3]                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[4]                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hblank_reg                                                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hblank_reg                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[0]                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[1]                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pl_reg[2]                                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pl_reg[2]                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile2|count_reg[1]                                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile2|count_reg[1]                                                                                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile2|shift_reg[6]                                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile2|shift_reg[6]                                                                                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pl_reg[0]                                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pl_reg[0]                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|count_reg[1]                                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|count_reg[1]                                                                                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|shift_reg[6]                                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|shift_reg[6]                                                                                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|shift_reg[7]                                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|shift_reg[7]                                                                                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pl_reg[0]                                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pl_reg[0]                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[7]                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[7]                                                                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pl_reg[1]                                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pl_reg[1]                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[7]                                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[7]                                                                                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pl_reg[0]                                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pl_reg[0]                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player3|count_reg[1]                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player3|count_reg[1]                                                                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pl_reg[3]                                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pl_reg[3]                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pf_reg[0]                                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pf_reg[0]                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pf_reg[0]                                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pf_reg[0]                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pf_reg[0]                                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pf_reg[0]                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pf_reg[0]                                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pf_reg[0]                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p3pf_reg[0]                                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p3pf_reg[0]                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pf_reg[0]                                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pf_reg[0]                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|CB2_output_reg                                                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|CB2_output_reg                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                   ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                 ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.186 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; sdram_ctrl:sdram_controller|sdram_rdy                     ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.187 ; sdram_ctrl:sdram_controller|r_refr_act                    ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sdram_request_reg                                         ; sdram_request_reg                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sdram_ctrl:sdram_controller|r_rd_act                      ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sdram_ctrl:sdram_controller|r_wr_act                      ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.193 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.314      ;
; 0.212 ; seq_reg[11]                                               ; seq_reg[0]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.332      ;
; 0.216 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.337      ;
; 0.260 ; sdram_ctrl:sdram_controller|r_rd_act                      ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.380      ;
; 0.277 ; seq_reg[9]                                                ; seq_reg[10]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.397      ;
; 0.280 ; seq_reg[2]                                                ; seq_reg[3]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.400      ;
; 0.289 ; seq_reg[3]                                                ; seq_reg[4]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.409      ;
; 0.293 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.414      ;
; 0.293 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.414      ;
; 0.294 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.415      ;
; 0.294 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.415      ;
; 0.294 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.415      ;
; 0.294 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.415      ;
; 0.295 ; seq_reg[0]                                                ; seq_reg[1]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.295 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.416      ;
; 0.295 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.295 ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.298 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.418      ;
; 0.299 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.420      ;
; 0.300 ; seq_reg[4]                                                ; seq_reg[5]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.420      ;
; 0.300 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.421      ;
; 0.327 ; sdram_ctrl:sdram_controller|r_rd_act                      ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.447      ;
; 0.334 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.455      ;
; 0.336 ; seq_reg[10]                                               ; seq_reg[11]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.456      ;
; 0.338 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.459      ;
; 0.341 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.462      ;
; 0.349 ; seq_reg[8]                                                ; seq_reg[9]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.469      ;
; 0.360 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.481      ;
; 0.361 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.481      ;
; 0.362 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.483      ;
; 0.364 ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.484      ;
; 0.390 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.511      ;
; 0.412 ; seq_reg[4]                                                ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.532      ;
; 0.425 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.548      ;
; 0.442 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.563      ;
; 0.443 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.564      ;
; 0.443 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.564      ;
; 0.451 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.572      ;
; 0.452 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.573      ;
; 0.452 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.573      ;
; 0.453 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.574      ;
; 0.453 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.574      ;
; 0.454 ; sdram_ctrl:sdram_controller|r_refr_act                    ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.045      ; 0.583      ;
; 0.454 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.575      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.576      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.576      ;
; 0.456 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.577      ;
; 0.456 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.577      ;
; 0.461 ; sdram_ctrl:sdram_controller|r_refr_act                    ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.045      ; 0.590      ;
; 0.472 ; seq_reg[7]                                                ; seq_reg[8]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.592      ;
; 0.485 ; seq_reg[1]                                                ; seq_reg[2]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.606      ;
; 0.505 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.626      ;
; 0.506 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.627      ;
; 0.508 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.629      ;
; 0.509 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.630      ;
; 0.509 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.630      ;
; 0.512 ; seq_reg[1]                                                ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.633      ;
; 0.517 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.638      ;
; 0.518 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.639      ;
; 0.519 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.640      ;
; 0.519 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.640      ;
; 0.520 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.641      ;
; 0.521 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.642      ;
; 0.522 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.643      ;
; 0.522 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.643      ;
; 0.529 ; sdram_ctrl:sdram_controller|r_rd_reg                      ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.027      ; 0.640      ;
; 0.538 ; sdram_request_reg                                         ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.658      ;
; 0.541 ; seq_reg[0]                                                ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.662      ;
; 0.547 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.668      ;
; 0.552 ; sdram_ctrl:sdram_controller|r_wr_reg                      ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.027      ; 0.663      ;
; 0.559 ; sdram_request_complete_reg                                ; sdram_request_complete_reg                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.679      ;
; 0.559 ; sdram_ctrl:sdram_controller|r_refr_act                    ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.679      ;
; 0.561 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.682      ;
; 0.566 ; seq_reg[4]                                                ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.686      ;
; 0.571 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.692      ;
; 0.572 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.693      ;
; 0.574 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.695      ;
; 0.575 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.696      ;
; 0.583 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.704      ;
; 0.584 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.705      ;
; 0.585 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.706      ;
; 0.586 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.707      ;
; 0.587 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.708      ;
; 0.588 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.709      ;
; 0.593 ; seq_reg[5]                                                ; seq_reg[6]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.712      ;
; 0.597 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.718      ;
; 0.626 ; sdram_ctrl:sdram_controller|r_wr_act                      ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.033      ; 0.743      ;
; 0.627 ; seq_reg[9]                                                ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.748      ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                                      ;
+-------+--------------------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                        ; To Node                               ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.187 ; svideo_gtia:svideo|phase_count_reg[5]                                                            ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; svideo_gtia:svideo|phase_count_reg[6]                                                            ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; svideo_gtia:svideo|phase_count_reg[7]                                                            ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.307      ;
; 0.402 ; svideo_gtia:svideo|phase_count_reg[4]                                                            ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.522      ;
; 0.421 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                              ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.693      ;
; 0.447 ; svideo_gtia:svideo|phase_count_reg[4]                                                            ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.567      ;
; 0.460 ; svideo_gtia:svideo|phase_count_reg[3]                                                            ; svideo_gtia:svideo|phase_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.580      ;
; 0.569 ; svideo_gtia:svideo|phase_count_reg[6]                                                            ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.689      ;
; 0.610 ; svideo_gtia:svideo|phase_count_reg[4]                                                            ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.730      ;
; 0.620 ; svideo_gtia:svideo|phase_count_reg[2]                                                            ; svideo_gtia:svideo|phase_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.740      ;
; 0.639 ; svideo_gtia:svideo|phase_count_reg[5]                                                            ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.759      ;
; 0.655 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                              ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.927      ;
; 0.667 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                              ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.939      ;
; 0.669 ; svideo_gtia:svideo|phase_count_reg[2]                                                            ; svideo_gtia:svideo|phase_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.789      ;
; 0.670 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                              ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.942      ;
; 0.671 ; svideo_gtia:svideo|phase_count_reg[3]                                                            ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.791      ;
; 0.685 ; svideo_gtia:svideo|phase_count_reg[5]                                                            ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.805      ;
; 0.685 ; svideo_gtia:svideo|phase_count_reg[2]                                                            ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.805      ;
; 0.739 ; svideo_gtia:svideo|phase_count_reg[3]                                                            ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.859      ;
; 0.745 ; svideo_gtia:svideo|phase_count_reg[4]                                                            ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.865      ;
; 0.753 ; svideo_gtia:svideo|phase_count_reg[2]                                                            ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.873      ;
; 0.776 ; svideo_gtia:svideo|phase_count_reg[3]                                                            ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.896      ;
; 0.778 ; svideo_gtia:svideo|phase_count_reg[3]                                                            ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.898      ;
; 0.790 ; svideo_gtia:svideo|phase_count_reg[2]                                                            ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.910      ;
; 0.792 ; svideo_gtia:svideo|phase_count_reg[2]                                                            ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.912      ;
; 0.873 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                              ; svideo_gtia:svideo|phase_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 1.145      ;
; 0.873 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                              ; svideo_gtia:svideo|phase_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 1.145      ;
; 0.909 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.184      ;
; 0.954 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.077      ; 1.225      ;
; 0.956 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.077      ; 1.227      ;
; 0.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.270      ;
; 1.027 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hblank_reg    ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.077      ; 1.298      ;
; 1.035 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hblank_reg    ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.077      ; 1.306      ;
; 1.045 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.320      ;
; 1.046 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.321      ;
; 1.050 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hblank_reg    ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.077      ; 1.321      ;
; 1.058 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hblank_reg    ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.077      ; 1.329      ;
; 1.058 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.333      ;
; 1.065 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.340      ;
; 1.068 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.077      ; 1.339      ;
; 1.096 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.371      ;
; 1.100 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hblank_reg    ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.077      ; 1.371      ;
; 1.102 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.066      ; 1.362      ;
; 1.114 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.389      ;
; 1.115 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.077      ; 1.386      ;
; 1.118 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.077      ; 1.389      ;
; 1.127 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|phase_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 1.401      ;
; 1.128 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|phase_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 1.402      ;
; 1.128 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.403      ;
; 1.129 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.404      ;
; 1.131 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.406      ;
; 1.134 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.066      ; 1.394      ;
; 1.147 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.422      ;
; 1.151 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.426      ;
; 1.160 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hblank_reg    ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.077      ; 1.431      ;
; 1.160 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.435      ;
; 1.164 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.439      ;
; 1.172 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.447      ;
; 1.175 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.450      ;
; 1.176 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.451      ;
; 1.179 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.454      ;
; 1.181 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.077      ; 1.452      ;
; 1.183 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.077      ; 1.454      ;
; 1.184 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.077      ; 1.455      ;
; 1.189 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hblank_reg    ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.077      ; 1.460      ;
; 1.189 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.464      ;
; 1.197 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.472      ;
; 1.198 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.077      ; 1.469      ;
; 1.198 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.473      ;
; 1.202 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.477      ;
; 1.223 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.498      ;
; 1.226 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.501      ;
; 1.227 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.077      ; 1.498      ;
; 1.227 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.502      ;
; 1.229 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 1.503      ;
; 1.229 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 1.503      ;
; 1.229 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 1.503      ;
; 1.230 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.077      ; 1.501      ;
; 1.231 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.066      ; 1.491      ;
; 1.237 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hblank_reg    ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.077      ; 1.508      ;
; 1.242 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.066      ; 1.502      ;
; 1.247 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.077      ; 1.518      ;
; 1.247 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.522      ;
; 1.264 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.066      ; 1.524      ;
; 1.266 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.541      ;
; 1.270 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.545      ;
; 1.274 ; svideo_gtia:svideo|phase_count_reg[7]                                                            ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.033      ; 1.391      ;
; 1.281 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.556      ;
; 1.285 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.560      ;
; 1.291 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.566      ;
; 1.293 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.077      ; 1.564      ;
; 1.294 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.569      ;
; 1.295 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.570      ;
; 1.296 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.077      ; 1.567      ;
; 1.296 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.077      ; 1.567      ;
; 1.296 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.077      ; 1.567      ;
; 1.298 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.573      ;
; 1.306 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.581      ;
; 1.308 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.077      ; 1.579      ;
; 1.309 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.584      ;
+-------+--------------------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                                                              ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                 ; To Node                                                                                                                                             ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 11.482 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -10.281      ; -0.781     ; 0.557      ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                           ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                            ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -1.187 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.624      ; 1.697      ;
; -1.187 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.624      ; 1.697      ;
; -1.187 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.624      ; 1.697      ;
; -1.187 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.624      ; 1.697      ;
; -1.187 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.624      ; 1.697      ;
; -1.187 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.624      ; 1.697      ;
; -1.187 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.624      ; 1.697      ;
; -1.187 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.624      ; 1.697      ;
; -1.187 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.624      ; 1.697      ;
; -1.172 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 0.623      ; 1.746      ;
; -1.172 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 0.623      ; 1.746      ;
; -1.172 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 0.623      ; 1.746      ;
; -1.172 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 0.623      ; 1.746      ;
; -1.172 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 0.623      ; 1.746      ;
; -1.172 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 0.623      ; 1.746      ;
; -1.172 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 0.623      ; 1.746      ;
; -1.172 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 0.623      ; 1.746      ;
; -1.172 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 0.623      ; 1.746      ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: 'FPGA_CLK'                                                                                                                                                                                                                                                                               ;
+-------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                                            ; To Node                                                                     ; Launch Clock                                                                        ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; 0.196 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.725      ; 2.282      ;
; 0.196 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.725      ; 2.282      ;
; 0.196 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.725      ; 2.282      ;
; 0.196 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.725      ; 2.282      ;
; 0.196 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.725      ; 2.282      ;
; 0.196 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.725      ; 2.282      ;
; 0.196 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.725      ; 2.282      ;
; 0.196 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.725      ; 2.282      ;
; 0.196 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.725      ; 2.282      ;
; 0.196 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.725      ; 2.282      ;
; 0.196 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.725      ; 2.282      ;
; 0.196 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.725      ; 2.282      ;
; 0.205 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.724      ; 2.272      ;
; 0.205 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.722      ; 2.270      ;
; 0.205 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.722      ; 2.270      ;
; 0.205 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.722      ; 2.270      ;
; 0.205 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.722      ; 2.270      ;
; 0.205 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.722      ; 2.270      ;
; 0.205 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.722      ; 2.270      ;
; 0.205 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.722      ; 2.270      ;
; 0.205 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.722      ; 2.270      ;
; 0.205 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.722      ; 2.270      ;
; 0.205 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.722      ; 2.270      ;
; 0.205 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.722      ; 2.270      ;
; 0.205 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.722      ; 2.270      ;
; 0.205 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.722      ; 2.270      ;
+-------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                               ;
+-------+---------------------------------------+-----------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                                                                                       ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+-----------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 9.573 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 1.986      ;
; 9.573 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 1.986      ;
; 9.573 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 1.986      ;
; 9.573 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 1.986      ;
; 9.573 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 1.986      ;
; 9.573 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 1.986      ;
; 9.573 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 1.986      ;
; 9.598 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|scl_ena                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 1.952      ;
; 9.598 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|ack_error                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 1.952      ;
; 9.601 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[2]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.090     ; 1.954      ;
; 9.606 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[14]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 1.954      ;
; 9.606 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[15]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 1.954      ;
; 9.606 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[13]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 1.954      ;
; 9.615 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[21]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 1.944      ;
; 9.615 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[19]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 1.944      ;
; 9.615 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[18]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 1.944      ;
; 9.616 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_select_reg[0]                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 1.945      ;
; 9.625 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 1.931      ;
; 9.625 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[30]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 1.931      ;
; 9.625 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[29]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 1.931      ;
; 9.625 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[31]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 1.931      ;
; 9.625 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[13]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 1.931      ;
; 9.625 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[12]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 1.931      ;
; 9.625 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[24]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 1.931      ;
; 9.625 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[23]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 1.931      ;
; 9.625 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[14]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 1.931      ;
; 9.625 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[28]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 1.931      ;
; 9.627 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[6]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 1.934      ;
; 9.627 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[5]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 1.934      ;
; 9.627 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[4]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 1.934      ;
; 9.627 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[2]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 1.934      ;
; 9.794 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[0]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.100     ; 1.751      ;
; 9.794 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[1]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.100     ; 1.751      ;
; 9.794 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[2]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.100     ; 1.751      ;
; 9.794 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[3]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.100     ; 1.751      ;
; 9.794 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[4]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.100     ; 1.751      ;
; 9.794 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[5]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.100     ; 1.751      ;
; 9.794 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[6]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.100     ; 1.751      ;
; 9.794 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[7]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.100     ; 1.751      ;
; 9.794 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[8]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.100     ; 1.751      ;
; 9.794 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[9]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.100     ; 1.751      ;
; 9.794 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[10]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.100     ; 1.751      ;
; 9.794 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[11]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.100     ; 1.751      ;
; 9.794 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[12]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.100     ; 1.751      ;
; 9.794 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[13]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.100     ; 1.751      ;
; 9.794 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[14]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.100     ; 1.751      ;
; 9.794 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[15]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.100     ; 1.751      ;
; 9.795 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[6]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.093     ; 1.757      ;
; 9.795 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[4]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.093     ; 1.757      ;
; 9.795 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[7]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.093     ; 1.757      ;
; 9.795 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[6]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.093     ; 1.757      ;
; 9.795 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[5]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.090     ; 1.760      ;
; 9.795 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[4]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.093     ; 1.757      ;
; 9.795 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[0]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.100     ; 1.750      ;
; 9.795 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[30]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.099     ; 1.751      ;
; 9.795 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[8]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 1.756      ;
; 9.795 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[9]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 1.756      ;
; 9.795 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[14]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.099     ; 1.751      ;
; 9.795 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[15]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.099     ; 1.751      ;
; 9.795 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[29]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 1.756      ;
; 9.795 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[29]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.100     ; 1.750      ;
; 9.795 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[29]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.100     ; 1.750      ;
; 9.795 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[0]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.090     ; 1.760      ;
; 9.795 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[16]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 1.756      ;
; 9.795 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[17]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 1.756      ;
; 9.795 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[8]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.093     ; 1.757      ;
; 9.795 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[9]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.093     ; 1.757      ;
; 9.795 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[15]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 1.756      ;
; 9.795 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[2]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 1.756      ;
; 9.795 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[3]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.093     ; 1.757      ;
; 9.795 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[6]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 1.756      ;
; 9.795 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[0]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.100     ; 1.750      ;
; 9.795 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[21]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.099     ; 1.751      ;
; 9.795 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[21]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.100     ; 1.750      ;
; 9.795 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[21]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.100     ; 1.750      ;
; 9.795 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[16]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 1.756      ;
; 9.795 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[10]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.099     ; 1.751      ;
; 9.795 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[11]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.099     ; 1.751      ;
; 9.795 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[12]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.099     ; 1.751      ;
; 9.795 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[13]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.099     ; 1.751      ;
; 9.795 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[14]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.099     ; 1.751      ;
; 9.795 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[15]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.099     ; 1.751      ;
; 9.795 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[9]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.100     ; 1.750      ;
; 9.795 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[5]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.100     ; 1.750      ;
; 9.795 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[13]         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 1.755      ;
; 9.795 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[6]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 1.756      ;
; 9.795 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[22]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 1.756      ;
; 9.795 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[17]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 1.756      ;
; 9.795 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[13]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.099     ; 1.751      ;
; 9.795 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[9]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.093     ; 1.757      ;
; 9.795 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[16]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 1.756      ;
; 9.795 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[2]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 1.756      ;
; 9.795 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[15]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 1.756      ;
; 9.795 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[15]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.100     ; 1.750      ;
; 9.795 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[15]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.100     ; 1.750      ;
; 9.795 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[8]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.093     ; 1.757      ;
; 9.795 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[3]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.093     ; 1.757      ;
; 9.796 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|bit_cnt[0]                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 1.754      ;
; 9.796 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|bit_cnt[1]                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 1.754      ;
; 9.796 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|state.mstr_ack                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.096     ; 1.753      ;
+-------+---------------------------------------+-----------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                        ;
+-------+------------------------+-------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                               ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+-------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 9.603 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[7]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.149     ; 1.842      ;
; 9.635 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[4]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.109     ; 1.852      ;
; 9.635 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[5]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.109     ; 1.852      ;
; 9.635 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[6]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.111     ; 1.850      ;
; 9.635 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[7]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.111     ; 1.850      ;
; 9.635 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[8]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.111     ; 1.850      ;
; 9.635 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.110     ; 1.851      ;
; 9.635 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[11]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.110     ; 1.851      ;
; 9.638 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.087     ; 1.919      ;
; 9.639 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[8]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.125     ; 1.833      ;
; 9.640 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[9]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.131     ; 1.826      ;
; 9.641 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[8]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.179     ; 1.775      ;
; 9.642 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[9]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.185     ; 1.768      ;
; 9.642 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[13]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.126     ; 1.829      ;
; 9.642 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[14]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.126     ; 1.829      ;
; 9.642 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[15]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.126     ; 1.829      ;
; 9.644 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[15]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.180     ; 1.771      ;
; 9.644 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[14]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.180     ; 1.771      ;
; 9.644 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[13]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.180     ; 1.771      ;
; 9.644 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[10]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.127     ; 1.826      ;
; 9.644 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[11]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.127     ; 1.826      ;
; 9.644 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[12]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.127     ; 1.826      ;
; 9.646 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[11]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.181     ; 1.768      ;
; 9.646 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[10]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.181     ; 1.768      ;
; 9.646 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[12]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.181     ; 1.768      ;
; 9.648 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[0]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 1.843      ;
; 9.648 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[1]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 1.843      ;
; 9.648 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[2]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 1.846      ;
; 9.648 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[3]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 1.846      ;
; 9.648 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[5]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.115     ; 1.834      ;
; 9.648 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[7]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.845      ;
; 9.648 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[0]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 1.843      ;
; 9.648 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[1]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 1.843      ;
; 9.648 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 1.843      ;
; 9.649 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[4]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.129     ; 1.819      ;
; 9.650 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[5]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.169     ; 1.776      ;
; 9.651 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[4]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.183     ; 1.761      ;
; 9.651 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[3]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.114     ; 1.832      ;
; 9.652 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[6]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.120     ; 1.825      ;
; 9.653 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[3]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.168     ; 1.774      ;
; 9.653 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[0]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.118     ; 1.826      ;
; 9.653 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[1]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.118     ; 1.826      ;
; 9.653 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[2]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.118     ; 1.826      ;
; 9.654 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[6]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 1.767      ;
; 9.655 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[2]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.172     ; 1.768      ;
; 9.655 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[0]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.172     ; 1.768      ;
; 9.655 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[1]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.172     ; 1.768      ;
; 9.670 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 1.872      ;
; 9.671 ; sdram_reset_ctrl_n_reg ; ram_di_reg[3]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 1.868      ;
; 9.671 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 1.868      ;
; 9.671 ; sdram_reset_ctrl_n_reg ; ram_di_reg[6]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 1.868      ;
; 9.671 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 1.868      ;
; 9.671 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 1.868      ;
; 9.671 ; sdram_reset_ctrl_n_reg ; ram_di_reg[14]                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 1.868      ;
; 9.671 ; sdram_reset_ctrl_n_reg ; ram_di_reg[15]                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 1.868      ;
; 9.676 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.104     ; 1.864      ;
; 9.676 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.104     ; 1.864      ;
; 9.676 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.865      ;
; 9.676 ; sdram_reset_ctrl_n_reg ; ram_do_reg[19]                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.865      ;
; 9.676 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.865      ;
; 9.676 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.865      ;
; 9.676 ; sdram_reset_ctrl_n_reg ; ram_do_reg[25]                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.865      ;
; 9.676 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.865      ;
; 9.676 ; sdram_reset_ctrl_n_reg ; ram_do_reg[20]                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.104     ; 1.864      ;
; 9.676 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.104     ; 1.864      ;
; 9.676 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.869      ;
; 9.676 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.869      ;
; 9.676 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.869      ;
; 9.677 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 1.865      ;
; 9.677 ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.868      ;
; 9.682 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.859      ;
; 9.682 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.859      ;
; 9.682 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.094     ; 1.868      ;
; 9.682 ; sdram_reset_ctrl_n_reg ; ram_do_reg[5]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.094     ; 1.868      ;
; 9.682 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.094     ; 1.868      ;
; 9.682 ; sdram_reset_ctrl_n_reg ; ram_do_reg[13]                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.094     ; 1.868      ;
; 9.682 ; sdram_reset_ctrl_n_reg ; ram_do_reg[12]                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.094     ; 1.868      ;
; 9.682 ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.859      ;
; 9.682 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.859      ;
; 9.682 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.859      ;
; 9.682 ; sdram_reset_ctrl_n_reg ; ram_do_reg[10]                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.094     ; 1.868      ;
; 9.682 ; sdram_reset_ctrl_n_reg ; ram_do_reg[9]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.094     ; 1.868      ;
; 9.682 ; sdram_reset_ctrl_n_reg ; ram_do_reg[8]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.094     ; 1.868      ;
; 9.682 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 1.865      ;
; 9.683 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.098     ; 1.863      ;
; 9.745 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.109     ; 1.742      ;
; 9.758 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.735      ;
; 9.758 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.735      ;
; 9.759 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.734      ;
; 9.759 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.734      ;
; 9.759 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.734      ;
; 9.871 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.091     ; 1.682      ;
; 9.871 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.091     ; 1.682      ;
; 9.871 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_bctr[0]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.670      ;
; 9.871 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.670      ;
; 9.871 ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.670      ;
; 9.871 ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.670      ;
; 9.871 ; sdram_reset_ctrl_n_reg ; ram_di_reg[11]                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.670      ;
; 9.871 ; sdram_reset_ctrl_n_reg ; ram_di_reg[12]                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.670      ;
; 9.871 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.091     ; 1.682      ;
+-------+------------------------+-------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                       ;
+--------+--------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                            ; To Node                               ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 15.130 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.110     ; 2.278      ;
; 15.130 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.110     ; 2.278      ;
; 15.130 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.110     ; 2.278      ;
; 15.130 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.110     ; 2.278      ;
; 15.130 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.110     ; 2.278      ;
; 15.130 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.110     ; 2.278      ;
; 15.130 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.110     ; 2.278      ;
; 15.130 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.110     ; 2.278      ;
; 15.139 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.107     ; 2.272      ;
; 15.139 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.107     ; 2.272      ;
; 15.139 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.107     ; 2.272      ;
; 15.139 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.107     ; 2.272      ;
; 15.139 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.107     ; 2.272      ;
; 15.139 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.107     ; 2.272      ;
+--------+--------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: 'FPGA_CLK'                                                                                                                                                                                                                                                                                 ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                            ; To Node                                                                     ; Launch Clock                                                                        ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.387 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.160      ; 2.023      ;
; -0.387 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.158      ; 2.021      ;
; -0.387 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.158      ; 2.021      ;
; -0.387 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.158      ; 2.021      ;
; -0.387 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.158      ; 2.021      ;
; -0.387 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.158      ; 2.021      ;
; -0.387 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.158      ; 2.021      ;
; -0.387 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.158      ; 2.021      ;
; -0.387 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.158      ; 2.021      ;
; -0.387 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.158      ; 2.021      ;
; -0.387 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.158      ; 2.021      ;
; -0.387 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.158      ; 2.021      ;
; -0.387 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.158      ; 2.021      ;
; -0.387 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.158      ; 2.021      ;
; -0.380 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.161      ; 2.031      ;
; -0.380 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.161      ; 2.031      ;
; -0.380 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.161      ; 2.031      ;
; -0.380 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.161      ; 2.031      ;
; -0.380 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.161      ; 2.031      ;
; -0.380 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.161      ; 2.031      ;
; -0.380 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.161      ; 2.031      ;
; -0.380 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.161      ; 2.031      ;
; -0.380 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.161      ; 2.031      ;
; -0.380 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.161      ; 2.031      ;
; -0.380 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.161      ; 2.031      ;
; -0.380 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.161      ; 2.031      ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                           ;
+-------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                            ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; 0.100 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 1.258      ; 1.667      ;
; 0.100 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 1.258      ; 1.667      ;
; 0.100 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 1.258      ; 1.667      ;
; 0.100 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 1.258      ; 1.667      ;
; 0.100 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 1.258      ; 1.667      ;
; 0.100 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 1.258      ; 1.667      ;
; 0.100 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 1.258      ; 1.667      ;
; 0.100 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 1.258      ; 1.667      ;
; 0.100 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 1.258      ; 1.667      ;
; 0.161 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.259      ; 1.612      ;
; 0.161 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.259      ; 1.612      ;
; 0.161 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.259      ; 1.612      ;
; 0.161 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.259      ; 1.612      ;
; 0.161 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.259      ; 1.612      ;
; 0.161 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.259      ; 1.612      ;
; 0.161 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.259      ; 1.612      ;
; 0.161 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.259      ; 1.612      ;
; 0.161 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.259      ; 1.612      ;
+-------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                         ; To Node                                                                                                                                                                                                               ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.851 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a47 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.115      ;
; 0.851 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a46 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.115      ;
; 0.851 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a45 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.115      ;
; 0.851 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a44 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.115      ;
; 0.851 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a43 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.115      ;
; 0.851 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a42 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.115      ;
; 0.851 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a41 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.115      ;
; 0.851 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a40 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.115      ;
; 0.851 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a35 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.115      ;
; 0.851 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a34 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.115      ;
; 0.851 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a33 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.115      ;
; 0.851 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a32 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.115      ;
; 0.851 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a15 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.115      ;
; 0.851 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a14 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.115      ;
; 0.851 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a13 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.115      ;
; 0.851 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a12 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.115      ;
; 0.851 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a11 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.115      ;
; 0.851 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a10 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.115      ;
; 0.851 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a9  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.115      ;
; 0.851 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a8  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.115      ;
; 0.851 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a7  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.115      ;
; 0.851 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a6  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.115      ;
; 0.851 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a5  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.115      ;
; 0.851 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a4  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.115      ;
; 0.851 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a3  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.115      ;
; 0.851 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a2  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.115      ;
; 0.851 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a1  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.115      ;
; 0.851 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.115      ;
; 1.007 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a63 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.271      ;
; 1.007 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a62 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.271      ;
; 1.007 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a61 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.271      ;
; 1.007 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a60 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.271      ;
; 1.007 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a59 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.271      ;
; 1.007 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a58 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.271      ;
; 1.007 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a57 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.271      ;
; 1.007 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a56 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.271      ;
; 1.007 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a55 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.271      ;
; 1.007 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a54 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.271      ;
; 1.007 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a53 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.271      ;
; 1.007 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a52 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.271      ;
; 1.007 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a51 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.271      ;
; 1.007 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a50 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.271      ;
; 1.007 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a49 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.271      ;
; 1.007 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a48 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.271      ;
; 1.007 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a39 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.271      ;
; 1.007 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a38 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.271      ;
; 1.007 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a37 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.271      ;
; 1.007 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a36 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.271      ;
; 1.007 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a31 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.271      ;
; 1.007 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a30 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.271      ;
; 1.007 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a29 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.271      ;
; 1.007 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a28 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.271      ;
; 1.007 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a27 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.271      ;
; 1.007 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a26 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.271      ;
; 1.007 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a25 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.271      ;
; 1.007 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a24 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.271      ;
; 1.007 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a23 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.271      ;
; 1.007 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a22 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.271      ;
; 1.007 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a21 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.271      ;
; 1.007 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a20 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.271      ;
; 1.007 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a19 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.271      ;
; 1.007 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a18 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.271      ;
; 1.007 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a17 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.271      ;
; 1.007 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 1.271      ;
; 1.194 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[3]                                                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.279      ; 1.668      ;
; 1.194 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[1]                                                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.279      ; 1.668      ;
; 1.249 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[3]                                                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.280      ; 1.613      ;
; 1.249 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[1]                                                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.280      ; 1.613      ;
; 1.373 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]                                                                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 1.665      ;
; 1.373 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                                                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 1.665      ;
; 1.373 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[8]                                                                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 1.665      ;
; 1.373 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[2]                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.094      ; 1.662      ;
; 1.373 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[0]                                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.095      ; 1.663      ;
; 1.373 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[1]                                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.094      ; 1.662      ;
; 1.373 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[6]                                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.095      ; 1.663      ;
; 1.373 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[7]                                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.095      ; 1.663      ;
; 1.373 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[10]                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.094      ; 1.662      ;
; 1.373 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[11]                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.094      ; 1.662      ;
; 1.373 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[13]                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.095      ; 1.663      ;
; 1.373 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[27]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.094      ; 1.662      ;
; 1.373 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[10]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.087      ; 1.655      ;
; 1.373 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[11]                                                                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 1.665      ;
; 1.373 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[24]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.094      ; 1.662      ;
; 1.373 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[16]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.094      ; 1.662      ;
; 1.373 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[23]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.094      ; 1.662      ;
; 1.374 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[16]                                                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.088      ; 1.657      ;
; 1.374 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[18]                                                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.088      ; 1.657      ;
; 1.374 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[19]                                                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.088      ; 1.657      ;
; 1.374 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[20]                                                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.088      ; 1.657      ;
; 1.374 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[21]                                                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.088      ; 1.657      ;
; 1.374 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[22]                                                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.088      ; 1.657      ;
; 1.374 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[23]                                                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.088      ; 1.657      ;
; 1.374 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[24]                                                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.088      ; 1.657      ;
; 1.374 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[25]                                                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.088      ; 1.657      ;
; 1.374 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[26]                                                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.088      ; 1.657      ;
; 1.374 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[27]                                                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.088      ; 1.657      ;
; 1.374 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[28]                                                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.088      ; 1.657      ;
; 1.374 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[29]                                                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.088      ; 1.657      ;
; 1.374 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[26]                                                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.085      ; 1.654      ;
; 1.374 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[30]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.087      ; 1.656      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                             ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 1.236 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.087      ; 1.516      ;
; 1.236 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 1.519      ;
; 1.236 ; sdram_reset_ctrl_n_reg ; ram_do_reg[15]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.087      ; 1.516      ;
; 1.236 ; sdram_reset_ctrl_n_reg ; ram_do_reg[14]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.087      ; 1.516      ;
; 1.236 ; sdram_reset_ctrl_n_reg ; ram_do_reg[11]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.087      ; 1.516      ;
; 1.237 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.514      ;
; 1.237 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.512      ;
; 1.238 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 1.521      ;
; 1.238 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 1.521      ;
; 1.238 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 1.521      ;
; 1.238 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 1.521      ;
; 1.238 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 1.521      ;
; 1.238 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 1.521      ;
; 1.238 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 1.521      ;
; 1.238 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 1.521      ;
; 1.238 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 1.521      ;
; 1.238 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 1.521      ;
; 1.238 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 1.521      ;
; 1.238 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 1.521      ;
; 1.238 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 1.521      ;
; 1.238 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 1.521      ;
; 1.238 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 1.521      ;
; 1.238 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 1.521      ;
; 1.240 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 1.523      ;
; 1.240 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 1.523      ;
; 1.240 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 1.523      ;
; 1.241 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.514      ;
; 1.241 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.514      ;
; 1.241 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.514      ;
; 1.241 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.515      ;
; 1.241 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.515      ;
; 1.241 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.515      ;
; 1.241 ; sdram_reset_ctrl_n_reg ; seq_reg[5]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.515      ;
; 1.241 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.514      ;
; 1.241 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.514      ;
; 1.241 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.514      ;
; 1.241 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.514      ;
; 1.241 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.514      ;
; 1.241 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.515      ;
; 1.241 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.515      ;
; 1.241 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.515      ;
; 1.241 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.515      ;
; 1.241 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.515      ;
; 1.241 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.515      ;
; 1.241 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.515      ;
; 1.241 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.512      ;
; 1.241 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.515      ;
; 1.241 ; sdram_reset_ctrl_n_reg ; ram_di_reg[5]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.515      ;
; 1.241 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.512      ;
; 1.241 ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.512      ;
; 1.241 ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.512      ;
; 1.241 ; sdram_reset_ctrl_n_reg ; ram_di_reg[11]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.512      ;
; 1.241 ; sdram_reset_ctrl_n_reg ; ram_di_reg[12]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.512      ;
; 1.241 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[1]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.512      ;
; 1.241 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[0]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.512      ;
; 1.354 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.067      ; 1.586      ;
; 1.354 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.067      ; 1.586      ;
; 1.354 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.067      ; 1.586      ;
; 1.355 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.067      ; 1.587      ;
; 1.355 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.067      ; 1.587      ;
; 1.367 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.061      ; 1.593      ;
; 1.409 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.087      ; 1.689      ;
; 1.409 ; sdram_reset_ctrl_n_reg ; ram_do_reg[5]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.087      ; 1.689      ;
; 1.409 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.087      ; 1.689      ;
; 1.409 ; sdram_reset_ctrl_n_reg ; ram_do_reg[13]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.087      ; 1.689      ;
; 1.409 ; sdram_reset_ctrl_n_reg ; ram_do_reg[12]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.087      ; 1.689      ;
; 1.409 ; sdram_reset_ctrl_n_reg ; ram_do_reg[10]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.087      ; 1.689      ;
; 1.409 ; sdram_reset_ctrl_n_reg ; ram_do_reg[9]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.087      ; 1.689      ;
; 1.409 ; sdram_reset_ctrl_n_reg ; ram_do_reg[8]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.087      ; 1.689      ;
; 1.410 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.681      ;
; 1.410 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.681      ;
; 1.410 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 1.686      ;
; 1.410 ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.681      ;
; 1.410 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.681      ;
; 1.410 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.681      ;
; 1.410 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.687      ;
; 1.413 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.077      ; 1.683      ;
; 1.413 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.077      ; 1.683      ;
; 1.413 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.684      ;
; 1.413 ; sdram_reset_ctrl_n_reg ; ram_do_reg[19]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.684      ;
; 1.413 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.684      ;
; 1.413 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.684      ;
; 1.413 ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.688      ;
; 1.413 ; sdram_reset_ctrl_n_reg ; ram_do_reg[25]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.684      ;
; 1.413 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.684      ;
; 1.413 ; sdram_reset_ctrl_n_reg ; ram_do_reg[20]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.077      ; 1.683      ;
; 1.413 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.077      ; 1.683      ;
; 1.414 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.689      ;
; 1.414 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.689      ;
; 1.414 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.689      ;
; 1.415 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 1.687      ;
; 1.418 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 1.690      ;
; 1.418 ; sdram_reset_ctrl_n_reg ; ram_di_reg[3]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.076      ; 1.687      ;
; 1.418 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.076      ; 1.687      ;
; 1.418 ; sdram_reset_ctrl_n_reg ; ram_di_reg[6]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.076      ; 1.687      ;
; 1.418 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.076      ; 1.687      ;
; 1.418 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.076      ; 1.687      ;
; 1.418 ; sdram_reset_ctrl_n_reg ; ram_di_reg[14]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.076      ; 1.687      ;
; 1.418 ; sdram_reset_ctrl_n_reg ; ram_di_reg[15]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.076      ; 1.687      ;
; 1.435 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.095      ; 1.723      ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                       ;
+-------+--------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                            ; To Node                               ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 1.756 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.074      ; 2.024      ;
; 1.756 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.074      ; 2.024      ;
; 1.756 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.074      ; 2.024      ;
; 1.756 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.074      ; 2.024      ;
; 1.756 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.074      ; 2.024      ;
; 1.756 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.074      ; 2.024      ;
; 1.762 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 2.027      ;
; 1.762 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 2.027      ;
; 1.762 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 2.027      ;
; 1.762 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 2.027      ;
; 1.762 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 2.027      ;
; 1.762 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 2.027      ;
; 1.762 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 2.027      ;
; 1.762 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 2.027      ;
+-------+--------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                         ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                               ; Clock Edge ; Target                                                    ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[0]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[1]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[2]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[5]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[17]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[18]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[1]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[20]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[21]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[23]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[26]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[27]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[28]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[29]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[30]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[6]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel[0]                     ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_act                      ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_act                    ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_req                    ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_act                      ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_complete_reg                                ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[0]                                                ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[10]                                               ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[11]                                               ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[1]                                                ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[2]                                                ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[3]                                                ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[4]                                                ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[5]                                                ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[6]                                                ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[7]                                                ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[8]                                                ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[9]                                                ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[0]                                           ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[1]                                           ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[10]                                            ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[11]                                            ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[12]                                            ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[13]                                            ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[14]                                            ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[15]                                            ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[3]                                             ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[4]                                             ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[6]                                             ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[7]                                             ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[8]                                             ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[9]                                             ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[0]                                             ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[10]                                            ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[11]                                            ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[12]                                            ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[13]                                            ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[14]                                            ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[15]                                            ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[16]                                            ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[19]                                            ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[22]                                            ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[24]                                            ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[25]                                            ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[2]                                             ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[31]                                            ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[3]                                             ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[4]                                             ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[5]                                             ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[8]                                             ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[9]                                             ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|sdram_rdy                     ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_reg                                         ;
; 5.657 ; 5.873        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_reg                      ;
; 5.657 ; 5.873        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ;
; 5.657 ; 5.873        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_reg                      ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[7]                                             ;
; 5.663 ; 5.818        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[3]                   ;
; 5.664 ; 5.819        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[5]                   ;
; 5.665 ; 5.820        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[9]                   ;
; 5.666 ; 5.821        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[0]                   ;
; 5.666 ; 5.821        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[10]                  ;
; 5.666 ; 5.821        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[11]                  ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                   ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                               ; Clock Edge ; Target                                                                                                                                              ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; 5.801 ; 5.870        ; 0.069          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 5.824 ; 5.877        ; 0.053          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 5.870 ; 5.870        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 5.877 ; 5.877        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                    ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                               ; Clock Edge ; Target                                                                                                                                              ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; 8.592  ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ;
; 8.592  ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ;
; 8.592  ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ;
; 8.592  ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ;
; 8.592  ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ;
; 8.592  ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ;
; 8.592  ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ;
; 8.592  ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ;
; 8.593  ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[2]                                                                                                               ;
; 8.593  ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[3]                                                                                                               ;
; 8.593  ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[4]                                                                                                               ;
; 8.593  ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[5]                                                                                                               ;
; 8.593  ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[6]                                                                                                               ;
; 8.593  ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[7]                                                                                                               ;
; 8.626  ; 8.810        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[2]                                                                                                               ;
; 8.626  ; 8.810        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[3]                                                                                                               ;
; 8.626  ; 8.810        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[4]                                                                                                               ;
; 8.626  ; 8.810        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[5]                                                                                                               ;
; 8.626  ; 8.810        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[6]                                                                                                               ;
; 8.626  ; 8.810        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[7]                                                                                                               ;
; 8.627  ; 8.811        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ;
; 8.627  ; 8.811        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ;
; 8.627  ; 8.811        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ;
; 8.627  ; 8.811        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ;
; 8.627  ; 8.811        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ;
; 8.627  ; 8.811        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ;
; 8.627  ; 8.811        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ;
; 8.627  ; 8.811        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ;
; 8.738  ; 8.807        ; 0.069          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 8.761  ; 8.814        ; 0.053          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 8.806  ; 8.806        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[2]|clk                                                                                                                       ;
; 8.806  ; 8.806        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[3]|clk                                                                                                                       ;
; 8.806  ; 8.806        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[4]|clk                                                                                                                       ;
; 8.806  ; 8.806        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[5]|clk                                                                                                                       ;
; 8.806  ; 8.806        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[6]|clk                                                                                                                       ;
; 8.806  ; 8.806        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[7]|clk                                                                                                                       ;
; 8.807  ; 8.807        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 8.807  ; 8.807        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|outclk                                                 ;
; 8.807  ; 8.807        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[0]|clk                                                                                                                              ;
; 8.807  ; 8.807        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[1]|clk                                                                                                                              ;
; 8.807  ; 8.807        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[2]|clk                                                                                                                              ;
; 8.807  ; 8.807        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[3]|clk                                                                                                                              ;
; 8.807  ; 8.807        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[4]|clk                                                                                                                              ;
; 8.807  ; 8.807        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[5]|clk                                                                                                                              ;
; 8.807  ; 8.807        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[6]|clk                                                                                                                              ;
; 8.807  ; 8.807        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[7]|clk                                                                                                                              ;
; 8.814  ; 8.814        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 8.814  ; 8.814        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|outclk                                                 ;
; 8.814  ; 8.814        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[0]|clk                                                                                                                              ;
; 8.814  ; 8.814        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[1]|clk                                                                                                                              ;
; 8.814  ; 8.814        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[2]|clk                                                                                                                              ;
; 8.814  ; 8.814        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[3]|clk                                                                                                                              ;
; 8.814  ; 8.814        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[4]|clk                                                                                                                              ;
; 8.814  ; 8.814        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[5]|clk                                                                                                                              ;
; 8.814  ; 8.814        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[6]|clk                                                                                                                              ;
; 8.814  ; 8.814        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[7]|clk                                                                                                                              ;
; 8.815  ; 8.815        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[2]|clk                                                                                                                       ;
; 8.815  ; 8.815        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[3]|clk                                                                                                                       ;
; 8.815  ; 8.815        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[4]|clk                                                                                                                       ;
; 8.815  ; 8.815        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[5]|clk                                                                                                                       ;
; 8.815  ; 8.815        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[6]|clk                                                                                                                       ;
; 8.815  ; 8.815        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[7]|clk                                                                                                                       ;
; 15.621 ; 17.621       ; 2.000          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ;
; 15.621 ; 17.621       ; 2.000          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ;
; 15.621 ; 17.621       ; 2.000          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ;
; 15.621 ; 17.621       ; 2.000          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ;
; 15.621 ; 17.621       ; 2.000          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ;
; 15.621 ; 17.621       ; 2.000          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ;
; 15.621 ; 17.621       ; 2.000          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ;
; 15.621 ; 17.621       ; 2.000          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ;
; 15.621 ; 17.621       ; 2.000          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[2]                                                                                                               ;
; 15.621 ; 17.621       ; 2.000          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[3]                                                                                                               ;
; 15.621 ; 17.621       ; 2.000          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[4]                                                                                                               ;
; 15.621 ; 17.621       ; 2.000          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[5]                                                                                                               ;
; 15.621 ; 17.621       ; 2.000          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[6]                                                                                                               ;
; 15.621 ; 17.621       ; 2.000          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[7]                                                                                                               ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                    ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                               ; Clock Edge ; Target                                                                                                                                                                                                                                                              ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 9.376  ; 10.386       ; 1.010          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                                         ;
; 9.435  ; 10.445       ; 1.010          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                                         ;
; 10.161 ; 10.391       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|altsyncram:altsyncram4|altsyncram_i0m3:auto_generated|ram_block1a0~porta_address_reg0                 ;
; 10.161 ; 10.391       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|altsyncram:altsyncram4|altsyncram_nsl3:auto_generated|ram_block1a0~porta_address_reg0 ;
; 10.163 ; 10.393       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|altsyncram:altsyncram4|altsyncram_i0m3:auto_generated|ram_block1a0~porta_datain_reg0                  ;
; 10.163 ; 10.393       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|altsyncram:altsyncram4|altsyncram_nsl3:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 10.163 ; 10.393       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_address_reg0                    ;
; 10.163 ; 10.393       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_we_reg                          ;
; 10.165 ; 10.395       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0                     ;
; 10.165 ; 10.395       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~portb_address_reg0                    ;
; 10.165 ; 10.395       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]                                                                                                ;
; 10.165 ; 10.395       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]                                                                                                ;
; 10.165 ; 10.395       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]                                                                                                ;
; 10.165 ; 10.395       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]                                                                                                ;
; 10.165 ; 10.395       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]                                                                                                ;
; 10.165 ; 10.395       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]                                                                                                ;
; 10.165 ; 10.395       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]                                                                                                ;
; 10.165 ; 10.395       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]                                                                                                ;
; 10.165 ; 10.395       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_address_reg0                    ;
; 10.165 ; 10.395       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_we_reg                          ;
; 10.166 ; 10.396       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~portb_address_reg0                    ;
; 10.166 ; 10.396       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]                                                                                                ;
; 10.166 ; 10.396       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]                                                                                                ;
; 10.166 ; 10.396       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]                                                                                                ;
; 10.166 ; 10.396       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]                                                                                                ;
; 10.166 ; 10.396       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]                                                                                                ;
; 10.166 ; 10.396       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]                                                                                                ;
; 10.166 ; 10.396       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]                                                                                                ;
; 10.166 ; 10.396       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]                                                                                                ;
; 10.167 ; 10.397       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0                     ;
; 10.184 ; 10.400       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|configupdate3_state                                                                                   ;
; 10.184 ; 10.400       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|configupdate3_state                                                                   ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[10]                                                                                     ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[11]                                                                                     ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[12]                                                                                     ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]                                                                                     ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[14]                                                                                     ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[15]                                                                                     ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2]                                                                                      ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3]                                                                                      ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[4]                                                                                      ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[5]                                                                                      ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[6]                                                                                      ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[7]                                                                                      ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[8]                                                                                      ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9]                                                                                      ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[0]                                                                                                ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[1]                                                                                                ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[6]                                                                                                ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[7]                                                                                                ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[0]                                                                                        ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[1]                                                                                        ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[0]                                                                                                 ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[1]                                                                                                 ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[2]                                                                                                 ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[3]                                                                                                 ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|rxStatusMonitor:u_rxStatusMonitor|oldConnectState[0]                                                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|rxStatusMonitor:u_rxStatusMonitor|oldConnectState[1]                                                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[0]                                                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[1]                                                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg2                                                         ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireEdgeDetect                                                         ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[0]                                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[1]                                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[2]                                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[3]                                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[4]                                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[5]                                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[6]                                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[7]                                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                                                                          ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[1]                                                                                          ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[2]                                                                                          ;
; 10.202 ; 10.432       ; 0.230          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]                                                                                                ;
; 10.202 ; 10.432       ; 0.230          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]                                                                                                ;
; 10.202 ; 10.432       ; 0.230          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]                                                                                                ;
; 10.202 ; 10.432       ; 0.230          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]                                                                                                ;
; 10.202 ; 10.432       ; 0.230          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]                                                                                                ;
; 10.202 ; 10.432       ; 0.230          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]                                                                                                ;
; 10.202 ; 10.432       ; 0.230          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]                                                                                                ;
; 10.202 ; 10.432       ; 0.230          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]                                                                                                ;
; 10.202 ; 10.386       ; 0.184          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]                                                                                      ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[0]                                                                                            ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[1]                                                                                            ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[2]                                                                                            ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[3]                                                                                            ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[4]                                                                                            ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[5]                                                                                            ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[6]                                                                                            ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[7]                                                                                            ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[0]                                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[1]                                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[2]                                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[3]                                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[4]                                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[5]                                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[6]                                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[7]                                                           ;
; 10.203 ; 10.433       ; 0.230          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]                                                                                                ;
; 10.203 ; 10.433       ; 0.230          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]                                                                                                ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                ;
+--------+--------------+----------------+-----------------+-------------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type            ; Clock                                                                               ; Clock Edge ; Target                                                                                                                                                                                                                                           ;
+--------+--------------+----------------+-----------------+-------------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a33~porta_address_reg0                                                                                                                                 ;
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_qg41:auto_generated|ram_block1a2~porta_address_reg0                                                                                                                 ;
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_qg41:auto_generated|ram_block1a2~porta_we_reg                                                                                                                       ;
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_qg41:auto_generated|ram_block1a2~porta_address_reg0                                                                                                                ;
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_qg41:auto_generated|ram_block1a2~porta_we_reg                                                                                                                      ;
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_qg41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                  ;
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_qg41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                        ;
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_qg41:auto_generated|ram_block1a2~porta_address_reg0                                                                                                                  ;
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_qg41:auto_generated|ram_block1a2~porta_we_reg                                                                                                                        ;
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|altsyncram_lh81:FIFOram|ram_block1a0~porta_address_reg0                   ;
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|altsyncram_lh81:FIFOram|ram_block1a0~porta_we_reg                         ;
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_address_reg0 ;
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_we_reg       ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|generic_ram_infer:freezer_bram|altsyncram:ram_block_rtl_0|altsyncram_sd41:auto_generated|ram_block1a0~porta_address_reg0       ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|generic_ram_infer:freezer_bram|altsyncram:ram_block_rtl_0|altsyncram_sd41:auto_generated|ram_block1a0~porta_we_reg             ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_address_reg0          ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_address_reg0         ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                                  ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a10~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a12~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a13~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a14~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a15~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a16~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a18~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a19~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a1~porta_address_reg0                                                                                                                                  ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a21~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a26~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a27~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a29~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a2~porta_address_reg0                                                                                                                                  ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a30~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a3~porta_address_reg0                                                                                                                                  ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a5~porta_address_reg0                                                                                                                                  ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a8~porta_address_reg0                                                                                                                                  ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a9~porta_address_reg0                                                                                                                                  ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_qg41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_qg41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                       ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_address_reg0 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_we_reg       ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|generic_ram_infer:reg_file1|altsyncram:ram_block_rtl_0|altsyncram_ud41:auto_generated|ram_block1a0~porta_address_reg0                                       ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|generic_ram_infer:reg_file1|altsyncram:ram_block_rtl_0|altsyncram_ud41:auto_generated|ram_block1a0~porta_we_reg                                             ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~portb_address_reg0          ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~portb_address_reg0         ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a17~porta_address_reg0                                                                                                                                 ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a20~porta_address_reg0                                                                                                                                 ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a25~porta_address_reg0                                                                                                                                 ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a28~porta_address_reg0                                                                                                                                 ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a31~porta_address_reg0                                                                                                                                 ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a32~porta_address_reg0                                                                                                                                 ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a35~porta_address_reg0                                                                                                                                 ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a39~porta_address_reg0                                                                                                                                 ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a7~porta_address_reg0                                                                                                                                  ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_qg41:auto_generated|ram_block1a2~porta_address_reg0                                                                                                                 ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_qg41:auto_generated|ram_block1a2~porta_we_reg                                                                                                                       ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_qg41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                 ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_qg41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                       ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_qg41:auto_generated|ram_block1a2~porta_datain_reg0                                                                                                                  ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_qg41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_qg41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_qg41:auto_generated|ram_block1a2~porta_datain_reg0                                                                                                                 ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_qg41:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                   ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_qg41:auto_generated|ram_block1a2~porta_datain_reg0                                                                                                                   ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|altsyncram_lh81:FIFOram|ram_block1a0~porta_datain_reg0                    ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|generic_ram_infer:freezer_bram|altsyncram:ram_block_rtl_0|altsyncram_sd41:auto_generated|ram_block1a0~porta_datain_reg0        ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0                             ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a1                             ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a10                            ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a11                            ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a12                            ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a13                            ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a14                            ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a15                            ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a2                             ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a3                             ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a32                            ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a33                            ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a34                            ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a35                            ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a4                             ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a40                            ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a41                            ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a42                            ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a43                            ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a44                            ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a45                            ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a46                            ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a47                            ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a5                             ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a6                             ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a7                             ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a8                             ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a9                             ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a11~porta_address_reg0                                                                                                                                 ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a4~porta_address_reg0                                                                                                                                  ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a6~porta_address_reg0                                                                                                                                  ;
+--------+--------------+----------------+-----------------+-------------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                         ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                              ; Clock Edge ; Target                                                                                                   ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------+
; 17.601 ; 17.601       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.601 ; 17.601       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.601 ; 17.601       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.601 ; 17.601       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]                      ;
; 17.601 ; 17.601       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 17.616 ; 17.616       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.619 ; 17.619       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.619 ; 17.619       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.623 ; 17.623       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.623 ; 17.623       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.626 ; 17.626       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.640 ; 17.640       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.640 ; 17.640       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.640 ; 17.640       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.640 ; 17.640       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]                      ;
; 17.640 ; 17.640       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'                                                                                                                              ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------------+
; Slack   ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                                                       ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------------+
; 89.338  ; 99.438       ; 10.100         ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout        ;
; 90.462  ; 100.562      ; 10.100         ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout        ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                                   ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                                  ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                                  ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                                  ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                                  ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                                  ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                                  ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                                  ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                                  ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                                  ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                                  ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                                   ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                                  ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                                  ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                                  ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                                  ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                                  ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                                   ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                                   ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                                   ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                                   ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                                   ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                                   ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                                   ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                                   ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8                  ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]              ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1]              ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]              ;
; 99.418  ; 99.418       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 99.418  ; 99.418       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 99.420  ; 99.420       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                          ;
; 99.420  ; 99.420       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|observablevcoout                                ;
; 99.438  ; 99.438       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|remote|sd4|clk                                                           ;
; 99.449  ; 99.449       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                             ;
; 99.454  ; 99.454       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[12]|clk                                               ;
; 99.454  ; 99.454       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[13]|clk                                               ;
; 99.454  ; 99.454       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[14]|clk                                               ;
; 99.454  ; 99.454       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[15]|clk                                               ;
; 99.454  ; 99.454       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[16]|clk                                               ;
; 99.454  ; 99.454       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[17]|clk                                               ;
; 99.454  ; 99.454       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[18]|clk                                               ;
; 99.454  ; 99.454       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[19]|clk                                               ;
; 99.454  ; 99.454       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[20]|clk                                               ;
; 99.454  ; 99.454       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[21]|clk                                               ;
; 99.454  ; 99.454       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[22]|clk                                               ;
; 99.454  ; 99.454       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[23]|clk                                               ;
; 99.454  ; 99.454       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[24]|clk                                               ;
; 99.455  ; 99.455       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[0]|clk                                        ;
; 99.455  ; 99.455       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[1]|clk                                        ;
; 99.455  ; 99.455       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[2]|clk                                        ;
; 99.455  ; 99.455       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[0]|clk                                                ;
; 99.455  ; 99.455       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[10]|clk                                               ;
; 99.455  ; 99.455       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[11]|clk                                               ;
; 99.455  ; 99.455       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[1]|clk                                                ;
; 99.455  ; 99.455       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[2]|clk                                                ;
; 99.455  ; 99.455       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[3]|clk                                                ;
; 99.455  ; 99.455       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[4]|clk                                                ;
; 99.455  ; 99.455       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[5]|clk                                                ;
; 99.455  ; 99.455       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[6]|clk                                                ;
; 99.455  ; 99.455       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[7]|clk                                                ;
; 99.455  ; 99.455       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[8]|clk                                                ;
; 99.455  ; 99.455       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[9]|clk                                                ;
; 99.455  ; 99.455       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|remote|dffe8|clk                                                         ;
; 99.460  ; 99.460       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 99.462  ; 99.462       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|inclk[0]                                        ;
; 99.463  ; 99.463       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~inputclkctrl|inclk[0]                                                               ;
; 99.463  ; 99.463       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~inputclkctrl|outclk                                                                 ;
; 100.000 ; 100.000      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                             ;
; 100.000 ; 100.000      ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                             ;
; 100.323 ; 100.539      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                                   ;
; 100.323 ; 100.539      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                                  ;
; 100.323 ; 100.539      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                                  ;
; 100.323 ; 100.539      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                                   ;
; 100.323 ; 100.539      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                                   ;
; 100.323 ; 100.539      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                                   ;
; 100.323 ; 100.539      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                                   ;
; 100.323 ; 100.539      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                                   ;
; 100.323 ; 100.539      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                                   ;
; 100.323 ; 100.539      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                                   ;
; 100.323 ; 100.539      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                                   ;
; 100.323 ; 100.539      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                                   ;
; 100.323 ; 100.539      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8                  ;
; 100.323 ; 100.539      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]              ;
; 100.323 ; 100.539      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1]              ;
; 100.323 ; 100.539      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]              ;
; 100.324 ; 100.540      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                                  ;
; 100.324 ; 100.540      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                                  ;
; 100.324 ; 100.540      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                                  ;
; 100.324 ; 100.540      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                                  ;
; 100.324 ; 100.540      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                                  ;
; 100.324 ; 100.540      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                                  ;
; 100.324 ; 100.540      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                                  ;
; 100.324 ; 100.540      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                                  ;
; 100.324 ; 100.540      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                                  ;
; 100.324 ; 100.540      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                                  ;
; 100.324 ; 100.540      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                                  ;
; 100.324 ; 100.540      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                                  ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                                   ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.441 ; 1.992 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.428 ; 1.979 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.428 ; 1.979 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.428 ; 1.979 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 1.424 ; 1.975 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 1.439 ; 1.990 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 1.425 ; 1.976 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 1.430 ; 1.981 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 1.408 ; 1.957 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 1.435 ; 1.986 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 1.441 ; 1.992 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.437 ; 1.988 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.437 ; 1.988 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.437 ; 1.988 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 1.436 ; 1.987 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.436 ; 1.987 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.436 ; 1.987 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_DAT0       ; FPGA_CLK   ; 1.939 ; 2.431 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 0.405 ; 0.956 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 0.411 ; 0.962 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 0.414 ; 0.965 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 0.409 ; 0.960 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                      ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; -0.960 ; -1.509 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; -0.978 ; -1.529 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; -0.978 ; -1.529 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; -0.978 ; -1.529 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; -0.975 ; -1.526 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; -0.990 ; -1.541 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; -0.976 ; -1.527 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; -0.981 ; -1.532 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; -0.960 ; -1.509 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; -0.986 ; -1.537 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; -0.993 ; -1.544 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; -0.988 ; -1.539 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; -0.988 ; -1.539 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; -0.988 ; -1.539 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; -0.987 ; -1.538 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; -0.987 ; -1.538 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; -0.987 ; -1.538 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_DAT0       ; FPGA_CLK   ; -1.440 ; -1.927 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; -0.093 ; -0.644 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; -0.100 ; -0.651 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; -0.102 ; -0.653 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; -0.097 ; -0.648 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                           ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; SDRAM_A[*]    ; FPGA_CLK   ; 3.420  ; 3.797  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; FPGA_CLK   ; 1.649  ; 1.554  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; FPGA_CLK   ; 1.649  ; 1.554  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; FPGA_CLK   ; 1.652  ; 1.557  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; FPGA_CLK   ; 1.652  ; 1.557  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; FPGA_CLK   ; 1.645  ; 1.550  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; FPGA_CLK   ; 1.645  ; 1.550  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; FPGA_CLK   ; 1.643  ; 1.548  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; FPGA_CLK   ; 1.206  ; 1.180  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; FPGA_CLK   ; 3.420  ; 3.797  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; FPGA_CLK   ; 1.644  ; 1.549  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; FPGA_CLK   ; 1.649  ; 1.554  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; FPGA_CLK   ; 1.644  ; 1.549  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; FPGA_CLK   ; 3.427  ; 3.804  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; FPGA_CLK   ; 3.427  ; 3.804  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; FPGA_CLK   ; 1.213  ; 1.187  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N   ; FPGA_CLK   ; 1.214  ; 1.188  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N    ; FPGA_CLK   ; 1.651  ; 1.556  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; FPGA_CLK   ; 3.072  ; 3.547  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.896  ; 1.854  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.896  ; 1.854  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.896  ; 1.854  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.072  ; 3.547  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 3.057  ; 3.532  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 1.295  ; 1.356  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 1.748  ; 1.744  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 1.651  ; 1.556  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 1.888  ; 1.846  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.054  ; 3.529  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.886  ; 1.844  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.886  ; 1.844  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.886  ; 1.844  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 3.060  ; 3.535  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.887  ; 1.845  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.887  ; 1.845  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH_n  ; FPGA_CLK   ; 1.645  ; 1.550  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML_n  ; FPGA_CLK   ; 1.651  ; 1.556  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N   ; FPGA_CLK   ; 1.651  ; 1.556  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N    ; FPGA_CLK   ; 3.428  ; 3.805  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L       ; FPGA_CLK   ; 4.298  ; 4.902  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R       ; FPGA_CLK   ; 2.176  ; 2.300  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK        ; FPGA_CLK   ; 2.089  ; 2.195  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD        ; FPGA_CLK   ; 1.963  ; 2.058  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3       ; FPGA_CLK   ; 2.637  ; 2.488  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]      ; FPGA_CLK   ; 4.850  ; 5.366  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; FPGA_CLK   ; 3.048  ; 3.105  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; FPGA_CLK   ; 4.850  ; 5.366  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; FPGA_CLK   ; 3.276  ; 3.341  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; FPGA_CLK   ; 2.945  ; 2.983  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; FPGA_CLK   ; 4.958  ; 5.498  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; FPGA_CLK   ; 3.284  ; 3.373  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; FPGA_CLK   ; 3.364  ; 3.456  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; FPGA_CLK   ; 3.264  ; 3.345  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; FPGA_CLK   ; 4.958  ; 5.498  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; FPGA_CLK   ; 10.144 ;        ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; FPGA_CLK   ;        ; 10.618 ; Fall       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]      ; FPGA_CLK   ; 3.990  ; 4.572  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]     ; FPGA_CLK   ; 2.005  ; 2.079  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]     ; FPGA_CLK   ; 3.990  ; 4.572  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]     ; FPGA_CLK   ; 2.203  ; 2.311  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]     ; FPGA_CLK   ; 2.083  ; 2.159  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]      ; FPGA_CLK   ; 4.111  ; 4.701  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]     ; FPGA_CLK   ; 2.420  ; 2.551  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]     ; FPGA_CLK   ; 2.498  ; 2.634  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]     ; FPGA_CLK   ; 2.419  ; 2.550  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]     ; FPGA_CLK   ; 4.111  ; 4.701  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; dminus1       ; FPGA_CLK   ; 2.323  ; 2.346  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 2.171  ; 2.232  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 3.945  ; 4.420  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 2.174  ; 2.235  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                                  ;
+---------------+------------+-------+--------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall   ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-------+--------+------------+-------------------------------------------------------------------------------------+
; SDRAM_A[*]    ; FPGA_CLK   ; 0.822 ; 0.796  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; FPGA_CLK   ; 1.247 ; 1.155  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; FPGA_CLK   ; 1.247 ; 1.155  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; FPGA_CLK   ; 1.250 ; 1.158  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; FPGA_CLK   ; 1.250 ; 1.158  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; FPGA_CLK   ; 1.243 ; 1.151  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; FPGA_CLK   ; 1.243 ; 1.151  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; FPGA_CLK   ; 1.241 ; 1.149  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; FPGA_CLK   ; 0.822 ; 0.796  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; FPGA_CLK   ; 3.018 ; 3.398  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; FPGA_CLK   ; 1.242 ; 1.150  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; FPGA_CLK   ; 1.247 ; 1.155  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; FPGA_CLK   ; 1.242 ; 1.150  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; FPGA_CLK   ; 0.828 ; 0.802  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; FPGA_CLK   ; 3.024 ; 3.404  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; FPGA_CLK   ; 0.828 ; 0.802  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N   ; FPGA_CLK   ; 0.830 ; 0.804  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N    ; FPGA_CLK   ; 1.249 ; 1.157  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; FPGA_CLK   ; 0.911 ; 0.973  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.493 ; 1.455  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.493 ; 1.455  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.493 ; 1.455  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.688 ; 3.164  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.673 ; 3.149  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 0.911 ; 0.973  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 1.346 ; 1.346  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 1.249 ; 1.157  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 1.486 ; 1.448  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.671 ; 3.147  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.484 ; 1.446  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.484 ; 1.446  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.484 ; 1.446  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.676 ; 3.152  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.485 ; 1.447  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.485 ; 1.447  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH_n  ; FPGA_CLK   ; 1.243 ; 1.151  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML_n  ; FPGA_CLK   ; 1.249 ; 1.157  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N   ; FPGA_CLK   ; 1.249 ; 1.157  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N    ; FPGA_CLK   ; 3.026 ; 3.406  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L       ; FPGA_CLK   ; 3.817 ; 4.415  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R       ; FPGA_CLK   ; 1.708 ; 1.827  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK        ; FPGA_CLK   ; 1.625 ; 1.726  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD        ; FPGA_CLK   ; 1.505 ; 1.594  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3       ; FPGA_CLK   ; 2.150 ; 2.008  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]      ; FPGA_CLK   ; 2.259 ; 2.287  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; FPGA_CLK   ; 2.358 ; 2.405  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; FPGA_CLK   ; 4.168 ; 4.700  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; FPGA_CLK   ; 2.491 ; 2.558  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; FPGA_CLK   ; 2.259 ; 2.287  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; FPGA_CLK   ; 2.565 ; 2.634  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; FPGA_CLK   ; 2.585 ; 2.662  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; FPGA_CLK   ; 2.662 ; 2.741  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; FPGA_CLK   ; 2.565 ; 2.634  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; FPGA_CLK   ; 4.262 ; 4.791  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; FPGA_CLK   ; 9.729 ;        ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; FPGA_CLK   ;       ; 10.201 ; Fall       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]      ; FPGA_CLK   ; 1.543 ; 1.615  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]     ; FPGA_CLK   ; 1.543 ; 1.615  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]     ; FPGA_CLK   ; 3.521 ; 4.098  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]     ; FPGA_CLK   ; 1.735 ; 1.838  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]     ; FPGA_CLK   ; 1.619 ; 1.692  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]      ; FPGA_CLK   ; 1.941 ; 2.067  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]     ; FPGA_CLK   ; 1.942 ; 2.068  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]     ; FPGA_CLK   ; 2.017 ; 2.147  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]     ; FPGA_CLK   ; 1.941 ; 2.067  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]     ; FPGA_CLK   ; 3.637 ; 4.222  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; dminus1       ; FPGA_CLK   ; 2.076 ; 2.100  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 1.925 ; 1.987  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 3.698 ; 4.174  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 1.927 ; 1.989  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-------+--------+------------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                                           ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.687 ; 1.686 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.687 ; 1.686 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.687 ; 1.686 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.687 ; 1.686 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.485 ; 3.932 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 3.998 ; 4.445 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.076 ; 2.109 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.224 ; 2.257 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 1.924 ; 1.869 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.346 ; 2.345 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.814 ; 4.261 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.019 ; 2.018 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.019 ; 2.018 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.019 ; 2.018 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 3.644 ; 4.091 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.013 ; 2.012 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.013 ; 2.012 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.361 ; 2.306 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 3.255 ; 3.254 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 3.794 ; 3.827 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 5.066 ; 5.513 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 3.645 ; 3.678 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                                   ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.256 ; 1.255 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.256 ; 1.255 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.256 ; 1.255 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.256 ; 1.255 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.046 ; 3.493 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 3.539 ; 3.986 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 1.623 ; 1.656 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 1.765 ; 1.798 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 1.466 ; 1.411 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 1.888 ; 1.887 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.362 ; 3.809 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.574 ; 1.573 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.574 ; 1.573 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.574 ; 1.573 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 3.200 ; 3.647 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.569 ; 1.568 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.569 ; 1.568 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 1.886 ; 1.831 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 2.933 ; 2.932 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 3.444 ; 3.477 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 4.737 ; 5.184 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 3.302 ; 3.335 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                                  ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.729     ; 1.730     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.729     ; 1.730     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.729     ; 1.730     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.729     ; 1.730     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.998     ; 3.551     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 4.576     ; 4.129     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.219     ; 2.186     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.384     ; 2.351     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 1.972     ; 2.027     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.469     ; 2.470     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 4.369     ; 3.922     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.106     ; 2.107     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.106     ; 2.107     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.106     ; 2.107     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 4.170     ; 3.723     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.091     ; 2.092     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.091     ; 2.092     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.472     ; 2.527     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 3.378     ; 3.379     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 4.070     ; 4.037     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 5.659     ; 5.212     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 3.901     ; 3.868     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                                          ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.296     ; 1.297     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.296     ; 1.297     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.296     ; 1.297     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.296     ; 1.297     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.557     ; 3.110     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 4.112     ; 3.665     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 1.762     ; 1.729     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 1.920     ; 1.887     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 1.510     ; 1.565     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.006     ; 2.007     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.913     ; 3.466     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.658     ; 1.659     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.658     ; 1.659     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.658     ; 1.659     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 3.722     ; 3.275     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.643     ; 1.644     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.643     ; 1.644     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 1.990     ; 2.045     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 3.051     ; 3.052     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 3.711     ; 3.678     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 5.324     ; 4.877     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 3.548     ; 3.515     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+


---------------------------------------------
; Fast 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary                                                                                                                   ;
+--------------------------------------------------------------------------------------+----------+----------+----------+---------+---------------------+
; Clock                                                                                ; Setup    ; Hold     ; Recovery ; Removal ; Minimum Pulse Width ;
+--------------------------------------------------------------------------------------+----------+----------+----------+---------+---------------------+
; Worst-case Slack                                                                     ; -3.665   ; -1.833   ; -2.348   ; -0.387  ; 5.595               ;
;  FPGA_CLK                                                                            ; 0.011    ; -0.735   ; -0.304   ; -0.387  ; 89.338              ;
;  \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.949    ; 0.186    ; 7.659    ; 1.236   ; 5.595               ;
;  \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; -3.665   ; 0.134    ; 7.512    ; 0.851   ; 17.258              ;
;  \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -1.765   ; 11.482   ; N/A      ; N/A     ; 5.720               ;
;  \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 2.079    ; 0.187    ; 12.988   ; 1.756   ; 8.533               ;
;  \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; N/A      ; N/A      ; N/A      ; N/A     ; 17.589              ;
;  usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; -0.278   ; -1.833   ; -2.348   ; 0.100   ; 9.376               ;
; Design-wide TNS                                                                      ; -288.713 ; -131.32  ; -28.724  ; -9.978  ; 0.0                 ;
;  FPGA_CLK                                                                            ; 0.000    ; -0.735   ; -7.751   ; -9.978  ; 0.000               ;
;  \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000    ; 0.000    ; 0.000    ; 0.000   ; 0.000               ;
;  \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; -275.360 ; 0.000    ; 0.000    ; 0.000   ; 0.000               ;
;  \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -1.765   ; 0.000    ; N/A      ; N/A     ; 0.000               ;
;  \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000    ; 0.000    ; 0.000    ; 0.000   ; 0.000               ;
;  \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; N/A      ; N/A      ; N/A      ; N/A     ; 0.000               ;
;  usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; -11.678  ; -130.585 ; -21.132  ; 0.000   ; 0.000               ;
+--------------------------------------------------------------------------------------+----------+----------+----------+---------+---------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                                   ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.771 ; 2.950 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.753 ; 2.932 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.753 ; 2.932 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.753 ; 2.932 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.745 ; 2.924 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.764 ; 2.943 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.746 ; 2.925 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.756 ; 2.935 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.704 ; 2.882 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.764 ; 2.943 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.771 ; 2.950 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.767 ; 2.946 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.767 ; 2.946 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.767 ; 2.946 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.765 ; 2.944 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.765 ; 2.944 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.765 ; 2.944 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_DAT0       ; FPGA_CLK   ; 3.641 ; 3.845 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 0.790 ; 0.969 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 0.796 ; 0.975 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 0.799 ; 0.978 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 0.793 ; 0.972 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                      ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; -0.960 ; -1.509 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; -0.978 ; -1.529 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; -0.978 ; -1.529 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; -0.978 ; -1.529 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; -0.975 ; -1.526 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; -0.990 ; -1.541 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; -0.976 ; -1.527 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; -0.981 ; -1.532 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; -0.960 ; -1.509 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; -0.986 ; -1.537 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; -0.993 ; -1.544 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; -0.988 ; -1.539 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; -0.988 ; -1.539 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; -0.988 ; -1.539 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; -0.987 ; -1.538 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; -0.987 ; -1.538 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; -0.987 ; -1.538 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_DAT0       ; FPGA_CLK   ; -1.440 ; -1.927 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; -0.093 ; -0.303 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; -0.100 ; -0.309 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; -0.102 ; -0.312 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; -0.097 ; -0.307 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                           ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; SDRAM_A[*]    ; FPGA_CLK   ; 5.639  ; 5.886  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; FPGA_CLK   ; 3.034  ; 2.821  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; FPGA_CLK   ; 3.034  ; 2.821  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; FPGA_CLK   ; 3.037  ; 2.824  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; FPGA_CLK   ; 3.037  ; 2.824  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; FPGA_CLK   ; 3.025  ; 2.812  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; FPGA_CLK   ; 3.025  ; 2.812  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; FPGA_CLK   ; 3.023  ; 2.810  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; FPGA_CLK   ; 2.202  ; 2.128  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; FPGA_CLK   ; 5.639  ; 5.886  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; FPGA_CLK   ; 3.024  ; 2.811  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; FPGA_CLK   ; 3.034  ; 2.821  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; FPGA_CLK   ; 3.024  ; 2.811  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; FPGA_CLK   ; 5.651  ; 5.898  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; FPGA_CLK   ; 5.651  ; 5.898  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; FPGA_CLK   ; 2.214  ; 2.140  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N   ; FPGA_CLK   ; 2.216  ; 2.142  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N    ; FPGA_CLK   ; 3.036  ; 2.823  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; FPGA_CLK   ; 4.986  ; 5.410  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.406  ; 3.261  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.406  ; 3.261  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.406  ; 3.261  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 4.986  ; 5.410  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 4.966  ; 5.390  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.372  ; 2.351  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.223  ; 3.069  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.036  ; 2.823  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.394  ; 3.249  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 4.959  ; 5.383  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.392  ; 3.247  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.392  ; 3.247  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.392  ; 3.247  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 4.965  ; 5.389  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 3.393  ; 3.248  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 3.393  ; 3.248  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH_n  ; FPGA_CLK   ; 3.025  ; 2.812  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML_n  ; FPGA_CLK   ; 3.036  ; 2.823  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N   ; FPGA_CLK   ; 3.036  ; 2.823  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N    ; FPGA_CLK   ; 5.653  ; 5.900  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L       ; FPGA_CLK   ; 7.539  ; 7.874  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R       ; FPGA_CLK   ; 4.250  ; 4.188  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK        ; FPGA_CLK   ; 4.033  ; 4.003  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD        ; FPGA_CLK   ; 3.775  ; 3.752  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3       ; FPGA_CLK   ; 4.784  ; 4.870  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]      ; FPGA_CLK   ; 8.440  ; 8.771  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; FPGA_CLK   ; 5.757  ; 5.651  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; FPGA_CLK   ; 8.440  ; 8.771  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; FPGA_CLK   ; 6.106  ; 6.015  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; FPGA_CLK   ; 5.534  ; 5.389  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; FPGA_CLK   ; 8.646  ; 8.951  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; FPGA_CLK   ; 6.240  ; 6.108  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; FPGA_CLK   ; 6.396  ; 6.231  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; FPGA_CLK   ; 6.164  ; 6.021  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; FPGA_CLK   ; 8.646  ; 8.951  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; FPGA_CLK   ; 11.844 ;        ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; FPGA_CLK   ;        ; 12.193 ; Fall       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]      ; FPGA_CLK   ; 7.007  ; 7.392  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]     ; FPGA_CLK   ; 3.962  ; 3.906  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]     ; FPGA_CLK   ; 7.007  ; 7.392  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]     ; FPGA_CLK   ; 4.303  ; 4.277  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]     ; FPGA_CLK   ; 4.129  ; 4.015  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]      ; FPGA_CLK   ; 7.286  ; 7.629  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]     ; FPGA_CLK   ; 4.823  ; 4.736  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]     ; FPGA_CLK   ; 4.988  ; 4.868  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]     ; FPGA_CLK   ; 4.818  ; 4.717  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]     ; FPGA_CLK   ; 7.286  ; 7.629  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; dminus1       ; FPGA_CLK   ; 4.249  ; 4.237  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 4.063  ; 4.042  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 6.673  ; 7.097  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 4.066  ; 4.045  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                                  ;
+---------------+------------+-------+--------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall   ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-------+--------+------------+-------------------------------------------------------------------------------------+
; SDRAM_A[*]    ; FPGA_CLK   ; 0.822 ; 0.796  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; FPGA_CLK   ; 1.247 ; 1.155  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; FPGA_CLK   ; 1.247 ; 1.155  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; FPGA_CLK   ; 1.250 ; 1.158  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; FPGA_CLK   ; 1.250 ; 1.158  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; FPGA_CLK   ; 1.243 ; 1.151  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; FPGA_CLK   ; 1.243 ; 1.151  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; FPGA_CLK   ; 1.241 ; 1.149  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; FPGA_CLK   ; 0.822 ; 0.796  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; FPGA_CLK   ; 3.018 ; 3.398  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; FPGA_CLK   ; 1.242 ; 1.150  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; FPGA_CLK   ; 1.247 ; 1.155  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; FPGA_CLK   ; 1.242 ; 1.150  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; FPGA_CLK   ; 0.828 ; 0.802  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; FPGA_CLK   ; 3.024 ; 3.404  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; FPGA_CLK   ; 0.828 ; 0.802  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N   ; FPGA_CLK   ; 0.830 ; 0.804  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N    ; FPGA_CLK   ; 1.249 ; 1.157  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; FPGA_CLK   ; 0.911 ; 0.973  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.493 ; 1.455  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.493 ; 1.455  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.493 ; 1.455  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.688 ; 3.164  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.673 ; 3.149  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 0.911 ; 0.973  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 1.346 ; 1.346  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 1.249 ; 1.157  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 1.486 ; 1.448  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.671 ; 3.147  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.484 ; 1.446  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.484 ; 1.446  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.484 ; 1.446  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.676 ; 3.152  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.485 ; 1.447  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.485 ; 1.447  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH_n  ; FPGA_CLK   ; 1.243 ; 1.151  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML_n  ; FPGA_CLK   ; 1.249 ; 1.157  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N   ; FPGA_CLK   ; 1.249 ; 1.157  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N    ; FPGA_CLK   ; 3.026 ; 3.406  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L       ; FPGA_CLK   ; 3.817 ; 4.415  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R       ; FPGA_CLK   ; 1.708 ; 1.827  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK        ; FPGA_CLK   ; 1.625 ; 1.726  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD        ; FPGA_CLK   ; 1.505 ; 1.594  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3       ; FPGA_CLK   ; 2.150 ; 2.008  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]      ; FPGA_CLK   ; 2.259 ; 2.287  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; FPGA_CLK   ; 2.358 ; 2.405  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; FPGA_CLK   ; 4.168 ; 4.700  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; FPGA_CLK   ; 2.491 ; 2.558  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; FPGA_CLK   ; 2.259 ; 2.287  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; FPGA_CLK   ; 2.565 ; 2.634  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; FPGA_CLK   ; 2.585 ; 2.662  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; FPGA_CLK   ; 2.662 ; 2.741  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; FPGA_CLK   ; 2.565 ; 2.634  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; FPGA_CLK   ; 4.262 ; 4.791  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; FPGA_CLK   ; 9.729 ;        ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; FPGA_CLK   ;       ; 10.201 ; Fall       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]      ; FPGA_CLK   ; 1.543 ; 1.615  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]     ; FPGA_CLK   ; 1.543 ; 1.615  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]     ; FPGA_CLK   ; 3.521 ; 4.098  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]     ; FPGA_CLK   ; 1.735 ; 1.838  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]     ; FPGA_CLK   ; 1.619 ; 1.692  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]      ; FPGA_CLK   ; 1.941 ; 2.067  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]     ; FPGA_CLK   ; 1.942 ; 2.068  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]     ; FPGA_CLK   ; 2.017 ; 2.147  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]     ; FPGA_CLK   ; 1.941 ; 2.067  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]     ; FPGA_CLK   ; 3.637 ; 4.222  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; dminus1       ; FPGA_CLK   ; 2.076 ; 2.100  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 1.925 ; 1.987  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 3.698 ; 4.174  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 1.927 ; 1.989  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-------+--------+------------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                   ;
+--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; Pin          ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
+--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; VGA_B[0]     ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[1]     ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[2]     ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[3]     ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[0]     ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[1]     ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[2]     ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[3]     ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; AUDIO_L      ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; AUDIO_R      ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_BA[0]  ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_BA[1]  ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_CS_N   ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_RAS_N  ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_CAS_N  ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_WE_N   ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQMH_n ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQML_n ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_CLK    ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_CKE    ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[0]   ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[1]   ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[2]   ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[3]   ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[4]   ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[5]   ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[6]   ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[7]   ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[8]   ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[9]   ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[10]  ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[11]  ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[12]  ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SD_CLK       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SD_CMD       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SD_DAT3      ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; CFG_CLK      ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; CFG_CS_n     ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; CFG_DOUT     ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; dplus1       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; dminus1      ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; dplus2       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; dminus2      ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[0]  ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[1]  ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[2]  ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[3]  ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[4]  ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[5]  ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[6]  ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[7]  ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[8]  ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[9]  ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[10] ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[11] ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[12] ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[13] ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[14] ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[15] ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+


+-----------------------------------------------------------------+
; Input Transition Times                                          ;
+--------------+--------------+-----------------+-----------------+
; Pin          ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+--------------+--------------+-----------------+-----------------+
; CFG_DIN      ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; dplus1       ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; dminus1      ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; dplus2       ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; dminus2      ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[0]  ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[1]  ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[2]  ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[3]  ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[4]  ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[5]  ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[6]  ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[7]  ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[8]  ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[9]  ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[10] ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[11] ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[12] ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[13] ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[14] ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[15] ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; FPGA_CLK     ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SD_DAT0      ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
+--------------+--------------+-----------------+-----------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1200mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                           ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin          ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; VGA_B[0]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; VGA_B[1]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.09 V              ; -0.00419 V          ; 0.108 V                              ; 0.251 V                              ; 5.73e-09 s                  ; 5.85e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.69e-08 V                  ; 3.09 V             ; -0.00419 V         ; 0.108 V                             ; 0.251 V                             ; 5.73e-09 s                 ; 5.85e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[2]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; VGA_B[3]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; VGA_G[0]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; VGA_G[1]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; VGA_G[2]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; VGA_G[3]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.09 V              ; -0.00419 V          ; 0.108 V                              ; 0.251 V                              ; 5.73e-09 s                  ; 5.85e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.69e-08 V                  ; 3.09 V             ; -0.00419 V         ; 0.108 V                             ; 0.251 V                             ; 5.73e-09 s                 ; 5.85e-09 s                 ; Yes                       ; Yes                       ;
; AUDIO_L      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.09 V              ; -0.00419 V          ; 0.108 V                              ; 0.251 V                              ; 5.73e-09 s                  ; 5.85e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.69e-08 V                  ; 3.09 V             ; -0.00419 V         ; 0.108 V                             ; 0.251 V                             ; 5.73e-09 s                 ; 5.85e-09 s                 ; Yes                       ; Yes                       ;
; AUDIO_R      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_BA[0]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.09 V              ; -0.00419 V          ; 0.108 V                              ; 0.251 V                              ; 5.73e-09 s                  ; 5.85e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.69e-08 V                  ; 3.09 V             ; -0.00419 V         ; 0.108 V                             ; 0.251 V                             ; 5.73e-09 s                 ; 5.85e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_BA[1]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_CS_N   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_RAS_N  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_CAS_N  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_WE_N   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.09 V              ; -0.00419 V          ; 0.108 V                              ; 0.251 V                              ; 5.73e-09 s                  ; 5.85e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.69e-08 V                  ; 3.09 V             ; -0.00419 V         ; 0.108 V                             ; 0.251 V                             ; 5.73e-09 s                 ; 5.85e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQMH_n ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_DQML_n ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_CLK    ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.09 V              ; -0.00419 V          ; 0.108 V                              ; 0.251 V                              ; 5.73e-09 s                  ; 5.85e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.69e-08 V                  ; 3.09 V             ; -0.00419 V         ; 0.108 V                             ; 0.251 V                             ; 5.73e-09 s                 ; 5.85e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_CKE    ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[0]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[1]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[2]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[3]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[4]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[5]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[6]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[7]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[8]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.09 V              ; -0.00419 V          ; 0.108 V                              ; 0.251 V                              ; 5.73e-09 s                  ; 5.85e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.69e-08 V                  ; 3.09 V             ; -0.00419 V         ; 0.108 V                             ; 0.251 V                             ; 5.73e-09 s                 ; 5.85e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[9]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[10]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[11]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[12]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SD_CLK       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SD_CMD       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SD_DAT3      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; CFG_CLK      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.15e-09 V                   ; 3.18 V              ; -0.0303 V           ; 0.317 V                              ; 0.07 V                               ; 3.25e-10 s                  ; 3.88e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 6.15e-09 V                  ; 3.18 V             ; -0.0303 V          ; 0.317 V                             ; 0.07 V                              ; 3.25e-10 s                 ; 3.88e-10 s                 ; No                        ; Yes                       ;
; CFG_CS_n     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.76e-08 V                   ; 3.09 V              ; -0.0166 V           ; 0.084 V                              ; 0.289 V                              ; 2.05e-09 s                  ; 1.96e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.76e-08 V                  ; 3.09 V             ; -0.0166 V          ; 0.084 V                             ; 0.289 V                             ; 2.05e-09 s                 ; 1.96e-09 s                 ; Yes                       ; Yes                       ;
; CFG_DOUT     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.76e-08 V                   ; 3.09 V              ; -0.0166 V           ; 0.084 V                              ; 0.289 V                              ; 2.05e-09 s                  ; 1.96e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.76e-08 V                  ; 3.09 V             ; -0.0166 V          ; 0.084 V                             ; 0.289 V                             ; 2.05e-09 s                 ; 1.96e-09 s                 ; Yes                       ; Yes                       ;
; dplus1       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.09 V              ; -0.00398 V          ; 0.168 V                              ; 0.263 V                              ; 6.02e-09 s                  ; 6.14e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.09 V             ; -0.00398 V         ; 0.168 V                             ; 0.263 V                             ; 6.02e-09 s                 ; 6.14e-09 s                 ; Yes                       ; Yes                       ;
; dminus1      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0249 V           ; 0.153 V                              ; 0.299 V                              ; 1.37e-09 s                  ; 1.36e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0249 V          ; 0.153 V                             ; 0.299 V                             ; 1.37e-09 s                 ; 1.36e-09 s                 ; Yes                       ; Yes                       ;
; dplus2       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0307 V           ; 0.185 V                              ; 0.216 V                              ; 1.07e-09 s                  ; 1.08e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0307 V          ; 0.185 V                             ; 0.216 V                             ; 1.07e-09 s                 ; 1.08e-09 s                 ; Yes                       ; Yes                       ;
; dminus2      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0307 V           ; 0.185 V                              ; 0.216 V                              ; 1.07e-09 s                  ; 1.08e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0307 V          ; 0.185 V                             ; 0.216 V                             ; 1.07e-09 s                 ; 1.08e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[0]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0249 V           ; 0.153 V                              ; 0.299 V                              ; 1.37e-09 s                  ; 1.36e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0249 V          ; 0.153 V                             ; 0.299 V                             ; 1.37e-09 s                 ; 1.36e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[1]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0249 V           ; 0.153 V                              ; 0.299 V                              ; 1.37e-09 s                  ; 1.36e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0249 V          ; 0.153 V                             ; 0.299 V                             ; 1.37e-09 s                 ; 1.36e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[2]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0249 V           ; 0.153 V                              ; 0.299 V                              ; 1.37e-09 s                  ; 1.36e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0249 V          ; 0.153 V                             ; 0.299 V                             ; 1.37e-09 s                 ; 1.36e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[3]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.09 V              ; -0.00398 V          ; 0.168 V                              ; 0.263 V                              ; 6.02e-09 s                  ; 6.14e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.09 V             ; -0.00398 V         ; 0.168 V                             ; 0.263 V                             ; 6.02e-09 s                 ; 6.14e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[4]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.09 V              ; -0.00398 V          ; 0.168 V                              ; 0.263 V                              ; 6.02e-09 s                  ; 6.14e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.09 V             ; -0.00398 V         ; 0.168 V                             ; 0.263 V                             ; 6.02e-09 s                 ; 6.14e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[5]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0307 V           ; 0.185 V                              ; 0.216 V                              ; 1.07e-09 s                  ; 1.08e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0307 V          ; 0.185 V                             ; 0.216 V                             ; 1.07e-09 s                 ; 1.08e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[6]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0307 V           ; 0.185 V                              ; 0.216 V                              ; 1.07e-09 s                  ; 1.08e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0307 V          ; 0.185 V                             ; 0.216 V                             ; 1.07e-09 s                 ; 1.08e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[7]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_DQ[8]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0249 V           ; 0.153 V                              ; 0.299 V                              ; 1.37e-09 s                  ; 1.36e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0249 V          ; 0.153 V                             ; 0.299 V                             ; 1.37e-09 s                 ; 1.36e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[9]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.09 V              ; -0.00398 V          ; 0.168 V                              ; 0.263 V                              ; 6.02e-09 s                  ; 6.14e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.09 V             ; -0.00398 V         ; 0.168 V                             ; 0.263 V                             ; 6.02e-09 s                 ; 6.14e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[10] ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0249 V           ; 0.153 V                              ; 0.299 V                              ; 1.37e-09 s                  ; 1.36e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0249 V          ; 0.153 V                             ; 0.299 V                             ; 1.37e-09 s                 ; 1.36e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[11] ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0249 V           ; 0.153 V                              ; 0.299 V                              ; 1.37e-09 s                  ; 1.36e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0249 V          ; 0.153 V                             ; 0.299 V                             ; 1.37e-09 s                 ; 1.36e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[12] ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0249 V           ; 0.153 V                              ; 0.299 V                              ; 1.37e-09 s                  ; 1.36e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0249 V          ; 0.153 V                             ; 0.299 V                             ; 1.37e-09 s                 ; 1.36e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[13] ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.09 V              ; -0.00398 V          ; 0.168 V                              ; 0.263 V                              ; 6.02e-09 s                  ; 6.14e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.09 V             ; -0.00398 V         ; 0.168 V                             ; 0.263 V                             ; 6.02e-09 s                 ; 6.14e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[14] ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0249 V           ; 0.153 V                              ; 0.299 V                              ; 1.37e-09 s                  ; 1.36e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0249 V          ; 0.153 V                             ; 0.299 V                             ; 1.37e-09 s                 ; 1.36e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[15] ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0249 V           ; 0.153 V                              ; 0.299 V                              ; 1.37e-09 s                  ; 1.36e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0249 V          ; 0.153 V                             ; 0.299 V                             ; 1.37e-09 s                 ; 1.36e-09 s                 ; Yes                       ; Yes                       ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1200mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                          ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin          ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; VGA_B[0]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; VGA_B[1]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.00169 V          ; 0.058 V                              ; 0.159 V                              ; 6.95e-09 s                  ; 7.33e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.00169 V         ; 0.058 V                             ; 0.159 V                             ; 6.95e-09 s                 ; 7.33e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[2]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; VGA_B[3]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; VGA_G[0]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; VGA_G[1]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; VGA_G[2]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; VGA_G[3]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.00169 V          ; 0.058 V                              ; 0.159 V                              ; 6.95e-09 s                  ; 7.33e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.00169 V         ; 0.058 V                             ; 0.159 V                             ; 6.95e-09 s                 ; 7.33e-09 s                 ; Yes                       ; Yes                       ;
; AUDIO_L      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.00169 V          ; 0.058 V                              ; 0.159 V                              ; 6.95e-09 s                  ; 7.33e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.00169 V         ; 0.058 V                             ; 0.159 V                             ; 6.95e-09 s                 ; 7.33e-09 s                 ; Yes                       ; Yes                       ;
; AUDIO_R      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_BA[0]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.00169 V          ; 0.058 V                              ; 0.159 V                              ; 6.95e-09 s                  ; 7.33e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.00169 V         ; 0.058 V                             ; 0.159 V                             ; 6.95e-09 s                 ; 7.33e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_BA[1]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_CS_N   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_RAS_N  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_CAS_N  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_WE_N   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.00169 V          ; 0.058 V                              ; 0.159 V                              ; 6.95e-09 s                  ; 7.33e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.00169 V         ; 0.058 V                             ; 0.159 V                             ; 6.95e-09 s                 ; 7.33e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQMH_n ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQML_n ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_CLK    ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.00169 V          ; 0.058 V                              ; 0.159 V                              ; 6.95e-09 s                  ; 7.33e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.00169 V         ; 0.058 V                             ; 0.159 V                             ; 6.95e-09 s                 ; 7.33e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_CKE    ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[0]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[1]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[2]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[3]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[4]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[5]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[6]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[7]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[8]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.00169 V          ; 0.058 V                              ; 0.159 V                              ; 6.95e-09 s                  ; 7.33e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.00169 V         ; 0.058 V                             ; 0.159 V                             ; 6.95e-09 s                 ; 7.33e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[9]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[10]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[11]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[12]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SD_CLK       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SD_CMD       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SD_DAT3      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; CFG_CLK      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.52e-07 V                   ; 3.14 V              ; -0.0428 V           ; 0.161 V                              ; 0.071 V                              ; 4.71e-10 s                  ; 4.5e-10 s                   ; Yes                        ; Yes                        ; 3.08 V                      ; 6.52e-07 V                  ; 3.14 V             ; -0.0428 V          ; 0.161 V                             ; 0.071 V                             ; 4.71e-10 s                 ; 4.5e-10 s                  ; Yes                       ; Yes                       ;
; CFG_CS_n     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.13e-06 V                   ; 3.08 V              ; -0.00721 V          ; 0.043 V                              ; 0.226 V                              ; 2.47e-09 s                  ; 2.5e-09 s                   ; Yes                        ; Yes                        ; 3.08 V                      ; 3.13e-06 V                  ; 3.08 V             ; -0.00721 V         ; 0.043 V                             ; 0.226 V                             ; 2.47e-09 s                 ; 2.5e-09 s                  ; Yes                       ; Yes                       ;
; CFG_DOUT     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.13e-06 V                   ; 3.08 V              ; -0.00721 V          ; 0.043 V                              ; 0.226 V                              ; 2.47e-09 s                  ; 2.5e-09 s                   ; Yes                        ; Yes                        ; 3.08 V                      ; 3.13e-06 V                  ; 3.08 V             ; -0.00721 V         ; 0.043 V                             ; 0.226 V                             ; 2.47e-09 s                 ; 2.5e-09 s                  ; Yes                       ; Yes                       ;
; dplus1       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.00144 V          ; 0.08 V                               ; 0.174 V                              ; 7.33e-09 s                  ; 7.73e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.00144 V         ; 0.08 V                              ; 0.174 V                             ; 7.33e-09 s                 ; 7.73e-09 s                 ; Yes                       ; Yes                       ;
; dminus1      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.012 V            ; 0.078 V                              ; 0.167 V                              ; 1.65e-09 s                  ; 1.74e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.012 V           ; 0.078 V                             ; 0.167 V                             ; 1.65e-09 s                 ; 1.74e-09 s                 ; Yes                       ; Yes                       ;
; dplus2       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.0139 V           ; 0.07 V                               ; 0.155 V                              ; 1.28e-09 s                  ; 1.32e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.0139 V          ; 0.07 V                              ; 0.155 V                             ; 1.28e-09 s                 ; 1.32e-09 s                 ; Yes                       ; Yes                       ;
; dminus2      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.0139 V           ; 0.07 V                               ; 0.155 V                              ; 1.28e-09 s                  ; 1.32e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.0139 V          ; 0.07 V                              ; 0.155 V                             ; 1.28e-09 s                 ; 1.32e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[0]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.012 V            ; 0.078 V                              ; 0.167 V                              ; 1.65e-09 s                  ; 1.74e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.012 V           ; 0.078 V                             ; 0.167 V                             ; 1.65e-09 s                 ; 1.74e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[1]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.012 V            ; 0.078 V                              ; 0.167 V                              ; 1.65e-09 s                  ; 1.74e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.012 V           ; 0.078 V                             ; 0.167 V                             ; 1.65e-09 s                 ; 1.74e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[2]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.012 V            ; 0.078 V                              ; 0.167 V                              ; 1.65e-09 s                  ; 1.74e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.012 V           ; 0.078 V                             ; 0.167 V                             ; 1.65e-09 s                 ; 1.74e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[3]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.00144 V          ; 0.08 V                               ; 0.174 V                              ; 7.33e-09 s                  ; 7.73e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.00144 V         ; 0.08 V                              ; 0.174 V                             ; 7.33e-09 s                 ; 7.73e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[4]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.00144 V          ; 0.08 V                               ; 0.174 V                              ; 7.33e-09 s                  ; 7.73e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.00144 V         ; 0.08 V                              ; 0.174 V                             ; 7.33e-09 s                 ; 7.73e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[5]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.0139 V           ; 0.07 V                               ; 0.155 V                              ; 1.28e-09 s                  ; 1.32e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.0139 V          ; 0.07 V                              ; 0.155 V                             ; 1.28e-09 s                 ; 1.32e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[6]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.0139 V           ; 0.07 V                               ; 0.155 V                              ; 1.28e-09 s                  ; 1.32e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.0139 V          ; 0.07 V                              ; 0.155 V                             ; 1.28e-09 s                 ; 1.32e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[7]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[8]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.012 V            ; 0.078 V                              ; 0.167 V                              ; 1.65e-09 s                  ; 1.74e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.012 V           ; 0.078 V                             ; 0.167 V                             ; 1.65e-09 s                 ; 1.74e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[9]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.00144 V          ; 0.08 V                               ; 0.174 V                              ; 7.33e-09 s                  ; 7.73e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.00144 V         ; 0.08 V                              ; 0.174 V                             ; 7.33e-09 s                 ; 7.73e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[10] ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.012 V            ; 0.078 V                              ; 0.167 V                              ; 1.65e-09 s                  ; 1.74e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.012 V           ; 0.078 V                             ; 0.167 V                             ; 1.65e-09 s                 ; 1.74e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[11] ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.012 V            ; 0.078 V                              ; 0.167 V                              ; 1.65e-09 s                  ; 1.74e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.012 V           ; 0.078 V                             ; 0.167 V                             ; 1.65e-09 s                 ; 1.74e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[12] ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.012 V            ; 0.078 V                              ; 0.167 V                              ; 1.65e-09 s                  ; 1.74e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.012 V           ; 0.078 V                             ; 0.167 V                             ; 1.65e-09 s                 ; 1.74e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[13] ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.00144 V          ; 0.08 V                               ; 0.174 V                              ; 7.33e-09 s                  ; 7.73e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.00144 V         ; 0.08 V                              ; 0.174 V                             ; 7.33e-09 s                 ; 7.73e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[14] ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.012 V            ; 0.078 V                              ; 0.167 V                              ; 1.65e-09 s                  ; 1.74e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.012 V           ; 0.078 V                             ; 0.167 V                             ; 1.65e-09 s                 ; 1.74e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[15] ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.012 V            ; 0.078 V                              ; 0.167 V                              ; 1.65e-09 s                  ; 1.74e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.012 V           ; 0.078 V                             ; 0.167 V                             ; 1.65e-09 s                 ; 1.74e-09 s                 ; Yes                       ; Yes                       ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Fast 1200mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                           ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin          ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; VGA_B[0]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_B[1]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.47 V              ; -0.00753 V          ; 0.323 V                              ; 0.336 V                              ; 4.77e-09 s                  ; 5.18e-09 s                  ; Yes                        ; No                         ; 3.46 V                      ; 3.12e-07 V                  ; 3.47 V             ; -0.00753 V         ; 0.323 V                             ; 0.336 V                             ; 4.77e-09 s                 ; 5.18e-09 s                 ; Yes                       ; No                        ;
; VGA_B[2]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_B[3]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_G[0]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_G[1]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_G[2]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_G[3]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.47 V              ; -0.00753 V          ; 0.323 V                              ; 0.336 V                              ; 4.77e-09 s                  ; 5.18e-09 s                  ; Yes                        ; No                         ; 3.46 V                      ; 3.12e-07 V                  ; 3.47 V             ; -0.00753 V         ; 0.323 V                             ; 0.336 V                             ; 4.77e-09 s                 ; 5.18e-09 s                 ; Yes                       ; No                        ;
; AUDIO_L      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.47 V              ; -0.00753 V          ; 0.323 V                              ; 0.336 V                              ; 4.77e-09 s                  ; 5.18e-09 s                  ; Yes                        ; No                         ; 3.46 V                      ; 3.12e-07 V                  ; 3.47 V             ; -0.00753 V         ; 0.323 V                             ; 0.336 V                             ; 4.77e-09 s                 ; 5.18e-09 s                 ; Yes                       ; No                        ;
; AUDIO_R      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_BA[0]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.47 V              ; -0.00753 V          ; 0.323 V                              ; 0.336 V                              ; 4.77e-09 s                  ; 5.18e-09 s                  ; Yes                        ; No                         ; 3.46 V                      ; 3.12e-07 V                  ; 3.47 V             ; -0.00753 V         ; 0.323 V                             ; 0.336 V                             ; 4.77e-09 s                 ; 5.18e-09 s                 ; Yes                       ; No                        ;
; SDRAM_BA[1]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_CS_N   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_RAS_N  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_CAS_N  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_WE_N   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.47 V              ; -0.00753 V          ; 0.323 V                              ; 0.336 V                              ; 4.77e-09 s                  ; 5.18e-09 s                  ; Yes                        ; No                         ; 3.46 V                      ; 3.12e-07 V                  ; 3.47 V             ; -0.00753 V         ; 0.323 V                             ; 0.336 V                             ; 4.77e-09 s                 ; 5.18e-09 s                 ; Yes                       ; No                        ;
; SDRAM_DQMH_n ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQML_n ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_CLK    ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.47 V              ; -0.00753 V          ; 0.323 V                              ; 0.336 V                              ; 4.77e-09 s                  ; 5.18e-09 s                  ; Yes                        ; No                         ; 3.46 V                      ; 3.12e-07 V                  ; 3.47 V             ; -0.00753 V         ; 0.323 V                             ; 0.336 V                             ; 4.77e-09 s                 ; 5.18e-09 s                 ; Yes                       ; No                        ;
; SDRAM_CKE    ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[0]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[1]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[2]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[3]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[4]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[5]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[6]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[7]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[8]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.47 V              ; -0.00753 V          ; 0.323 V                              ; 0.336 V                              ; 4.77e-09 s                  ; 5.18e-09 s                  ; Yes                        ; No                         ; 3.46 V                      ; 3.12e-07 V                  ; 3.47 V             ; -0.00753 V         ; 0.323 V                             ; 0.336 V                             ; 4.77e-09 s                 ; 5.18e-09 s                 ; Yes                       ; No                        ;
; SDRAM_A[9]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[10]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[11]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[12]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SD_CLK       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SD_CMD       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SD_DAT3      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; CFG_CLK      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 6.59e-08 V                   ; 3.58 V              ; -0.0703 V           ; 0.234 V                              ; 0.091 V                              ; 2.93e-10 s                  ; 3.09e-10 s                  ; Yes                        ; Yes                        ; 3.46 V                      ; 6.59e-08 V                  ; 3.58 V             ; -0.0703 V          ; 0.234 V                             ; 0.091 V                             ; 2.93e-10 s                 ; 3.09e-10 s                 ; Yes                       ; Yes                       ;
; CFG_CS_n     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.08e-07 V                   ; 3.48 V              ; -0.026 V            ; 0.261 V                              ; 0.327 V                              ; 1.74e-09 s                  ; 1.77e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 3.08e-07 V                  ; 3.48 V             ; -0.026 V           ; 0.261 V                             ; 0.327 V                             ; 1.74e-09 s                 ; 1.77e-09 s                 ; No                        ; No                        ;
; CFG_DOUT     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.08e-07 V                   ; 3.48 V              ; -0.026 V            ; 0.261 V                              ; 0.327 V                              ; 1.74e-09 s                  ; 1.77e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 3.08e-07 V                  ; 3.48 V             ; -0.026 V           ; 0.261 V                             ; 0.327 V                             ; 1.74e-09 s                 ; 1.77e-09 s                 ; No                        ; No                        ;
; dplus1       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.47 V              ; -0.00704 V          ; 0.325 V                              ; 0.344 V                              ; 5.02e-09 s                  ; 5.44e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.47 V             ; -0.00704 V         ; 0.325 V                             ; 0.344 V                             ; 5.02e-09 s                 ; 5.44e-09 s                 ; No                        ; No                        ;
; dminus1      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.5 V               ; -0.041 V            ; 0.29 V                               ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.5 V              ; -0.041 V           ; 0.29 V                              ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; dplus2       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.51 V              ; -0.0513 V           ; 0.246 V                              ; 0.327 V                              ; 8.76e-10 s                  ; 8.99e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.51 V             ; -0.0513 V          ; 0.246 V                             ; 0.327 V                             ; 8.76e-10 s                 ; 8.99e-10 s                 ; No                        ; No                        ;
; dminus2      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.51 V              ; -0.0513 V           ; 0.246 V                              ; 0.327 V                              ; 8.76e-10 s                  ; 8.99e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.51 V             ; -0.0513 V          ; 0.246 V                             ; 0.327 V                             ; 8.76e-10 s                 ; 8.99e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[0]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.5 V               ; -0.041 V            ; 0.29 V                               ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.5 V              ; -0.041 V           ; 0.29 V                              ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[1]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.5 V               ; -0.041 V            ; 0.29 V                               ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.5 V              ; -0.041 V           ; 0.29 V                              ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[2]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.5 V               ; -0.041 V            ; 0.29 V                               ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.5 V              ; -0.041 V           ; 0.29 V                              ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[3]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.47 V              ; -0.00704 V          ; 0.325 V                              ; 0.344 V                              ; 5.02e-09 s                  ; 5.44e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.47 V             ; -0.00704 V         ; 0.325 V                             ; 0.344 V                             ; 5.02e-09 s                 ; 5.44e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[4]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.47 V              ; -0.00704 V          ; 0.325 V                              ; 0.344 V                              ; 5.02e-09 s                  ; 5.44e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.47 V             ; -0.00704 V         ; 0.325 V                             ; 0.344 V                             ; 5.02e-09 s                 ; 5.44e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[5]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.51 V              ; -0.0513 V           ; 0.246 V                              ; 0.327 V                              ; 8.76e-10 s                  ; 8.99e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.51 V             ; -0.0513 V          ; 0.246 V                             ; 0.327 V                             ; 8.76e-10 s                 ; 8.99e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[6]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.51 V              ; -0.0513 V           ; 0.246 V                              ; 0.327 V                              ; 8.76e-10 s                  ; 8.99e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.51 V             ; -0.0513 V          ; 0.246 V                             ; 0.327 V                             ; 8.76e-10 s                 ; 8.99e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[7]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[8]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.5 V               ; -0.041 V            ; 0.29 V                               ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.5 V              ; -0.041 V           ; 0.29 V                              ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[9]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.47 V              ; -0.00704 V          ; 0.325 V                              ; 0.344 V                              ; 5.02e-09 s                  ; 5.44e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.47 V             ; -0.00704 V         ; 0.325 V                             ; 0.344 V                             ; 5.02e-09 s                 ; 5.44e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[10] ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.5 V               ; -0.041 V            ; 0.29 V                               ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.5 V              ; -0.041 V           ; 0.29 V                              ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[11] ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.5 V               ; -0.041 V            ; 0.29 V                               ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.5 V              ; -0.041 V           ; 0.29 V                              ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[12] ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.5 V               ; -0.041 V            ; 0.29 V                               ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.5 V              ; -0.041 V           ; 0.29 V                              ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[13] ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.47 V              ; -0.00704 V          ; 0.325 V                              ; 0.344 V                              ; 5.02e-09 s                  ; 5.44e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.47 V             ; -0.00704 V         ; 0.325 V                             ; 0.344 V                             ; 5.02e-09 s                 ; 5.44e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[14] ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.5 V               ; -0.041 V            ; 0.29 V                               ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.5 V              ; -0.041 V           ; 0.29 V                              ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[15] ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.5 V               ; -0.041 V            ; 0.29 V                               ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.5 V              ; -0.041 V           ; 0.29 V                              ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Transfers                                                                                                                                                                                                       ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                                          ; To Clock                                                                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+----------+----------+----------+----------+
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1820     ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1        ; 249      ; 1        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 9331     ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 22120808 ; 0        ; 135563   ; 0        ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 91       ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 0        ; 0        ; 1        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 1486291  ; 0        ; 1        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 19111    ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK                                                                            ; 1        ; 0        ; 0        ; 0        ;
; FPGA_CLK                                                                            ; FPGA_CLK                                                                            ; 354      ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 81       ; 0        ; 0        ; 0        ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 25307    ; 7        ; 42       ; 1        ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Transfers                                                                                                                                                                                                        ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                                          ; To Clock                                                                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+----------+----------+----------+----------+
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1820     ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1        ; 249      ; 1        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 9331     ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 22120808 ; 0        ; 135563   ; 0        ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 91       ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 0        ; 0        ; 1        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 1486291  ; 0        ; 1        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 19111    ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK                                                                            ; 1        ; 0        ; 0        ; 0        ;
; FPGA_CLK                                                                            ; FPGA_CLK                                                                            ; 354      ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 81       ; 0        ; 0        ; 0        ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 25307    ; 7        ; 42       ; 1        ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Recovery Transfers                                                                                                                                                                                                    ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                                          ; To Clock                                                                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+----------+----------+----------+----------+
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 146      ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 677      ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 4756     ; 0        ; 59       ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 14       ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK                                                                            ; 26       ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 9        ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 9        ; 0        ; 0        ; 0        ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Removal Transfers                                                                                                                                                                                                     ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                                          ; To Clock                                                                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+----------+----------+----------+----------+
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 146      ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 677      ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 4756     ; 0        ; 59       ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 14       ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK                                                                            ; 26       ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 9        ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 9        ; 0        ; 0        ; 0        ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design


---------------
; Report RSKM ;
---------------
No dedicated SERDES Receiver circuitry present in device or used in design


+------------------------------------------------+
; Unconstrained Paths                            ;
+---------------------------------+-------+------+
; Property                        ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks                  ; 0     ; 0    ;
; Unconstrained Clocks            ; 0     ; 0    ;
; Unconstrained Input Ports       ; 21    ; 21   ;
; Unconstrained Input Port Paths  ; 21    ; 21   ;
; Unconstrained Output Ports      ; 54    ; 54   ;
; Unconstrained Output Port Paths ; 92    ; 92   ;
+---------------------------------+-------+------+


+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II 32-bit TimeQuest Timing Analyzer
    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
    Info: Processing started: Sat Jul 13 22:15:41 2019
Info: Command: quartus_sta atari800core -c atari800core
Info: qsta_default_script.tcl version: #1
Info (11104): Parallel Compilation has detected 12 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 6 of the 6 physical processors detected instead.
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (332104): Reading SDC File: 'atari800core.sdc'
Info (332110): Deriving PLL clocks
    Info (332110): create_generated_clock -source {\gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 40 -multiply_by 227 -duty_cycle 50.00 -name {\gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]} {\gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]}
    Info (332110): create_generated_clock -source {usb_pll|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 5 -multiply_by 48 -duty_cycle 50.00 -name {usb_pll|altpll_component|auto_generated|pll1|clk[0]} {usb_pll|altpll_component|auto_generated|pll1|clk[0]}
    Info (332110): create_generated_clock -source {\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 3 -duty_cycle 50.00 -name {\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]} {\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]}
    Info (332110): create_generated_clock -source {\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]} -duty_cycle 50.00 -name {\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]} {\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]}
    Info (332110): create_generated_clock -source {\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 3 -phase 225.00 -duty_cycle 50.00 -name {\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]} {\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]}
    Info (332110): create_generated_clock -source {\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -duty_cycle 50.00 -name {\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]} {\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]}
Info (332151): Clock uncertainty is not calculated until you update the timing netlist.
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Analyzing Slow 1200mV 85C Model
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -3.665
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -3.665      -275.360 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    -1.765        -1.765 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):    -0.274       -11.588 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.140         0.000 FPGA_CLK 
    Info (332119):     0.949         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     2.079         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case hold slack is -1.833
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -1.833      -130.585 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    -0.735        -0.735 FPGA_CLK 
    Info (332119):     0.343         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.413         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.414         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):    12.748         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
Info (332146): Worst-case recovery slack is -2.348
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -2.348       -21.132 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    -0.299        -7.592 FPGA_CLK 
    Info (332119):     7.512         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     7.659         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    12.988         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case removal slack is -0.360
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -0.360        -9.143 FPGA_CLK 
    Info (332119):     0.482         0.000 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     1.744         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     2.565         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     3.656         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case minimum pulse width slack is 5.595
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     5.595         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     5.720         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     8.534         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):     9.381         0.000 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    17.258         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    17.595         0.000 \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    89.530         0.000 FPGA_CLK 
Info: Analyzing Slow 1200mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -3.260
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -3.260      -243.956 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    -1.459        -1.459 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):    -0.278       -11.678 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.011         0.000 FPGA_CLK 
    Info (332119):     1.416         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     3.650         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case hold slack is -1.616
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -1.616      -113.847 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    -0.594        -0.594 FPGA_CLK 
    Info (332119):     0.344         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.362         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.363         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):    12.480         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
Info (332146): Worst-case recovery slack is -2.135
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -2.135       -19.215 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    -0.304        -7.751 FPGA_CLK 
    Info (332119):     7.912         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     8.066         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    13.404         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case removal slack is -0.281
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -0.281        -7.174 FPGA_CLK 
    Info (332119):     0.438         0.000 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     1.577         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     2.293         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     3.253         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case minimum pulse width slack is 5.595
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     5.595         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     5.733         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     8.533         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):     9.380         0.000 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    17.284         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    17.589         0.000 \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    89.643         0.000 FPGA_CLK 
Info: Analyzing Fast 1200mV 0C Model
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -1.898
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -1.898      -144.257 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    -0.230        -0.230 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):    -0.146        -7.463 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.343         0.000 FPGA_CLK 
    Info (332119):     3.238         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     6.985         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case hold slack is -1.063
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -1.063       -77.853 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    -0.632        -0.632 FPGA_CLK 
    Info (332119):     0.134         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.186         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.187         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):    11.482         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
Info (332146): Worst-case recovery slack is -1.187
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -1.187       -10.683 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.196         0.000 FPGA_CLK 
    Info (332119):     9.573         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     9.603         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    15.130         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case removal slack is -0.387
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -0.387        -9.978 FPGA_CLK 
    Info (332119):     0.100         0.000 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.851         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     1.236         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     1.756         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case minimum pulse width slack is 5.655
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     5.655         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     5.801         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     8.592         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):     9.376         0.000 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    17.369         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    17.601         0.000 \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    89.338         0.000 FPGA_CLK 
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 3 warnings
    Info: Peak virtual memory: 588 megabytes
    Info: Processing ended: Sat Jul 13 22:15:51 2019
    Info: Elapsed time: 00:00:10
    Info: Total CPU time (on all processors): 00:00:14


