TimeQuest Timing Analyzer report for atari800core
Mon Jun  1 15:43:36 2020
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. Parallel Compilation
  4. SDC File List
  5. Clocks
  6. Slow 1200mV 85C Model Fmax Summary
  7. Timing Closure Recommendations
  8. Slow 1200mV 85C Model Setup Summary
  9. Slow 1200mV 85C Model Hold Summary
 10. Slow 1200mV 85C Model Recovery Summary
 11. Slow 1200mV 85C Model Removal Summary
 12. Slow 1200mV 85C Model Minimum Pulse Width Summary
 13. Slow 1200mV 85C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 14. Slow 1200mV 85C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 15. Slow 1200mV 85C Model Setup: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'
 16. Slow 1200mV 85C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 17. Slow 1200mV 85C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]'
 18. Slow 1200mV 85C Model Setup: 'CLOCK_27[0]'
 19. Slow 1200mV 85C Model Hold: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'
 20. Slow 1200mV 85C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 21. Slow 1200mV 85C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 22. Slow 1200mV 85C Model Hold: 'CLOCK_27[0]'
 23. Slow 1200mV 85C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]'
 24. Slow 1200mV 85C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 25. Slow 1200mV 85C Model Recovery: 'CLOCK_27[0]'
 26. Slow 1200mV 85C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 27. Slow 1200mV 85C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 28. Slow 1200mV 85C Model Removal: 'CLOCK_27[0]'
 29. Slow 1200mV 85C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 30. Slow 1200mV 85C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 31. Slow 1200mV 85C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 32. Slow 1200mV 85C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 33. Slow 1200mV 85C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 34. Slow 1200mV 85C Model Minimum Pulse Width: 'pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'
 35. Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK_27[0]'
 36. Slow 1200mV 85C Model Minimum Pulse Width: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'
 37. Slow 1200mV 85C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]'
 38. Setup Times
 39. Hold Times
 40. Clock to Output Times
 41. Minimum Clock to Output Times
 42. Propagation Delay
 43. Minimum Propagation Delay
 44. Output Enable Times
 45. Minimum Output Enable Times
 46. Output Disable Times
 47. Minimum Output Disable Times
 48. Slow 1200mV 85C Model Metastability Report
 49. Slow 1200mV 0C Model Fmax Summary
 50. Slow 1200mV 0C Model Setup Summary
 51. Slow 1200mV 0C Model Hold Summary
 52. Slow 1200mV 0C Model Recovery Summary
 53. Slow 1200mV 0C Model Removal Summary
 54. Slow 1200mV 0C Model Minimum Pulse Width Summary
 55. Slow 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 56. Slow 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 57. Slow 1200mV 0C Model Setup: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'
 58. Slow 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 59. Slow 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]'
 60. Slow 1200mV 0C Model Setup: 'CLOCK_27[0]'
 61. Slow 1200mV 0C Model Hold: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'
 62. Slow 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 63. Slow 1200mV 0C Model Hold: 'CLOCK_27[0]'
 64. Slow 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 65. Slow 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]'
 66. Slow 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 67. Slow 1200mV 0C Model Recovery: 'CLOCK_27[0]'
 68. Slow 1200mV 0C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 69. Slow 1200mV 0C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 70. Slow 1200mV 0C Model Removal: 'CLOCK_27[0]'
 71. Slow 1200mV 0C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 72. Slow 1200mV 0C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 73. Slow 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 74. Slow 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 75. Slow 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 76. Slow 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'
 77. Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK_27[0]'
 78. Slow 1200mV 0C Model Minimum Pulse Width: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'
 79. Slow 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]'
 80. Setup Times
 81. Hold Times
 82. Clock to Output Times
 83. Minimum Clock to Output Times
 84. Propagation Delay
 85. Minimum Propagation Delay
 86. Output Enable Times
 87. Minimum Output Enable Times
 88. Output Disable Times
 89. Minimum Output Disable Times
 90. Slow 1200mV 0C Model Metastability Report
 91. Fast 1200mV 0C Model Setup Summary
 92. Fast 1200mV 0C Model Hold Summary
 93. Fast 1200mV 0C Model Recovery Summary
 94. Fast 1200mV 0C Model Removal Summary
 95. Fast 1200mV 0C Model Minimum Pulse Width Summary
 96. Fast 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 97. Fast 1200mV 0C Model Setup: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'
 98. Fast 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 99. Fast 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
100. Fast 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]'
101. Fast 1200mV 0C Model Setup: 'CLOCK_27[0]'
102. Fast 1200mV 0C Model Hold: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'
103. Fast 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
104. Fast 1200mV 0C Model Hold: 'CLOCK_27[0]'
105. Fast 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
106. Fast 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]'
107. Fast 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
108. Fast 1200mV 0C Model Recovery: 'CLOCK_27[0]'
109. Fast 1200mV 0C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
110. Fast 1200mV 0C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
111. Fast 1200mV 0C Model Removal: 'CLOCK_27[0]'
112. Fast 1200mV 0C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
113. Fast 1200mV 0C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
114. Fast 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
115. Fast 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
116. Fast 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
117. Fast 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'
118. Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK_27[0]'
119. Fast 1200mV 0C Model Minimum Pulse Width: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'
120. Fast 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]'
121. Setup Times
122. Hold Times
123. Clock to Output Times
124. Minimum Clock to Output Times
125. Propagation Delay
126. Minimum Propagation Delay
127. Output Enable Times
128. Minimum Output Enable Times
129. Output Disable Times
130. Minimum Output Disable Times
131. Fast 1200mV 0C Model Metastability Report
132. Multicorner Timing Analysis Summary
133. Setup Times
134. Hold Times
135. Clock to Output Times
136. Minimum Clock to Output Times
137. Progagation Delay
138. Minimum Progagation Delay
139. Board Trace Model Assignments
140. Input Transition Times
141. Slow Corner Signal Integrity Metrics
142. Fast Corner Signal Integrity Metrics
143. Setup Transfers
144. Hold Transfers
145. Recovery Transfers
146. Removal Transfers
147. Report TCCS
148. Report RSKM
149. Unconstrained Paths
150. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                                      ;
+--------------------+-------------------------------------------------------------------+
; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition ;
; Revision Name      ; atari800core                                                      ;
; Device Family      ; Cyclone III                                                       ;
; Device Name        ; EP3C25E144C8                                                      ;
; Timing Models      ; Final                                                             ;
; Delay Model        ; Combined                                                          ;
; Rise/Fall Delays   ; Enabled                                                           ;
+--------------------+-------------------------------------------------------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 12          ;
; Maximum allowed            ; 6           ;
;                            ;             ;
; Average used               ; 1.00        ;
; Maximum used               ; 6           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processors 2-6         ; < 0.1%      ;
;     Processors 7-12        ;   0.0%      ;
+----------------------------+-------------+


+------------------------------------------------------+
; SDC File List                                        ;
+------------------+--------+--------------------------+
; SDC File Path    ; Status ; Read at                  ;
+------------------+--------+--------------------------+
; atari800core.sdc ; OK     ; Mon Jun  1 15:43:28 2020 ;
+------------------+--------+--------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
+-----------------------------------------------------------------------+-----------+-----------+------------+--------+-----------+------------+-----------+-------------+--------+--------+-----------+------------+----------+----------------------------------------------------------------------+-------------------------------------------------------------------------+---------------------------------------------------------------------------+
; Clock Name                                                            ; Type      ; Period    ; Frequency  ; Rise   ; Fall      ; Duty Cycle ; Divide by ; Multiply by ; Phase  ; Offset ; Edge List ; Edge Shift ; Inverted ; Master                                                               ; Source                                                                  ; Targets                                                                   ;
+-----------------------------------------------------------------------+-----------+-----------+------------+--------+-----------+------------+-----------+-------------+--------+--------+-----------+------------+----------+----------------------------------------------------------------------+-------------------------------------------------------------------------+---------------------------------------------------------------------------+
; CLOCK_27[0]                                                           ; Base      ; 37.037    ; 27.0 MHz   ; 0.000  ; 18.518    ;            ;           ;             ;        ;        ;           ;            ;          ;                                                                      ;                                                                         ; { CLOCK_27[0] }                                                           ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Generated ; 8.810     ; 113.51 MHz ; 0.000  ; 4.405     ; 50.00      ; 27        ; 100         ;        ;        ;           ;            ; false    ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] } ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Generated ; 17.621    ; 56.75 MHz  ; 0.000  ; 8.810     ; 50.00      ; 27        ; 50          ;        ;        ;           ;            ; false    ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] } ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Generated ; 8.810     ; 113.51 MHz ; -2.447 ; 1.958     ; 50.00      ; 27        ; 100         ; -100.0 ;        ;           ;            ; false    ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] } ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Generated ; 88105.638 ; 0.01 MHz   ; -2.447 ; 44050.372 ; 50.00      ; 2700      ; 1           ; -0.0   ;        ;           ;            ; false    ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] } ;
; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; Generated ; 32.631    ; 30.65 MHz  ; 0.000  ; 16.315    ; 50.00      ; 200       ; 227         ;        ;        ;           ;            ; false    ; CLOCK_27[0]                                                          ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]  ; { pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] }  ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; Generated ; 83.333    ; 12.0 MHz   ; 0.000  ; 41.666    ; 50.00      ; 9         ; 4           ;        ;        ;           ;            ; false    ; CLOCK_27[0]                                                          ; reconfig_pll|altpll_component|auto_generated|pll1|inclk[0]              ; { reconfig_pll|altpll_component|auto_generated|pll1|clk[0] }              ;
+-----------------------------------------------------------------------+-----------+-----------+------------+--------+-----------+------------+-----------+-------------+--------+--------+-----------+------------+----------+----------------------------------------------------------------------+-------------------------------------------------------------------------+---------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Fmax Summary                                                                                                                                   ;
+------------+-----------------+-----------------------------------------------------------------------+---------------------------------------------------------------+
; Fmax       ; Restricted Fmax ; Clock Name                                                            ; Note                                                          ;
+------------+-----------------+-----------------------------------------------------------------------+---------------------------------------------------------------+
; 59.47 MHz  ; 59.47 MHz       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;                                                               ;
; 84.7 MHz   ; 84.7 MHz        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ;                                                               ;
; 135.91 MHz ; 135.91 MHz      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;                                                               ;
; 182.52 MHz ; 182.52 MHz      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ;                                                               ;
; 296.12 MHz ; 250.0 MHz       ; CLOCK_27[0]                                                           ; limit due to minimum period restriction (max I/O toggle rate) ;
+------------+-----------------+-----------------------------------------------------------------------+---------------------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


----------------------------------
; Timing Closure Recommendations ;
----------------------------------
HTML report is unavailable in plain text report export.


+------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup Summary                                                            ;
+-----------------------------------------------------------------------+--------+---------------+
; Clock                                                                 ; Slack  ; End Point TNS ;
+-----------------------------------------------------------------------+--------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; -4.849 ; -10.688       ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -1.547 ; -1.547        ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 0.123  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.890  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 11.442 ; 0.000         ;
; CLOCK_27[0]                                                           ; 33.660 ; 0.000         ;
+-----------------------------------------------------------------------+--------+---------------+


+------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold Summary                                                             ;
+-----------------------------------------------------------------------+--------+---------------+
; Clock                                                                 ; Slack  ; End Point TNS ;
+-----------------------------------------------------------------------+--------+---------------+
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; -1.838 ; -1.838        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.393  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.453  ; 0.000         ;
; CLOCK_27[0]                                                           ; 0.454  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.454  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 9.627  ; 0.000         ;
+-----------------------------------------------------------------------+--------+---------------+


+------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery Summary                                                         ;
+-----------------------------------------------------------------------+--------+---------------+
; Clock                                                                 ; Slack  ; End Point TNS ;
+-----------------------------------------------------------------------+--------+---------------+
; CLOCK_27[0]                                                           ; -1.239 ; -11.151       ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 2.099  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 10.098 ; 0.000         ;
+-----------------------------------------------------------------------+--------+---------------+


+------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal Summary                                                          ;
+-----------------------------------------------------------------------+--------+---------------+
; Clock                                                                 ; Slack  ; End Point TNS ;
+-----------------------------------------------------------------------+--------+---------------+
; CLOCK_27[0]                                                           ; -0.423 ; -3.806        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 1.688  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 4.888  ; 0.000         ;
+-----------------------------------------------------------------------+--------+---------------+


+---------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width Summary                                                 ;
+-----------------------------------------------------------------------+-----------+---------------+
; Clock                                                                 ; Slack     ; End Point TNS ;
+-----------------------------------------------------------------------+-----------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 4.093     ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 4.224     ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.373     ; 0.000         ;
; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; 16.275    ; 0.000         ;
; CLOCK_27[0]                                                           ; 18.274    ; 0.000         ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 40.596    ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 44052.506 ; 0.000         ;
+-----------------------------------------------------------------------+-----------+---------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                           ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                            ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; -4.849 ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|synchronizer:tick_toggle_synchronizer|ff_reg[2]                                               ; CLOCK_27[0]                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.150        ; -4.049     ; 0.881      ;
; -2.920 ; switch_pal_ntsc:pll_switcher|reset_n_reg                                                                                             ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[2]                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.354        ; -2.243     ; 0.882      ;
; -2.919 ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                                          ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[2]                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.354        ; -2.243     ; 0.881      ;
; 0.678  ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|synchronizer:sync_clk|ff_reg[2]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 1.809        ; -0.182     ; 0.950      ;
; 0.717  ; user_io:my_user_io|ps2_kbd_data                                                                                                      ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|synchronizer:sync_dat|ff_reg[2]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 1.809        ; -0.182     ; 0.911      ;
; 0.805  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[30]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[6]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.075     ; 16.742     ;
; 0.846  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[28]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[6]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.156     ; 16.620     ;
; 0.854  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[0]                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[6]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.114     ; 16.654     ;
; 0.939  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[30]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[7]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.063     ; 16.620     ;
; 0.980  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[28]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[7]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.144     ; 16.498     ;
; 0.988  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[0]                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[7]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.102     ; 16.532     ;
; 1.033  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[30]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[6]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.122     ; 16.467     ;
; 1.039  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|PC[9]                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.085     ; 16.498     ;
; 1.074  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[28]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[6]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.203     ; 16.345     ;
; 1.076  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[0]~_Duplicate_4         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.380      ; 16.926     ;
; 1.082  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[0]                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[6]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.161     ; 16.379     ;
; 1.093  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[30]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[6]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.099     ; 16.430     ;
; 1.113  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[29]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[6]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.072     ; 16.437     ;
; 1.119  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|write_en_r                                                                     ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[25]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.092     ; 16.411     ;
; 1.126  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[30]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[7]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.122     ; 16.374     ;
; 1.134  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[28]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[6]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.180     ; 16.308     ;
; 1.138  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[6]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.377      ; 16.861     ;
; 1.142  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[0]                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[6]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.138     ; 16.342     ;
; 1.167  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[28]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[7]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.203     ; 16.252     ;
; 1.172  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|PC[9]                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.085     ; 16.365     ;
; 1.175  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[0]                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[7]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.161     ; 16.286     ;
; 1.177  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]~_Duplicate_7 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[6]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.156     ; 16.289     ;
; 1.209  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[0]~_Duplicate_4         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.380      ; 16.793     ;
; 1.217  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[30]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[7]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.079     ; 16.326     ;
; 1.228  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[10]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.338      ; 16.732     ;
; 1.228  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[7]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.338      ; 16.732     ;
; 1.228  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[8]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.338      ; 16.732     ;
; 1.228  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[9]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.338      ; 16.732     ;
; 1.236  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|write_en_r                                                                     ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[29]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.070     ; 16.316     ;
; 1.247  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[29]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[7]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.060     ; 16.315     ;
; 1.258  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[28]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[7]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.160     ; 16.204     ;
; 1.266  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[10]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.086     ; 16.270     ;
; 1.266  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.086     ; 16.270     ;
; 1.266  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[7]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.086     ; 16.270     ;
; 1.266  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[0]                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[7]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.118     ; 16.238     ;
; 1.268  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|write_en_r                                                                     ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[27]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.089     ; 16.265     ;
; 1.271  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[6]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.377      ; 16.728     ;
; 1.299  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[2]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.395      ; 16.718     ;
; 1.299  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[6]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.395      ; 16.718     ;
; 1.299  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[3]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.395      ; 16.718     ;
; 1.299  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|PC[9]                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.108     ; 16.215     ;
; 1.308  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[29]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.368      ; 16.682     ;
; 1.308  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.368      ; 16.682     ;
; 1.308  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[43]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.368      ; 16.682     ;
; 1.308  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[34]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.368      ; 16.682     ;
; 1.309  ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|PC[9]                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.207     ; 16.106     ;
; 1.311  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]~_Duplicate_7 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[7]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.144     ; 16.167     ;
; 1.319  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|byte_write_r                                                                   ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[25]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.086     ; 16.217     ;
; 1.321  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|write_en_r                                                                     ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[24]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.092     ; 16.209     ;
; 1.328  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_enable~0_OTERM3                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|PC[9]                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.102     ; 16.192     ;
; 1.336  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[0]~_Duplicate_4         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.357      ; 16.643     ;
; 1.341  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[29]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[6]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.119     ; 16.162     ;
; 1.346  ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[0]~_Duplicate_4         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.258      ; 16.534     ;
; 1.353  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[30]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[5]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.099     ; 16.170     ;
; 1.361  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[10]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.338      ; 16.599     ;
; 1.361  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[7]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.338      ; 16.599     ;
; 1.361  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[8]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.338      ; 16.599     ;
; 1.361  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[9]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.338      ; 16.599     ;
; 1.365  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_enable~0_OTERM3                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[0]~_Duplicate_4         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.363      ; 16.620     ;
; 1.374  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[30]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.371      ; 16.619     ;
; 1.374  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[35]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.371      ; 16.619     ;
; 1.394  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[28]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[5]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.180     ; 16.048     ;
; 1.398  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[6]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.354      ; 16.578     ;
; 1.399  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[10]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.086     ; 16.137     ;
; 1.399  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.086     ; 16.137     ;
; 1.399  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[7]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.086     ; 16.137     ;
; 1.401  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[29]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[6]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.096     ; 16.125     ;
; 1.402  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[0]                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[5]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.138     ; 16.082     ;
; 1.405  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[7]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.391      ; 16.608     ;
; 1.405  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]~_Duplicate_7 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[6]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.203     ; 16.014     ;
; 1.408  ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[6]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.255      ; 16.469     ;
; 1.410  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|write_en_r                                                                     ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[23]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.090     ; 16.122     ;
; 1.411  ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|PC[9]                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.108     ; 16.103     ;
; 1.414  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[31]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[6]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.156     ; 16.052     ;
; 1.419  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[34]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[6]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.072     ; 16.131     ;
; 1.427  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_enable~0_OTERM3                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[6]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.360      ; 16.555     ;
; 1.432  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[2]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.395      ; 16.585     ;
; 1.432  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[6]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.395      ; 16.585     ;
; 1.432  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[3]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.395      ; 16.585     ;
; 1.434  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[4]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.413      ; 16.601     ;
; 1.434  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[1]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.413      ; 16.601     ;
; 1.434  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[29]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[7]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.119     ; 16.069     ;
; 1.436  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[4]                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[6]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.140     ; 16.046     ;
; 1.436  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|byte_write_r                                                                   ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[29]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.064     ; 16.122     ;
; 1.437  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]                                                                ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|synchronizer:sync_clk|ff_reg[2]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 1.809        ; 4.063      ; 4.436      ;
; 1.438  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cycleIndirect ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.059     ; 16.125     ;
; 1.438  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cycle3        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.059     ; 16.125     ;
; 1.438  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cycleWrite    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.059     ; 16.125     ;
; 1.440  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|PC[8]                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.069     ; 16.113     ;
; 1.440  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|PC[0]                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.069     ; 16.113     ;
; 1.441  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[29]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.368      ; 16.549     ;
; 1.441  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.368      ; 16.549     ;
; 1.441  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[43]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.368      ; 16.549     ;
; 1.441  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[34]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.368      ; 16.549     ;
; 1.443  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[0]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.409      ; 16.588     ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                  ;
+--------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; -1.547 ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 1.958        ; -2.032     ; 1.341      ;
+--------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                                                           ; To Node                                                                                                                                                                                                                     ; Launch Clock                                                          ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 0.123  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.371        ; 1.368      ; 1.457      ;
; 35.763 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|altsyncram:altsyncram4|altsyncram_72m3:auto_generated|ram_block1a0~porta_address_reg0                 ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.803     ; 7.492      ;
; 36.843 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|altsyncram:altsyncram4|altsyncram_cul3:auto_generated|ram_block1a0~porta_address_reg0 ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.806     ; 6.409      ;
; 36.961 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.412     ; 6.685      ;
; 37.001 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C2_data_state                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.405     ; 6.652      ;
; 37.004 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C1_data_state                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.405     ; 6.649      ;
; 37.231 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C0_data_state                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.405     ; 6.422      ;
; 37.376 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C3_data_state                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.405     ; 6.277      ;
; 38.004 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C4_data_state                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.405     ; 5.649      ;
; 38.264 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3]                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.405     ; 5.389      ;
; 38.265 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4]                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.405     ; 5.388      ;
; 38.358 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.405     ; 5.295      ;
; 38.392 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_seq_data_state                                                                               ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.405     ; 5.261      ;
; 38.451 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2]                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.405     ; 5.202      ;
; 38.520 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2]                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.410     ; 5.128      ;
; 38.599 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1]                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.405     ; 5.054      ;
; 38.681 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 4.113      ; 7.100      ;
; 38.702 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_data_state                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.414     ; 4.942      ;
; 38.708 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_data_state                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.414     ; 4.936      ;
; 38.734 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1]                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.410     ; 4.914      ;
; 38.799 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 4.090      ; 6.959      ;
; 38.911 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C2_data_state                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.414     ; 4.733      ;
; 38.919 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3]                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.410     ; 4.729      ;
; 38.986 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 4.090      ; 6.772      ;
; 39.042 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_data_state                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.414     ; 4.602      ;
; 39.067 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4]                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.410     ; 4.581      ;
; 39.079 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 4.113      ; 6.702      ;
; 39.116 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 4.108      ; 6.660      ;
; 39.127 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 4.104      ; 6.645      ;
; 39.153 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|areset_init_state_1                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 4.090      ; 6.605      ;
; 39.346 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[0]                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.405     ; 4.307      ;
; 39.494 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_seq_data_state                                                               ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.402     ; 4.162      ;
; 39.583 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C4_data_state                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.414     ; 4.061      ;
; 39.756 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[0]                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.410     ; 3.892      ;
; 40.136 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.401     ; 3.521      ;
; 40.453 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|configupdate2_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|configupdate3_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.123     ; 1.091      ;
; 40.454 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|configupdate2_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|configupdate3_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.123     ; 1.090      ;
; 74.393 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.082     ; 8.859      ;
; 74.467 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.105     ; 8.762      ;
; 74.679 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.105     ; 8.550      ;
; 74.782 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.082     ; 8.470      ;
; 74.792 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.087     ; 8.455      ;
; 74.810 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.091     ; 8.433      ;
; 74.813 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|areset_init_state_1                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.105     ; 8.416      ;
; 74.831 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.093     ; 8.410      ;
; 75.207 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.093     ; 8.034      ;
; 75.208 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.093     ; 8.033      ;
; 75.286 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.093     ; 7.955      ;
; 75.900 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.080     ; 7.354      ;
; 75.974 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.103     ; 7.257      ;
; 76.186 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.103     ; 7.045      ;
; 76.289 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.080     ; 6.965      ;
; 76.299 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.085     ; 6.950      ;
; 76.317 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.089     ; 6.928      ;
; 76.320 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|areset_init_state_1                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.103     ; 6.911      ;
; 76.373 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                                            ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.110     ; 6.851      ;
; 76.741 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                                            ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.110     ; 6.483      ;
; 76.743 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                                            ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.110     ; 6.481      ;
; 76.836 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                                            ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.110     ; 6.388      ;
; 77.201 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.056     ; 6.077      ;
; 77.275 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.079     ; 5.980      ;
; 77.366 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.111     ; 5.857      ;
; 77.479 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                                            ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.086     ; 5.769      ;
; 77.482 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.056     ; 5.796      ;
; 77.487 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.079     ; 5.768      ;
; 77.522 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.088     ; 5.724      ;
; 77.544 ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.111     ; 5.679      ;
; 77.556 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.079     ; 5.699      ;
; 77.578 ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.111     ; 5.645      ;
; 77.590 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.056     ; 5.688      ;
; 77.600 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.061     ; 5.673      ;
; 77.614 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_init_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.088     ; 5.632      ;
; 77.618 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.065     ; 5.651      ;
; 77.621 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|areset_init_state_1                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.079     ; 5.634      ;
; 77.700 ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.088     ; 5.546      ;
; 77.730 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_init_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.111     ; 5.493      ;
; 77.734 ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.088     ; 5.512      ;
; 77.768 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.079     ; 5.487      ;
; 77.792 ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_init_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.088     ; 5.454      ;
; 77.818 ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.111     ; 5.405      ;
; 77.826 ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_init_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.088     ; 5.420      ;
; 77.855 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                                            ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.086     ; 5.393      ;
; 77.856 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                                            ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.086     ; 5.392      ;
; 77.871 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.056     ; 5.407      ;
; 77.881 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.061     ; 5.392      ;
; 77.899 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.065     ; 5.370      ;
; 77.902 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|areset_init_state_1                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.079     ; 5.353      ;
; 77.905 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.086     ; 5.343      ;
; 77.908 ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_init_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.111     ; 5.315      ;
; 77.934 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                                            ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.086     ; 5.314      ;
; 77.942 ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_init_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.111     ; 5.281      ;
; 77.974 ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.088     ; 5.272      ;
; 78.066 ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_init_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.088     ; 5.180      ;
; 78.086 ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[0]                                                                                                                                                                                ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 5.177      ;
; 78.110 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0]                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.079     ; 5.145      ;
; 78.110 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0]                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.079     ; 5.145      ;
; 78.110 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0]                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[2] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.079     ; 5.145      ;
; 78.110 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0]                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[3] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.079     ; 5.145      ;
; 78.110 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0]                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[4] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.079     ; 5.145      ;
; 78.110 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0]                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[5] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.079     ; 5.145      ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                 ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.890 ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:0:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 4.405        ; -2.032     ; 1.341      ;
; 1.452 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.158     ; 7.071      ;
; 1.564 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.144     ; 6.973      ;
; 1.636 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.158     ; 6.887      ;
; 1.734 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.158     ; 6.789      ;
; 1.738 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.144     ; 6.799      ;
; 1.881 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.156     ; 6.644      ;
; 1.886 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.158     ; 6.637      ;
; 1.890 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.156     ; 6.635      ;
; 1.911 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.162     ; 6.608      ;
; 1.914 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.162     ; 6.605      ;
; 1.945 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.144     ; 6.592      ;
; 1.946 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.168     ; 6.567      ;
; 1.976 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.174     ; 6.531      ;
; 1.983 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.081     ; 6.747      ;
; 2.003 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.122     ; 6.556      ;
; 2.015 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.168     ; 6.498      ;
; 2.039 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[2]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.180     ; 6.462      ;
; 2.039 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.174     ; 6.468      ;
; 2.057 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.180     ; 6.444      ;
; 2.061 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.144     ; 6.476      ;
; 2.072 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.146     ; 6.463      ;
; 2.089 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.156     ; 6.436      ;
; 2.113 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.162     ; 6.406      ;
; 2.132 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.132     ; 6.417      ;
; 2.139 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[9]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.169     ; 6.373      ;
; 2.143 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.122     ; 6.416      ;
; 2.157 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.161     ; 6.363      ;
; 2.190 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.159     ; 6.332      ;
; 2.196 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[2]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.180     ; 6.305      ;
; 2.210 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.069     ; 6.532      ;
; 2.222 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.173     ; 6.286      ;
; 2.223 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.161     ; 6.297      ;
; 2.241 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.180     ; 6.260      ;
; 2.247 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.146     ; 6.288      ;
; 2.248 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.159     ; 6.274      ;
; 2.255 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.171     ; 6.255      ;
; 2.258 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.121     ; 6.302      ;
; 2.269 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.156     ; 6.256      ;
; 2.280 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.146     ; 6.255      ;
; 2.293 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.162     ; 6.226      ;
; 2.297 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[9]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.169     ; 6.215      ;
; 2.299 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.158     ; 6.224      ;
; 2.299 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.110     ; 6.272      ;
; 2.309 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.069     ; 6.433      ;
; 2.318 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.121     ; 6.242      ;
; 2.348 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.173     ; 6.160      ;
; 2.359 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.132     ; 6.190      ;
; 2.359 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.144     ; 6.178      ;
; 2.364 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.110     ; 6.207      ;
; 2.364 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.122     ; 6.195      ;
; 2.373 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.171     ; 6.137      ;
; 2.422 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.161     ; 6.098      ;
; 2.427 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[13]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.157     ; 6.097      ;
; 2.434 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.121     ; 6.126      ;
; 2.434 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.121     ; 6.126      ;
; 2.447 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.159     ; 6.075      ;
; 2.455 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.132     ; 6.094      ;
; 2.467 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.169     ; 6.045      ;
; 2.477 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.146     ; 6.058      ;
; 2.486 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.110     ; 6.085      ;
; 2.489 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.122     ; 6.070      ;
; 2.494 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.110     ; 6.077      ;
; 2.501 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.069     ; 6.241      ;
; 2.507 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.158     ; 6.016      ;
; 2.512 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.146     ; 6.023      ;
; 2.524 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.156     ; 6.001      ;
; 2.535 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.148     ; 5.962      ;
; 2.535 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.148     ; 5.962      ;
; 2.537 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.110     ; 6.034      ;
; 2.550 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.069     ; 6.192      ;
; 2.551 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.122     ; 6.008      ;
; 2.558 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.121     ; 6.002      ;
; 2.561 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[13]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.157     ; 5.963      ;
; 2.563 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.110     ; 6.008      ;
; 2.569 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.132     ; 5.980      ;
; 2.571 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.161     ; 5.949      ;
; 2.572 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[1]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.188     ; 5.921      ;
; 2.574 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.146     ; 5.961      ;
; 2.589 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.168     ; 5.924      ;
; 2.590 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[2]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.168     ; 5.923      ;
; 2.604 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.159     ; 5.918      ;
; 2.606 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.156     ; 5.919      ;
; 2.607 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.156     ; 5.918      ;
; 2.610 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.156     ; 5.915      ;
; 2.611 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.111     ; 5.959      ;
; 2.614 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.111     ; 5.956      ;
; 2.619 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.122     ; 5.940      ;
; 2.630 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.162     ; 5.889      ;
; 2.640 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.162     ; 5.879      ;
; 2.651 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.168     ; 5.862      ;
; 2.651 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.169     ; 5.861      ;
; 2.675 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.174     ; 5.832      ;
; 2.676 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[10]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.112     ; 5.893      ;
; 2.679 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.123     ; 5.879      ;
; 2.682 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.144     ; 5.855      ;
; 2.683 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.168     ; 5.830      ;
; 2.686 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.132     ; 5.863      ;
; 2.687 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.132     ; 5.862      ;
; 2.691 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[9]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.157     ; 5.833      ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]'                                                                                                                                                                                                                                                                                                                     ;
+-----------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack     ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-----------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 11.442    ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 15.493       ; -2.032     ; 1.877      ;
; 88100.159 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 5.400      ;
; 88100.175 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 5.384      ;
; 88100.772 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 4.787      ;
; 88100.779 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 4.780      ;
; 88100.782 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 4.777      ;
; 88100.960 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 4.599      ;
; 88100.968 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 4.591      ;
; 88101.031 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 4.528      ;
; 88101.065 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 4.494      ;
; 88101.068 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.081     ; 4.490      ;
; 88101.071 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.081     ; 4.487      ;
; 88101.078 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 4.481      ;
; 88101.198 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 4.361      ;
; 88101.415 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 4.144      ;
; 88101.417 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 4.142      ;
; 88101.422 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 4.137      ;
; 88101.430 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 4.129      ;
; 88101.451 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 4.108      ;
; 88101.580 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 3.979      ;
; 88101.582 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.081     ; 3.976      ;
; 88101.585 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.081     ; 3.973      ;
; 88101.752 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.081     ; 3.806      ;
; 88102.044 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_r_inc                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 3.515      ;
; 88102.090 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 3.469      ;
; 88102.276 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.079     ; 3.284      ;
; 88102.276 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.079     ; 3.284      ;
; 88102.276 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.079     ; 3.284      ;
; 88102.276 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.079     ; 3.284      ;
; 88102.276 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.079     ; 3.284      ;
; 88102.276 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.079     ; 3.284      ;
; 88102.276 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.079     ; 3.284      ;
; 88102.276 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.079     ; 3.284      ;
; 88102.285 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.081     ; 3.273      ;
; 88102.434 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.079     ; 3.126      ;
; 88102.434 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.079     ; 3.126      ;
; 88102.434 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.079     ; 3.126      ;
; 88102.434 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.079     ; 3.126      ;
; 88102.434 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.079     ; 3.126      ;
; 88102.434 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.079     ; 3.126      ;
; 88102.434 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.079     ; 3.126      ;
; 88102.434 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.079     ; 3.126      ;
; 88102.458 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.079     ; 3.102      ;
; 88102.458 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.079     ; 3.102      ;
; 88102.458 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.079     ; 3.102      ;
; 88102.458 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.079     ; 3.102      ;
; 88102.458 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.079     ; 3.102      ;
; 88102.458 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.079     ; 3.102      ;
; 88102.458 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.079     ; 3.102      ;
; 88102.458 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.079     ; 3.102      ;
; 88102.488 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 3.071      ;
; 88102.554 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_r_inc                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 3.005      ;
; 88102.576 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 2.983      ;
; 88102.579 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 2.980      ;
; 88102.596 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 2.963      ;
; 88102.633 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 2.926      ;
; 88102.641 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 2.918      ;
; 88102.641 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 2.918      ;
; 88102.641 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 2.918      ;
; 88102.641 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 2.918      ;
; 88102.641 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 2.918      ;
; 88102.641 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 2.918      ;
; 88102.641 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 2.918      ;
; 88102.641 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 2.918      ;
; 88102.741 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.079     ; 2.819      ;
; 88102.741 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.079     ; 2.819      ;
; 88102.741 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.079     ; 2.819      ;
; 88102.741 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.079     ; 2.819      ;
; 88102.741 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.079     ; 2.819      ;
; 88102.741 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.079     ; 2.819      ;
; 88102.741 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.079     ; 2.819      ;
; 88102.741 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.079     ; 2.819      ;
; 88102.857 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 2.702      ;
; 88102.860 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 2.699      ;
; 88102.860 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.081     ; 2.698      ;
; 88102.900 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 2.659      ;
; 88102.945 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 2.614      ;
; 88102.986 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 2.573      ;
; 88102.989 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 2.570      ;
; 88102.992 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 2.567      ;
; 88102.995 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 2.564      ;
; 88103.067 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.081     ; 2.491      ;
; 88103.070 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.081     ; 2.488      ;
; 88103.326 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 2.233      ;
; 88103.329 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 2.230      ;
; 88103.474 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_state[3]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 2.085      ;
; 88103.484 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.079     ; 2.076      ;
; 88103.484 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.079     ; 2.076      ;
; 88103.484 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.079     ; 2.076      ;
; 88103.484 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.079     ; 2.076      ;
; 88103.484 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.079     ; 2.076      ;
; 88103.484 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.079     ; 2.076      ;
; 88103.484 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.079     ; 2.076      ;
; 88103.484 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.079     ; 2.076      ;
; 88103.488 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 2.071      ;
; 88103.536 ; user_io:my_user_io|ps2_kbd_data                                             ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 2.023      ;
; 88103.592 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.079     ; 1.968      ;
; 88103.595 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_r_inc                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.079     ; 1.965      ;
; 88103.612 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_state[3]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 1.947      ;
; 88103.654 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_state[3]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 1.905      ;
+-----------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'CLOCK_27[0]'                                                                                                                                                           ;
+--------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                 ; To Node                                                   ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 33.660 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 3.298      ;
; 33.806 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 3.152      ;
; 33.821 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 3.137      ;
; 33.950 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 3.008      ;
; 33.967 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 2.991      ;
; 34.069 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 2.889      ;
; 34.099 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 2.859      ;
; 34.113 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 2.845      ;
; 34.116 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 2.842      ;
; 34.128 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 2.830      ;
; 34.189 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 2.769      ;
; 34.214 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 2.744      ;
; 34.215 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 2.743      ;
; 34.239 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 2.719      ;
; 34.256 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 2.702      ;
; 34.257 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 2.701      ;
; 34.262 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 2.696      ;
; 34.338 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 2.620      ;
; 34.360 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 2.598      ;
; 34.364 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 2.594      ;
; 34.466 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 2.492      ;
; 34.699 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 2.259      ;
; 34.707 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 2.251      ;
; 34.713 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 2.245      ;
; 34.716 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 2.242      ;
; 34.743 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 2.215      ;
; 34.825 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 2.133      ;
; 34.826 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 2.132      ;
; 34.829 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 2.129      ;
; 34.833 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 2.125      ;
; 34.834 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 2.124      ;
; 34.849 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 2.109      ;
; 34.858 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 2.100      ;
; 34.859 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 2.099      ;
; 34.885 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 2.073      ;
; 34.891 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 2.067      ;
; 34.958 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 2.000      ;
; 35.007 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 1.951      ;
; 35.012 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 1.946      ;
; 35.033 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 1.925      ;
; 35.034 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 1.924      ;
; 35.041 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 1.917      ;
; 35.062 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 1.896      ;
; 35.067 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 1.891      ;
; 35.087 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 1.871      ;
; 35.097 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 1.861      ;
; 35.122 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 1.836      ;
; 35.198 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 1.760      ;
; 35.198 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 1.760      ;
; 35.199 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 1.759      ;
; 35.202 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 1.756      ;
; 35.219 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 1.739      ;
; 35.262 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 1.696      ;
; 35.406 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 1.552      ;
; 35.445 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 1.513      ;
; 35.452 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 1.506      ;
; 35.682 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 1.276      ;
; 35.685 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 1.273      ;
; 35.722 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 1.236      ;
; 36.100 ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.080     ; 0.858      ;
+--------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                                   ; To Node                                                                                                                                                                                                                             ; Launch Clock                                                          ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; -1.838 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.017        ; 2.716      ; 1.277      ;
; 0.453  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_data_state                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C2_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C2_data_state                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_data_state                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_data_state                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C4_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C4_data_state                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.454  ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                               ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                                       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                               ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                               ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                                       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C2_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C2_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C1_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C1_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C3_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C3_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C0_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C0_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C4_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C4_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_seq_data_state                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_seq_data_state                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_seq_data_state                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_seq_data_state                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.492  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4]         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.784      ;
; 0.493  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.785      ;
; 0.494  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5]         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.786      ;
; 0.503  ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[1]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[0]                                                                                                                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.794      ;
; 0.509  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[24]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[24]                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.801      ;
; 0.509  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|configupdate_state                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|configupdate2_state                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.801      ;
; 0.510  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|configupdate_state                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|configupdate2_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.802      ;
; 0.510  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C1_ena_state                                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C1_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.802      ;
; 0.511  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C3_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C2_ena_state                                                                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.803      ;
; 0.511  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C2_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C1_ena_state                                                                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.803      ;
; 0.512  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C1_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C0_ena_state                                                                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.804      ;
; 0.521  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reset_state                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.812      ;
; 0.527  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_counter_state                                                        ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|tmp_seq_ena_state                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.819      ;
; 0.536  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_init_state                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.828      ;
; 0.537  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C3_ena_state                                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C3_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.829      ;
; 0.651  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C0_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|tmp_seq_ena_state                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.943      ;
; 0.652  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C2_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_ena_state                                                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 0.945      ;
; 0.653  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|tmp_seq_ena_state                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 0.946      ;
; 0.658  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C4_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C3_ena_state                                                                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.950      ;
; 0.662  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C4_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_counter_state                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.954      ;
; 0.677  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[1]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|altsyncram:altsyncram4|altsyncram_72m3:auto_generated|ram_block1a0~porta_address_reg0 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.476      ; 1.407      ;
; 0.679  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_init_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_counter_state                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.971      ;
; 0.713  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_init_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C4_ena_state                                                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.003      ;
; 0.722  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|tmp_seq_ena_state                                                             ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_seq_ena_state                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.014      ;
; 0.736  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.028      ;
; 0.736  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[9]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[9]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.028      ;
; 0.736  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[11]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[11]                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.028      ;
; 0.737  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.029      ;
; 0.737  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[13]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[13]                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.029      ;
; 0.737  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[15]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[15]                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.029      ;
; 0.737  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[23]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[23]                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.029      ;
; 0.738  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[17]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[17]                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.030      ;
; 0.739  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.031      ;
; 0.739  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.031      ;
; 0.739  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.031      ;
; 0.739  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[12]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[12]                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.031      ;
; 0.740  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.032      ;
; 0.740  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[8]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[8]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.032      ;
; 0.740  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[10]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[10]                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.032      ;
; 0.740  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[14]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[14]                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.032      ;
; 0.740  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[18]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[18]                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.032      ;
; 0.740  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[19]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[19]                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.032      ;
; 0.740  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[21]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[21]                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.032      ;
; 0.741  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.033      ;
; 0.741  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[16]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[16]                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.033      ;
; 0.742  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[20]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[20]                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.034      ;
; 0.742  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[22]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[22]                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.034      ;
; 0.744  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|areset_init_state_1                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.035      ;
; 0.745  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1]         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.036      ;
; 0.746  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3]         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.038      ;
; 0.746  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.038      ;
; 0.746  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[3]         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.037      ;
; 0.747  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.039      ;
; 0.747  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1]         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.039      ;
; 0.748  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1]         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.040      ;
; 0.748  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[4]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.040      ;
; 0.748  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[4] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[4]         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.039      ;
; 0.748  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[5] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[5]         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.039      ;
; 0.748  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[7] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[7]         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.039      ;
; 0.748  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_ena_state                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_data_state                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.041      ;
; 0.749  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.041      ;
; 0.749  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.041      ;
; 0.749  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3]         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.041      ;
; 0.749  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[2]         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.040      ;
; 0.750  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.042      ;
; 0.750  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[6] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[6]         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.041      ;
; 0.751  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.043      ;
; 0.751  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2]         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.043      ;
; 0.757  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_ena_state                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_data_state                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.050      ;
; 0.758  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_ena_state                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_data_state                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.051      ;
; 0.759  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_init_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.050      ;
; 0.760  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.052      ;
; 0.760  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C0_ena_state                                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C0_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.052      ;
; 0.761  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[3]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.053      ;
; 0.762  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[4] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[4]         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.054      ;
; 0.762  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[5] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[5]         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.054      ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                   ; To Node                                                                                                                                                                                                                                ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.393 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[5]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.482      ; 1.129      ;
; 0.399 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp3_snap_reg[1]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a8~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.482      ; 1.135      ;
; 0.401 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_snap_reg[5]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a8~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.482      ; 1.137      ;
; 0.404 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp3_snap_reg[6]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a8~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.482      ; 1.140      ;
; 0.405 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[6]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a8~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.482      ; 1.141      ;
; 0.405 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[3]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.486      ; 1.145      ;
; 0.406 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[4]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a8~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.482      ; 1.142      ;
; 0.406 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[7]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.482      ; 1.142      ;
; 0.407 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[2]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a8~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.482      ; 1.143      ;
; 0.410 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[1]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.482      ; 1.146      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[2]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.483      ; 1.149      ;
; 0.417 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[7]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.482      ; 1.153      ;
; 0.421 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_snap_reg[6]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a8~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.480      ; 1.155      ;
; 0.423 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[3]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.482      ; 1.159      ;
; 0.423 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[0]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.482      ; 1.159      ;
; 0.424 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[4]                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|altsyncram_aj81:FIFOram|ram_block1a0~porta_datain_reg0          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.485      ; 1.163      ;
; 0.431 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_rj31:auto_generated|a_dpfifo_2q31:dpfifo|cntr_o8b:wr_ptr|counter_reg_bit[5] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_rj31:auto_generated|a_dpfifo_2q31:dpfifo|altsyncram_eg81:FIFOram|ram_block1a0~porta_address_reg0       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.476      ; 1.161      ;
; 0.431 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[1]                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|altsyncram_aj81:FIFOram|ram_block1a0~porta_datain_reg0          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.485      ; 1.170      ;
; 0.431 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp3_snap_reg[4]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a8~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.482      ; 1.167      ;
; 0.433 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cycleBranchTaken                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cycleBranchTaken                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.101      ; 0.746      ;
; 0.433 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cyclePreRead                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cyclePreRead                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.101      ; 0.746      ;
; 0.433 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[16]                                                                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[16]                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.101      ; 0.746      ;
; 0.433 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[2]                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|altsyncram_aj81:FIFOram|ram_block1a0~porta_datain_reg0          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.485      ; 1.172      ;
; 0.433 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[1]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.482      ; 1.169      ;
; 0.434 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Creg                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Creg                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 0.746      ;
; 0.434 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[7]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[7]                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 0.746      ;
; 0.434 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[7]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[7]                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 0.746      ;
; 0.434 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[7]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[7]                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 0.746      ;
; 0.435 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[0]_OTERM269                                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[0]_OTERM269                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.099      ; 0.746      ;
; 0.435 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[7]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[7]                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.099      ; 0.746      ;
; 0.436 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[68]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[68]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.098      ; 0.746      ;
; 0.436 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[6]                                                                                                                                   ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[6]                                                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.098      ; 0.746      ;
; 0.436 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[7]                                                                                                                                   ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[7]                                                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.098      ; 0.746      ;
; 0.436 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[0]                                                                                                                                   ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[0]                                                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.098      ; 0.746      ;
; 0.436 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[3]                                                                                                                                   ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[3]                                                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.098      ; 0.746      ;
; 0.436 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_snap_reg[2]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a8~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.480      ; 1.170      ;
; 0.436 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[4]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.482      ; 1.172      ;
; 0.436 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[0]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.479      ; 1.169      ;
; 0.437 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp3_snap_reg[2]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a8~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.482      ; 1.173      ;
; 0.438 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp3_snap_reg[0]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a8~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.482      ; 1.174      ;
; 0.439 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[5]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a8~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.472      ; 1.165      ;
; 0.441 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[1]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a8~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.482      ; 1.177      ;
; 0.444 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[4]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.482      ; 1.180      ;
; 0.445 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_snap_reg[3]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a8~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.480      ; 1.179      ;
; 0.445 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_snap_reg[1]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a8~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.482      ; 1.181      ;
; 0.446 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[6]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.482      ; 1.182      ;
; 0.447 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_snap_reg[7]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a8~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.482      ; 1.183      ;
; 0.448 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|cntr_o8b:wr_ptr|counter_reg_bit[6]   ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|altsyncram_aj81:FIFOram|ram_block1a0~porta_address_reg0         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.476      ; 1.178      ;
; 0.448 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[2]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.479      ; 1.181      ;
; 0.449 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[2]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.482      ; 1.185      ;
; 0.449 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[7]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.486      ; 1.189      ;
; 0.452 ; sdram_statemachine:sdram_adaptor|sdram_request_reg                                                                                                                                                          ; sdram_statemachine:sdram_adaptor|sdram_request_reg                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[2]                                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[2]                                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[13]                                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[13]                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[14]                                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[14]                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|cfg_enable                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|cfg_enable                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|serin_clock_reg                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|serin_clock_reg                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|delay_line:serout_clock_delay|shift_reg[1]                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|delay_line:serout_clock_delay|shift_reg[1]                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|delay_line:serout_clock_delay|shift_reg[0]                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|delay_line:serout_clock_delay|shift_reg[0]                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[2]                                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[2]                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[0]                                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[0]                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[1]                                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[1]                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[7]                                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[7]                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[4]                                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[4]                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[5]                                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[5]                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[6]                                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[6]                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.082      ; 0.746      ;
; 0.452 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|cntr_8rf:cntr1|counter_reg_bit[6]                                                               ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|altsyncram_v6b1:altsyncram2|ram_block5a0~portb_address_reg0                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.478      ; 1.184      ;
; 0.452 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|cntr_8rf:cntr1|counter_reg_bit[6]                                                               ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|altsyncram_v6b1:altsyncram2|ram_block5a0~porta_address_reg0                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.477      ; 1.183      ;
; 0.453 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]                                                                                                                                                          ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[9]                                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[9]                                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cyclePreIndirect                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cyclePreIndirect                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|nmiReg                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|nmiReg                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[10]                                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[10]                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|use_status_as_ram_address                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|use_status_as_ram_address                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_bitcount_reg[1]                                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_bitcount_reg[1]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_bitcount_reg[2]                                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_bitcount_reg[2]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_bitcount_reg[3]                                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_bitcount_reg[3]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|vector_a2                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|vector_a2                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|oldcycle_state_reg[1]                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|oldcycle_state_reg[1]                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|oldcycle_state_reg[0]                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|oldcycle_state_reg[0]                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_ready_reg                                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_ready_reg                                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[5]                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[5]                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[4]                                                                                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[4]                                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[4]                                                                                                                                                           ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[4]                                                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[1]                                                                                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[1]                                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[5]                                                                                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[5]                                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[45]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[45]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[6]                                                                                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[6]                                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_add_sp2                                                                                                                                      ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_add_sp2                                                                                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[31]                                                                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[31]                                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_resync                                                                                                                                       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_resync                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_load2                                                                                                                                        ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_load2                                                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|mosi~reg0                                                                                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|mosi~reg0                                                                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[13]                                                                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[13]                                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|idim_r                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|idim_r                                                                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_loadb2                                                                                                                                       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_loadb2                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[28]                                                                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[28]                                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                            ;
+-------+---------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                     ; To Node                                                       ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.453 ; sdram_statemachine:sdram_adaptor|reply_reg                    ; sdram_statemachine:sdram_adaptor|reply_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.509 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 0.802      ;
; 0.582 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 0.875      ;
; 0.583 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 0.876      ;
; 0.736 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.029      ;
; 0.739 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.032      ;
; 0.739 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.032      ;
; 0.739 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.032      ;
; 0.740 ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.033      ;
; 0.741 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.034      ;
; 0.741 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.034      ;
; 0.744 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.037      ;
; 0.745 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.038      ;
; 0.745 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.038      ;
; 0.748 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.041      ;
; 0.748 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.041      ;
; 0.748 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.041      ;
; 0.748 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.041      ;
; 0.748 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.041      ;
; 0.750 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.043      ;
; 0.755 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.048      ;
; 0.756 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.049      ;
; 0.758 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.051      ;
; 0.761 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.054      ;
; 0.763 ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.056      ;
; 0.770 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.063      ;
; 0.771 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.064      ;
; 0.772 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.065      ;
; 0.774 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.067      ;
; 0.774 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.067      ;
; 0.777 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.070      ;
; 0.778 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.071      ;
; 0.781 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.074      ;
; 0.787 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.080      ;
; 0.795 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.088      ;
; 0.802 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.095      ;
; 0.899 ; sdram_statemachine:sdram_adaptor|request_sreg                 ; sdram_statemachine:sdram_adaptor|reply_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.185      ; 1.315      ;
; 0.963 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.256      ;
; 0.972 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.265      ;
; 0.982 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.275      ;
; 0.983 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.276      ;
; 0.984 ; sdram_statemachine:sdram_adaptor|dqm_mask_sreg[0]             ; sdram_statemachine:sdram_adaptor|data_out_reg[1]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.185      ; 1.400      ;
; 0.985 ; sdram_statemachine:sdram_adaptor|dqm_mask_sreg[0]             ; sdram_statemachine:sdram_adaptor|data_out_reg[4]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.185      ; 1.401      ;
; 1.060 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.353      ;
; 1.091 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.384      ;
; 1.093 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.386      ;
; 1.093 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.386      ;
; 1.099 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.392      ;
; 1.099 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.392      ;
; 1.100 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.393      ;
; 1.100 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.393      ;
; 1.101 ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.394      ;
; 1.102 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.395      ;
; 1.102 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.395      ;
; 1.102 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.395      ;
; 1.102 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.395      ;
; 1.108 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.401      ;
; 1.109 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.402      ;
; 1.109 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.402      ;
; 1.109 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.402      ;
; 1.109 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.402      ;
; 1.111 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.404      ;
; 1.111 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.404      ;
; 1.111 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.404      ;
; 1.115 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.408      ;
; 1.117 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.410      ;
; 1.118 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.411      ;
; 1.118 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.411      ;
; 1.118 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.411      ;
; 1.118 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.411      ;
; 1.119 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.412      ;
; 1.120 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.413      ;
; 1.126 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.419      ;
; 1.126 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.419      ;
; 1.128 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.421      ;
; 1.132 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.425      ;
; 1.133 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.426      ;
; 1.133 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.426      ;
; 1.134 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.427      ;
; 1.135 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.428      ;
; 1.140 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.433      ;
; 1.142 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.435      ;
; 1.142 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.435      ;
; 1.143 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.436      ;
; 1.144 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.437      ;
; 1.148 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.441      ;
; 1.149 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.442      ;
; 1.151 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.444      ;
; 1.157 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.450      ;
; 1.222 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.515      ;
; 1.224 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.517      ;
; 1.224 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.517      ;
; 1.230 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.523      ;
; 1.230 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.523      ;
; 1.231 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.524      ;
; 1.233 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.526      ;
; 1.233 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.526      ;
+-------+---------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'CLOCK_27[0]'                                                                                                                                                           ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                 ; To Node                                                   ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.466 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 0.758      ;
; 0.748 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 1.040      ;
; 0.748 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 1.040      ;
; 0.749 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 1.041      ;
; 1.090 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 1.382      ;
; 1.090 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 1.382      ;
; 1.092 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 1.384      ;
; 1.101 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 1.393      ;
; 1.106 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 1.398      ;
; 1.110 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 1.402      ;
; 1.119 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 1.411      ;
; 1.127 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 1.419      ;
; 1.131 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 1.423      ;
; 1.132 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 1.424      ;
; 1.201 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 1.493      ;
; 1.208 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 1.500      ;
; 1.232 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 1.524      ;
; 1.233 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 1.525      ;
; 1.233 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 1.525      ;
; 1.235 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 1.527      ;
; 1.241 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 1.533      ;
; 1.250 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 1.542      ;
; 1.256 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 1.548      ;
; 1.277 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 1.569      ;
; 1.292 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 1.584      ;
; 1.329 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 1.621      ;
; 1.345 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 1.637      ;
; 1.345 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 1.637      ;
; 1.352 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 1.644      ;
; 1.383 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 1.675      ;
; 1.384 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 1.676      ;
; 1.388 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 1.680      ;
; 1.400 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 1.692      ;
; 1.409 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 1.701      ;
; 1.409 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 1.701      ;
; 1.411 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 1.703      ;
; 1.422 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 1.714      ;
; 1.422 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 1.714      ;
; 1.429 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 1.721      ;
; 1.431 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 1.723      ;
; 1.453 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 1.745      ;
; 1.469 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 1.761      ;
; 1.513 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 1.805      ;
; 1.524 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 1.816      ;
; 1.526 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 1.818      ;
; 1.526 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 1.818      ;
; 1.531 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 1.823      ;
; 1.579 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 1.871      ;
; 1.581 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 1.873      ;
; 1.598 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 1.890      ;
; 1.602 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 1.894      ;
; 1.661 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 1.953      ;
; 1.665 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 1.957      ;
; 1.668 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 1.960      ;
; 1.668 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 1.960      ;
; 1.670 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 1.962      ;
; 1.766 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 2.058      ;
; 1.773 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 2.065      ;
; 1.781 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.080      ; 2.073      ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]'                                                                                                                                                                      ;
+-------+------------------------------------+------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                          ; To Node                            ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------+------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.454 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_rptr[0]     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; user_io:my_user_io|ps2_rptr[1]     ; user_io:my_user_io|ps2_rptr[1]     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_rptr[2]     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; user_io:my_user_io|ps2_tx_state[1] ; user_io:my_user_io|ps2_tx_state[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_tx_state[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; user_io:my_user_io|ps2_tx_byte[7]  ; user_io:my_user_io|ps2_tx_byte[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; user_io:my_user_io|ps2_parity      ; user_io:my_user_io|ps2_parity      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 0.746      ;
; 0.502 ; user_io:my_user_io|ps2_r_inc       ; user_io:my_user_io|ps2_rptr[0]     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 0.794      ;
; 0.502 ; user_io:my_user_io|ps2_r_inc       ; user_io:my_user_io|ps2_rptr[1]     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 0.794      ;
; 0.510 ; user_io:my_user_io|ps2_tx_byte[0]  ; user_io:my_user_io|ps2_parity      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 0.802      ;
; 0.520 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_rptr[2]     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 0.812      ;
; 0.527 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_state[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 0.819      ;
; 0.549 ; user_io:my_user_io|ps2_tx_state[0] ; user_io:my_user_io|ps2_tx_state[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 0.841      ;
; 0.576 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_tx_byte[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 0.868      ;
; 0.576 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_tx_byte[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 0.868      ;
; 0.577 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_tx_byte[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 0.869      ;
; 0.701 ; user_io:my_user_io|ps2_tx_byte[5]  ; user_io:my_user_io|ps2_tx_byte[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 0.993      ;
; 0.701 ; user_io:my_user_io|ps2_tx_byte[4]  ; user_io:my_user_io|ps2_tx_byte[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 0.993      ;
; 0.701 ; user_io:my_user_io|ps2_tx_byte[3]  ; user_io:my_user_io|ps2_tx_byte[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 0.993      ;
; 0.701 ; user_io:my_user_io|ps2_tx_byte[2]  ; user_io:my_user_io|ps2_tx_byte[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 0.993      ;
; 0.702 ; user_io:my_user_io|ps2_tx_byte[6]  ; user_io:my_user_io|ps2_tx_byte[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 0.994      ;
; 0.702 ; user_io:my_user_io|ps2_tx_byte[1]  ; user_io:my_user_io|ps2_tx_byte[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 0.994      ;
; 0.725 ; user_io:my_user_io|ps2_parity      ; user_io:my_user_io|ps2_kbd_data    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.079      ; 1.016      ;
; 0.759 ; user_io:my_user_io|ps2_r_inc       ; user_io:my_user_io|ps2_rptr[2]     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.051      ;
; 0.767 ; user_io:my_user_io|ps2_rptr[1]     ; user_io:my_user_io|ps2_rptr[2]     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.059      ;
; 0.778 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_rptr[1]     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.070      ;
; 0.821 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_state[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.113      ;
; 0.857 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_tx_byte[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.149      ;
; 0.857 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_tx_byte[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.149      ;
; 0.857 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_tx_byte[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.149      ;
; 0.863 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_tx_byte[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.155      ;
; 0.875 ; user_io:my_user_io|ps2_tx_state[0] ; user_io:my_user_io|ps2_tx_state[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.167      ;
; 0.901 ; user_io:my_user_io|ps2_tx_byte[7]  ; user_io:my_user_io|ps2_tx_byte[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.193      ;
; 0.948 ; user_io:my_user_io|Equal5~0_OTERM1 ; user_io:my_user_io|Equal5~0_OTERM1 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.240      ;
; 0.951 ; user_io:my_user_io|Equal5~0_OTERM1 ; user_io:my_user_io|ps2_tx_state[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.243      ;
; 0.992 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_r_inc       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.284      ;
; 0.992 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_tx_byte[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.284      ;
; 1.007 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|Equal5~0_OTERM1 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.299      ;
; 1.025 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_tx_state[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.317      ;
; 1.047 ; user_io:my_user_io|ps2_tx_state[1] ; user_io:my_user_io|ps2_tx_state[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.339      ;
; 1.061 ; user_io:my_user_io|Equal5~0_OTERM1 ; user_io:my_user_io|ps2_parity      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 1.354      ;
; 1.082 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|Equal5~0_OTERM1 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.374      ;
; 1.085 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_kbd_data    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.377      ;
; 1.152 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_state[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.444      ;
; 1.153 ; user_io:my_user_io|ps2_kbd_data    ; user_io:my_user_io|ps2_kbd_data    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.445      ;
; 1.181 ; user_io:my_user_io|ps2_tx_state[1] ; user_io:my_user_io|Equal5~0_OTERM1 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.473      ;
; 1.248 ; user_io:my_user_io|ps2_tx_state[0] ; user_io:my_user_io|Equal5~0_OTERM1 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.540      ;
; 1.250 ; user_io:my_user_io|ps2_tx_state[0] ; user_io:my_user_io|ps2_tx_state[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.542      ;
; 1.263 ; user_io:my_user_io|Equal5~0_OTERM1 ; user_io:my_user_io|ps2_tx_byte[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 1.556      ;
; 1.263 ; user_io:my_user_io|Equal5~0_OTERM1 ; user_io:my_user_io|ps2_tx_byte[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 1.556      ;
; 1.263 ; user_io:my_user_io|Equal5~0_OTERM1 ; user_io:my_user_io|ps2_tx_byte[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 1.556      ;
; 1.263 ; user_io:my_user_io|Equal5~0_OTERM1 ; user_io:my_user_io|ps2_tx_byte[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 1.556      ;
; 1.263 ; user_io:my_user_io|Equal5~0_OTERM1 ; user_io:my_user_io|ps2_tx_byte[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 1.556      ;
; 1.263 ; user_io:my_user_io|Equal5~0_OTERM1 ; user_io:my_user_io|ps2_tx_byte[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 1.556      ;
; 1.263 ; user_io:my_user_io|Equal5~0_OTERM1 ; user_io:my_user_io|ps2_tx_byte[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 1.556      ;
; 1.346 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_tx_byte[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.638      ;
; 1.367 ; user_io:my_user_io|ps2_tx_byte[0]  ; user_io:my_user_io|ps2_kbd_data    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.079      ; 1.658      ;
; 1.391 ; user_io:my_user_io|ps2_tx_state[0] ; user_io:my_user_io|ps2_kbd_data    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.683      ;
; 1.418 ; user_io:my_user_io|Equal5~0_OTERM1 ; user_io:my_user_io|ps2_kbd_data    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.710      ;
; 1.425 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_kbd_data    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.717      ;
; 1.462 ; user_io:my_user_io|ps2_tx_state[0] ; user_io:my_user_io|ps2_tx_state[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.754      ;
; 1.477 ; user_io:my_user_io|Equal5~0_OTERM1 ; user_io:my_user_io|ps2_r_inc       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 1.770      ;
; 1.477 ; user_io:my_user_io|Equal5~0_OTERM1 ; user_io:my_user_io|ps2_tx_byte[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 1.770      ;
; 1.492 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_tx_state[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.784      ;
; 1.524 ; user_io:my_user_io|ps2_tx_state[1] ; user_io:my_user_io|ps2_kbd_data    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.816      ;
; 1.636 ; user_io:my_user_io|ps2_tx_state[1] ; user_io:my_user_io|ps2_tx_state[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.928      ;
; 1.644 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_tx_byte[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.936      ;
; 1.646 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_tx_byte[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.938      ;
; 1.658 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_tx_byte[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.950      ;
; 1.686 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_tx_byte[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.978      ;
; 1.805 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_state[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 2.097      ;
; 1.849 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|Equal5~0_OTERM1 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.079      ; 2.140      ;
; 1.851 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_tx_state[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.079      ; 2.142      ;
; 1.865 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_tx_byte[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 2.157      ;
; 1.953 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_tx_byte[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 2.245      ;
; 2.062 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_kbd_data    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.079      ; 2.353      ;
; 2.141 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_tx_state[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 2.433      ;
; 2.199 ; user_io:my_user_io|ps2_rptr[1]     ; user_io:my_user_io|ps2_tx_byte[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 2.491      ;
; 2.245 ; user_io:my_user_io|ps2_tx_state[1] ; user_io:my_user_io|ps2_tx_state[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 2.537      ;
; 2.323 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_tx_byte[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 2.615      ;
; 2.380 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_byte[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 2.673      ;
; 2.380 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_byte[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 2.673      ;
; 2.380 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_byte[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 2.673      ;
; 2.380 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_byte[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 2.673      ;
; 2.380 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_byte[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 2.673      ;
; 2.380 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_byte[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 2.673      ;
; 2.380 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_byte[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 2.673      ;
; 2.380 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_parity      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 2.673      ;
; 2.463 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_parity      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 2.755      ;
; 2.482 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_r_inc       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 2.774      ;
; 2.489 ; user_io:my_user_io|ps2_rptr[1]     ; user_io:my_user_io|ps2_tx_byte[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 2.781      ;
; 2.673 ; user_io:my_user_io|ps2_rptr[1]     ; user_io:my_user_io|ps2_tx_byte[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 2.965      ;
; 2.689 ; user_io:my_user_io|ps2_tx_state[0] ; user_io:my_user_io|ps2_tx_byte[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 2.982      ;
; 2.689 ; user_io:my_user_io|ps2_tx_state[0] ; user_io:my_user_io|ps2_tx_byte[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 2.982      ;
; 2.689 ; user_io:my_user_io|ps2_tx_state[0] ; user_io:my_user_io|ps2_tx_byte[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 2.982      ;
; 2.689 ; user_io:my_user_io|ps2_tx_state[0] ; user_io:my_user_io|ps2_tx_byte[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 2.982      ;
; 2.689 ; user_io:my_user_io|ps2_tx_state[0] ; user_io:my_user_io|ps2_tx_byte[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 2.982      ;
; 2.689 ; user_io:my_user_io|ps2_tx_state[0] ; user_io:my_user_io|ps2_tx_byte[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 2.982      ;
; 2.689 ; user_io:my_user_io|ps2_tx_state[0] ; user_io:my_user_io|ps2_tx_byte[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 2.982      ;
; 2.689 ; user_io:my_user_io|ps2_tx_state[0] ; user_io:my_user_io|ps2_parity      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 2.982      ;
+-------+------------------------------------+------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                  ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 9.627 ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -6.853       ; -1.747     ; 1.138      ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: 'CLOCK_27[0]'                                                                                                                                                                                                                              ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------+-----------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                              ; To Node                                                   ; Launch Clock                                                          ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------+-----------------------------------------------------------------------+-------------+--------------+------------+------------+
; -1.239 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.597      ; 4.906      ;
; -1.239 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.597      ; 4.906      ;
; -1.239 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.597      ; 4.906      ;
; -1.239 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.597      ; 4.906      ;
; -1.239 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.597      ; 4.906      ;
; -1.239 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.597      ; 4.906      ;
; -1.239 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.597      ; 4.906      ;
; -1.239 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.597      ; 4.906      ;
; -1.239 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.597      ; 4.906      ;
; -1.110 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.593      ; 4.773      ;
; -1.110 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.593      ; 4.773      ;
; -1.110 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.593      ; 4.773      ;
; -1.110 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.593      ; 4.773      ;
; -1.110 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.593      ; 4.773      ;
; -1.110 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.593      ; 4.773      ;
; -1.110 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.593      ; 4.773      ;
; -1.110 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.593      ; 4.773      ;
; -1.110 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.593      ; 4.773      ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------+-----------------------------------------------------------------------+-------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                 ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                              ; To Node                                                       ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 2.099 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.335     ; 6.235      ;
; 2.099 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.334     ; 6.236      ;
; 2.099 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.334     ; 6.236      ;
; 2.099 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.334     ; 6.236      ;
; 2.103 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.401     ; 6.165      ;
; 2.108 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.388     ; 6.173      ;
; 2.108 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.388     ; 6.173      ;
; 2.108 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[15]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.389     ; 6.172      ;
; 2.108 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[14]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.389     ; 6.172      ;
; 2.112 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[9]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.257     ; 6.312      ;
; 2.113 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.382     ; 6.174      ;
; 2.113 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[0]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.398     ; 6.158      ;
; 2.113 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.382     ; 6.174      ;
; 2.118 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[7]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.254     ; 6.309      ;
; 2.118 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[8]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.254     ; 6.309      ;
; 2.120 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.393     ; 6.156      ;
; 2.120 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.393     ; 6.156      ;
; 2.120 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.375     ; 6.174      ;
; 2.120 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.375     ; 6.174      ;
; 2.123 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[4]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.251     ; 6.307      ;
; 2.124 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[5]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.253     ; 6.304      ;
; 2.124 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[6]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.259     ; 6.298      ;
; 2.125 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[11]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.260     ; 6.296      ;
; 2.131 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|we_n_reg                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.209     ; 6.341      ;
; 2.131 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ldqm_reg                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.209     ; 6.341      ;
; 2.131 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[3]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.208     ; 6.342      ;
; 2.132 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.207     ; 6.342      ;
; 2.132 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.207     ; 6.342      ;
; 2.132 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.207     ; 6.342      ;
; 2.132 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.208     ; 6.341      ;
; 2.132 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ba_reg[0]                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.211     ; 6.338      ;
; 2.132 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ba_reg[1]                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.210     ; 6.339      ;
; 2.132 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ras_n_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.211     ; 6.338      ;
; 2.132 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cas_n_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.210     ; 6.339      ;
; 2.132 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[0]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.211     ; 6.338      ;
; 2.132 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[1]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.209     ; 6.340      ;
; 2.132 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[2]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.208     ; 6.341      ;
; 2.132 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[10]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.210     ; 6.339      ;
; 2.134 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|udqm_reg                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.268     ; 6.279      ;
; 2.136 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[1]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.274     ; 6.271      ;
; 2.141 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.261     ; 6.279      ;
; 2.141 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[13]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.261     ; 6.279      ;
; 2.141 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.262     ; 6.278      ;
; 2.141 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.262     ; 6.278      ;
; 2.146 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[0]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.271     ; 6.264      ;
; 2.146 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.255     ; 6.280      ;
; 2.146 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[9]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.255     ; 6.280      ;
; 2.153 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.266     ; 6.262      ;
; 2.153 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.266     ; 6.262      ;
; 2.153 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.248     ; 6.280      ;
; 2.153 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.248     ; 6.280      ;
; 2.334 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.223     ; 6.088      ;
; 2.334 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_5   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.223     ; 6.088      ;
; 2.334 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_6   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.223     ; 6.088      ;
; 2.334 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_7   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.224     ; 6.087      ;
; 2.338 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.290     ; 6.017      ;
; 2.343 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.277     ; 6.025      ;
; 2.343 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.277     ; 6.025      ;
; 2.343 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.278     ; 6.024      ;
; 2.343 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.278     ; 6.024      ;
; 2.348 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.287     ; 6.010      ;
; 2.348 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.271     ; 6.026      ;
; 2.348 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.271     ; 6.026      ;
; 2.355 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.282     ; 6.008      ;
; 2.355 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.282     ; 6.008      ;
; 2.355 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.264     ; 6.026      ;
; 2.355 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.264     ; 6.026      ;
; 2.652 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.206     ; 5.953      ;
; 2.652 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.206     ; 5.953      ;
; 2.652 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.206     ; 5.953      ;
; 2.652 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.206     ; 5.953      ;
; 2.652 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.206     ; 5.953      ;
; 2.652 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.206     ; 5.953      ;
; 2.652 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.206     ; 5.953      ;
; 2.652 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.206     ; 5.953      ;
; 2.652 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.206     ; 5.953      ;
; 2.652 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.206     ; 5.953      ;
; 2.652 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.206     ; 5.953      ;
; 2.659 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.197     ; 5.955      ;
; 2.659 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.197     ; 5.955      ;
; 2.659 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.197     ; 5.955      ;
; 2.659 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.197     ; 5.955      ;
; 2.659 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.197     ; 5.955      ;
; 2.659 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.197     ; 5.955      ;
; 2.659 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.197     ; 5.955      ;
; 2.659 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.197     ; 5.955      ;
; 2.659 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.197     ; 5.955      ;
; 2.659 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.197     ; 5.955      ;
; 2.659 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.197     ; 5.955      ;
; 2.659 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.197     ; 5.955      ;
; 2.659 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.197     ; 5.955      ;
; 2.659 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.197     ; 5.955      ;
; 2.665 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[28]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.194     ; 5.952      ;
; 2.665 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[20]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.199     ; 5.947      ;
; 2.665 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[0]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.194     ; 5.952      ;
; 2.665 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[3]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.194     ; 5.952      ;
; 2.665 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[1]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.194     ; 5.952      ;
; 2.665 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[4]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.194     ; 5.952      ;
; 2.665 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[5]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.194     ; 5.952      ;
; 2.665 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[7]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.194     ; 5.952      ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                          ;
+--------+------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                              ; To Node                                                                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 10.098 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[3]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.197     ; 7.327      ;
; 10.098 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[0]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.197     ; 7.327      ;
; 10.098 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_input_reg[7]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.197     ; 7.327      ;
; 10.098 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[4]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.197     ; 7.327      ;
; 10.099 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[3]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.080     ; 7.443      ;
; 10.099 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[0]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.080     ; 7.443      ;
; 10.099 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_input_reg[7]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.080     ; 7.443      ;
; 10.099 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[4]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.080     ; 7.443      ;
; 10.109 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|keycode_latch_reg[4] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.185     ; 7.328      ;
; 10.110 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|keycode_latch_reg[4] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.068     ; 7.444      ;
; 10.133 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[14]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.094     ; 7.395      ;
; 10.133 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[22]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.094     ; 7.395      ;
; 10.133 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[15]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.094     ; 7.395      ;
; 10.133 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[23]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.094     ; 7.395      ;
; 10.133 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[30]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.094     ; 7.395      ;
; 10.133 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[31]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.094     ; 7.395      ;
; 10.150 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[14]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.193     ; 7.279      ;
; 10.150 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[22]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.193     ; 7.279      ;
; 10.150 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[15]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.193     ; 7.279      ;
; 10.150 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[23]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.193     ; 7.279      ;
; 10.150 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[30]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.193     ; 7.279      ;
; 10.150 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[31]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.193     ; 7.279      ;
; 10.158 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.176     ; 7.288      ;
; 10.158 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[2]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.176     ; 7.288      ;
; 10.158 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[13]                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.176     ; 7.288      ;
; 10.158 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[15]                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.176     ; 7.288      ;
; 10.158 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[14]                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.176     ; 7.288      ;
; 10.158 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.176     ; 7.288      ;
; 10.158 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.176     ; 7.288      ;
; 10.158 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.176     ; 7.288      ;
; 10.159 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.059     ; 7.404      ;
; 10.159 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[2]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.059     ; 7.404      ;
; 10.159 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[13]                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.059     ; 7.404      ;
; 10.159 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[15]                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.059     ; 7.404      ;
; 10.159 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[14]                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.059     ; 7.404      ;
; 10.159 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.059     ; 7.404      ;
; 10.159 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.059     ; 7.404      ;
; 10.159 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.059     ; 7.404      ;
; 10.217 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[3]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.080     ; 7.325      ;
; 10.217 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[0]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.080     ; 7.325      ;
; 10.217 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_input_reg[7]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.080     ; 7.325      ;
; 10.217 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[4]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.080     ; 7.325      ;
; 10.228 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|keycode_latch_reg[4] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.068     ; 7.326      ;
; 10.251 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[14]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.094     ; 7.277      ;
; 10.251 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[22]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.094     ; 7.277      ;
; 10.251 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[15]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.094     ; 7.277      ;
; 10.251 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[23]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.094     ; 7.277      ;
; 10.251 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[30]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.094     ; 7.277      ;
; 10.251 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[31]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.094     ; 7.277      ;
; 10.277 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.059     ; 7.286      ;
; 10.277 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[2]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.059     ; 7.286      ;
; 10.277 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[13]                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.059     ; 7.286      ;
; 10.277 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[15]                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.059     ; 7.286      ;
; 10.277 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[14]                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.059     ; 7.286      ;
; 10.277 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.059     ; 7.286      ;
; 10.277 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.059     ; 7.286      ;
; 10.277 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.059     ; 7.286      ;
; 10.550 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|skctl_reg[1]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.104     ; 6.968      ;
; 10.550 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|porta_control_reg[4]                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.109     ; 6.963      ;
; 10.550 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|cb2_edge_reg                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.109     ; 6.963      ;
; 10.550 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_holding_reg[0]                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.101     ; 6.971      ;
; 10.550 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_holding_reg[1]                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.101     ; 6.971      ;
; 10.550 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_holding_reg[2]                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.101     ; 6.971      ;
; 10.550 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_holding_reg[3]                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.101     ; 6.971      ;
; 10.550 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_holding_reg[4]                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.101     ; 6.971      ;
; 10.550 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_holding_reg[5]                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.101     ; 6.971      ;
; 10.550 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_holding_reg[6]                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.101     ; 6.971      ;
; 10.550 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_holding_reg[7]                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.101     ; 6.971      ;
; 10.550 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_shift_reg[8]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.101     ; 6.971      ;
; 10.550 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_shift_reg[7]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.101     ; 6.971      ;
; 10.550 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_shift_reg[6]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.101     ; 6.971      ;
; 10.550 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_shift_reg[5]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.101     ; 6.971      ;
; 10.550 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_shift_reg[4]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.101     ; 6.971      ;
; 10.550 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_shift_reg[3]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.101     ; 6.971      ;
; 10.550 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_shift_reg[2]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.101     ; 6.971      ;
; 10.550 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_shift_reg[1]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.101     ; 6.971      ;
; 10.550 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|irqen_reg[7]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.104     ; 6.968      ;
; 10.550 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|irqa_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.109     ; 6.963      ;
; 10.550 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|irqb_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.109     ; 6.963      ;
; 10.550 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|porta_control_reg[3]                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.109     ; 6.963      ;
; 10.550 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_control_reg[3]                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.109     ; 6.963      ;
; 10.550 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_control_reg[5]                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.109     ; 6.963      ;
; 10.550 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|porta_control_reg[5]                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.109     ; 6.963      ;
; 10.550 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|CA2_output_reg                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.109     ; 6.963      ;
; 10.550 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|CB2_output_reg                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.109     ; 6.963      ;
; 10.550 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|noise_large_reg[0]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.100     ; 6.972      ;
; 10.550 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audc3_reg[5]                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.100     ; 6.972      ;
; 10.550 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audc3_reg[6]                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.100     ; 6.972      ;
; 10.550 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|noise_large_reg[1]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.100     ; 6.972      ;
; 10.550 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|noise_large_reg[2]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.100     ; 6.972      ;
; 10.550 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|noise_4_reg[2]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.100     ; 6.972      ;
; 10.550 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audc3_reg[7]                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.100     ; 6.972      ;
; 10.550 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|noise_5_reg[2]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.100     ; 6.972      ;
; 10.551 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|skctl_reg[0]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.115     ; 6.956      ;
; 10.551 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pot0_reg[4]                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.109     ; 6.962      ;
; 10.551 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|serin_reg[4]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.109     ; 6.962      ;
; 10.551 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|bincnt_reg[0]        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.115     ; 6.956      ;
; 10.551 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|bincnt_reg[1]        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.115     ; 6.956      ;
; 10.551 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|bincnt_reg[2]        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.115     ; 6.956      ;
; 10.551 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|bincnt_reg[3]        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.115     ; 6.956      ;
+--------+------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: 'CLOCK_27[0]'                                                                                                                                                                                                                               ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------+-----------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                              ; To Node                                                   ; Launch Clock                                                          ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------+-----------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.423 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 4.519      ; 4.427      ;
; -0.423 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 4.519      ; 4.427      ;
; -0.423 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 4.519      ; 4.427      ;
; -0.423 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 4.519      ; 4.427      ;
; -0.423 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 4.519      ; 4.427      ;
; -0.423 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 4.519      ; 4.427      ;
; -0.423 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 4.519      ; 4.427      ;
; -0.423 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 4.519      ; 4.427      ;
; -0.422 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 4.519      ; 4.428      ;
; -0.284 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 4.523      ; 4.570      ;
; -0.284 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 4.523      ; 4.570      ;
; -0.284 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 4.523      ; 4.570      ;
; -0.284 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 4.523      ; 4.570      ;
; -0.284 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 4.523      ; 4.570      ;
; -0.284 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 4.523      ; 4.570      ;
; -0.284 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 4.523      ; 4.570      ;
; -0.284 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 4.523      ; 4.570      ;
; -0.283 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 4.523      ; 4.571      ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------+-----------------------------------------------------------------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                         ; To Node                                                                                                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 1.688 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|dffe4                                                                 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|altsyncram_v6b1:altsyncram2|ram_block5a0                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.431      ; 2.330      ;
; 2.019 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a55 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.399      ; 2.629      ;
; 2.019 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a54 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.399      ; 2.629      ;
; 2.019 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a53 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.399      ; 2.629      ;
; 2.019 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a52 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.399      ; 2.629      ;
; 2.019 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a51 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.399      ; 2.629      ;
; 2.019 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a50 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.399      ; 2.629      ;
; 2.019 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a49 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.399      ; 2.629      ;
; 2.019 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a48 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.399      ; 2.629      ;
; 2.019 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a39 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.399      ; 2.629      ;
; 2.019 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a38 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.399      ; 2.629      ;
; 2.019 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a37 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.399      ; 2.629      ;
; 2.019 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a36 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.399      ; 2.629      ;
; 2.019 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a35 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.399      ; 2.629      ;
; 2.019 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a34 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.399      ; 2.629      ;
; 2.019 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a33 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.399      ; 2.629      ;
; 2.019 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a32 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.399      ; 2.629      ;
; 2.019 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a31 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.399      ; 2.629      ;
; 2.019 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a30 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.399      ; 2.629      ;
; 2.019 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a29 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.399      ; 2.629      ;
; 2.019 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a28 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.399      ; 2.629      ;
; 2.019 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a23 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.399      ; 2.629      ;
; 2.019 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a22 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.399      ; 2.629      ;
; 2.019 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a21 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.399      ; 2.629      ;
; 2.019 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a20 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.399      ; 2.629      ;
; 2.019 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a19 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.399      ; 2.629      ;
; 2.019 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a18 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.399      ; 2.629      ;
; 2.019 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a17 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.399      ; 2.629      ;
; 2.019 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a16 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.399      ; 2.629      ;
; 2.019 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a7  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.399      ; 2.629      ;
; 2.019 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a6  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.399      ; 2.629      ;
; 2.019 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a5  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.399      ; 2.629      ;
; 2.019 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a4  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.399      ; 2.629      ;
; 2.019 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a3  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.399      ; 2.629      ;
; 2.019 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a2  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.399      ; 2.629      ;
; 2.019 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a1  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.399      ; 2.629      ;
; 2.019 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.399      ; 2.629      ;
; 2.329 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a63 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 2.929      ;
; 2.329 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a62 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 2.929      ;
; 2.329 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a61 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 2.929      ;
; 2.329 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a60 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 2.929      ;
; 2.329 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a59 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 2.929      ;
; 2.329 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a58 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 2.929      ;
; 2.329 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a57 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 2.929      ;
; 2.329 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a56 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 2.929      ;
; 2.329 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a47 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 2.929      ;
; 2.329 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a46 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 2.929      ;
; 2.329 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a45 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 2.929      ;
; 2.329 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a44 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 2.929      ;
; 2.329 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a43 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 2.929      ;
; 2.329 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a42 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 2.929      ;
; 2.329 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a41 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 2.929      ;
; 2.329 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a40 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 2.929      ;
; 2.329 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a27 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 2.929      ;
; 2.329 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a26 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 2.929      ;
; 2.329 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a25 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 2.929      ;
; 2.329 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a24 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 2.929      ;
; 2.329 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a15 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 2.929      ;
; 2.329 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a14 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 2.929      ;
; 2.329 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a13 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 2.929      ;
; 2.329 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a12 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 2.929      ;
; 2.329 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a11 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 2.929      ;
; 2.329 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a10 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 2.929      ;
; 2.329 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a9  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 2.929      ;
; 2.329 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a8  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 2.929      ;
; 3.494 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[1]                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.693      ; 4.399      ;
; 3.497 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[25]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.687      ; 4.396      ;
; 3.525 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[21]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.678      ; 4.415      ;
; 3.525 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[18]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.678      ; 4.415      ;
; 3.525 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[22]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.678      ; 4.415      ;
; 3.530 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[6]                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.675      ; 4.417      ;
; 3.551 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[15]                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.661      ; 4.424      ;
; 3.564 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[10]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.638      ; 4.414      ;
; 3.564 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[13]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.640      ; 4.416      ;
; 3.564 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[14]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.638      ; 4.414      ;
; 3.564 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[11]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.640      ; 4.416      ;
; 3.565 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[23]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.639      ; 4.416      ;
; 3.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[13]                                                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.631      ; 4.419      ;
; 3.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[15]                                                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.631      ; 4.419      ;
; 3.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[14]                                                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.631      ; 4.419      ;
; 3.581 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[0]                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.632      ; 4.425      ;
; 3.588 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[0]                                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.617      ; 4.417      ;
; 3.731 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[25]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.596      ; 4.539      ;
; 3.746 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[1]                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.584      ; 4.542      ;
; 3.777 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[21]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.569      ; 4.558      ;
; 3.777 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[18]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.569      ; 4.558      ;
; 3.777 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[22]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.569      ; 4.558      ;
; 3.782 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[6]                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.566      ; 4.560      ;
; 3.803 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[15]                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.552      ; 4.567      ;
; 3.810 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[13]                                                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.540      ; 4.562      ;
; 3.810 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[15]                                                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.540      ; 4.562      ;
; 3.810 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[14]                                                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.540      ; 4.562      ;
; 3.816 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[10]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.529      ; 4.557      ;
; 3.816 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[13]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.531      ; 4.559      ;
; 3.816 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[14]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.529      ; 4.557      ;
; 3.816 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[11]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.531      ; 4.559      ;
; 3.817 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[23]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.530      ; 4.559      ;
; 3.822 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[0]                                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.526      ; 4.560      ;
; 3.833 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[0]                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.523      ; 4.568      ;
; 3.950 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[20]                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.655      ; 4.817      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                  ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                              ; To Node                                                       ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 4.888 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cke_reg                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.190      ; 5.309      ;
; 4.890 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.201      ; 5.322      ;
; 4.890 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.201      ; 5.322      ;
; 4.890 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.201      ; 5.322      ;
; 4.890 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.201      ; 5.322      ;
; 4.890 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.201      ; 5.322      ;
; 4.890 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.201      ; 5.322      ;
; 4.890 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.201      ; 5.322      ;
; 4.890 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.201      ; 5.322      ;
; 4.890 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.201      ; 5.322      ;
; 4.890 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.201      ; 5.322      ;
; 4.890 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.201      ; 5.322      ;
; 4.890 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|reply_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.202      ; 5.323      ;
; 4.890 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.202      ; 5.323      ;
; 4.890 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.201      ; 5.322      ;
; 4.890 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.202      ; 5.323      ;
; 4.890 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.202      ; 5.323      ;
; 4.895 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[23]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 5.301      ;
; 4.895 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[25]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 5.301      ;
; 4.895 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[30]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 5.301      ;
; 4.895 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[24]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 5.301      ;
; 4.895 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[22]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 5.297      ;
; 4.895 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[29]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 5.301      ;
; 4.895 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[16]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 5.297      ;
; 4.895 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[17]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 5.297      ;
; 4.898 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[28]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.192      ; 5.321      ;
; 4.898 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[0]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.193      ; 5.322      ;
; 4.898 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[3]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.193      ; 5.322      ;
; 4.898 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[1]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.193      ; 5.322      ;
; 4.898 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[4]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.193      ; 5.322      ;
; 4.898 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[5]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.193      ; 5.322      ;
; 4.898 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[7]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.193      ; 5.322      ;
; 4.898 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[2]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.193      ; 5.322      ;
; 4.898 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[6]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.193      ; 5.322      ;
; 4.898 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[15]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.193      ; 5.322      ;
; 4.898 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[13]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.193      ; 5.322      ;
; 4.898 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[10]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.193      ; 5.322      ;
; 4.898 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[31]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.192      ; 5.321      ;
; 4.898 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[8]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.193      ; 5.322      ;
; 4.898 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[14]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.193      ; 5.322      ;
; 4.898 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[26]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.192      ; 5.321      ;
; 4.898 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[27]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.192      ; 5.321      ;
; 4.898 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[12]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.193      ; 5.322      ;
; 4.898 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[9]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.193      ; 5.322      ;
; 4.898 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[11]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.193      ; 5.322      ;
; 4.899 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[20]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.187      ; 5.317      ;
; 4.899 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[21]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.187      ; 5.317      ;
; 4.899 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[18]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.187      ; 5.317      ;
; 4.899 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[19]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.187      ; 5.317      ;
; 4.903 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.190      ; 5.324      ;
; 4.903 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.190      ; 5.324      ;
; 4.903 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.190      ; 5.324      ;
; 4.903 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.190      ; 5.324      ;
; 4.903 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.190      ; 5.324      ;
; 4.903 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.190      ; 5.324      ;
; 4.903 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.190      ; 5.324      ;
; 4.903 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.190      ; 5.324      ;
; 4.903 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.190      ; 5.324      ;
; 4.903 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.190      ; 5.324      ;
; 4.903 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.190      ; 5.324      ;
; 4.903 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.190      ; 5.324      ;
; 4.903 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.190      ; 5.324      ;
; 4.903 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.190      ; 5.324      ;
; 4.909 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.181      ; 5.321      ;
; 4.909 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.181      ; 5.321      ;
; 4.909 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.181      ; 5.321      ;
; 4.909 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.181      ; 5.321      ;
; 4.909 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.181      ; 5.321      ;
; 4.909 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.181      ; 5.321      ;
; 4.909 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.181      ; 5.321      ;
; 4.909 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.181      ; 5.321      ;
; 4.909 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.181      ; 5.321      ;
; 4.909 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.181      ; 5.321      ;
; 4.909 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.181      ; 5.321      ;
; 5.097 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_6   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 5.428      ;
; 5.098 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 5.429      ;
; 5.098 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_5   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 5.429      ;
; 5.098 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_7   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 5.428      ;
; 5.125 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.107      ; 5.395      ;
; 5.125 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.107      ; 5.395      ;
; 5.127 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.126      ; 5.416      ;
; 5.127 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.126      ; 5.416      ;
; 5.131 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.102      ; 5.396      ;
; 5.134 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.118      ; 5.415      ;
; 5.134 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.118      ; 5.415      ;
; 5.139 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.112      ; 5.414      ;
; 5.139 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.112      ; 5.414      ;
; 5.139 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.111      ; 5.413      ;
; 5.139 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.111      ; 5.413      ;
; 5.147 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.098      ; 5.408      ;
; 5.454 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.184      ; 5.783      ;
; 5.454 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ba_reg[1]                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.181      ; 5.780      ;
; 5.454 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cas_n_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.181      ; 5.780      ;
; 5.454 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[2]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.183      ; 5.782      ;
; 5.454 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[10]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.181      ; 5.780      ;
; 5.455 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.184      ; 5.784      ;
; 5.455 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.184      ; 5.784      ;
; 5.455 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.183      ; 5.783      ;
; 5.455 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ba_reg[0]                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 5.780      ;
; 5.455 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ras_n_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 5.780      ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                            ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                 ; Clock Edge ; Target                                                        ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------+
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cke_reg                      ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[16]             ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[17]             ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[22]             ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[23]             ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[24]             ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[25]             ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[29]             ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[30]             ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ;
; 4.097 ; 4.317        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[0]              ;
; 4.097 ; 4.317        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[10]             ;
; 4.097 ; 4.317        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[11]             ;
; 4.097 ; 4.317        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[12]             ;
; 4.097 ; 4.317        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[13]             ;
; 4.097 ; 4.317        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[14]             ;
; 4.097 ; 4.317        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[15]             ;
; 4.097 ; 4.317        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[1]              ;
; 4.097 ; 4.317        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[26]             ;
; 4.097 ; 4.317        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[27]             ;
; 4.097 ; 4.317        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[28]             ;
; 4.097 ; 4.317        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[2]              ;
; 4.097 ; 4.317        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[31]             ;
; 4.097 ; 4.317        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[3]              ;
; 4.097 ; 4.317        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[4]              ;
; 4.097 ; 4.317        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[5]              ;
; 4.097 ; 4.317        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[6]              ;
; 4.097 ; 4.317        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[7]              ;
; 4.097 ; 4.317        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[8]              ;
; 4.097 ; 4.317        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[9]              ;
; 4.098 ; 4.318        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[18]             ;
; 4.098 ; 4.318        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[19]             ;
; 4.098 ; 4.318        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[20]             ;
; 4.098 ; 4.318        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[21]             ;
; 4.098 ; 4.318        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ;
; 4.098 ; 4.318        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ;
; 4.098 ; 4.318        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ;
; 4.098 ; 4.318        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ;
; 4.098 ; 4.318        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ;
; 4.098 ; 4.318        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ;
; 4.098 ; 4.318        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ;
; 4.098 ; 4.318        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ;
; 4.098 ; 4.318        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ;
; 4.098 ; 4.318        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ;
; 4.098 ; 4.318        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ;
; 4.098 ; 4.318        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ;
; 4.098 ; 4.318        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|reply_reg                    ;
; 4.098 ; 4.318        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ;
; 4.098 ; 4.318        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ;
; 4.098 ; 4.318        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ;
; 4.200 ; 4.358        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[10]                ;
; 4.200 ; 4.358        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[11]                ;
; 4.200 ; 4.358        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10  ;
; 4.200 ; 4.358        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11  ;
; 4.202 ; 4.360        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[8]                 ;
; 4.202 ; 4.360        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[9]                 ;
; 4.202 ; 4.360        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8   ;
; 4.202 ; 4.360        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9   ;
; 4.205 ; 4.358        ; 0.153          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[11]                 ;
; 4.205 ; 4.358        ; 0.153          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[5]                  ;
; 4.205 ; 4.358        ; 0.153          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[7]                  ;
; 4.205 ; 4.358        ; 0.153          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[8]                  ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[12]                ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[13]                ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[1]                 ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[2]                 ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[3]                 ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1   ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12  ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13  ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2   ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3   ;
; 4.206 ; 4.359        ; 0.153          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[10]                 ;
; 4.206 ; 4.359        ; 0.153          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[1]                  ;
; 4.206 ; 4.359        ; 0.153          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[2]                  ;
; 4.206 ; 4.359        ; 0.153          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|ba_reg[0]                    ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                    ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                 ; Clock Edge ; Target                                                                                                                                ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+
; 4.224 ; 4.368        ; 0.144          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 4.316 ; 4.440        ; 0.124          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 4.368 ; 4.368        ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 4.440 ; 4.440        ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                        ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                 ; Clock Edge ; Target                                                                                                                                                    ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; 8.373 ; 8.774        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[0] ;
; 8.373 ; 8.774        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[1] ;
; 8.373 ; 8.774        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[2] ;
; 8.373 ; 8.774        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[3] ;
; 8.373 ; 8.774        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[4] ;
; 8.373 ; 8.774        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[10]      ;
; 8.373 ; 8.774        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[11]      ;
; 8.373 ; 8.774        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[12]      ;
; 8.373 ; 8.774        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[13]      ;
; 8.373 ; 8.774        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[14]      ;
; 8.373 ; 8.774        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[15]      ;
; 8.373 ; 8.774        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[16]      ;
; 8.373 ; 8.774        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[17]      ;
; 8.373 ; 8.774        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[18]      ;
; 8.373 ; 8.774        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[19]      ;
; 8.373 ; 8.774        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[20]      ;
; 8.373 ; 8.774        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[5]       ;
; 8.373 ; 8.774        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[6]       ;
; 8.373 ; 8.774        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[7]       ;
; 8.373 ; 8.774        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[8]       ;
; 8.373 ; 8.774        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[9]       ;
; 8.426 ; 8.827        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[0] ;
; 8.426 ; 8.827        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[1] ;
; 8.426 ; 8.827        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[2] ;
; 8.426 ; 8.827        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[3] ;
; 8.426 ; 8.827        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[4] ;
; 8.426 ; 8.827        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[10]      ;
; 8.426 ; 8.827        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[11]      ;
; 8.426 ; 8.827        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[12]      ;
; 8.426 ; 8.827        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[13]      ;
; 8.426 ; 8.827        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[14]      ;
; 8.426 ; 8.827        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[15]      ;
; 8.426 ; 8.827        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[16]      ;
; 8.426 ; 8.827        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[17]      ;
; 8.426 ; 8.827        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[18]      ;
; 8.426 ; 8.827        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[19]      ;
; 8.426 ; 8.827        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[20]      ;
; 8.426 ; 8.827        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[5]       ;
; 8.426 ; 8.827        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[6]       ;
; 8.426 ; 8.827        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[7]       ;
; 8.426 ; 8.827        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[8]       ;
; 8.426 ; 8.827        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[9]       ;
; 8.472 ; 8.692        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[29]                                   ;
; 8.472 ; 8.692        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[2]                                    ;
; 8.472 ; 8.692        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[34]                                   ;
; 8.472 ; 8.692        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[43]                                   ;
; 8.472 ; 8.692        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[0]                                                                                 ;
; 8.472 ; 8.692        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_32BIT_WRITE_ENABLE_reg                                                                                              ;
; 8.472 ; 8.692        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_8BIT_WRITE_ENABLE_reg                                                                                               ;
; 8.472 ; 8.692        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_READ_reg                                                                                                            ;
; 8.472 ; 8.692        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[0]                                                                                                         ;
; 8.473 ; 8.693        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[10]                                                  ;
; 8.473 ; 8.693        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[7]                                                   ;
; 8.473 ; 8.693        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[8]                                                   ;
; 8.473 ; 8.693        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[9]                                                   ;
; 8.473 ; 8.693        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_destination_reg[1]                                         ;
; 8.473 ; 8.693        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Y[0]~_Duplicate_3                             ;
; 8.474 ; 8.694        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[30]                                   ;
; 8.474 ; 8.694        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[35]                                   ;
; 8.475 ; 8.695        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|PC[4]                                         ;
; 8.475 ; 8.695        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|PC[7]                                         ;
; 8.477 ; 8.697        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[0]                                                                                 ;
; 8.477 ; 8.697        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[3]                                                                                 ;
; 8.477 ; 8.697        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[6]                                                                                 ;
; 8.477 ; 8.697        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[7]                                                                                 ;
; 8.477 ; 8.697        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[13]                                                                     ;
; 8.477 ; 8.697        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[14]                                                                     ;
; 8.477 ; 8.697        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[15]                                                                     ;
; 8.477 ; 8.697        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[0]                                                                                      ;
; 8.477 ; 8.697        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[10]                                                                                     ;
; 8.477 ; 8.697        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[11]                                                                                     ;
; 8.477 ; 8.697        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[12]                                                                                     ;
; 8.477 ; 8.697        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[13]                                                                                     ;
; 8.477 ; 8.697        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[14]                                                                                     ;
; 8.477 ; 8.697        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[15]                                                                                     ;
; 8.477 ; 8.697        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[16]                                                                                     ;
; 8.477 ; 8.697        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[17]                                                                                     ;
; 8.477 ; 8.697        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[8]                                                                                      ;
; 8.477 ; 8.697        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[9]                                                                                      ;
; 8.478 ; 8.698        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|PC[1]                                         ;
; 8.478 ; 8.698        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gractl_reg[1]                                                          ;
; 8.478 ; 8.698        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[5]                                                                                                         ;
; 8.479 ; 8.699        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[0]                                          ;
; 8.479 ; 8.699        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[2]                                          ;
; 8.479 ; 8.699        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[4]                                          ;
; 8.479 ; 8.699        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[7]                                          ;
; 8.479 ; 8.699        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|doReg[1]                                      ;
; 8.479 ; 8.699        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cyclePreWrite                     ;
; 8.480 ; 8.700        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[1]                                          ;
; 8.480 ; 8.700        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[5]                                          ;
; 8.480 ; 8.700        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[6]                                          ;
; 8.480 ; 8.700        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[28]                                   ;
; 8.480 ; 8.700        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[31]                                   ;
; 8.480 ; 8.700        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]~_Duplicate_7                      ;
; 8.480 ; 8.700        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[68]                                                                                                            ;
; 8.480 ; 8.700        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[11]                                                                     ;
; 8.480 ; 8.700        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[12]                                                                     ;
; 8.480 ; 8.700        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[1]                                                                                                         ;
; 8.481 ; 8.701        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[3]                                          ;
; 8.481 ; 8.701        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|PC[13]                                        ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                          ;
+--------+--------------+----------------+------------------+----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                ; Clock Edge ; Target                                                                                     ;
+--------+--------------+----------------+------------------+----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------+
; 16.275 ; 16.275       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 16.280 ; 16.280       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 16.280 ; 16.280       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 16.297 ; 16.297       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 16.297 ; 16.297       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 16.297 ; 16.297       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 16.297 ; 16.297       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]                      ;
; 16.297 ; 16.297       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 16.331 ; 16.331       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 16.331 ; 16.331       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 16.331 ; 16.331       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 16.331 ; 16.331       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]                      ;
; 16.331 ; 16.331       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 16.350 ; 16.350       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 16.350 ; 16.350       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 16.354 ; 16.354       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
+--------+--------------+----------------+------------------+----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK_27[0]'                                                                                                              ;
+--------+--------------+----------------+------------------+-------------+------------+--------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock       ; Clock Edge ; Target                                                                         ;
+--------+--------------+----------------+------------------+-------------+------------+--------------------------------------------------------------------------------+
; 18.274 ; 18.462       ; 0.188          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                      ;
; 18.275 ; 18.463       ; 0.188          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                      ;
; 18.275 ; 18.463       ; 0.188          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                      ;
; 18.275 ; 18.463       ; 0.188          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                      ;
; 18.275 ; 18.463       ; 0.188          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                      ;
; 18.275 ; 18.463       ; 0.188          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                      ;
; 18.275 ; 18.463       ; 0.188          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                      ;
; 18.275 ; 18.463       ; 0.188          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                      ;
; 18.275 ; 18.463       ; 0.188          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                        ;
; 18.352 ; 18.572       ; 0.220          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                      ;
; 18.352 ; 18.572       ; 0.220          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                      ;
; 18.352 ; 18.572       ; 0.220          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                      ;
; 18.352 ; 18.572       ; 0.220          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                      ;
; 18.352 ; 18.572       ; 0.220          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                      ;
; 18.352 ; 18.572       ; 0.220          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                      ;
; 18.352 ; 18.572       ; 0.220          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                      ;
; 18.352 ; 18.572       ; 0.220          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                        ;
; 18.353 ; 18.573       ; 0.220          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                      ;
; 18.362 ; 18.362       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                       ;
; 18.362 ; 18.362       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|observablevcoout             ;
; 18.366 ; 18.366       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 18.366 ; 18.366       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 18.400 ; 18.400       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~input|o                                                            ;
; 18.410 ; 18.410       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~inputclkctrl|inclk[0]                                              ;
; 18.410 ; 18.410       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~inputclkctrl|outclk                                                ;
; 18.414 ; 18.414       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[0]|clk                                          ;
; 18.415 ; 18.415       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[1]|clk                                          ;
; 18.415 ; 18.415       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[2]|clk                                          ;
; 18.415 ; 18.415       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[3]|clk                                          ;
; 18.415 ; 18.415       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[4]|clk                                          ;
; 18.415 ; 18.415       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[5]|clk                                          ;
; 18.415 ; 18.415       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[6]|clk                                          ;
; 18.415 ; 18.415       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[7]|clk                                          ;
; 18.415 ; 18.415       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_toggle_reg|clk                                            ;
; 18.434 ; 18.434       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|inclk[0]                     ;
; 18.438 ; 18.438       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~input|i                                                            ;
; 18.519 ; 18.519       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~input|i                                                            ;
; 18.598 ; 18.598       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 18.602 ; 18.602       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|inclk[0]                     ;
; 18.621 ; 18.621       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[1]|clk                                          ;
; 18.621 ; 18.621       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[2]|clk                                          ;
; 18.621 ; 18.621       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[3]|clk                                          ;
; 18.621 ; 18.621       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[4]|clk                                          ;
; 18.621 ; 18.621       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[5]|clk                                          ;
; 18.621 ; 18.621       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[6]|clk                                          ;
; 18.621 ; 18.621       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[7]|clk                                          ;
; 18.621 ; 18.621       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_toggle_reg|clk                                            ;
; 18.622 ; 18.622       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[0]|clk                                          ;
; 18.626 ; 18.626       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~inputclkctrl|inclk[0]                                              ;
; 18.626 ; 18.626       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~inputclkctrl|outclk                                                ;
; 18.637 ; 18.637       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~input|o                                                            ;
; 18.668 ; 18.668       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 18.668 ; 18.668       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 18.672 ; 18.672       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                       ;
; 18.672 ; 18.672       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|observablevcoout             ;
; 33.037 ; 37.037       ; 4.000          ; Port Rate        ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]                                                                    ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                        ;
+--------+--------------+----------------+------------------+-------------+------------+--------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                           ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                                                                                                                                                                                      ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 40.596 ; 41.626       ; 1.030          ; Low Pulse Width  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ;
; 40.674 ; 41.704       ; 1.030          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[12]                                                                                                                                                      ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[13]                                                                                                                                                      ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[14]                                                                                                                                                      ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[15]                                                                                                                                                      ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[16]                                                                                                                                                      ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[17]                                                                                                                                                      ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[18]                                                                                                                                                      ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[19]                                                                                                                                                      ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[20]                                                                                                                                                      ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[21]                                                                                                                                                      ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[22]                                                                                                                                                      ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[23]                                                                                                                                                      ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[24]                                                                                                                                                      ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C4_ena_state                                                  ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                  ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                    ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_init_state                                           ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                           ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reset_state                                                   ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|areset_init_state_1                           ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                                                                                                                 ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[0]                                                                                                                                                       ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[10]                                                                                                                                                      ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[11]                                                                                                                                                      ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                       ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                       ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                       ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                       ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                       ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                       ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                       ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[8]                                                                                                                                                       ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[9]                                                                                                                                                       ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                               ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                               ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                               ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                               ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                            ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|reset_n_reg                                                                                                                                                                    ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[0]                                                                                                                                        ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[1]                                                                                                                                        ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                                        ;
; 41.362 ; 41.582       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|configupdate2_state                                           ;
; 41.362 ; 41.582       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|configupdate_state                                            ;
; 41.362 ; 41.582       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_data_state                                 ;
; 41.362 ; 41.582       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_ena_state                                  ;
; 41.362 ; 41.582       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_data_state                                 ;
; 41.362 ; 41.582       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_ena_state                                  ;
; 41.362 ; 41.582       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C2_data_state                                 ;
; 41.362 ; 41.582       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C2_ena_state                                  ;
; 41.362 ; 41.582       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_data_state                                 ;
; 41.362 ; 41.582       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_ena_state                                  ;
; 41.362 ; 41.582       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C4_data_state                                 ;
; 41.362 ; 41.582       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|configupdate2_state                           ;
; 41.362 ; 41.582       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|configupdate_state                            ;
; 41.362 ; 41.582       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|tmp_seq_ena_state                             ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C0_data_state                                                 ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C0_ena_state                                                  ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C1_data_state                                                 ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C1_ena_state                                                  ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C2_data_state                                                 ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C2_ena_state                                                  ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C3_data_state                                                 ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C3_ena_state                                                  ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C4_data_state                                                 ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[0] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[1] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[2] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[3] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[4] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[5] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[6] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[7] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[0] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[4] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[0] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[2] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[3] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[4] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[5] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[6] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[7] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_counter_state                                        ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                           ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_seq_data_state                                       ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_seq_ena_state                                        ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|tmp_seq_ena_state                                             ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C4_ena_state                                  ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]'                                                                                                                                                                        ;
+-----------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+
; Slack     ; Actual Width ; Required Width ; Type             ; Clock                                                                 ; Clock Edge ; Target                                                                                                                                ;
+-----------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+
; 44052.506 ; 44052.726    ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ;
; 44052.506 ; 44052.726    ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_kbd_data                                                                                                       ;
; 44052.506 ; 44052.726    ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_parity                                                                                                         ;
; 44052.506 ; 44052.726    ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_r_inc                                                                                                          ;
; 44052.506 ; 44052.726    ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[0]                                                                                                        ;
; 44052.506 ; 44052.726    ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[1]                                                                                                        ;
; 44052.506 ; 44052.726    ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[2]                                                                                                        ;
; 44052.506 ; 44052.726    ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ;
; 44052.506 ; 44052.726    ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ;
; 44052.506 ; 44052.726    ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ;
; 44052.506 ; 44052.726    ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ;
; 44052.506 ; 44052.726    ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ;
; 44052.506 ; 44052.726    ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ;
; 44052.506 ; 44052.726    ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ;
; 44052.506 ; 44052.726    ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ;
; 44052.506 ; 44052.726    ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ;
; 44052.506 ; 44052.726    ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[1]                                                                                                    ;
; 44052.506 ; 44052.726    ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[2]                                                                                                    ;
; 44052.506 ; 44052.726    ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[3]                                                                                                    ;
; 44052.638 ; 44052.782    ; 0.144          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Fall       ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 44052.720 ; 44052.908    ; 0.188          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ;
; 44052.720 ; 44052.908    ; 0.188          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_kbd_data                                                                                                       ;
; 44052.720 ; 44052.908    ; 0.188          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ;
; 44052.720 ; 44052.908    ; 0.188          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[1]                                                                                                    ;
; 44052.720 ; 44052.908    ; 0.188          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[2]                                                                                                    ;
; 44052.720 ; 44052.908    ; 0.188          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[3]                                                                                                    ;
; 44052.721 ; 44052.909    ; 0.188          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_parity                                                                                                         ;
; 44052.721 ; 44052.909    ; 0.188          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_r_inc                                                                                                          ;
; 44052.721 ; 44052.909    ; 0.188          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[0]                                                                                                        ;
; 44052.721 ; 44052.909    ; 0.188          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[1]                                                                                                        ;
; 44052.721 ; 44052.909    ; 0.188          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[2]                                                                                                        ;
; 44052.721 ; 44052.909    ; 0.188          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ;
; 44052.721 ; 44052.909    ; 0.188          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ;
; 44052.721 ; 44052.909    ; 0.188          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ;
; 44052.721 ; 44052.909    ; 0.188          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ;
; 44052.721 ; 44052.909    ; 0.188          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ;
; 44052.721 ; 44052.909    ; 0.188          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ;
; 44052.721 ; 44052.909    ; 0.188          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ;
; 44052.721 ; 44052.909    ; 0.188          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ;
; 44052.730 ; 44052.854    ; 0.124          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Fall       ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 44052.775 ; 44052.775    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|Equal5~0_NEW_REG0|clk                                                                                                      ;
; 44052.775 ; 44052.775    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_kbd_data|clk                                                                                                           ;
; 44052.775 ; 44052.775    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_parity|clk                                                                                                             ;
; 44052.775 ; 44052.775    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_r_inc|clk                                                                                                              ;
; 44052.775 ; 44052.775    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_rptr[0]|clk                                                                                                            ;
; 44052.775 ; 44052.775    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_rptr[1]|clk                                                                                                            ;
; 44052.775 ; 44052.775    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_rptr[2]|clk                                                                                                            ;
; 44052.775 ; 44052.775    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[0]|clk                                                                                                         ;
; 44052.775 ; 44052.775    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[1]|clk                                                                                                         ;
; 44052.775 ; 44052.775    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[2]|clk                                                                                                         ;
; 44052.775 ; 44052.775    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[3]|clk                                                                                                         ;
; 44052.775 ; 44052.775    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[4]|clk                                                                                                         ;
; 44052.775 ; 44052.775    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[5]|clk                                                                                                         ;
; 44052.775 ; 44052.775    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[6]|clk                                                                                                         ;
; 44052.775 ; 44052.775    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[7]|clk                                                                                                         ;
; 44052.775 ; 44052.775    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[0]|clk                                                                                                        ;
; 44052.775 ; 44052.775    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[1]|clk                                                                                                        ;
; 44052.775 ; 44052.775    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[2]|clk                                                                                                        ;
; 44052.775 ; 44052.775    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[3]|clk                                                                                                        ;
; 44052.782 ; 44052.782    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; pll_switcher|\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 44052.782 ; 44052.782    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; pll_switcher|\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|outclk                                                 ;
; 44052.854 ; 44052.854    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; pll_switcher|\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 44052.854 ; 44052.854    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; pll_switcher|\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|outclk                                                 ;
; 44052.860 ; 44052.860    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|Equal5~0_NEW_REG0|clk                                                                                                      ;
; 44052.860 ; 44052.860    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_kbd_data|clk                                                                                                           ;
; 44052.860 ; 44052.860    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[0]|clk                                                                                                        ;
; 44052.860 ; 44052.860    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[1]|clk                                                                                                        ;
; 44052.860 ; 44052.860    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[2]|clk                                                                                                        ;
; 44052.860 ; 44052.860    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[3]|clk                                                                                                        ;
; 44052.861 ; 44052.861    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_parity|clk                                                                                                             ;
; 44052.861 ; 44052.861    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_r_inc|clk                                                                                                              ;
; 44052.861 ; 44052.861    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_rptr[0]|clk                                                                                                            ;
; 44052.861 ; 44052.861    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_rptr[1]|clk                                                                                                            ;
; 44052.861 ; 44052.861    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_rptr[2]|clk                                                                                                            ;
; 44052.861 ; 44052.861    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[0]|clk                                                                                                         ;
; 44052.861 ; 44052.861    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[1]|clk                                                                                                         ;
; 44052.861 ; 44052.861    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[2]|clk                                                                                                         ;
; 44052.861 ; 44052.861    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[3]|clk                                                                                                         ;
; 44052.861 ; 44052.861    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[4]|clk                                                                                                         ;
; 44052.861 ; 44052.861    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[5]|clk                                                                                                         ;
; 44052.861 ; 44052.861    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[6]|clk                                                                                                         ;
; 44052.861 ; 44052.861    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[7]|clk                                                                                                         ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_kbd_data                                                                                                       ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_parity                                                                                                         ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_r_inc                                                                                                          ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[0]                                                                                                        ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[1]                                                                                                        ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[2]                                                                                                        ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[1]                                                                                                    ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[2]                                                                                                    ;
+-----------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                      ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 3.029 ; 3.142 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 3.024 ; 3.137 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 3.027 ; 3.140 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 3.029 ; 3.142 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 3.029 ; 3.142 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 2.966 ; 3.083 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 2.976 ; 3.093 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 2.966 ; 3.083 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 2.967 ; 3.084 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 2.998 ; 3.111 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 2.998 ; 3.111 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 3.001 ; 3.114 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 3.001 ; 3.114 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 3.014 ; 3.127 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 3.014 ; 3.127 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 3.025 ; 3.138 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 3.025 ; 3.138 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                         ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; SDRAM_DQ[*]   ; CLOCK_27[0] ; -1.950 ; -2.067 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; -2.010 ; -2.123 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; -2.014 ; -2.127 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; -2.015 ; -2.128 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; -2.015 ; -2.128 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; -1.950 ; -2.067 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; -1.960 ; -2.077 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; -1.950 ; -2.067 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; -1.951 ; -2.068 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; -1.984 ; -2.097 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; -1.984 ; -2.097 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; -1.986 ; -2.099 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; -1.986 ; -2.099 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; -2.000 ; -2.113 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; -2.000 ; -2.113 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; -2.011 ; -2.124 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; -2.011 ; -2.124 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                              ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; SDRAM_A[*]    ; CLOCK_27[0] ; 2.550  ; 2.205  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; CLOCK_27[0] ; 2.331  ; 2.037  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; CLOCK_27[0] ; 2.333  ; 2.039  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; CLOCK_27[0] ; 2.334  ; 2.040  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; CLOCK_27[0] ; 2.344  ; 2.050  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; CLOCK_27[0] ; 2.249  ; 1.981  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; CLOCK_27[0] ; 2.550  ; 2.205  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; CLOCK_27[0] ; 2.534  ; 2.189  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; CLOCK_27[0] ; 2.539  ; 2.194  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; CLOCK_27[0] ; 2.539  ; 2.194  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; CLOCK_27[0] ; 2.536  ; 2.191  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; CLOCK_27[0] ; 2.332  ; 2.038  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; CLOCK_27[0] ; 2.543  ; 2.198  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; CLOCK_27[0] ; 2.331  ; 2.037  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; CLOCK_27[0] ; 2.331  ; 2.037  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; CLOCK_27[0] ; 2.322  ; 2.028  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CKE     ; CLOCK_27[0] ; 2.586  ; 2.354  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 2.546  ; 2.201  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 2.522  ; 2.177  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 2.518  ; 2.173  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 2.234  ; 1.966  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 2.234  ; 1.966  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 2.345  ; 2.051  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 2.355  ; 2.061  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 2.345  ; 2.051  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 2.344  ; 2.050  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 2.528  ; 2.183  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 2.528  ; 2.183  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 2.546  ; 2.201  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 2.546  ; 2.201  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 2.229  ; 1.961  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 2.532  ; 2.187  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 2.541  ; 2.196  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 2.238  ; 1.970  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH    ; CLOCK_27[0] ; 2.515  ; 2.170  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML    ; CLOCK_27[0] ; 2.343  ; 2.049  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nCAS    ; CLOCK_27[0] ; 2.332  ; 2.038  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nRAS    ; CLOCK_27[0] ; 2.331  ; 2.037  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nWE     ; CLOCK_27[0] ; 2.343  ; 2.049  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L       ; CLOCK_27[0] ; 5.189  ; 4.650  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R       ; CLOCK_27[0] ; 5.448  ; 4.927  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; LED           ; CLOCK_27[0] ; 5.636  ; 6.277  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]      ; CLOCK_27[0] ; 26.804 ; 26.232 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; CLOCK_27[0] ; 26.060 ; 25.577 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; CLOCK_27[0] ; 26.804 ; 26.232 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; CLOCK_27[0] ; 26.009 ; 25.605 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; CLOCK_27[0] ; 23.902 ; 23.523 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[4]     ; CLOCK_27[0] ; 24.734 ; 24.270 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[5]     ; CLOCK_27[0] ; 24.671 ; 24.187 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; CLOCK_27[0] ; 26.391 ; 26.002 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; CLOCK_27[0] ; 26.377 ; 25.839 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; CLOCK_27[0] ; 26.391 ; 26.002 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; CLOCK_27[0] ; 26.194 ; 25.623 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; CLOCK_27[0] ; 25.511 ; 25.044 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[4]     ; CLOCK_27[0] ; 24.018 ; 23.617 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[5]     ; CLOCK_27[0] ; 19.143 ; 18.492 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS        ; CLOCK_27[0] ; 6.164  ; 5.457  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]      ; CLOCK_27[0] ; 30.761 ; 30.248 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]     ; CLOCK_27[0] ; 29.276 ; 28.789 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]     ; CLOCK_27[0] ; 29.871 ; 29.608 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]     ; CLOCK_27[0] ; 30.761 ; 30.248 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]     ; CLOCK_27[0] ; 28.876 ; 28.425 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[4]     ; CLOCK_27[0] ; 28.321 ; 27.935 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[5]     ; CLOCK_27[0] ; 28.117 ; 27.625 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS        ; CLOCK_27[0] ; 5.903  ; 5.428  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; CLOCK_27[0] ; -0.825 ;        ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; CLOCK_27[0] ;        ; -1.189 ; Fall       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                      ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; SDRAM_A[*]    ; CLOCK_27[0] ; 1.417  ; 1.150  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; CLOCK_27[0] ; 1.497  ; 1.204  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; CLOCK_27[0] ; 1.499  ; 1.206  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; CLOCK_27[0] ; 1.500  ; 1.207  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; CLOCK_27[0] ; 1.510  ; 1.217  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; CLOCK_27[0] ; 1.417  ; 1.150  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; CLOCK_27[0] ; 1.718  ; 1.374  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; CLOCK_27[0] ; 1.702  ; 1.358  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; CLOCK_27[0] ; 1.707  ; 1.363  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; CLOCK_27[0] ; 1.707  ; 1.363  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; CLOCK_27[0] ; 1.704  ; 1.360  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; CLOCK_27[0] ; 1.498  ; 1.205  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; CLOCK_27[0] ; 1.711  ; 1.367  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; CLOCK_27[0] ; 1.488  ; 1.195  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; CLOCK_27[0] ; 1.497  ; 1.204  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; CLOCK_27[0] ; 1.488  ; 1.195  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CKE     ; CLOCK_27[0] ; 1.746  ; 1.513  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 1.397  ; 1.130  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 1.690  ; 1.346  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 1.687  ; 1.343  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 1.402  ; 1.135  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 1.402  ; 1.135  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 1.511  ; 1.218  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 1.521  ; 1.228  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 1.511  ; 1.218  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 1.510  ; 1.217  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 1.696  ; 1.352  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 1.696  ; 1.352  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 1.713  ; 1.369  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 1.713  ; 1.369  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 1.397  ; 1.130  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 1.700  ; 1.356  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 1.709  ; 1.365  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 1.406  ; 1.139  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH    ; CLOCK_27[0] ; 1.683  ; 1.339  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML    ; CLOCK_27[0] ; 1.509  ; 1.216  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nCAS    ; CLOCK_27[0] ; 1.498  ; 1.205  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nRAS    ; CLOCK_27[0] ; 1.497  ; 1.204  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nWE     ; CLOCK_27[0] ; 1.509  ; 1.216  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L       ; CLOCK_27[0] ; 4.322  ; 3.786  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R       ; CLOCK_27[0] ; 4.568  ; 4.050  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; LED           ; CLOCK_27[0] ; 4.730  ; 5.365  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]      ; CLOCK_27[0] ; 4.297  ; 4.018  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; CLOCK_27[0] ; 4.751  ; 4.299  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; CLOCK_27[0] ; 4.916  ; 4.489  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; CLOCK_27[0] ; 4.297  ; 4.018  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; CLOCK_27[0] ; 4.971  ; 4.601  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[4]     ; CLOCK_27[0] ; 5.235  ; 4.759  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[5]     ; CLOCK_27[0] ; 5.251  ; 4.798  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; CLOCK_27[0] ; 5.210  ; 4.736  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; CLOCK_27[0] ; 5.210  ; 4.736  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; CLOCK_27[0] ; 5.271  ; 4.881  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; CLOCK_27[0] ; 5.557  ; 4.999  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; CLOCK_27[0] ; 5.448  ; 4.995  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[4]     ; CLOCK_27[0] ; 5.534  ; 4.910  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[5]     ; CLOCK_27[0] ; 5.613  ; 5.009  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS        ; CLOCK_27[0] ; 5.258  ; 4.560  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]      ; CLOCK_27[0] ; 4.361  ; 3.811  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]     ; CLOCK_27[0] ; 4.361  ; 3.811  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]     ; CLOCK_27[0] ; 4.888  ; 4.424  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]     ; CLOCK_27[0] ; 6.255  ; 5.785  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]     ; CLOCK_27[0] ; 6.663  ; 6.220  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[4]     ; CLOCK_27[0] ; 5.562  ; 4.960  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[5]     ; CLOCK_27[0] ; 5.860  ; 5.239  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS        ; CLOCK_27[0] ; 5.008  ; 4.533  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; CLOCK_27[0] ; -1.612 ;        ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; CLOCK_27[0] ;        ; -1.971 ; Fall       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+


+------------------------------------------------------------+
; Propagation Delay                                          ;
+------------+-------------+-------+-------+--------+--------+
; Input Port ; Output Port ; RR    ; RF    ; FR     ; FF     ;
+------------+-------------+-------+-------+--------+--------+
; CONF_DATA0 ; SPI_DO      ; 9.760 ; 9.520 ; 10.233 ; 10.233 ;
+------------+-------------+-------+-------+--------+--------+


+----------------------------------------------------------+
; Minimum Propagation Delay                                ;
+------------+-------------+-------+-------+-------+-------+
; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
+------------+-------------+-------+-------+-------+-------+
; CONF_DATA0 ; SPI_DO      ; 8.995 ; 8.995 ; 9.447 ; 9.476 ;
+------------+-------------+-------+-------+-------+-------+


+----------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                              ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 2.850 ; 2.850 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 2.854 ; 2.854 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 2.850 ; 2.850 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 2.869 ; 2.869 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 2.869 ; 2.869 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 2.958 ; 2.958 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 2.968 ; 2.968 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 2.958 ; 2.958 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 2.957 ; 2.957 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 2.860 ; 2.860 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 2.860 ; 2.860 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 2.878 ; 2.878 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 2.878 ; 2.878 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 2.864 ; 2.864 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 2.864 ; 2.864 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 2.873 ; 2.873 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 2.873 ; 2.873 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                      ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 1.012 ; 1.039 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 1.015 ; 1.042 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 1.012 ; 1.039 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 1.030 ; 1.057 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 1.030 ; 1.057 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 1.086 ; 1.113 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 1.096 ; 1.123 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 1.086 ; 1.113 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 1.085 ; 1.112 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 1.021 ; 1.048 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 1.021 ; 1.048 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 1.038 ; 1.065 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 1.038 ; 1.065 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 1.025 ; 1.052 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 1.025 ; 1.052 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 1.034 ; 1.061 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 1.034 ; 1.061 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                     ;
+---------------+-------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 2.443     ; 2.929     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 2.447     ; 2.933     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 2.443     ; 2.929     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 2.462     ; 2.948     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 2.462     ; 2.948     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 2.533     ; 3.037     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 2.543     ; 3.047     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 2.533     ; 3.037     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 2.532     ; 3.036     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 2.453     ; 2.939     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 2.453     ; 2.939     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 2.471     ; 2.957     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 2.471     ; 2.957     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 2.457     ; 2.943     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 2.457     ; 2.943     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 2.466     ; 2.952     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 2.466     ; 2.952     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+-------------+-----------+-----------+------------+-----------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                             ;
+---------------+-------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 1.088     ; 1.088     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 1.091     ; 1.091     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 1.088     ; 1.088     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 1.106     ; 1.106     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 1.106     ; 1.106     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 1.162     ; 1.162     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 1.172     ; 1.172     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 1.162     ; 1.162     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 1.161     ; 1.161     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 1.097     ; 1.097     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 1.097     ; 1.097     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 1.114     ; 1.114     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 1.114     ; 1.114     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 1.101     ; 1.101     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 1.101     ; 1.101     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 1.110     ; 1.110     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 1.110     ; 1.110     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+-------------+-----------+-----------+------------+-----------------------------------------------------------------------+


----------------------------------------------
; Slow 1200mV 85C Model Metastability Report ;
----------------------------------------------
No synchronizer chains to report.


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Fmax Summary                                                                                                                                    ;
+------------+-----------------+-----------------------------------------------------------------------+---------------------------------------------------------------+
; Fmax       ; Restricted Fmax ; Clock Name                                                            ; Note                                                          ;
+------------+-----------------+-----------------------------------------------------------------------+---------------------------------------------------------------+
; 63.2 MHz   ; 63.2 MHz        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;                                                               ;
; 88.66 MHz  ; 88.66 MHz       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ;                                                               ;
; 145.22 MHz ; 145.22 MHz      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;                                                               ;
; 191.28 MHz ; 191.28 MHz      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ;                                                               ;
; 323.83 MHz ; 250.0 MHz       ; CLOCK_27[0]                                                           ; limit due to minimum period restriction (max I/O toggle rate) ;
+------------+-----------------+-----------------------------------------------------------------------+---------------------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup Summary                                                             ;
+-----------------------------------------------------------------------+--------+---------------+
; Clock                                                                 ; Slack  ; End Point TNS ;
+-----------------------------------------------------------------------+--------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; -4.207 ; -9.258        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -1.241 ; -1.241        ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 0.069  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1.197  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 11.785 ; 0.000         ;
; CLOCK_27[0]                                                           ; 33.949 ; 0.000         ;
+-----------------------------------------------------------------------+--------+---------------+


+------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold Summary                                                              ;
+-----------------------------------------------------------------------+--------+---------------+
; Clock                                                                 ; Slack  ; End Point TNS ;
+-----------------------------------------------------------------------+--------+---------------+
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; -1.629 ; -1.629        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.383  ; 0.000         ;
; CLOCK_27[0]                                                           ; 0.402  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.402  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.403  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 9.341  ; 0.000         ;
+-----------------------------------------------------------------------+--------+---------------+


+------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery Summary                                                          ;
+-----------------------------------------------------------------------+--------+---------------+
; Clock                                                                 ; Slack  ; End Point TNS ;
+-----------------------------------------------------------------------+--------+---------------+
; CLOCK_27[0]                                                           ; -1.292 ; -11.620       ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 2.515  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 10.529 ; 0.000         ;
+-----------------------------------------------------------------------+--------+---------------+


+------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal Summary                                                           ;
+-----------------------------------------------------------------------+--------+---------------+
; Clock                                                                 ; Slack  ; End Point TNS ;
+-----------------------------------------------------------------------+--------+---------------+
; CLOCK_27[0]                                                           ; -0.277 ; -2.492        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 1.542  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 4.359  ; 0.000         ;
+-----------------------------------------------------------------------+--------+---------------+


+---------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width Summary                                                  ;
+-----------------------------------------------------------------------+-----------+---------------+
; Clock                                                                 ; Slack     ; End Point TNS ;
+-----------------------------------------------------------------------+-----------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 4.097     ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 4.243     ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.406     ; 0.000         ;
; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; 16.279    ; 0.000         ;
; CLOCK_27[0]                                                           ; 18.273    ; 0.000         ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 40.596    ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 44052.511 ; 0.000         ;
+-----------------------------------------------------------------------+-----------+---------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                            ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                            ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; -4.207 ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|synchronizer:tick_toggle_synchronizer|ff_reg[2]                                               ; CLOCK_27[0]                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.150        ; -3.495     ; 0.794      ;
; -2.526 ; switch_pal_ntsc:pll_switcher|reset_n_reg                                                                                             ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[2]                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.354        ; -1.937     ; 0.795      ;
; -2.525 ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                                          ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[2]                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.354        ; -1.937     ; 0.794      ;
; 0.789  ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|synchronizer:sync_clk|ff_reg[2]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 1.809        ; -0.160     ; 0.862      ;
; 0.831  ; user_io:my_user_io|ps2_kbd_data                                                                                                      ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|synchronizer:sync_dat|ff_reg[2]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 1.809        ; -0.160     ; 0.820      ;
; 1.455  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]                                                                ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|synchronizer:sync_clk|ff_reg[2]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 1.809        ; 3.581      ; 3.937      ;
; 1.797  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[0]                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[6]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.096     ; 15.730     ;
; 1.840  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[30]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[6]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.057     ; 15.726     ;
; 1.861  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]                                                                ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|synchronizer:sync_clk|ff_reg[2]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 2.128        ; 3.581      ; 3.850      ;
; 1.870  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[28]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[6]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.140     ; 15.613     ;
; 1.909  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[0]                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[7]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.090     ; 15.624     ;
; 1.952  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[30]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[7]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.051     ; 15.620     ;
; 1.982  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[28]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[7]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.134     ; 15.507     ;
; 2.004  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[0]                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[6]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.145     ; 15.474     ;
; 2.032  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|PC[9]                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.076     ; 15.515     ;
; 2.047  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[30]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[6]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.106     ; 15.470     ;
; 2.049  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|write_en_r                                                                     ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[25]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.079     ; 15.495     ;
; 2.057  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[0]                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[6]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.115     ; 15.451     ;
; 2.066  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[0]~_Duplicate_4         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.358      ; 15.915     ;
; 2.077  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[28]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[6]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.189     ; 15.357     ;
; 2.088  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[0]                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[7]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.145     ; 15.390     ;
; 2.100  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[30]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[6]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.076     ; 15.447     ;
; 2.112  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[3]                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]~_Duplicate_7  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.428      ; 15.939     ;
; 2.130  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[28]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[6]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.159     ; 15.334     ;
; 2.131  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[30]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[7]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.106     ; 15.386     ;
; 2.142  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[29]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[6]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.053     ; 15.428     ;
; 2.143  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[6]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.364      ; 15.844     ;
; 2.157  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|PC[9]                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.076     ; 15.390     ;
; 2.159  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]~_Duplicate_7 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[6]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.140     ; 15.324     ;
; 2.161  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[28]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[7]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.189     ; 15.273     ;
; 2.176  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[0]                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[7]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.099     ; 15.348     ;
; 2.184  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|write_en_r                                                                     ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[29]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.057     ; 15.382     ;
; 2.191  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[0]~_Duplicate_4         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.358      ; 15.790     ;
; 2.211  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|write_en_r                                                                     ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[27]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.079     ; 15.333     ;
; 2.219  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[30]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[7]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.060     ; 15.344     ;
; 2.228  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[2]                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]~_Duplicate_7  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.384      ; 15.779     ;
; 2.230  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|write_en_r                                                                     ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[24]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.079     ; 15.314     ;
; 2.249  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[28]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[7]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.143     ; 15.231     ;
; 2.250  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|byte_write_r                                                                   ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[25]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.073     ; 15.300     ;
; 2.254  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[29]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[7]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.047     ; 15.322     ;
; 2.267  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[0]                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[5]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.115     ; 15.241     ;
; 2.268  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[6]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.364      ; 15.719     ;
; 2.270  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[10]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.078     ; 15.275     ;
; 2.270  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.078     ; 15.275     ;
; 2.270  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[7]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.078     ; 15.275     ;
; 2.271  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]~_Duplicate_7 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[7]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.134     ; 15.218     ;
; 2.272  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[10]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.317      ; 15.668     ;
; 2.272  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[7]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.317      ; 15.668     ;
; 2.272  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[8]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.317      ; 15.668     ;
; 2.272  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[9]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.317      ; 15.668     ;
; 2.278  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[29]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.344      ; 15.689     ;
; 2.278  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.344      ; 15.689     ;
; 2.278  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[43]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.344      ; 15.689     ;
; 2.278  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[34]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.344      ; 15.689     ;
; 2.281  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_enable~0_OTERM3                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|PC[9]                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.096     ; 15.246     ;
; 2.310  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[30]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[5]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.076     ; 15.237     ;
; 2.315  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_enable~0_OTERM3                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[0]~_Duplicate_4         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.338      ; 15.646     ;
; 2.322  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|write_en_r                                                                     ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[23]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.080     ; 15.221     ;
; 2.338  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[2]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.379      ; 15.664     ;
; 2.338  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[6]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.379      ; 15.664     ;
; 2.338  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[3]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.379      ; 15.664     ;
; 2.340  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[28]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[5]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.159     ; 15.124     ;
; 2.346  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[30]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.348      ; 15.625     ;
; 2.346  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[35]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.348      ; 15.625     ;
; 2.346  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_out_OTERM131                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|PC[9]                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.103     ; 15.174     ;
; 2.349  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[29]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[6]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.102     ; 15.172     ;
; 2.351  ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|PC[9]                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.184     ; 15.088     ;
; 2.366  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]~_Duplicate_7 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[6]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.189     ; 15.068     ;
; 2.372  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[0]                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[5]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.090     ; 15.161     ;
; 2.380  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[0]                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[6]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.098     ; 15.145     ;
; 2.380  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_out_OTERM131                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[0]~_Duplicate_4         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.331      ; 15.574     ;
; 2.380  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|PC[9]                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.098     ; 15.145     ;
; 2.385  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|byte_write_r                                                                   ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[29]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.051     ; 15.187     ;
; 2.385  ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[0]~_Duplicate_4         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.250      ; 15.488     ;
; 2.392  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_enable~0_OTERM3                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[6]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.344      ; 15.575     ;
; 2.395  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[10]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.078     ; 15.150     ;
; 2.395  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.078     ; 15.150     ;
; 2.395  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[7]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.078     ; 15.150     ;
; 2.397  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[10]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.317      ; 15.543     ;
; 2.397  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[7]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.317      ; 15.543     ;
; 2.397  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[8]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.317      ; 15.543     ;
; 2.397  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[9]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.317      ; 15.543     ;
; 2.399  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|PC[8]                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.063     ; 15.161     ;
; 2.399  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|PC[0]                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.063     ; 15.161     ;
; 2.402  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[29]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[6]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.072     ; 15.149     ;
; 2.403  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[29]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.344      ; 15.564     ;
; 2.403  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.344      ; 15.564     ;
; 2.403  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[43]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.344      ; 15.564     ;
; 2.403  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[34]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.344      ; 15.564     ;
; 2.405  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[31]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[6]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.140     ; 15.078     ;
; 2.412  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|byte_write_r                                                                   ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[27]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.073     ; 15.138     ;
; 2.414  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[0]~_Duplicate_4         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.336      ; 15.545     ;
; 2.415  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[30]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[5]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.051     ; 15.157     ;
; 2.419  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]~_Duplicate_7 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[6]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.159     ; 15.045     ;
; 2.420  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[7]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.376      ; 15.579     ;
; 2.431  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|byte_write_r                                                                   ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[24]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.073     ; 15.119     ;
; 2.433  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cycleIndirect ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.048     ; 15.142     ;
; 2.433  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cycle3        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.048     ; 15.142     ;
; 2.433  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cycleWrite    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.048     ; 15.142     ;
; 2.433  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[29]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[7]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.102     ; 15.088     ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                   ;
+--------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; -1.241 ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 1.958        ; -1.815     ; 1.267      ;
+--------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                                                           ; To Node                                                                                                                                                                                                                     ; Launch Clock                                                          ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 0.069  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.371        ; 1.212      ; 1.356      ;
; 36.027 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|altsyncram:altsyncram4|altsyncram_72m3:auto_generated|ram_block1a0~porta_address_reg0                 ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.734     ; 7.019      ;
; 36.959 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.393     ; 6.428      ;
; 37.081 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|altsyncram:altsyncram4|altsyncram_cul3:auto_generated|ram_block1a0~porta_address_reg0 ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.737     ; 5.962      ;
; 37.234 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C2_data_state                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.383     ; 6.163      ;
; 37.236 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C1_data_state                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.383     ; 6.161      ;
; 37.450 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C0_data_state                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.383     ; 5.947      ;
; 37.585 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C3_data_state                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.383     ; 5.812      ;
; 38.150 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C4_data_state                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.383     ; 5.247      ;
; 38.213 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3]                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.383     ; 5.184      ;
; 38.214 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4]                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.383     ; 5.183      ;
; 38.301 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.383     ; 5.096      ;
; 38.308 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_seq_data_state                                                                               ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.383     ; 5.089      ;
; 38.389 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2]                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.383     ; 5.008      ;
; 38.492 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2]                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.388     ; 4.900      ;
; 38.525 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1]                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.383     ; 4.872      ;
; 38.714 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1]                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.388     ; 4.678      ;
; 38.780 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_data_state                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.391     ; 4.609      ;
; 38.782 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_data_state                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.391     ; 4.607      ;
; 38.887 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3]                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.388     ; 4.505      ;
; 38.911 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 3.623      ; 6.381      ;
; 38.997 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C2_data_state                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.391     ; 4.392      ;
; 39.021 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 3.604      ; 6.252      ;
; 39.025 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4]                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.388     ; 4.367      ;
; 39.130 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_data_state                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.391     ; 4.259      ;
; 39.213 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 3.604      ; 6.060      ;
; 39.227 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[0]                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.383     ; 4.170      ;
; 39.287 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 3.623      ; 6.005      ;
; 39.317 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 3.618      ; 5.970      ;
; 39.324 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 3.615      ; 5.960      ;
; 39.349 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|areset_init_state_1                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 3.604      ; 5.924      ;
; 39.427 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_seq_data_state                                                               ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.380     ; 3.973      ;
; 39.520 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C4_data_state                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.391     ; 3.869      ;
; 39.679 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[0]                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.388     ; 3.713      ;
; 40.029 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.379     ; 3.372      ;
; 40.547 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|configupdate2_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|configupdate3_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.119     ; 1.002      ;
; 40.548 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|configupdate2_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|configupdate3_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.119     ; 1.001      ;
; 75.016 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.076     ; 8.243      ;
; 75.073 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.095     ; 8.167      ;
; 75.225 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.081     ; 8.029      ;
; 75.256 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.095     ; 7.984      ;
; 75.357 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.076     ; 7.902      ;
; 75.374 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.081     ; 7.880      ;
; 75.383 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|areset_init_state_1                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.095     ; 7.857      ;
; 75.385 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.084     ; 7.866      ;
; 75.564 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.081     ; 7.690      ;
; 75.565 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.081     ; 7.689      ;
; 75.651 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.081     ; 7.603      ;
; 76.449 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.072     ; 6.814      ;
; 76.506 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.091     ; 6.738      ;
; 76.689 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.091     ; 6.555      ;
; 76.790 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.072     ; 6.473      ;
; 76.807 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.077     ; 6.451      ;
; 76.816 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|areset_init_state_1                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.091     ; 6.428      ;
; 76.818 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.080     ; 6.437      ;
; 76.828 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                                            ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.093     ; 6.414      ;
; 77.167 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                                            ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.093     ; 6.075      ;
; 77.168 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                                            ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.093     ; 6.074      ;
; 77.254 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                                            ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.093     ; 5.988      ;
; 77.699 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.101     ; 5.535      ;
; 77.713 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.052     ; 5.570      ;
; 77.770 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 5.494      ;
; 77.800 ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.101     ; 5.434      ;
; 77.808 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                                            ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.073     ; 5.454      ;
; 77.827 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.082     ; 5.426      ;
; 77.866 ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.101     ; 5.368      ;
; 77.909 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_init_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.082     ; 5.344      ;
; 77.928 ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.082     ; 5.325      ;
; 77.953 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 5.311      ;
; 77.975 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.052     ; 5.308      ;
; 77.994 ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.082     ; 5.259      ;
; 78.010 ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_init_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.082     ; 5.243      ;
; 78.032 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 5.232      ;
; 78.032 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_init_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.101     ; 5.202      ;
; 78.054 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.052     ; 5.229      ;
; 78.064 ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.101     ; 5.170      ;
; 78.071 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.057     ; 5.207      ;
; 78.076 ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_init_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.082     ; 5.177      ;
; 78.080 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|areset_init_state_1                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 5.184      ;
; 78.082 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.060     ; 5.193      ;
; 78.133 ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_init_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.101     ; 5.101      ;
; 78.147 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                                            ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.073     ; 5.115      ;
; 78.148 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                                            ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.073     ; 5.114      ;
; 78.173 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.073     ; 5.089      ;
; 78.192 ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.082     ; 5.061      ;
; 78.199 ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_init_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.101     ; 5.035      ;
; 78.215 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 5.049      ;
; 78.234 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                                            ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.073     ; 5.028      ;
; 78.274 ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_init_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.082     ; 4.979      ;
; 78.316 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.052     ; 4.967      ;
; 78.333 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.057     ; 4.945      ;
; 78.342 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|areset_init_state_1                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.922      ;
; 78.344 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.060     ; 4.931      ;
; 78.381 ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[0]                                                                                                                                                                                ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.062     ; 4.892      ;
; 78.397 ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_init_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.101     ; 4.837      ;
; 78.463 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_ena_state                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.084     ; 4.788      ;
; 78.463 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_ena_state                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.084     ; 4.788      ;
; 78.463 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_ena_state                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[2] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.084     ; 4.788      ;
; 78.463 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_ena_state                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[3] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.084     ; 4.788      ;
; 78.463 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_ena_state                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[4] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.084     ; 4.788      ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                  ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 1.197 ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:0:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 4.405        ; -1.814     ; 1.267      ;
; 1.924 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.140     ; 6.622      ;
; 2.044 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.130     ; 6.512      ;
; 2.153 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.140     ; 6.393      ;
; 2.207 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.130     ; 6.349      ;
; 2.212 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.140     ; 6.334      ;
; 2.345 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.140     ; 6.201      ;
; 2.373 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.141     ; 6.172      ;
; 2.390 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.148     ; 6.148      ;
; 2.394 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.149     ; 6.143      ;
; 2.411 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.130     ; 6.145      ;
; 2.411 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.156     ; 6.119      ;
; 2.429 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.141     ; 6.116      ;
; 2.436 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.108     ; 6.142      ;
; 2.446 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.148     ; 6.092      ;
; 2.448 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.149     ; 6.089      ;
; 2.468 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[2]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.160     ; 6.058      ;
; 2.479 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.160     ; 6.047      ;
; 2.481 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.156     ; 6.049      ;
; 2.487 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.130     ; 6.069      ;
; 2.494 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.072     ; 6.246      ;
; 2.495 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.132     ; 6.059      ;
; 2.549 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.122     ; 6.015      ;
; 2.577 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.146     ; 5.963      ;
; 2.578 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[9]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.153     ; 5.955      ;
; 2.583 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.141     ; 5.962      ;
; 2.594 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.108     ; 5.984      ;
; 2.598 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.154     ; 5.934      ;
; 2.600 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.148     ; 5.938      ;
; 2.633 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.146     ; 5.907      ;
; 2.644 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.132     ; 5.910      ;
; 2.649 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[2]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.160     ; 5.877      ;
; 2.653 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.064     ; 6.095      ;
; 2.655 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.108     ; 5.923      ;
; 2.665 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.145     ; 5.876      ;
; 2.682 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.064     ; 6.066      ;
; 2.686 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.153     ; 5.847      ;
; 2.687 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.132     ; 5.867      ;
; 2.707 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.101     ; 5.878      ;
; 2.717 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.141     ; 5.828      ;
; 2.720 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.140     ; 5.826      ;
; 2.721 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.145     ; 5.820      ;
; 2.728 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.109     ; 5.849      ;
; 2.730 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.160     ; 5.796      ;
; 2.734 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.148     ; 5.804      ;
; 2.739 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.108     ; 5.839      ;
; 2.749 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[9]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.153     ; 5.784      ;
; 2.763 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.101     ; 5.822      ;
; 2.764 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.122     ; 5.800      ;
; 2.767 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.154     ; 5.765      ;
; 2.774 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.130     ; 5.782      ;
; 2.776 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.153     ; 5.757      ;
; 2.787 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.146     ; 5.753      ;
; 2.823 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[13]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.139     ; 5.724      ;
; 2.825 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.135     ; 5.690      ;
; 2.825 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.135     ; 5.690      ;
; 2.829 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.122     ; 5.735      ;
; 2.855 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.108     ; 5.723      ;
; 2.858 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.153     ; 5.675      ;
; 2.863 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.132     ; 5.691      ;
; 2.875 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.145     ; 5.666      ;
; 2.879 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.108     ; 5.699      ;
; 2.887 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.064     ; 5.861      ;
; 2.908 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.101     ; 5.677      ;
; 2.912 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.132     ; 5.642      ;
; 2.912 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.140     ; 5.634      ;
; 2.917 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.101     ; 5.668      ;
; 2.921 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.146     ; 5.619      ;
; 2.926 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.109     ; 5.651      ;
; 2.929 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.109     ; 5.648      ;
; 2.935 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.064     ; 5.813      ;
; 2.936 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.100     ; 5.650      ;
; 2.940 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.108     ; 5.638      ;
; 2.944 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.141     ; 5.601      ;
; 2.956 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.122     ; 5.608      ;
; 2.957 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[1]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.169     ; 5.560      ;
; 2.964 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.101     ; 5.621      ;
; 2.965 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.149     ; 5.572      ;
; 2.971 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.132     ; 5.583      ;
; 2.991 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[2]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.152     ; 5.543      ;
; 2.993 ; sdram_statemachine:sdram_adaptor|ADDRESS_IN_sreg[3]                         ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.178     ; 5.515      ;
; 3.000 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.141     ; 5.545      ;
; 3.003 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[13]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.139     ; 5.544      ;
; 3.009 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.102     ; 5.575      ;
; 3.009 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.145     ; 5.532      ;
; 3.016 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.141     ; 5.529      ;
; 3.030 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.110     ; 5.546      ;
; 3.033 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.148     ; 5.505      ;
; 3.040 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.141     ; 5.505      ;
; 3.050 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.109     ; 5.527      ;
; 3.051 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.101     ; 5.534      ;
; 3.054 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.122     ; 5.510      ;
; 3.054 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.130     ; 5.502      ;
; 3.057 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.148     ; 5.481      ;
; 3.065 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.102     ; 5.519      ;
; 3.072 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.152     ; 5.462      ;
; 3.081 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.149     ; 5.456      ;
; 3.085 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.135     ; 5.430      ;
; 3.085 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.135     ; 5.430      ;
; 3.089 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[10]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.102     ; 5.495      ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]'                                                                                                                                                                                                                                                                                                                      ;
+-----------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack     ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-----------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 11.785    ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 15.493       ; -1.814     ; 1.767      ;
; 88100.410 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 5.160      ;
; 88100.420 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 5.150      ;
; 88100.984 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 4.586      ;
; 88100.987 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 4.583      ;
; 88101.035 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 4.535      ;
; 88101.168 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 4.402      ;
; 88101.171 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 4.399      ;
; 88101.262 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 4.308      ;
; 88101.282 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 4.288      ;
; 88101.290 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 4.280      ;
; 88101.348 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.071     ; 4.221      ;
; 88101.351 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.071     ; 4.218      ;
; 88101.389 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 4.181      ;
; 88101.604 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 3.966      ;
; 88101.606 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 3.964      ;
; 88101.607 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 3.963      ;
; 88101.612 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 3.958      ;
; 88101.619 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 3.951      ;
; 88101.803 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 3.767      ;
; 88101.852 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.071     ; 3.717      ;
; 88101.855 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.071     ; 3.714      ;
; 88101.974 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.071     ; 3.595      ;
; 88102.248 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_r_inc                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 3.322      ;
; 88102.278 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 3.292      ;
; 88102.449 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.071     ; 3.120      ;
; 88102.463 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 3.107      ;
; 88102.463 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 3.107      ;
; 88102.463 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 3.107      ;
; 88102.463 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 3.107      ;
; 88102.463 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 3.107      ;
; 88102.463 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 3.107      ;
; 88102.463 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 3.107      ;
; 88102.463 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 3.107      ;
; 88102.641 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 2.929      ;
; 88102.641 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 2.929      ;
; 88102.641 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 2.929      ;
; 88102.641 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 2.929      ;
; 88102.641 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 2.929      ;
; 88102.641 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 2.929      ;
; 88102.641 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 2.929      ;
; 88102.641 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 2.929      ;
; 88102.653 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 2.917      ;
; 88102.653 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 2.917      ;
; 88102.653 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 2.917      ;
; 88102.653 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 2.917      ;
; 88102.653 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 2.917      ;
; 88102.653 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 2.917      ;
; 88102.653 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 2.917      ;
; 88102.653 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 2.917      ;
; 88102.689 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.071     ; 2.880      ;
; 88102.723 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_r_inc                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 2.847      ;
; 88102.786 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.071     ; 2.783      ;
; 88102.810 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.071     ; 2.759      ;
; 88102.813 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.071     ; 2.756      ;
; 88102.850 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 2.720      ;
; 88102.850 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 2.720      ;
; 88102.850 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 2.720      ;
; 88102.850 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 2.720      ;
; 88102.850 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 2.720      ;
; 88102.850 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 2.720      ;
; 88102.850 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 2.720      ;
; 88102.850 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 2.720      ;
; 88102.877 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.071     ; 2.692      ;
; 88102.937 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 2.633      ;
; 88102.937 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 2.633      ;
; 88102.937 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 2.633      ;
; 88102.937 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 2.633      ;
; 88102.937 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 2.633      ;
; 88102.937 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 2.633      ;
; 88102.937 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 2.633      ;
; 88102.937 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 2.633      ;
; 88103.062 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.071     ; 2.507      ;
; 88103.065 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.071     ; 2.504      ;
; 88103.079 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 2.491      ;
; 88103.088 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.071     ; 2.481      ;
; 88103.134 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.071     ; 2.435      ;
; 88103.159 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.071     ; 2.410      ;
; 88103.162 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.071     ; 2.407      ;
; 88103.244 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.071     ; 2.325      ;
; 88103.247 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.071     ; 2.322      ;
; 88103.250 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.071     ; 2.319      ;
; 88103.253 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.071     ; 2.316      ;
; 88103.507 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.071     ; 2.062      ;
; 88103.510 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.071     ; 2.059      ;
; 88103.620 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 1.950      ;
; 88103.620 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 1.950      ;
; 88103.620 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 1.950      ;
; 88103.620 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 1.950      ;
; 88103.620 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 1.950      ;
; 88103.620 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 1.950      ;
; 88103.620 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 1.950      ;
; 88103.620 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 1.950      ;
; 88103.676 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_state[3]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.071     ; 1.893      ;
; 88103.704 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.071     ; 1.865      ;
; 88103.724 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 1.846      ;
; 88103.743 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_r_inc                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.070     ; 1.827      ;
; 88103.745 ; user_io:my_user_io|ps2_kbd_data                                             ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.071     ; 1.824      ;
; 88103.804 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_state[3]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.071     ; 1.765      ;
; 88103.828 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_state[3]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.071     ; 1.741      ;
+-----------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'CLOCK_27[0]'                                                                                                                                                            ;
+--------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                 ; To Node                                                   ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 33.949 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 3.018      ;
; 34.075 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 2.892      ;
; 34.106 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 2.861      ;
; 34.266 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 2.701      ;
; 34.297 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 2.670      ;
; 34.344 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 2.623      ;
; 34.373 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 2.594      ;
; 34.395 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 2.572      ;
; 34.423 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 2.544      ;
; 34.426 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 2.541      ;
; 34.470 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 2.497      ;
; 34.472 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 2.495      ;
; 34.479 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 2.488      ;
; 34.517 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 2.450      ;
; 34.517 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 2.450      ;
; 34.548 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 2.419      ;
; 34.552 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 2.415      ;
; 34.594 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 2.373      ;
; 34.598 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 2.369      ;
; 34.601 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 2.366      ;
; 34.606 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 2.361      ;
; 34.861 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 2.106      ;
; 34.864 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 2.103      ;
; 34.870 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 2.097      ;
; 34.892 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 2.075      ;
; 34.931 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 2.036      ;
; 34.953 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 2.014      ;
; 35.018 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 1.949      ;
; 35.038 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 1.929      ;
; 35.043 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 1.924      ;
; 35.044 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 1.923      ;
; 35.045 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 1.922      ;
; 35.047 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 1.920      ;
; 35.050 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 1.917      ;
; 35.052 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 1.915      ;
; 35.083 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 1.884      ;
; 35.166 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 1.801      ;
; 35.178 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 1.789      ;
; 35.180 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 1.787      ;
; 35.212 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 1.755      ;
; 35.212 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 1.755      ;
; 35.228 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 1.739      ;
; 35.229 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 1.738      ;
; 35.235 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 1.732      ;
; 35.248 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 1.719      ;
; 35.287 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 1.680      ;
; 35.296 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 1.671      ;
; 35.381 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 1.586      ;
; 35.381 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 1.586      ;
; 35.383 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 1.584      ;
; 35.385 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 1.582      ;
; 35.395 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 1.572      ;
; 35.403 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 1.564      ;
; 35.539 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 1.428      ;
; 35.541 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 1.426      ;
; 35.566 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 1.401      ;
; 35.817 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 1.150      ;
; 35.819 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 1.148      ;
; 35.851 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 1.116      ;
; 36.197 ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.072     ; 0.770      ;
+--------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                                   ; To Node                                                                                                                                                                                                                             ; Launch Clock                                                          ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; -1.629 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.017        ; 2.385      ; 1.138      ;
; 0.402  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_data_state                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C2_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C2_data_state                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_data_state                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_data_state                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_seq_data_state                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_seq_data_state                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C4_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C4_data_state                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_seq_data_state                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_seq_data_state                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                               ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                                       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                               ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                               ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                                       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C2_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C2_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C1_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C1_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C3_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C3_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C0_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C0_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C4_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C4_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.454  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4]         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.721      ;
; 0.454  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.721      ;
; 0.456  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5]         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.723      ;
; 0.469  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[24]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[24]                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.736      ;
; 0.471  ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[1]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[0]                                                                                                                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.737      ;
; 0.476  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|configupdate_state                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|configupdate2_state                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.743      ;
; 0.477  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|configupdate_state                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|configupdate2_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.744      ;
; 0.479  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C3_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C2_ena_state                                                                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.745      ;
; 0.479  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C1_ena_state                                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C1_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.745      ;
; 0.481  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C2_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C1_ena_state                                                                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.747      ;
; 0.482  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C1_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C0_ena_state                                                                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.748      ;
; 0.489  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reset_state                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.755      ;
; 0.493  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_counter_state                                                        ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|tmp_seq_ena_state                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.759      ;
; 0.500  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C3_ena_state                                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C3_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.766      ;
; 0.502  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_init_state                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.769      ;
; 0.609  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C2_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_ena_state                                                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.876      ;
; 0.609  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C0_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|tmp_seq_ena_state                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.875      ;
; 0.610  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|tmp_seq_ena_state                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.877      ;
; 0.615  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C4_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C3_ena_state                                                                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.881      ;
; 0.618  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C4_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_counter_state                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.884      ;
; 0.628  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[1]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|altsyncram:altsyncram4|altsyncram_72m3:auto_generated|ram_block1a0~porta_address_reg0 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.421      ; 1.279      ;
; 0.631  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_init_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_counter_state                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.898      ;
; 0.634  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_init_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C4_ena_state                                                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.899      ;
; 0.644  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|tmp_seq_ena_state                                                             ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_seq_ena_state                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.910      ;
; 0.684  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[9]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[9]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.950      ;
; 0.684  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[11]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[11]                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.950      ;
; 0.684  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[15]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[15]                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.951      ;
; 0.685  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.951      ;
; 0.685  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.951      ;
; 0.685  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[17]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[17]                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.952      ;
; 0.685  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[23]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[23]                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.952      ;
; 0.686  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[13]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[13]                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.953      ;
; 0.687  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.953      ;
; 0.687  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[18]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[18]                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.954      ;
; 0.688  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.954      ;
; 0.688  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.954      ;
; 0.688  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[12]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[12]                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.955      ;
; 0.688  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[19]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[19]                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.955      ;
; 0.688  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[21]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[21]                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.955      ;
; 0.689  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[14]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[14]                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.956      ;
; 0.690  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[8]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[8]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.956      ;
; 0.690  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[10]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[10]                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.956      ;
; 0.690  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|areset_init_state_1                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.956      ;
; 0.691  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.957      ;
; 0.691  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.957      ;
; 0.691  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[16]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[16]                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.958      ;
; 0.691  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[20]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[20]                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.958      ;
; 0.692  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[22]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[22]                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.959      ;
; 0.693  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3]         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.960      ;
; 0.693  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1]         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.959      ;
; 0.694  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.961      ;
; 0.694  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.961      ;
; 0.695  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1]         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.962      ;
; 0.695  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[3]         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.961      ;
; 0.695  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_ena_state                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_data_state                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.962      ;
; 0.696  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[4]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.963      ;
; 0.696  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[7] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[7]         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.962      ;
; 0.697  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1]         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.964      ;
; 0.697  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.964      ;
; 0.697  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[4] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[4]         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.963      ;
; 0.697  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[5] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[5]         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.963      ;
; 0.698  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.965      ;
; 0.698  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3]         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.965      ;
; 0.698  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[2]         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.964      ;
; 0.698  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[6] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[6]         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.964      ;
; 0.700  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2]         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.967      ;
; 0.701  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.968      ;
; 0.701  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.968      ;
; 0.705  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.972      ;
; 0.706  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[3]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.973      ;
; 0.706  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_ena_state                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_data_state                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.973      ;
; 0.706  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_ena_state                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_data_state                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.973      ;
; 0.707  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[4]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.974      ;
; 0.707  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[6]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[6]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.974      ;
; 0.707  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[7]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[7]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.974      ;
; 0.708  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_init_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.974      ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                   ; To Node                                                                                                                                                                                                                                ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.383 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cyclePreRead        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cyclePreRead                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.091      ; 0.669      ;
; 0.383 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[16]                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[16]                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.091      ; 0.669      ;
; 0.384 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cycleBranchTaken    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cycleBranchTaken                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.090      ; 0.669      ;
; 0.384 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Creg                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Creg                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.090      ; 0.669      ;
; 0.384 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[7]                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[7]                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.090      ; 0.669      ;
; 0.384 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[7]                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[7]                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.090      ; 0.669      ;
; 0.384 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[7]                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[7]                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.090      ; 0.669      ;
; 0.385 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[0]_OTERM269                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[0]_OTERM269                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.089      ; 0.669      ;
; 0.385 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[7]                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[7]                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.089      ; 0.669      ;
; 0.386 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[68]                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[68]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.088      ; 0.669      ;
; 0.386 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[6]                                                                   ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[6]                                                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.088      ; 0.669      ;
; 0.386 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[7]                                                                   ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[7]                                                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.088      ; 0.669      ;
; 0.386 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[0]                                                                   ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[0]                                                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.088      ; 0.669      ;
; 0.386 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[3]                                                                   ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[3]                                                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.088      ; 0.669      ;
; 0.394 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[1]                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.425      ; 1.049      ;
; 0.394 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[2]                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.424      ; 1.048      ;
; 0.399 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_snap_reg[6]                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a8~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.423      ; 1.052      ;
; 0.399 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[5]                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.425      ; 1.054      ;
; 0.400 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[7]                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.425      ; 1.055      ;
; 0.401 ; sdram_statemachine:sdram_adaptor|sdram_request_reg                                                                                          ; sdram_statemachine:sdram_adaptor|sdram_request_reg                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.073      ; 0.669      ;
; 0.401 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_popped                                                                       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_popped                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.073      ; 0.669      ;
; 0.401 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_mult5                                                                        ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_mult5                                                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.073      ; 0.669      ;
; 0.401 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_store_sp2                                                                    ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_store_sp2                                                                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.073      ; 0.669      ;
; 0.401 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                                                                                         ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.073      ; 0.669      ;
; 0.401 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[16]                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[16]                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.073      ; 0.669      ;
; 0.401 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[17]                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[17]                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.073      ; 0.669      ;
; 0.401 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[4]                                               ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|altsyncram_aj81:FIFOram|ram_block1a0~porta_datain_reg0          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.429      ; 1.060      ;
; 0.401 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf3_reg[4]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf3_reg[4]                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.073      ; 0.669      ;
; 0.401 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf3_reg[0]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf3_reg[0]                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.073      ; 0.669      ;
; 0.401 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf3_reg[1]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf3_reg[1]                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.073      ; 0.669      ;
; 0.401 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf3_reg[2]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf3_reg[2]                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.073      ; 0.669      ;
; 0.401 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf3_reg[3]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf3_reg[3]                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.073      ; 0.669      ;
; 0.401 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf3_reg[5]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf3_reg[5]                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.073      ; 0.669      ;
; 0.401 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf3_reg[6]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf3_reg[6]                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.073      ; 0.669      ;
; 0.401 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf3_reg[7]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf3_reg[7]                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.073      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]                                                                                          ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[5]                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[5]                                                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[9]                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[9]                                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[6]                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[6]                                                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cyclePreIndirect    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cyclePreIndirect                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cycleEnd            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cycleEnd                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Vreg                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Vreg                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vbi_nmi_reg                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vbi_nmi_reg                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|nmiReg                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|nmiReg                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[10]                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[10]                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|use_status_as_ram_address ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|use_status_as_ram_address                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|porta_control_reg[4]                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|porta_control_reg[4]                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|cb2_edge_reg                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|cb2_edge_reg                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_bitcount_reg[1]                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_bitcount_reg[1]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_bitcount_reg[2]                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_bitcount_reg[2]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_bitcount_reg[3]                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_bitcount_reg[3]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|vector_a2                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|vector_a2                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|irqa_reg[1]                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|irqa_reg[1]                                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hblank_reg                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hblank_reg                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|oldcycle_state_reg[1]                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|oldcycle_state_reg[1]                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|oldcycle_state_reg[0]                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|oldcycle_state_reg[0]                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|porta_control_reg[3]                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|porta_control_reg[3]                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_control_reg[3]                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_control_reg[3]                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_control_reg[5]                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_control_reg[5]                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|porta_control_reg[5]                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|porta_control_reg[5]                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|CA2_output_reg                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|CA2_output_reg                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cycleBranchPage     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cycleBranchPage                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[5]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[5]                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[4]                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[4]                                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[4]                                                                                           ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[4]                                                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[1]                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[1]                                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[5]                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[5]                                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.ready                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.ready                                                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[45]                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[45]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[31]                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[31]                                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|state                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|state                                                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_reg                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_reg                                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|ss_n[1]                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|ss_n[1]                                                                                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|ss_n[0]                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|ss_n[0]                                                                                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|assert_data                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|assert_data                                                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|sclk                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|sclk                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|mosi~reg0                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|mosi~reg0                                                                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[13]                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[13]                                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[28]                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[28]                                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[12]                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[12]                                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[25]                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[25]                                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[51]                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[51]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[15]                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[15]                                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[6]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[6]                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[2]                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[2]                                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[18]                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[18]                                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[1]                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[1]                                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[7]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[7]                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[13]                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[13]                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[13]                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[13]                                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[12]                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[12]                                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[14]                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[14]                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                                                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[5]                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[5]                                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                                                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[0]                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[0]                                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[4]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[4]                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]                                                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[364]                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[364]                                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[59]                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[59]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'CLOCK_27[0]'                                                                                                                                                            ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                 ; To Node                                                   ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.417 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 0.684      ;
; 0.694 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 0.961      ;
; 0.696 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 0.963      ;
; 0.698 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 0.965      ;
; 1.006 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.273      ;
; 1.009 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.276      ;
; 1.014 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.281      ;
; 1.020 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.287      ;
; 1.023 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.290      ;
; 1.023 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.290      ;
; 1.024 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.291      ;
; 1.028 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.295      ;
; 1.035 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.302      ;
; 1.041 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.308      ;
; 1.116 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.383      ;
; 1.127 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.394      ;
; 1.132 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.399      ;
; 1.141 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.408      ;
; 1.152 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.419      ;
; 1.152 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.419      ;
; 1.153 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.420      ;
; 1.166 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.433      ;
; 1.169 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.436      ;
; 1.174 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.441      ;
; 1.179 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.446      ;
; 1.187 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.454      ;
; 1.260 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.527      ;
; 1.262 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.529      ;
; 1.265 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.532      ;
; 1.270 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.537      ;
; 1.270 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.537      ;
; 1.290 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.557      ;
; 1.294 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.561      ;
; 1.296 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.563      ;
; 1.309 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.576      ;
; 1.312 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.579      ;
; 1.319 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.586      ;
; 1.320 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.587      ;
; 1.320 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.587      ;
; 1.321 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.588      ;
; 1.342 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.609      ;
; 1.344 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.611      ;
; 1.416 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.683      ;
; 1.430 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.697      ;
; 1.430 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.697      ;
; 1.430 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.697      ;
; 1.432 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.699      ;
; 1.433 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.700      ;
; 1.434 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.701      ;
; 1.478 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.745      ;
; 1.480 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.747      ;
; 1.481 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.748      ;
; 1.482 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.749      ;
; 1.511 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.778      ;
; 1.512 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.779      ;
; 1.513 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.780      ;
; 1.580 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.847      ;
; 1.587 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.854      ;
; 1.593 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.072      ; 1.860      ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                             ;
+-------+---------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                     ; To Node                                                       ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.402 ; sdram_statemachine:sdram_adaptor|reply_reg                    ; sdram_statemachine:sdram_adaptor|reply_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.471 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.737      ;
; 0.540 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.807      ;
; 0.542 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.809      ;
; 0.685 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.952      ;
; 0.687 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.954      ;
; 0.688 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.955      ;
; 0.688 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.955      ;
; 0.691 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.958      ;
; 0.691 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.958      ;
; 0.691 ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.958      ;
; 0.694 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.960      ;
; 0.694 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.960      ;
; 0.695 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.961      ;
; 0.698 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.964      ;
; 0.698 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.964      ;
; 0.699 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.965      ;
; 0.699 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.965      ;
; 0.700 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.966      ;
; 0.700 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.966      ;
; 0.704 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.971      ;
; 0.705 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.972      ;
; 0.707 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.974      ;
; 0.708 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.975      ;
; 0.708 ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.975      ;
; 0.717 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.984      ;
; 0.718 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.985      ;
; 0.720 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.986      ;
; 0.721 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.988      ;
; 0.722 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.989      ;
; 0.722 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.989      ;
; 0.724 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.991      ;
; 0.728 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.995      ;
; 0.733 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.000      ;
; 0.744 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.011      ;
; 0.750 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.017      ;
; 0.798 ; sdram_statemachine:sdram_adaptor|request_sreg                 ; sdram_statemachine:sdram_adaptor|reply_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 1.168      ;
; 0.875 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.142      ;
; 0.877 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.144      ;
; 0.880 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.147      ;
; 0.881 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.148      ;
; 0.891 ; sdram_statemachine:sdram_adaptor|dqm_mask_sreg[0]             ; sdram_statemachine:sdram_adaptor|data_out_reg[1]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.161      ; 1.266      ;
; 0.896 ; sdram_statemachine:sdram_adaptor|dqm_mask_sreg[0]             ; sdram_statemachine:sdram_adaptor|data_out_reg[4]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.161      ; 1.271      ;
; 0.988 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.255      ;
; 1.006 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.273      ;
; 1.007 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.274      ;
; 1.008 ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.275      ;
; 1.009 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.276      ;
; 1.009 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.276      ;
; 1.012 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.279      ;
; 1.012 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.279      ;
; 1.015 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.281      ;
; 1.016 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.282      ;
; 1.016 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.282      ;
; 1.017 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.283      ;
; 1.018 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.284      ;
; 1.019 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.285      ;
; 1.019 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.285      ;
; 1.019 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.285      ;
; 1.021 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.288      ;
; 1.022 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.288      ;
; 1.023 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.289      ;
; 1.025 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.292      ;
; 1.025 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.292      ;
; 1.026 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.293      ;
; 1.027 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.294      ;
; 1.030 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.296      ;
; 1.031 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.298      ;
; 1.032 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.298      ;
; 1.033 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.299      ;
; 1.034 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.300      ;
; 1.034 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.300      ;
; 1.039 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.306      ;
; 1.039 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.306      ;
; 1.039 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.306      ;
; 1.041 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.308      ;
; 1.042 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.309      ;
; 1.043 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.310      ;
; 1.044 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.311      ;
; 1.045 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.312      ;
; 1.046 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.313      ;
; 1.047 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.314      ;
; 1.050 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.317      ;
; 1.054 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.321      ;
; 1.054 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.321      ;
; 1.055 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.322      ;
; 1.060 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.327      ;
; 1.062 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.329      ;
; 1.067 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.334      ;
; 1.101 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.368      ;
; 1.107 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.374      ;
; 1.107 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.374      ;
; 1.112 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.378      ;
; 1.113 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.379      ;
; 1.116 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.382      ;
; 1.120 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.386      ;
; 1.125 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.392      ;
+-------+---------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]'                                                                                                                                                                       ;
+-------+------------------------------------+------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                          ; To Node                            ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------+------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.403 ; user_io:my_user_io|ps2_tx_state[1] ; user_io:my_user_io|ps2_tx_state[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_tx_state[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.404 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_rptr[0]     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; user_io:my_user_io|ps2_rptr[1]     ; user_io:my_user_io|ps2_rptr[1]     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_rptr[2]     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; user_io:my_user_io|ps2_tx_byte[7]  ; user_io:my_user_io|ps2_tx_byte[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; user_io:my_user_io|ps2_parity      ; user_io:my_user_io|ps2_parity      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 0.669      ;
; 0.467 ; user_io:my_user_io|ps2_r_inc       ; user_io:my_user_io|ps2_rptr[0]     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 0.732      ;
; 0.469 ; user_io:my_user_io|ps2_r_inc       ; user_io:my_user_io|ps2_rptr[1]     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 0.734      ;
; 0.471 ; user_io:my_user_io|ps2_tx_byte[0]  ; user_io:my_user_io|ps2_parity      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 0.736      ;
; 0.482 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_rptr[2]     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 0.747      ;
; 0.486 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_state[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 0.752      ;
; 0.514 ; user_io:my_user_io|ps2_tx_state[0] ; user_io:my_user_io|ps2_tx_state[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 0.780      ;
; 0.536 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_tx_byte[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 0.801      ;
; 0.536 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_tx_byte[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 0.801      ;
; 0.537 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_tx_byte[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 0.802      ;
; 0.646 ; user_io:my_user_io|ps2_parity      ; user_io:my_user_io|ps2_kbd_data    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 0.911      ;
; 0.648 ; user_io:my_user_io|ps2_tx_byte[4]  ; user_io:my_user_io|ps2_tx_byte[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 0.913      ;
; 0.649 ; user_io:my_user_io|ps2_tx_byte[6]  ; user_io:my_user_io|ps2_tx_byte[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 0.914      ;
; 0.649 ; user_io:my_user_io|ps2_tx_byte[5]  ; user_io:my_user_io|ps2_tx_byte[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 0.914      ;
; 0.649 ; user_io:my_user_io|ps2_tx_byte[3]  ; user_io:my_user_io|ps2_tx_byte[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 0.914      ;
; 0.649 ; user_io:my_user_io|ps2_tx_byte[2]  ; user_io:my_user_io|ps2_tx_byte[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 0.914      ;
; 0.649 ; user_io:my_user_io|ps2_tx_byte[1]  ; user_io:my_user_io|ps2_tx_byte[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 0.914      ;
; 0.705 ; user_io:my_user_io|ps2_r_inc       ; user_io:my_user_io|ps2_rptr[2]     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 0.970      ;
; 0.714 ; user_io:my_user_io|ps2_rptr[1]     ; user_io:my_user_io|ps2_rptr[2]     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 0.979      ;
; 0.724 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_rptr[1]     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 0.989      ;
; 0.759 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_state[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.025      ;
; 0.799 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_tx_byte[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.064      ;
; 0.802 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_tx_byte[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.067      ;
; 0.802 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_tx_byte[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.067      ;
; 0.808 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_tx_byte[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.073      ;
; 0.812 ; user_io:my_user_io|ps2_tx_state[0] ; user_io:my_user_io|ps2_tx_state[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.078      ;
; 0.843 ; user_io:my_user_io|ps2_tx_byte[7]  ; user_io:my_user_io|ps2_tx_byte[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.108      ;
; 0.873 ; user_io:my_user_io|Equal5~0_OTERM1 ; user_io:my_user_io|Equal5~0_OTERM1 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.139      ;
; 0.875 ; user_io:my_user_io|Equal5~0_OTERM1 ; user_io:my_user_io|ps2_tx_state[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.141      ;
; 0.906 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|Equal5~0_OTERM1 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.172      ;
; 0.910 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_r_inc       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.175      ;
; 0.910 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_tx_byte[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.175      ;
; 0.948 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_tx_state[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.214      ;
; 0.956 ; user_io:my_user_io|Equal5~0_OTERM1 ; user_io:my_user_io|ps2_parity      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.222      ;
; 0.989 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|Equal5~0_OTERM1 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.255      ;
; 0.992 ; user_io:my_user_io|ps2_tx_state[1] ; user_io:my_user_io|ps2_tx_state[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.258      ;
; 0.992 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_kbd_data    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.258      ;
; 1.059 ; user_io:my_user_io|ps2_tx_state[1] ; user_io:my_user_io|Equal5~0_OTERM1 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.325      ;
; 1.072 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_state[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.338      ;
; 1.083 ; user_io:my_user_io|ps2_kbd_data    ; user_io:my_user_io|ps2_kbd_data    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.349      ;
; 1.163 ; user_io:my_user_io|ps2_tx_state[0] ; user_io:my_user_io|Equal5~0_OTERM1 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.429      ;
; 1.165 ; user_io:my_user_io|ps2_tx_state[0] ; user_io:my_user_io|ps2_tx_state[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.431      ;
; 1.203 ; user_io:my_user_io|Equal5~0_OTERM1 ; user_io:my_user_io|ps2_tx_byte[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.469      ;
; 1.203 ; user_io:my_user_io|Equal5~0_OTERM1 ; user_io:my_user_io|ps2_tx_byte[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.469      ;
; 1.203 ; user_io:my_user_io|Equal5~0_OTERM1 ; user_io:my_user_io|ps2_tx_byte[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.469      ;
; 1.203 ; user_io:my_user_io|Equal5~0_OTERM1 ; user_io:my_user_io|ps2_tx_byte[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.469      ;
; 1.203 ; user_io:my_user_io|Equal5~0_OTERM1 ; user_io:my_user_io|ps2_tx_byte[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.469      ;
; 1.203 ; user_io:my_user_io|Equal5~0_OTERM1 ; user_io:my_user_io|ps2_tx_byte[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.469      ;
; 1.203 ; user_io:my_user_io|Equal5~0_OTERM1 ; user_io:my_user_io|ps2_tx_byte[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.469      ;
; 1.226 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_tx_byte[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.491      ;
; 1.239 ; user_io:my_user_io|ps2_tx_byte[0]  ; user_io:my_user_io|ps2_kbd_data    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.504      ;
; 1.284 ; user_io:my_user_io|ps2_tx_state[0] ; user_io:my_user_io|ps2_kbd_data    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.550      ;
; 1.322 ; user_io:my_user_io|Equal5~0_OTERM1 ; user_io:my_user_io|ps2_kbd_data    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.588      ;
; 1.324 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_kbd_data    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.590      ;
; 1.339 ; user_io:my_user_io|Equal5~0_OTERM1 ; user_io:my_user_io|ps2_tx_byte[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.605      ;
; 1.361 ; user_io:my_user_io|Equal5~0_OTERM1 ; user_io:my_user_io|ps2_r_inc       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.627      ;
; 1.365 ; user_io:my_user_io|ps2_tx_state[0] ; user_io:my_user_io|ps2_tx_state[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.631      ;
; 1.371 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_tx_state[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.637      ;
; 1.438 ; user_io:my_user_io|ps2_tx_state[1] ; user_io:my_user_io|ps2_kbd_data    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.704      ;
; 1.486 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_tx_byte[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.751      ;
; 1.486 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_tx_byte[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.751      ;
; 1.494 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_tx_byte[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.759      ;
; 1.517 ; user_io:my_user_io|ps2_tx_state[1] ; user_io:my_user_io|ps2_tx_state[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.783      ;
; 1.525 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_tx_byte[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.790      ;
; 1.667 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_state[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 1.933      ;
; 1.672 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|Equal5~0_OTERM1 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.937      ;
; 1.674 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_tx_state[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.939      ;
; 1.679 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_tx_byte[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.944      ;
; 1.735 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_tx_byte[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 2.000      ;
; 1.890 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_kbd_data    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 2.155      ;
; 1.950 ; user_io:my_user_io|ps2_rptr[1]     ; user_io:my_user_io|ps2_tx_byte[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 2.215      ;
; 1.952 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_tx_state[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 2.218      ;
; 2.068 ; user_io:my_user_io|ps2_tx_state[1] ; user_io:my_user_io|ps2_tx_state[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 2.334      ;
; 2.115 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_tx_byte[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 2.380      ;
; 2.175 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_byte[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 2.441      ;
; 2.175 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_byte[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 2.441      ;
; 2.175 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_byte[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 2.441      ;
; 2.175 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_byte[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 2.441      ;
; 2.175 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_byte[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 2.441      ;
; 2.175 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_byte[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 2.441      ;
; 2.175 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_byte[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 2.441      ;
; 2.175 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_parity      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 2.441      ;
; 2.204 ; user_io:my_user_io|ps2_rptr[1]     ; user_io:my_user_io|ps2_tx_byte[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 2.469      ;
; 2.240 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_r_inc       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 2.505      ;
; 2.257 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_parity      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 2.522      ;
; 2.379 ; user_io:my_user_io|ps2_rptr[1]     ; user_io:my_user_io|ps2_tx_byte[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 2.644      ;
; 2.448 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_kbd_data    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 2.713      ;
; 2.448 ; user_io:my_user_io|ps2_rptr[1]     ; user_io:my_user_io|ps2_tx_byte[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 2.713      ;
; 2.467 ; user_io:my_user_io|ps2_rptr[1]     ; user_io:my_user_io|ps2_tx_byte[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 2.732      ;
; 2.469 ; user_io:my_user_io|ps2_tx_state[0] ; user_io:my_user_io|ps2_tx_byte[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 2.735      ;
; 2.469 ; user_io:my_user_io|ps2_tx_state[0] ; user_io:my_user_io|ps2_tx_byte[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 2.735      ;
; 2.469 ; user_io:my_user_io|ps2_tx_state[0] ; user_io:my_user_io|ps2_tx_byte[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 2.735      ;
; 2.469 ; user_io:my_user_io|ps2_tx_state[0] ; user_io:my_user_io|ps2_tx_byte[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 2.735      ;
; 2.469 ; user_io:my_user_io|ps2_tx_state[0] ; user_io:my_user_io|ps2_tx_byte[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.071      ; 2.735      ;
+-------+------------------------------------+------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                   ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 9.341 ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -6.853       ; -1.565     ; 1.025      ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: 'CLOCK_27[0]'                                                                                                                                                                                                                               ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------+-----------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                              ; To Node                                                   ; Launch Clock                                                          ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------+-----------------------------------------------------------------------+-------------+--------------+------------+------------+
; -1.292 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.141      ; 4.504      ;
; -1.291 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.141      ; 4.503      ;
; -1.291 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.141      ; 4.503      ;
; -1.291 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.141      ; 4.503      ;
; -1.291 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.141      ; 4.503      ;
; -1.291 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.141      ; 4.503      ;
; -1.291 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.141      ; 4.503      ;
; -1.291 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.141      ; 4.503      ;
; -1.291 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.141      ; 4.503      ;
; -1.170 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.138      ; 4.379      ;
; -1.169 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.138      ; 4.378      ;
; -1.169 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.138      ; 4.378      ;
; -1.169 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.138      ; 4.378      ;
; -1.169 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.138      ; 4.378      ;
; -1.169 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.138      ; 4.378      ;
; -1.169 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.138      ; 4.378      ;
; -1.169 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.138      ; 4.378      ;
; -1.169 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.138      ; 4.378      ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------+-----------------------------------------------------------------------+-------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                  ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                              ; To Node                                                       ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 2.515 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.305     ; 5.855      ;
; 2.515 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.305     ; 5.855      ;
; 2.515 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.305     ; 5.855      ;
; 2.516 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.305     ; 5.854      ;
; 2.535 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.366     ; 5.774      ;
; 2.544 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.352     ; 5.779      ;
; 2.544 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.352     ; 5.779      ;
; 2.544 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[15]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.353     ; 5.778      ;
; 2.544 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[14]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.353     ; 5.778      ;
; 2.547 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.350     ; 5.778      ;
; 2.547 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[0]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.362     ; 5.766      ;
; 2.547 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.350     ; 5.778      ;
; 2.552 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.343     ; 5.780      ;
; 2.552 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.343     ; 5.780      ;
; 2.552 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.185     ; 5.949      ;
; 2.552 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.185     ; 5.949      ;
; 2.552 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.185     ; 5.949      ;
; 2.552 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ba_reg[0]                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.189     ; 5.945      ;
; 2.552 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ras_n_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.189     ; 5.945      ;
; 2.552 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|we_n_reg                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.186     ; 5.948      ;
; 2.552 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ldqm_reg                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.186     ; 5.948      ;
; 2.552 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[0]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.188     ; 5.946      ;
; 2.552 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[1]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.187     ; 5.947      ;
; 2.552 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[3]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.186     ; 5.948      ;
; 2.553 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.357     ; 5.765      ;
; 2.553 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.357     ; 5.765      ;
; 2.553 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.185     ; 5.948      ;
; 2.553 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ba_reg[1]                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.187     ; 5.946      ;
; 2.553 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cas_n_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.188     ; 5.945      ;
; 2.553 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[2]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.186     ; 5.947      ;
; 2.553 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[10]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.187     ; 5.946      ;
; 2.557 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[9]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.230     ; 5.899      ;
; 2.564 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[7]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.226     ; 5.896      ;
; 2.564 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[8]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.226     ; 5.896      ;
; 2.566 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[4]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.223     ; 5.897      ;
; 2.566 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[5]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.225     ; 5.895      ;
; 2.566 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[6]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.231     ; 5.889      ;
; 2.566 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[11]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.233     ; 5.887      ;
; 2.572 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[1]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.246     ; 5.868      ;
; 2.575 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|udqm_reg                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.239     ; 5.872      ;
; 2.581 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.232     ; 5.873      ;
; 2.581 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[13]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.232     ; 5.873      ;
; 2.581 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.233     ; 5.872      ;
; 2.581 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.233     ; 5.872      ;
; 2.584 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[0]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.242     ; 5.860      ;
; 2.584 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.230     ; 5.872      ;
; 2.584 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[9]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.230     ; 5.872      ;
; 2.589 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.223     ; 5.874      ;
; 2.589 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.223     ; 5.874      ;
; 2.590 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.237     ; 5.859      ;
; 2.590 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.237     ; 5.859      ;
; 2.739 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.198     ; 5.713      ;
; 2.739 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_5   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.198     ; 5.713      ;
; 2.739 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_6   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.198     ; 5.713      ;
; 2.740 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_7   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.198     ; 5.712      ;
; 2.759 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.259     ; 5.632      ;
; 2.768 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.245     ; 5.637      ;
; 2.768 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.245     ; 5.637      ;
; 2.768 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.246     ; 5.636      ;
; 2.768 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.246     ; 5.636      ;
; 2.771 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.255     ; 5.624      ;
; 2.771 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.243     ; 5.636      ;
; 2.771 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.243     ; 5.636      ;
; 2.776 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.236     ; 5.638      ;
; 2.776 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.236     ; 5.638      ;
; 2.777 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.250     ; 5.623      ;
; 2.777 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.250     ; 5.623      ;
; 3.060 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.181     ; 5.571      ;
; 3.060 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.181     ; 5.571      ;
; 3.060 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.181     ; 5.571      ;
; 3.060 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.181     ; 5.571      ;
; 3.060 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.181     ; 5.571      ;
; 3.060 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.181     ; 5.571      ;
; 3.060 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.181     ; 5.571      ;
; 3.060 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.181     ; 5.571      ;
; 3.060 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.181     ; 5.571      ;
; 3.060 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.181     ; 5.571      ;
; 3.060 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.181     ; 5.571      ;
; 3.065 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.173     ; 5.574      ;
; 3.065 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.173     ; 5.574      ;
; 3.065 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.173     ; 5.574      ;
; 3.065 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.173     ; 5.574      ;
; 3.065 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.173     ; 5.574      ;
; 3.065 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.173     ; 5.574      ;
; 3.065 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.173     ; 5.574      ;
; 3.065 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.173     ; 5.574      ;
; 3.065 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.173     ; 5.574      ;
; 3.065 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.173     ; 5.574      ;
; 3.065 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.173     ; 5.574      ;
; 3.065 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.173     ; 5.574      ;
; 3.065 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.173     ; 5.574      ;
; 3.065 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.173     ; 5.574      ;
; 3.067 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[20]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.179     ; 5.566      ;
; 3.067 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[1]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.174     ; 5.571      ;
; 3.067 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[21]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.179     ; 5.566      ;
; 3.067 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[18]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.179     ; 5.566      ;
; 3.067 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[19]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.179     ; 5.566      ;
; 3.067 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[9]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.174     ; 5.571      ;
; 3.068 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[23]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.187     ; 5.557      ;
; 3.068 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[28]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.174     ; 5.570      ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                           ;
+--------+------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                              ; To Node                                                                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 10.529 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[3]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.071     ; 7.023      ;
; 10.529 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[0]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.071     ; 7.023      ;
; 10.529 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_input_reg[7]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.071     ; 7.023      ;
; 10.529 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[4]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.071     ; 7.023      ;
; 10.538 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|keycode_latch_reg[4] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.062     ; 7.023      ;
; 10.562 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[14]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.087     ; 6.974      ;
; 10.562 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[22]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.087     ; 6.974      ;
; 10.562 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[15]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.087     ; 6.974      ;
; 10.562 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[23]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.087     ; 6.974      ;
; 10.562 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[30]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.087     ; 6.974      ;
; 10.562 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[31]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.087     ; 6.974      ;
; 10.592 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.048     ; 6.983      ;
; 10.592 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[2]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.048     ; 6.983      ;
; 10.592 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[13]                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.048     ; 6.983      ;
; 10.592 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[15]                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.048     ; 6.983      ;
; 10.592 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[14]                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.048     ; 6.983      ;
; 10.592 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.048     ; 6.983      ;
; 10.592 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.048     ; 6.983      ;
; 10.592 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.048     ; 6.983      ;
; 10.615 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[3]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.173     ; 6.835      ;
; 10.615 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[0]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.173     ; 6.835      ;
; 10.615 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_input_reg[7]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.173     ; 6.835      ;
; 10.615 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[4]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.173     ; 6.835      ;
; 10.624 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|keycode_latch_reg[4] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.164     ; 6.835      ;
; 10.664 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[14]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.173     ; 6.786      ;
; 10.664 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[22]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.173     ; 6.786      ;
; 10.664 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[15]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.173     ; 6.786      ;
; 10.664 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[23]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.173     ; 6.786      ;
; 10.664 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[30]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.173     ; 6.786      ;
; 10.664 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[31]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.173     ; 6.786      ;
; 10.678 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.150     ; 6.795      ;
; 10.678 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[2]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.150     ; 6.795      ;
; 10.678 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[13]                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.150     ; 6.795      ;
; 10.678 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[15]                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.150     ; 6.795      ;
; 10.678 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[14]                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.150     ; 6.795      ;
; 10.678 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.150     ; 6.795      ;
; 10.678 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.150     ; 6.795      ;
; 10.678 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.150     ; 6.795      ;
; 10.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[3]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.072     ; 6.834      ;
; 10.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[0]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.072     ; 6.834      ;
; 10.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_input_reg[7]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.072     ; 6.834      ;
; 10.717 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[4]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.072     ; 6.834      ;
; 10.726 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|keycode_latch_reg[4] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.063     ; 6.834      ;
; 10.750 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[14]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.088     ; 6.785      ;
; 10.750 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[22]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.088     ; 6.785      ;
; 10.750 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[15]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.088     ; 6.785      ;
; 10.750 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[23]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.088     ; 6.785      ;
; 10.750 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[30]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.088     ; 6.785      ;
; 10.750 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[31]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.088     ; 6.785      ;
; 10.780 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.049     ; 6.794      ;
; 10.780 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[2]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.049     ; 6.794      ;
; 10.780 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[13]                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.049     ; 6.794      ;
; 10.780 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[15]                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.049     ; 6.794      ;
; 10.780 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[14]                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.049     ; 6.794      ;
; 10.780 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.049     ; 6.794      ;
; 10.780 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.049     ; 6.794      ;
; 10.780 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.049     ; 6.794      ;
; 10.964 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_holding_reg[0]                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.090     ; 6.569      ;
; 10.964 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_holding_reg[1]                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.090     ; 6.569      ;
; 10.964 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_holding_reg[2]                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.090     ; 6.569      ;
; 10.964 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_holding_reg[3]                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.090     ; 6.569      ;
; 10.964 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_holding_reg[4]                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.090     ; 6.569      ;
; 10.964 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_holding_reg[5]                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.090     ; 6.569      ;
; 10.964 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_holding_reg[6]                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.090     ; 6.569      ;
; 10.964 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_holding_reg[7]                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.090     ; 6.569      ;
; 10.964 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_shift_reg[8]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.090     ; 6.569      ;
; 10.964 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_shift_reg[7]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.090     ; 6.569      ;
; 10.964 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_shift_reg[6]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.090     ; 6.569      ;
; 10.964 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_shift_reg[5]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.090     ; 6.569      ;
; 10.964 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_shift_reg[4]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.090     ; 6.569      ;
; 10.964 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_shift_reg[3]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.090     ; 6.569      ;
; 10.964 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_shift_reg[2]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.090     ; 6.569      ;
; 10.964 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_shift_reg[1]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.090     ; 6.569      ;
; 10.964 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|syncreset_enable_divider:enable_64_div|count_reg[0]                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.098     ; 6.561      ;
; 10.964 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|syncreset_enable_divider:enable_64_div|count_reg[2]                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.098     ; 6.561      ;
; 10.964 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|syncreset_enable_divider:enable_64_div|count_reg[3]                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.098     ; 6.561      ;
; 10.964 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|syncreset_enable_divider:enable_64_div|count_reg[4]                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.098     ; 6.561      ;
; 10.964 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|syncreset_enable_divider:enable_64_div|count_reg[1]                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.098     ; 6.561      ;
; 10.964 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|syncreset_enable_divider:enable_64_div|enabled_out_reg                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.098     ; 6.561      ;
; 10.964 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|sizem_raw_reg[1]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.108     ; 6.551      ;
; 10.964 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|chan3_output_reg                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.093     ; 6.566      ;
; 10.964 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|noise_4_reg[1]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.094     ; 6.565      ;
; 10.964 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audc2_reg[7]                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.094     ; 6.565      ;
; 10.965 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|skctl_reg[1]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.092     ; 6.566      ;
; 10.965 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|skctl_reg[0]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.103     ; 6.555      ;
; 10.965 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pot0_reg[4]                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.097     ; 6.561      ;
; 10.965 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|serin_reg[4]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.097     ; 6.561      ;
; 10.965 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|bincnt_reg[0]        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.103     ; 6.555      ;
; 10.965 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|bincnt_reg[1]        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.103     ; 6.555      ;
; 10.965 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|bincnt_reg[2]        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.103     ; 6.555      ;
; 10.965 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|bincnt_reg[3]        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.103     ; 6.555      ;
; 10.965 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|compare_latch_reg[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.103     ; 6.555      ;
; 10.965 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|compare_latch_reg[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.103     ; 6.555      ;
; 10.965 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|bincnt_reg[4]        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.103     ; 6.555      ;
; 10.965 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|compare_latch_reg[4] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.103     ; 6.555      ;
; 10.965 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|bincnt_reg[5]        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.103     ; 6.555      ;
; 10.965 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|compare_latch_reg[5] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.103     ; 6.555      ;
; 10.965 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|state_reg[0]         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.103     ; 6.555      ;
; 10.965 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|state_reg[1]         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.103     ; 6.555      ;
; 10.965 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|compare_latch_reg[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.103     ; 6.555      ;
+--------+------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: 'CLOCK_27[0]'                                                                                                                                                                                                                                ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------+-----------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                              ; To Node                                                   ; Launch Clock                                                          ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------+-----------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.277 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 3.946      ; 3.983      ;
; -0.277 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 3.946      ; 3.983      ;
; -0.277 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 3.946      ; 3.983      ;
; -0.277 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 3.946      ; 3.983      ;
; -0.277 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 3.946      ; 3.983      ;
; -0.277 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 3.946      ; 3.983      ;
; -0.277 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 3.946      ; 3.983      ;
; -0.277 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 3.946      ; 3.983      ;
; -0.276 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 3.946      ; 3.984      ;
; -0.146 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 3.949      ; 4.117      ;
; -0.146 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 3.949      ; 4.117      ;
; -0.146 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 3.949      ; 4.117      ;
; -0.146 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 3.949      ; 4.117      ;
; -0.146 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 3.949      ; 4.117      ;
; -0.146 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 3.949      ; 4.117      ;
; -0.146 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 3.949      ; 4.117      ;
; -0.146 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 3.949      ; 4.117      ;
; -0.145 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 3.949      ; 4.118      ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------+-----------------------------------------------------------------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                         ; To Node                                                                                                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 1.542 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|dffe4                                                                 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|altsyncram_v6b1:altsyncram2|ram_block5a0                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.381      ; 2.113      ;
; 1.838 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a55 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.372      ;
; 1.838 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a54 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.372      ;
; 1.838 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a53 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.372      ;
; 1.838 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a52 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.372      ;
; 1.838 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a51 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.372      ;
; 1.838 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a50 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.372      ;
; 1.838 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a49 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.372      ;
; 1.838 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a48 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.372      ;
; 1.838 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a39 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.372      ;
; 1.838 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a38 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.372      ;
; 1.838 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a37 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.372      ;
; 1.838 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a36 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.372      ;
; 1.838 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a35 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.372      ;
; 1.838 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a34 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.372      ;
; 1.838 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a33 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.372      ;
; 1.838 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a32 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.372      ;
; 1.838 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a31 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.372      ;
; 1.838 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a30 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.372      ;
; 1.838 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a29 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.372      ;
; 1.838 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a28 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.372      ;
; 1.838 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a23 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.372      ;
; 1.838 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a22 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.372      ;
; 1.838 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a21 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.372      ;
; 1.838 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a20 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.372      ;
; 1.838 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a19 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.372      ;
; 1.838 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a18 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.372      ;
; 1.838 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a17 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.372      ;
; 1.838 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a16 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.372      ;
; 1.838 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a7  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.372      ;
; 1.838 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a6  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.372      ;
; 1.838 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a5  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.372      ;
; 1.838 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a4  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.372      ;
; 1.838 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a3  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.372      ;
; 1.838 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a2  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.372      ;
; 1.838 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a1  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.372      ;
; 1.838 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.372      ;
; 2.112 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a63 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.338      ; 2.640      ;
; 2.112 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a62 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.338      ; 2.640      ;
; 2.112 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a61 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.338      ; 2.640      ;
; 2.112 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a60 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.338      ; 2.640      ;
; 2.112 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a59 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.338      ; 2.640      ;
; 2.112 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a58 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.338      ; 2.640      ;
; 2.112 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a57 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.338      ; 2.640      ;
; 2.112 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a56 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.338      ; 2.640      ;
; 2.112 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a47 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.338      ; 2.640      ;
; 2.112 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a46 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.338      ; 2.640      ;
; 2.112 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a45 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.338      ; 2.640      ;
; 2.112 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a44 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.338      ; 2.640      ;
; 2.112 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a43 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.338      ; 2.640      ;
; 2.112 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a42 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.338      ; 2.640      ;
; 2.112 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a41 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.338      ; 2.640      ;
; 2.112 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a40 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.338      ; 2.640      ;
; 2.112 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a27 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.338      ; 2.640      ;
; 2.112 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a26 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.338      ; 2.640      ;
; 2.112 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a25 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.338      ; 2.640      ;
; 2.112 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a24 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.338      ; 2.640      ;
; 2.112 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a15 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.338      ; 2.640      ;
; 2.112 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a14 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.338      ; 2.640      ;
; 2.112 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a13 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.338      ; 2.640      ;
; 2.112 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a12 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.338      ; 2.640      ;
; 2.112 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a11 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.338      ; 2.640      ;
; 2.112 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a10 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.338      ; 2.640      ;
; 2.112 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a9  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.338      ; 2.640      ;
; 2.112 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a8  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.338      ; 2.640      ;
; 3.112 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[1]                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.650      ; 3.957      ;
; 3.116 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[25]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.644      ; 3.955      ;
; 3.144 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[21]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.632      ; 3.971      ;
; 3.144 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[18]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.632      ; 3.971      ;
; 3.144 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[22]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.632      ; 3.971      ;
; 3.150 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[6]                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.626      ; 3.971      ;
; 3.170 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[15]                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.616      ; 3.981      ;
; 3.187 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[13]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.590      ; 3.972      ;
; 3.187 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[23]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.590      ; 3.972      ;
; 3.187 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[11]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.590      ; 3.972      ;
; 3.188 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[10]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.588      ; 3.971      ;
; 3.188 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[14]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.588      ; 3.971      ;
; 3.200 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[0]                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.586      ; 3.981      ;
; 3.200 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[13]                                                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.581      ; 3.976      ;
; 3.200 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[15]                                                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.581      ; 3.976      ;
; 3.200 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[14]                                                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.581      ; 3.976      ;
; 3.208 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[0]                                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.571      ; 3.974      ;
; 3.329 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[25]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.565      ; 4.089      ;
; 3.341 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[1]                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.555      ; 4.091      ;
; 3.373 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[21]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.537      ; 4.105      ;
; 3.373 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[18]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.537      ; 4.105      ;
; 3.373 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[22]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.537      ; 4.105      ;
; 3.379 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[6]                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.531      ; 4.105      ;
; 3.399 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[15]                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.521      ; 4.115      ;
; 3.413 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[13]                                                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.502      ; 4.110      ;
; 3.413 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[15]                                                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.502      ; 4.110      ;
; 3.413 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[14]                                                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.502      ; 4.110      ;
; 3.416 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[13]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.495      ; 4.106      ;
; 3.416 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[23]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.495      ; 4.106      ;
; 3.416 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[11]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.495      ; 4.106      ;
; 3.417 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[10]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.493      ; 4.105      ;
; 3.417 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[14]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.493      ; 4.105      ;
; 3.421 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[0]                                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.492      ; 4.108      ;
; 3.429 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[0]                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.491      ; 4.115      ;
; 3.521 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[1]                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.669      ; 4.385      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                   ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                              ; To Node                                                       ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 4.359 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cke_reg                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 4.740      ;
; 4.365 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.174      ; 4.753      ;
; 4.365 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.174      ; 4.753      ;
; 4.365 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.174      ; 4.753      ;
; 4.365 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.174      ; 4.753      ;
; 4.365 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.174      ; 4.753      ;
; 4.365 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.174      ; 4.753      ;
; 4.365 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.174      ; 4.753      ;
; 4.365 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.174      ; 4.753      ;
; 4.365 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.174      ; 4.753      ;
; 4.365 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.174      ; 4.753      ;
; 4.365 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.174      ; 4.753      ;
; 4.365 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|reply_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 4.754      ;
; 4.365 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 4.754      ;
; 4.365 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.174      ; 4.753      ;
; 4.365 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 4.754      ;
; 4.365 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 4.754      ;
; 4.368 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[23]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.152      ; 4.734      ;
; 4.368 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[25]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.152      ; 4.734      ;
; 4.368 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[30]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.152      ; 4.734      ;
; 4.368 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[24]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.152      ; 4.734      ;
; 4.368 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[22]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.148      ; 4.730      ;
; 4.368 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[29]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.152      ; 4.734      ;
; 4.368 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[16]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.148      ; 4.730      ;
; 4.368 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[17]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.148      ; 4.730      ;
; 4.372 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[20]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.161      ; 4.747      ;
; 4.372 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[0]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 4.752      ;
; 4.372 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[3]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 4.752      ;
; 4.372 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[1]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 4.752      ;
; 4.372 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[4]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 4.752      ;
; 4.372 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[5]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 4.752      ;
; 4.372 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[7]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 4.752      ;
; 4.372 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[2]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 4.752      ;
; 4.372 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[6]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 4.752      ;
; 4.372 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[15]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 4.752      ;
; 4.372 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[13]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 4.752      ;
; 4.372 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[10]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 4.752      ;
; 4.372 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[21]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.161      ; 4.747      ;
; 4.372 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[8]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 4.752      ;
; 4.372 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[14]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 4.752      ;
; 4.372 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[18]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.161      ; 4.747      ;
; 4.372 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[12]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 4.752      ;
; 4.372 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[19]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.161      ; 4.747      ;
; 4.372 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[9]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 4.752      ;
; 4.372 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[11]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 4.752      ;
; 4.373 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 4.754      ;
; 4.373 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 4.754      ;
; 4.373 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 4.754      ;
; 4.373 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 4.754      ;
; 4.373 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 4.754      ;
; 4.373 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[28]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.165      ; 4.752      ;
; 4.373 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[31]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.165      ; 4.752      ;
; 4.373 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[26]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.165      ; 4.752      ;
; 4.373 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[27]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.165      ; 4.752      ;
; 4.373 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 4.754      ;
; 4.373 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 4.754      ;
; 4.373 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 4.754      ;
; 4.373 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 4.754      ;
; 4.373 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 4.754      ;
; 4.373 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 4.754      ;
; 4.373 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 4.754      ;
; 4.373 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 4.754      ;
; 4.373 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 4.754      ;
; 4.380 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 4.752      ;
; 4.380 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 4.752      ;
; 4.380 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 4.752      ;
; 4.380 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 4.752      ;
; 4.380 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 4.752      ;
; 4.380 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 4.752      ;
; 4.380 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 4.752      ;
; 4.380 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 4.752      ;
; 4.380 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 4.752      ;
; 4.380 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 4.752      ;
; 4.380 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 4.752      ;
; 4.553 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 4.847      ;
; 4.553 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_5   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 4.847      ;
; 4.553 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_6   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.145      ; 4.846      ;
; 4.553 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_7   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.145      ; 4.846      ;
; 4.570 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.091      ; 4.809      ;
; 4.570 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.091      ; 4.809      ;
; 4.574 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.106      ; 4.828      ;
; 4.574 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.106      ; 4.828      ;
; 4.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.087      ; 4.811      ;
; 4.580 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.096      ; 4.824      ;
; 4.580 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.096      ; 4.824      ;
; 4.582 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.098      ; 4.828      ;
; 4.582 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.098      ; 4.828      ;
; 4.584 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.097      ; 4.829      ;
; 4.584 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.097      ; 4.829      ;
; 4.588 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 4.819      ;
; 4.887 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ras_n_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 5.174      ;
; 4.888 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.160      ; 5.179      ;
; 4.888 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.160      ; 5.179      ;
; 4.888 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 5.178      ;
; 4.888 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 5.178      ;
; 4.888 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ba_reg[0]                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 5.175      ;
; 4.888 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ba_reg[1]                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 5.176      ;
; 4.888 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cas_n_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 5.175      ;
; 4.888 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|we_n_reg                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 5.178      ;
; 4.888 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ldqm_reg                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 5.178      ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                             ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                 ; Clock Edge ; Target                                                        ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------+
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cke_reg                      ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[16]             ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[17]             ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[22]             ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[23]             ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[24]             ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[25]             ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[29]             ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[30]             ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[0]              ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[10]             ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[11]             ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[12]             ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[13]             ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[14]             ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[15]             ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[18]             ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[19]             ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[1]              ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[20]             ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[21]             ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[26]             ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[27]             ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[28]             ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[2]              ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[31]             ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[3]              ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[4]              ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[5]              ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[6]              ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[7]              ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[8]              ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[9]              ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|reply_reg                    ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ;
; 4.206 ; 4.356        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[7]                  ;
; 4.206 ; 4.356        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[8]                  ;
; 4.206 ; 4.356        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]               ;
; 4.206 ; 4.356        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[13]               ;
; 4.206 ; 4.356        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]               ;
; 4.206 ; 4.356        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]               ;
; 4.207 ; 4.357        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[5]                  ;
; 4.207 ; 4.357        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[6]                  ;
; 4.207 ; 4.357        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[0]                ;
; 4.207 ; 4.357        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[1]                ;
; 4.208 ; 4.358        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[11]                 ;
; 4.208 ; 4.358        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[4]                  ;
; 4.208 ; 4.358        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[2]                ;
; 4.208 ; 4.358        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                ;
; 4.208 ; 4.358        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|udqm_reg                     ;
; 4.209 ; 4.359        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[9]                  ;
; 4.210 ; 4.365        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[10]                ;
; 4.210 ; 4.365        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[11]                ;
; 4.211 ; 4.361        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[0]                  ;
; 4.211 ; 4.361        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[10]                 ;
; 4.211 ; 4.361        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[1]                  ;
; 4.211 ; 4.361        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[2]                  ;
; 4.211 ; 4.361        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[3]                  ;
; 4.211 ; 4.361        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|ba_reg[0]                    ;
; 4.211 ; 4.361        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|ba_reg[1]                    ;
; 4.211 ; 4.361        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cas_n_reg                    ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                     ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                 ; Clock Edge ; Target                                                                                                                                ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+
; 4.243 ; 4.369        ; 0.126          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 4.330 ; 4.439        ; 0.109          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 4.369 ; 4.369        ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 4.439 ; 4.439        ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                         ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                 ; Clock Edge ; Target                                                                                                                                                    ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; 8.406 ; 8.788        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[0] ;
; 8.406 ; 8.788        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[1] ;
; 8.406 ; 8.788        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[2] ;
; 8.406 ; 8.788        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[3] ;
; 8.406 ; 8.788        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[4] ;
; 8.406 ; 8.788        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[10]      ;
; 8.406 ; 8.788        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[11]      ;
; 8.406 ; 8.788        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[12]      ;
; 8.406 ; 8.788        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[13]      ;
; 8.406 ; 8.788        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[14]      ;
; 8.406 ; 8.788        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[15]      ;
; 8.406 ; 8.788        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[16]      ;
; 8.406 ; 8.788        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[17]      ;
; 8.406 ; 8.788        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[18]      ;
; 8.406 ; 8.788        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[19]      ;
; 8.406 ; 8.788        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[20]      ;
; 8.406 ; 8.788        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[5]       ;
; 8.406 ; 8.788        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[6]       ;
; 8.406 ; 8.788        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[7]       ;
; 8.406 ; 8.788        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[8]       ;
; 8.406 ; 8.788        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[9]       ;
; 8.438 ; 8.820        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[0] ;
; 8.438 ; 8.820        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[1] ;
; 8.438 ; 8.820        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[2] ;
; 8.438 ; 8.820        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[3] ;
; 8.438 ; 8.820        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[4] ;
; 8.438 ; 8.820        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[10]      ;
; 8.438 ; 8.820        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[11]      ;
; 8.438 ; 8.820        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[12]      ;
; 8.438 ; 8.820        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[13]      ;
; 8.438 ; 8.820        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[14]      ;
; 8.438 ; 8.820        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[15]      ;
; 8.438 ; 8.820        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[16]      ;
; 8.438 ; 8.820        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[17]      ;
; 8.438 ; 8.820        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[18]      ;
; 8.438 ; 8.820        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[19]      ;
; 8.438 ; 8.820        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[20]      ;
; 8.438 ; 8.820        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[5]       ;
; 8.438 ; 8.820        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[6]       ;
; 8.438 ; 8.820        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[7]       ;
; 8.438 ; 8.820        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[8]       ;
; 8.438 ; 8.820        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[9]       ;
; 8.444 ; 8.660        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[1]                                                                                                         ;
; 8.448 ; 8.664        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[0]                                                                                 ;
; 8.448 ; 8.664        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[0]                                                                                                         ;
; 8.449 ; 8.665        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_32BIT_WRITE_ENABLE_reg                                                                                              ;
; 8.449 ; 8.665        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_8BIT_WRITE_ENABLE_reg                                                                                               ;
; 8.449 ; 8.665        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_READ_reg                                                                                                            ;
; 8.450 ; 8.666        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[20]                                                                                                        ;
; 8.450 ; 8.666        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[23]                                                                                                        ;
; 8.452 ; 8.668        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[0]                                          ;
; 8.452 ; 8.668        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[2]                                          ;
; 8.452 ; 8.668        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[3]                                          ;
; 8.452 ; 8.668        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[4]                                          ;
; 8.452 ; 8.668        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[5]                                          ;
; 8.452 ; 8.668        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[7]                                          ;
; 8.452 ; 8.668        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[11]                                   ;
; 8.452 ; 8.668        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[15]                                   ;
; 8.452 ; 8.668        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[17]                                   ;
; 8.452 ; 8.668        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[1]                                    ;
; 8.452 ; 8.668        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[20]                                   ;
; 8.452 ; 8.668        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[42]                                   ;
; 8.452 ; 8.668        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[5]                                    ;
; 8.452 ; 8.668        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[4]                                                                                                         ;
; 8.452 ; 8.668        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[0]                                                                                 ;
; 8.452 ; 8.668        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[3]                                                                                 ;
; 8.452 ; 8.668        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[6]                                                                                 ;
; 8.452 ; 8.668        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[7]                                                                                 ;
; 8.452 ; 8.668        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[13]                                                                     ;
; 8.452 ; 8.668        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[14]                                                                     ;
; 8.452 ; 8.668        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[15]                                                                     ;
; 8.453 ; 8.669        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.opcodeFetch                       ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[10]                                                  ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[7]                                                   ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[8]                                                   ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[9]                                                   ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_destination_reg[1]                                         ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|PC[1]                                         ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[6]                                          ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[28]                                   ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[31]                                   ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]~_Duplicate_7                      ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[68]                                                                                                            ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[11]                                                                     ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[12]                                                                     ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[0]                                                                                      ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[10]                                                                                     ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[11]                                                                                     ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[12]                                                                                     ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[13]                                                                                     ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[14]                                                                                     ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[15]                                                                                     ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[16]                                                                                     ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[17]                                                                                     ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[8]                                                                                      ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[9]                                                                                      ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[1]                                                                                                           ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[6]                                                                                                           ;
; 8.455 ; 8.671        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[2]                                          ;
; 8.455 ; 8.671        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[4]                                          ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                           ;
+--------+--------------+----------------+------------------+----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                ; Clock Edge ; Target                                                                                     ;
+--------+--------------+----------------+------------------+----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------+
; 16.279 ; 16.279       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 16.279 ; 16.279       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 16.283 ; 16.283       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 16.294 ; 16.294       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 16.294 ; 16.294       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 16.294 ; 16.294       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 16.294 ; 16.294       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]                      ;
; 16.294 ; 16.294       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 16.334 ; 16.334       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 16.334 ; 16.334       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 16.334 ; 16.334       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 16.334 ; 16.334       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]                      ;
; 16.334 ; 16.334       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 16.348 ; 16.348       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 16.351 ; 16.351       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 16.351 ; 16.351       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
+--------+--------------+----------------+------------------+----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK_27[0]'                                                                                                               ;
+--------+--------------+----------------+------------------+-------------+------------+--------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock       ; Clock Edge ; Target                                                                         ;
+--------+--------------+----------------+------------------+-------------+------------+--------------------------------------------------------------------------------+
; 18.273 ; 18.457       ; 0.184          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                      ;
; 18.273 ; 18.457       ; 0.184          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                      ;
; 18.273 ; 18.457       ; 0.184          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                      ;
; 18.273 ; 18.457       ; 0.184          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                      ;
; 18.273 ; 18.457       ; 0.184          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                      ;
; 18.273 ; 18.457       ; 0.184          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                      ;
; 18.273 ; 18.457       ; 0.184          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                      ;
; 18.273 ; 18.457       ; 0.184          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                      ;
; 18.273 ; 18.457       ; 0.184          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                        ;
; 18.344 ; 18.344       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                       ;
; 18.344 ; 18.344       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|observablevcoout             ;
; 18.351 ; 18.351       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 18.351 ; 18.351       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 18.360 ; 18.576       ; 0.216          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                      ;
; 18.360 ; 18.576       ; 0.216          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                      ;
; 18.360 ; 18.576       ; 0.216          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                      ;
; 18.360 ; 18.576       ; 0.216          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                      ;
; 18.360 ; 18.576       ; 0.216          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                      ;
; 18.360 ; 18.576       ; 0.216          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                      ;
; 18.360 ; 18.576       ; 0.216          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                      ;
; 18.360 ; 18.576       ; 0.216          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                      ;
; 18.360 ; 18.576       ; 0.216          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                        ;
; 18.400 ; 18.400       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~input|o                                                            ;
; 18.403 ; 18.403       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~inputclkctrl|inclk[0]                                              ;
; 18.403 ; 18.403       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~inputclkctrl|outclk                                                ;
; 18.406 ; 18.406       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[0]|clk                                          ;
; 18.406 ; 18.406       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[1]|clk                                          ;
; 18.406 ; 18.406       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[2]|clk                                          ;
; 18.406 ; 18.406       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[3]|clk                                          ;
; 18.406 ; 18.406       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[4]|clk                                          ;
; 18.406 ; 18.406       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[5]|clk                                          ;
; 18.406 ; 18.406       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[6]|clk                                          ;
; 18.406 ; 18.406       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[7]|clk                                          ;
; 18.406 ; 18.406       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_toggle_reg|clk                                            ;
; 18.423 ; 18.423       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|inclk[0]                     ;
; 18.430 ; 18.430       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~input|i                                                            ;
; 18.519 ; 18.519       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~input|i                                                            ;
; 18.606 ; 18.606       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 18.613 ; 18.613       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|inclk[0]                     ;
; 18.630 ; 18.630       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[0]|clk                                          ;
; 18.630 ; 18.630       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[1]|clk                                          ;
; 18.630 ; 18.630       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[2]|clk                                          ;
; 18.630 ; 18.630       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[3]|clk                                          ;
; 18.630 ; 18.630       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[4]|clk                                          ;
; 18.630 ; 18.630       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[5]|clk                                          ;
; 18.630 ; 18.630       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[6]|clk                                          ;
; 18.630 ; 18.630       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[7]|clk                                          ;
; 18.630 ; 18.630       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_toggle_reg|clk                                            ;
; 18.633 ; 18.633       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~inputclkctrl|inclk[0]                                              ;
; 18.633 ; 18.633       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~inputclkctrl|outclk                                                ;
; 18.637 ; 18.637       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~input|o                                                            ;
; 18.684 ; 18.684       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 18.684 ; 18.684       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 18.691 ; 18.691       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                       ;
; 18.691 ; 18.691       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|observablevcoout             ;
; 33.037 ; 37.037       ; 4.000          ; Port Rate        ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]                                                                    ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                        ;
+--------+--------------+----------------+------------------+-------------+------------+--------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                            ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                                                                                                                                                                                                      ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 40.596 ; 41.606       ; 1.010          ; Low Pulse Width  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ;
; 40.713 ; 41.723       ; 1.010          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                               ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                               ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                               ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                               ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[0]                                                                                                                                                        ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[1]                                                                                                                                                        ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                                                                                                                                 ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[0]                                                                                                                                                                       ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[10]                                                                                                                                                                      ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[11]                                                                                                                                                                      ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[12]                                                                                                                                                                      ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[13]                                                                                                                                                                      ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[14]                                                                                                                                                                      ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[15]                                                                                                                                                                      ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[16]                                                                                                                                                                      ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[17]                                                                                                                                                                      ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[18]                                                                                                                                                                      ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[19]                                                                                                                                                                      ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                                       ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[20]                                                                                                                                                                      ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[21]                                                                                                                                                                      ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[22]                                                                                                                                                                      ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[23]                                                                                                                                                                      ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[24]                                                                                                                                                                      ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                                       ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                                       ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                                       ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                                       ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                                       ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                                       ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[8]                                                                                                                                                                       ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[9]                                                                                                                                                                       ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                            ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|reset_n_reg                                                                                                                                                                                    ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                                                        ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C4_ena_state                                                                  ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                  ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_init_state                                                           ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                           ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reset_state                                                                   ;
; 41.364 ; 41.580       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|areset_init_state_1                                           ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|configupdate2_state                                                           ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|configupdate_state                                                            ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[0]                 ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[1]                 ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[2]                 ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[3]                 ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[4]                 ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[5]                 ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[6]                 ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[7]                 ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[0]                 ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1]                 ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2]                 ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3]                 ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[4]                 ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5]                 ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[0]                 ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1]                 ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2]                 ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3]                 ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4]                 ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0]                 ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1]                 ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[2]                 ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[3]                 ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[4]                 ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[5]                 ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[6]                 ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[7]                 ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                           ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_seq_data_state                                                       ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_seq_ena_state                                                        ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_data_state                                                 ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_ena_state                                                  ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_data_state                                                 ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_ena_state                                                  ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C2_data_state                                                 ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C2_ena_state                                                  ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_data_state                                                 ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_ena_state                                                  ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C4_data_state                                                 ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C4_ena_state                                                  ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|configupdate2_state                                           ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|configupdate_state                                            ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[0] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[1] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[2] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[3] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[4] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[5] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[6] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[7] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[0] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2] ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]'                                                                                                                                                                         ;
+-----------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+
; Slack     ; Actual Width ; Required Width ; Type             ; Clock                                                                 ; Clock Edge ; Target                                                                                                                                ;
+-----------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+
; 44052.511 ; 44052.727    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ;
; 44052.511 ; 44052.727    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_kbd_data                                                                                                       ;
; 44052.511 ; 44052.727    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ;
; 44052.511 ; 44052.727    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[1]                                                                                                    ;
; 44052.511 ; 44052.727    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[2]                                                                                                    ;
; 44052.511 ; 44052.727    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[3]                                                                                                    ;
; 44052.512 ; 44052.728    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_parity                                                                                                         ;
; 44052.512 ; 44052.728    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_r_inc                                                                                                          ;
; 44052.512 ; 44052.728    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[0]                                                                                                        ;
; 44052.512 ; 44052.728    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[1]                                                                                                        ;
; 44052.512 ; 44052.728    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[2]                                                                                                        ;
; 44052.512 ; 44052.728    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ;
; 44052.512 ; 44052.728    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ;
; 44052.512 ; 44052.728    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ;
; 44052.512 ; 44052.728    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ;
; 44052.512 ; 44052.728    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ;
; 44052.512 ; 44052.728    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ;
; 44052.512 ; 44052.728    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ;
; 44052.512 ; 44052.728    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ;
; 44052.657 ; 44052.783    ; 0.126          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Fall       ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 44052.722 ; 44052.906    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ;
; 44052.722 ; 44052.906    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_kbd_data                                                                                                       ;
; 44052.722 ; 44052.906    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_parity                                                                                                         ;
; 44052.722 ; 44052.906    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_r_inc                                                                                                          ;
; 44052.722 ; 44052.906    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[0]                                                                                                        ;
; 44052.722 ; 44052.906    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[1]                                                                                                        ;
; 44052.722 ; 44052.906    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[2]                                                                                                        ;
; 44052.722 ; 44052.906    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ;
; 44052.722 ; 44052.906    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ;
; 44052.722 ; 44052.906    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ;
; 44052.722 ; 44052.906    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ;
; 44052.722 ; 44052.906    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ;
; 44052.722 ; 44052.906    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ;
; 44052.722 ; 44052.906    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ;
; 44052.722 ; 44052.906    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ;
; 44052.722 ; 44052.906    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ;
; 44052.722 ; 44052.906    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[1]                                                                                                    ;
; 44052.722 ; 44052.906    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[2]                                                                                                    ;
; 44052.722 ; 44052.906    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[3]                                                                                                    ;
; 44052.744 ; 44052.853    ; 0.109          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Fall       ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 44052.781 ; 44052.781    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|Equal5~0_NEW_REG0|clk                                                                                                      ;
; 44052.781 ; 44052.781    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_kbd_data|clk                                                                                                           ;
; 44052.781 ; 44052.781    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[0]|clk                                                                                                        ;
; 44052.781 ; 44052.781    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[1]|clk                                                                                                        ;
; 44052.781 ; 44052.781    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[2]|clk                                                                                                        ;
; 44052.781 ; 44052.781    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[3]|clk                                                                                                        ;
; 44052.782 ; 44052.782    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_parity|clk                                                                                                             ;
; 44052.782 ; 44052.782    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_r_inc|clk                                                                                                              ;
; 44052.782 ; 44052.782    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_rptr[0]|clk                                                                                                            ;
; 44052.782 ; 44052.782    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_rptr[1]|clk                                                                                                            ;
; 44052.782 ; 44052.782    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_rptr[2]|clk                                                                                                            ;
; 44052.782 ; 44052.782    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[0]|clk                                                                                                         ;
; 44052.782 ; 44052.782    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[1]|clk                                                                                                         ;
; 44052.782 ; 44052.782    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[2]|clk                                                                                                         ;
; 44052.782 ; 44052.782    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[3]|clk                                                                                                         ;
; 44052.782 ; 44052.782    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[4]|clk                                                                                                         ;
; 44052.782 ; 44052.782    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[5]|clk                                                                                                         ;
; 44052.782 ; 44052.782    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[6]|clk                                                                                                         ;
; 44052.782 ; 44052.782    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[7]|clk                                                                                                         ;
; 44052.783 ; 44052.783    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; pll_switcher|\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 44052.783 ; 44052.783    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; pll_switcher|\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|outclk                                                 ;
; 44052.853 ; 44052.853    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; pll_switcher|\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 44052.853 ; 44052.853    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; pll_switcher|\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|outclk                                                 ;
; 44052.855 ; 44052.855    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|Equal5~0_NEW_REG0|clk                                                                                                      ;
; 44052.855 ; 44052.855    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_kbd_data|clk                                                                                                           ;
; 44052.855 ; 44052.855    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_parity|clk                                                                                                             ;
; 44052.855 ; 44052.855    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_r_inc|clk                                                                                                              ;
; 44052.855 ; 44052.855    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_rptr[0]|clk                                                                                                            ;
; 44052.855 ; 44052.855    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_rptr[1]|clk                                                                                                            ;
; 44052.855 ; 44052.855    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_rptr[2]|clk                                                                                                            ;
; 44052.855 ; 44052.855    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[0]|clk                                                                                                         ;
; 44052.855 ; 44052.855    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[1]|clk                                                                                                         ;
; 44052.855 ; 44052.855    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[2]|clk                                                                                                         ;
; 44052.855 ; 44052.855    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[3]|clk                                                                                                         ;
; 44052.855 ; 44052.855    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[4]|clk                                                                                                         ;
; 44052.855 ; 44052.855    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[5]|clk                                                                                                         ;
; 44052.855 ; 44052.855    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[6]|clk                                                                                                         ;
; 44052.855 ; 44052.855    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[7]|clk                                                                                                         ;
; 44052.855 ; 44052.855    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[0]|clk                                                                                                        ;
; 44052.855 ; 44052.855    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[1]|clk                                                                                                        ;
; 44052.855 ; 44052.855    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[2]|clk                                                                                                        ;
; 44052.855 ; 44052.855    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[3]|clk                                                                                                        ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_kbd_data                                                                                                       ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_parity                                                                                                         ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_r_inc                                                                                                          ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[0]                                                                                                        ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[1]                                                                                                        ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[2]                                                                                                        ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[1]                                                                                                    ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[2]                                                                                                    ;
+-----------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                      ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 2.637 ; 2.750 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 2.632 ; 2.745 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 2.636 ; 2.749 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 2.637 ; 2.750 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 2.637 ; 2.750 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 2.581 ; 2.698 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 2.591 ; 2.708 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 2.581 ; 2.698 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 2.581 ; 2.698 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 2.610 ; 2.723 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 2.610 ; 2.723 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 2.613 ; 2.726 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 2.613 ; 2.726 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 2.622 ; 2.735 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 2.622 ; 2.735 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 2.633 ; 2.746 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 2.633 ; 2.746 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                         ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; SDRAM_DQ[*]   ; CLOCK_27[0] ; -1.686 ; -1.804 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; -1.739 ; -1.853 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; -1.743 ; -1.857 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; -1.745 ; -1.859 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; -1.745 ; -1.859 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; -1.686 ; -1.804 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; -1.696 ; -1.814 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; -1.687 ; -1.805 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; -1.687 ; -1.805 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; -1.718 ; -1.832 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; -1.718 ; -1.832 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; -1.720 ; -1.834 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; -1.720 ; -1.834 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; -1.729 ; -1.843 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; -1.729 ; -1.843 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; -1.740 ; -1.854 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; -1.740 ; -1.854 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                              ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; SDRAM_A[*]    ; CLOCK_27[0] ; 2.750  ; 2.412  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; CLOCK_27[0] ; 2.525  ; 2.238  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; CLOCK_27[0] ; 2.527  ; 2.240  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; CLOCK_27[0] ; 2.527  ; 2.240  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; CLOCK_27[0] ; 2.538  ; 2.251  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; CLOCK_27[0] ; 2.449  ; 2.188  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; CLOCK_27[0] ; 2.750  ; 2.412  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; CLOCK_27[0] ; 2.734  ; 2.396  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; CLOCK_27[0] ; 2.739  ; 2.401  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; CLOCK_27[0] ; 2.739  ; 2.401  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; CLOCK_27[0] ; 2.735  ; 2.397  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; CLOCK_27[0] ; 2.526  ; 2.239  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; CLOCK_27[0] ; 2.742  ; 2.404  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; CLOCK_27[0] ; 2.525  ; 2.238  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; CLOCK_27[0] ; 2.525  ; 2.238  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; CLOCK_27[0] ; 2.516  ; 2.229  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CKE     ; CLOCK_27[0] ; 2.786  ; 2.519  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 2.742  ; 2.404  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 2.723  ; 2.385  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 2.719  ; 2.381  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 2.434  ; 2.173  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 2.434  ; 2.173  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 2.539  ; 2.252  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 2.549  ; 2.262  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 2.538  ; 2.251  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 2.538  ; 2.251  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 2.724  ; 2.386  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 2.724  ; 2.386  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 2.742  ; 2.404  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 2.742  ; 2.404  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 2.430  ; 2.169  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 2.733  ; 2.395  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 2.742  ; 2.404  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 2.439  ; 2.178  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH    ; CLOCK_27[0] ; 2.715  ; 2.377  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML    ; CLOCK_27[0] ; 2.538  ; 2.251  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nCAS    ; CLOCK_27[0] ; 2.525  ; 2.238  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nRAS    ; CLOCK_27[0] ; 2.525  ; 2.238  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nWE     ; CLOCK_27[0] ; 2.538  ; 2.251  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L       ; CLOCK_27[0] ; 5.351  ; 4.759  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R       ; CLOCK_27[0] ; 5.612  ; 4.985  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; LED           ; CLOCK_27[0] ; 5.610  ; 6.466  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]      ; CLOCK_27[0] ; 25.244 ; 24.480 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; CLOCK_27[0] ; 24.671 ; 23.937 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; CLOCK_27[0] ; 25.244 ; 24.480 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; CLOCK_27[0] ; 24.561 ; 23.977 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; CLOCK_27[0] ; 22.533 ; 22.094 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[4]     ; CLOCK_27[0] ; 23.394 ; 22.714 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[5]     ; CLOCK_27[0] ; 23.224 ; 22.514 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; CLOCK_27[0] ; 25.192 ; 24.658 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; CLOCK_27[0] ; 25.162 ; 24.477 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; CLOCK_27[0] ; 25.192 ; 24.658 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; CLOCK_27[0] ; 25.028 ; 24.342 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; CLOCK_27[0] ; 24.346 ; 23.828 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[4]     ; CLOCK_27[0] ; 22.972 ; 22.395 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[5]     ; CLOCK_27[0] ; 18.256 ; 17.450 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS        ; CLOCK_27[0] ; 6.308  ; 5.483  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]      ; CLOCK_27[0] ; 29.102 ; 28.358 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]     ; CLOCK_27[0] ; 27.746 ; 26.978 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]     ; CLOCK_27[0] ; 28.259 ; 27.792 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]     ; CLOCK_27[0] ; 29.102 ; 28.358 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]     ; CLOCK_27[0] ; 27.332 ; 26.730 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[4]     ; CLOCK_27[0] ; 26.842 ; 26.182 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[5]     ; CLOCK_27[0] ; 26.666 ; 25.867 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS        ; CLOCK_27[0] ; 6.036  ; 5.459  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; CLOCK_27[0] ; -0.537 ;        ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; CLOCK_27[0] ;        ; -0.929 ; Fall       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                      ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; SDRAM_A[*]    ; CLOCK_27[0] ; 1.724  ; 1.464  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; CLOCK_27[0] ; 1.799  ; 1.513  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; CLOCK_27[0] ; 1.800  ; 1.514  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; CLOCK_27[0] ; 1.801  ; 1.515  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; CLOCK_27[0] ; 1.811  ; 1.525  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; CLOCK_27[0] ; 1.724  ; 1.464  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; CLOCK_27[0] ; 2.025  ; 1.688  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; CLOCK_27[0] ; 2.009  ; 1.672  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; CLOCK_27[0] ; 2.014  ; 1.677  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; CLOCK_27[0] ; 2.014  ; 1.677  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; CLOCK_27[0] ; 2.010  ; 1.673  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; CLOCK_27[0] ; 1.800  ; 1.514  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; CLOCK_27[0] ; 2.017  ; 1.680  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; CLOCK_27[0] ; 1.790  ; 1.504  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; CLOCK_27[0] ; 1.798  ; 1.512  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; CLOCK_27[0] ; 1.790  ; 1.504  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CKE     ; CLOCK_27[0] ; 2.054  ; 1.787  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 1.705  ; 1.445  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 1.998  ; 1.661  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 1.994  ; 1.657  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 1.710  ; 1.450  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 1.710  ; 1.450  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 1.812  ; 1.526  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 1.822  ; 1.536  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 1.812  ; 1.526  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 1.812  ; 1.526  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 2.000  ; 1.663  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 2.000  ; 1.663  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 2.017  ; 1.680  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 2.017  ; 1.680  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 1.705  ; 1.445  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 2.008  ; 1.671  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 2.017  ; 1.680  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 1.714  ; 1.454  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH    ; CLOCK_27[0] ; 1.991  ; 1.654  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML    ; CLOCK_27[0] ; 1.811  ; 1.525  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nCAS    ; CLOCK_27[0] ; 1.799  ; 1.513  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nRAS    ; CLOCK_27[0] ; 1.798  ; 1.512  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nWE     ; CLOCK_27[0] ; 1.811  ; 1.525  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L       ; CLOCK_27[0] ; 4.593  ; 4.005  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R       ; CLOCK_27[0] ; 4.842  ; 4.221  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; LED           ; CLOCK_27[0] ; 4.821  ; 5.661  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]      ; CLOCK_27[0] ; 4.398  ; 4.064  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; CLOCK_27[0] ; 4.853  ; 4.306  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; CLOCK_27[0] ; 4.957  ; 4.462  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; CLOCK_27[0] ; 4.398  ; 4.064  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; CLOCK_27[0] ; 5.034  ; 4.592  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[4]     ; CLOCK_27[0] ; 5.279  ; 4.723  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[5]     ; CLOCK_27[0] ; 5.308  ; 4.689  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; CLOCK_27[0] ; 5.256  ; 4.712  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; CLOCK_27[0] ; 5.256  ; 4.712  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; CLOCK_27[0] ; 5.303  ; 4.816  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; CLOCK_27[0] ; 5.583  ; 4.901  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; CLOCK_27[0] ; 5.434  ; 4.894  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[4]     ; CLOCK_27[0] ; 5.566  ; 4.812  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[5]     ; CLOCK_27[0] ; 5.714  ; 4.905  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS        ; CLOCK_27[0] ; 5.511  ; 4.701  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]      ; CLOCK_27[0] ; 4.560  ; 3.828  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]     ; CLOCK_27[0] ; 4.560  ; 3.828  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]     ; CLOCK_27[0] ; 5.019  ; 4.428  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]     ; CLOCK_27[0] ; 6.276  ; 5.627  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]     ; CLOCK_27[0] ; 6.628  ; 6.033  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[4]     ; CLOCK_27[0] ; 5.748  ; 4.868  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[5]     ; CLOCK_27[0] ; 6.018  ; 5.162  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS        ; CLOCK_27[0] ; 5.251  ; 4.678  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; CLOCK_27[0] ; -1.224 ;        ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; CLOCK_27[0] ;        ; -1.610 ; Fall       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+


+----------------------------------------------------------+
; Propagation Delay                                        ;
+------------+-------------+-------+-------+-------+-------+
; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
+------------+-------------+-------+-------+-------+-------+
; CONF_DATA0 ; SPI_DO      ; 8.771 ; 8.700 ; 9.148 ; 9.148 ;
+------------+-------------+-------+-------+-------+-------+


+----------------------------------------------------------+
; Minimum Propagation Delay                                ;
+------------+-------------+-------+-------+-------+-------+
; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
+------------+-------------+-------+-------+-------+-------+
; CONF_DATA0 ; SPI_DO      ; 8.373 ; 8.237 ; 8.601 ; 8.601 ;
+------------+-------------+-------+-------+-------+-------+


+----------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                              ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 2.530 ; 2.530 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 2.534 ; 2.534 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 2.530 ; 2.530 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 2.548 ; 2.548 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 2.548 ; 2.548 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 2.635 ; 2.635 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 2.645 ; 2.645 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 2.634 ; 2.634 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 2.634 ; 2.634 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 2.535 ; 2.535 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 2.535 ; 2.535 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 2.553 ; 2.553 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 2.553 ; 2.553 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 2.544 ; 2.544 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 2.544 ; 2.544 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 2.553 ; 2.553 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 2.553 ; 2.553 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                      ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 1.283 ; 1.317 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 1.287 ; 1.321 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 1.283 ; 1.317 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 1.302 ; 1.336 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 1.302 ; 1.336 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 1.353 ; 1.386 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 1.363 ; 1.396 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 1.353 ; 1.386 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 1.353 ; 1.386 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 1.289 ; 1.323 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 1.289 ; 1.323 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 1.306 ; 1.340 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 1.306 ; 1.340 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 1.297 ; 1.331 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 1.297 ; 1.331 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 1.306 ; 1.340 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 1.306 ; 1.340 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                     ;
+---------------+-------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 2.209     ; 2.606     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 2.213     ; 2.610     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 2.209     ; 2.606     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 2.227     ; 2.624     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 2.227     ; 2.624     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 2.290     ; 2.711     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 2.300     ; 2.721     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 2.289     ; 2.710     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 2.289     ; 2.710     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 2.214     ; 2.611     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 2.214     ; 2.611     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 2.232     ; 2.629     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 2.232     ; 2.629     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 2.223     ; 2.620     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 2.223     ; 2.620     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 2.232     ; 2.629     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 2.232     ; 2.629     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+-------------+-----------+-----------+------------+-----------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                             ;
+---------------+-------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 1.356     ; 1.356     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 1.360     ; 1.360     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 1.356     ; 1.356     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 1.375     ; 1.375     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 1.375     ; 1.375     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 1.426     ; 1.426     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 1.436     ; 1.436     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 1.426     ; 1.426     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 1.426     ; 1.426     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 1.362     ; 1.362     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 1.362     ; 1.362     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 1.379     ; 1.379     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 1.379     ; 1.379     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 1.370     ; 1.370     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 1.370     ; 1.370     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 1.379     ; 1.379     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 1.379     ; 1.379     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+-------------+-----------+-----------+------------+-----------------------------------------------------------------------+


---------------------------------------------
; Slow 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup Summary                                                             ;
+-----------------------------------------------------------------------+--------+---------------+
; Clock                                                                 ; Slack  ; End Point TNS ;
+-----------------------------------------------------------------------+--------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; -2.320 ; -4.912        ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 0.213  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 0.392  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 2.829  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 13.668 ; 0.000         ;
; CLOCK_27[0]                                                           ; 35.609 ; 0.000         ;
+-----------------------------------------------------------------------+--------+---------------+


+------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold Summary                                                              ;
+-----------------------------------------------------------------------+--------+---------------+
; Clock                                                                 ; Slack  ; End Point TNS ;
+-----------------------------------------------------------------------+--------+---------------+
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; -1.078 ; -1.078        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.136  ; 0.000         ;
; CLOCK_27[0]                                                           ; 0.186  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.186  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.186  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 8.109  ; 0.000         ;
+-----------------------------------------------------------------------+--------+---------------+


+------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery Summary                                                          ;
+-----------------------------------------------------------------------+--------+---------------+
; Clock                                                                 ; Slack  ; End Point TNS ;
+-----------------------------------------------------------------------+--------+---------------+
; CLOCK_27[0]                                                           ; -0.426 ; -3.834        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.725  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 14.146 ; 0.000         ;
+-----------------------------------------------------------------------+--------+---------------+


+------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal Summary                                                           ;
+-----------------------------------------------------------------------+--------+---------------+
; Clock                                                                 ; Slack  ; End Point TNS ;
+-----------------------------------------------------------------------+--------+---------------+
; CLOCK_27[0]                                                           ; -0.363 ; -3.266        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.727  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 2.227  ; 0.000         ;
+-----------------------------------------------------------------------+--------+---------------+


+---------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width Summary                                                  ;
+-----------------------------------------------------------------------+-----------+---------------+
; Clock                                                                 ; Slack     ; End Point TNS ;
+-----------------------------------------------------------------------+-----------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 4.186     ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 4.331     ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.560     ; 0.000         ;
; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; 16.300    ; 0.000         ;
; CLOCK_27[0]                                                           ; 17.784    ; 0.000         ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 40.631    ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 44052.600 ; 0.000         ;
+-----------------------------------------------------------------------+-----------+---------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                               ;
+--------+-------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                               ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; -2.320 ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|synchronizer:tick_toggle_synchronizer|ff_reg[2]                                               ; CLOCK_27[0]                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.150        ; -2.016     ; 0.371      ;
; -1.296 ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                             ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[2]                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.354        ; -1.115     ; 0.372      ;
; -1.296 ; switch_pal_ntsc:pll_switcher|reset_n_reg                                                                                ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[2]                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.354        ; -1.115     ; 0.372      ;
; 1.313  ; user_io:my_user_io|Equal5~0_OTERM1                                                                                      ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|synchronizer:sync_clk|ff_reg[2]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 1.809        ; -0.086     ; 0.397      ;
; 1.322  ; user_io:my_user_io|ps2_kbd_data                                                                                         ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|synchronizer:sync_dat|ff_reg[2]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 1.809        ; -0.086     ; 0.388      ;
; 1.663  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]                                                   ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|synchronizer:sync_clk|ff_reg[2]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 1.809        ; 1.946      ; 2.079      ;
; 1.939  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]                                                   ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|synchronizer:sync_clk|ff_reg[2]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 2.128        ; 1.946      ; 2.122      ;
; 7.173  ; sdram_statemachine:sdram_adaptor|data_out_reg[3]                                                                        ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[3]                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.097     ; 1.528      ;
; 7.234  ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0]                                             ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:1:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.810        ; -0.961     ; 0.543      ;
; 7.309  ; sdram_statemachine:sdram_adaptor|data_out_reg[2]                                                                        ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[2]                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.097     ; 1.392      ;
; 7.332  ; sdram_statemachine:sdram_adaptor|data_out_reg[1]                                                                        ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[1]                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.097     ; 1.369      ;
; 7.346  ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                                                                     ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.098     ; 1.354      ;
; 7.407  ; sdram_statemachine:sdram_adaptor|data_out_reg[7]                                                                        ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[7]                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; 0.090      ; 1.481      ;
; 7.431  ; sdram_statemachine:sdram_adaptor|data_out_reg[4]                                                                        ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[4]                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; 0.107      ; 1.474      ;
; 7.461  ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                                                                     ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.098     ; 1.239      ;
; 7.568  ; sdram_statemachine:sdram_adaptor|data_out_reg[6]                                                                        ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[6]                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; 0.088      ; 1.318      ;
; 7.603  ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                                                                     ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.098     ; 1.097      ;
; 7.612  ; sdram_statemachine:sdram_adaptor|data_out_reg[5]                                                                        ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[5]                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; 0.100      ; 1.286      ;
; 7.668  ; sdram_statemachine:sdram_adaptor|data_out_reg[0]                                                                        ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[0]                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; 0.094      ; 1.224      ;
; 7.698  ; sdram_statemachine:sdram_adaptor|data_out_reg[11]                                                                       ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[11]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.101     ; 0.999      ;
; 7.731  ; sdram_statemachine:sdram_adaptor|data_out_reg[12]                                                                       ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[12]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.101     ; 0.966      ;
; 7.784  ; sdram_statemachine:sdram_adaptor|data_out_reg[13]                                                                       ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[13]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.101     ; 0.913      ;
; 7.785  ; sdram_statemachine:sdram_adaptor|data_out_reg[14]                                                                       ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[14]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.101     ; 0.912      ;
; 7.904  ; sdram_statemachine:sdram_adaptor|data_out_reg[9]                                                                        ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[9]                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.097     ; 0.797      ;
; 7.905  ; sdram_statemachine:sdram_adaptor|data_out_reg[15]                                                                       ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[15]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.097     ; 0.796      ;
; 7.935  ; sdram_statemachine:sdram_adaptor|data_out_reg[10]                                                                       ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[10]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.093     ; 0.770      ;
; 7.987  ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                                                                     ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.085     ; 0.726      ;
; 8.070  ; sdram_statemachine:sdram_adaptor|reply_reg                                                                              ; sdram_statemachine:sdram_adaptor|reply_sreg                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.086     ; 0.642      ;
; 8.102  ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                                                                     ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.085     ; 0.611      ;
; 8.136  ; sdram_statemachine:sdram_adaptor|data_out_reg[8]                                                                        ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[8]                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.097     ; 0.565      ;
; 8.158  ; sdram_statemachine:sdram_adaptor|data_out_reg[20]                                                                       ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[20]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.097     ; 0.543      ;
; 8.160  ; sdram_statemachine:sdram_adaptor|data_out_reg[28]                                                                       ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[28]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.097     ; 0.541      ;
; 8.160  ; sdram_statemachine:sdram_adaptor|data_out_reg[18]                                                                       ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[18]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.097     ; 0.541      ;
; 8.169  ; sdram_statemachine:sdram_adaptor|data_out_reg[29]                                                                       ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[29]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.085     ; 0.544      ;
; 8.170  ; sdram_statemachine:sdram_adaptor|data_out_reg[23]                                                                       ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[23]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.085     ; 0.543      ;
; 8.170  ; sdram_statemachine:sdram_adaptor|data_out_reg[22]                                                                       ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[22]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.085     ; 0.543      ;
; 8.171  ; sdram_statemachine:sdram_adaptor|data_out_reg[30]                                                                       ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[30]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.085     ; 0.542      ;
; 8.171  ; sdram_statemachine:sdram_adaptor|data_out_reg[17]                                                                       ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[17]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.085     ; 0.542      ;
; 8.200  ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                                                                     ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.085     ; 0.513      ;
; 8.260  ; sdram_statemachine:sdram_adaptor|data_out_reg[21]                                                                       ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[21]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.097     ; 0.441      ;
; 8.260  ; sdram_statemachine:sdram_adaptor|data_out_reg[27]                                                                       ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[27]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.097     ; 0.441      ;
; 8.261  ; sdram_statemachine:sdram_adaptor|data_out_reg[26]                                                                       ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[26]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.097     ; 0.440      ;
; 8.262  ; sdram_statemachine:sdram_adaptor|data_out_reg[19]                                                                       ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[19]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.097     ; 0.439      ;
; 8.263  ; sdram_statemachine:sdram_adaptor|data_out_reg[31]                                                                       ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[31]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.097     ; 0.438      ;
; 8.272  ; sdram_statemachine:sdram_adaptor|data_out_reg[25]                                                                       ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[25]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.085     ; 0.441      ;
; 8.273  ; sdram_statemachine:sdram_adaptor|data_out_reg[24]                                                                       ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[24]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.085     ; 0.440      ;
; 8.275  ; sdram_statemachine:sdram_adaptor|data_out_reg[16]                                                                       ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[16]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.085     ; 0.438      ;
; 10.433 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_out_OTERM131             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[2]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.137      ; 7.312      ;
; 10.433 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_out_OTERM131             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[6]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.137      ; 7.312      ;
; 10.433 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_out_OTERM131             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[3]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.137      ; 7.312      ;
; 10.445 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[2]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.153      ; 7.316      ;
; 10.445 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[6]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.153      ; 7.316      ;
; 10.445 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[3]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.153      ; 7.316      ;
; 10.483 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_out_OTERM131             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[0]~_Duplicate_4         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.135      ; 7.260      ;
; 10.495 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[0]~_Duplicate_4         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.151      ; 7.264      ;
; 10.495 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_out_OTERM131             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|PC[9]                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.056     ; 7.057      ;
; 10.501 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[2]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.153      ; 7.260      ;
; 10.501 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[6]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.153      ; 7.260      ;
; 10.501 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[3]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.153      ; 7.260      ;
; 10.504 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_enable~0_OTERM3       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[2]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.141      ; 7.245      ;
; 10.504 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_enable~0_OTERM3       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[6]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.141      ; 7.245      ;
; 10.504 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_enable~0_OTERM3       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[3]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.141      ; 7.245      ;
; 10.506 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[2]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.090      ; 7.192      ;
; 10.506 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[6]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.090      ; 7.192      ;
; 10.506 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[3]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.090      ; 7.192      ;
; 10.507 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|PC[9]                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.040     ; 7.061      ;
; 10.519 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|write_en_r                                                        ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[24]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.039     ; 7.050      ;
; 10.521 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_out_OTERM131             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[6]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.128      ; 7.215      ;
; 10.524 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|write_en_r                                                        ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[25]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.039     ; 7.045      ;
; 10.533 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[6]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.144      ; 7.219      ;
; 10.535 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[0]        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[7]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.046     ; 7.027      ;
; 10.540 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[2]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.144      ; 7.212      ;
; 10.540 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[6]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.144      ; 7.212      ;
; 10.540 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[3]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.144      ; 7.212      ;
; 10.541 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[30] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[7]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.033     ; 7.034      ;
; 10.543 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_out_OTERM131             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[4]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.146      ; 7.211      ;
; 10.543 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_out_OTERM131             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[1]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.146      ; 7.211      ;
; 10.545 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_out_OTERM131             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[0]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.143      ; 7.206      ;
; 10.545 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_out_OTERM131             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[4]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.143      ; 7.206      ;
; 10.545 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_out_OTERM131             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[2]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.143      ; 7.206      ;
; 10.551 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[0]~_Duplicate_4         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.151      ; 7.208      ;
; 10.553 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_out_OTERM131             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[0]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.143      ; 7.198      ;
; 10.554 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_enable~0_OTERM3       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[0]~_Duplicate_4         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.139      ; 7.193      ;
; 10.555 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[4]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.162      ; 7.215      ;
; 10.555 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[1]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.162      ; 7.215      ;
; 10.556 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[2]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.138      ; 7.190      ;
; 10.556 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[6]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.138      ; 7.190      ;
; 10.556 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[3]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.138      ; 7.190      ;
; 10.556 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[0]~_Duplicate_4         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.088      ; 7.140      ;
; 10.557 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[0]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.159      ; 7.210      ;
; 10.557 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[4]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.159      ; 7.210      ;
; 10.557 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[2]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.159      ; 7.210      ;
; 10.558 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|write_en_r                                                        ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[27]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.041     ; 7.009      ;
; 10.558 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[2]                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]~_Duplicate_7  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.150      ; 7.200      ;
; 10.561 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_out_OTERM131             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[29]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.127      ; 7.174      ;
; 10.561 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_out_OTERM131             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.127      ; 7.174      ;
; 10.561 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_out_OTERM131             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[43]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.127      ; 7.174      ;
; 10.561 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_out_OTERM131             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[34]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.127      ; 7.174      ;
; 10.562 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_out_OTERM131             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[7]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.134      ; 7.180      ;
; 10.563 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[0]        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[6]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.050     ; 6.995      ;
+--------+-------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                                                           ; To Node                                                                                                                                                                           ; Launch Clock                                                          ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 0.213  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.371        ; 0.651      ; 0.636      ;
; 39.497 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.150     ; 3.205      ;
; 39.499 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|altsyncram:altsyncram4|altsyncram_72m3:auto_generated|ram_block1a0~porta_address_reg0                 ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.331     ; 3.022      ;
; 39.853 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C1_data_state                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.145     ; 2.854      ;
; 39.856 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C2_data_state                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.145     ; 2.851      ;
; 39.954 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C0_data_state                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.145     ; 2.753      ;
; 39.967 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|altsyncram:altsyncram4|altsyncram_cul3:auto_generated|ram_block1a0~porta_address_reg0 ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.333     ; 2.552      ;
; 40.006 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C3_data_state                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.145     ; 2.701      ;
; 40.253 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C4_data_state                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.145     ; 2.454      ;
; 40.338 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 1.976      ; 3.292      ;
; 40.344 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3]                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.145     ; 2.363      ;
; 40.347 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.145     ; 2.360      ;
; 40.349 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4]                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.145     ; 2.358      ;
; 40.378 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 1.963      ; 3.239      ;
; 40.400 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_seq_data_state                                                                               ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.145     ; 2.307      ;
; 40.428 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 1.963      ; 3.189      ;
; 40.429 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2]                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.145     ; 2.278      ;
; 40.465 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2]                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.146     ; 2.241      ;
; 40.484 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 1.976      ; 3.146      ;
; 40.501 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1]                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.145     ; 2.206      ;
; 40.518 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|areset_init_state_1 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 1.963      ; 3.099      ;
; 40.520 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 1.975      ; 3.109      ;
; 40.521 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 1.971      ; 3.104      ;
; 40.530 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_data_state                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.150     ; 2.172      ;
; 40.537 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_data_state                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.150     ; 2.165      ;
; 40.546 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1]                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.146     ; 2.160      ;
; 40.625 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3]                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.146     ; 2.081      ;
; 40.633 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C2_data_state                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.150     ; 2.069      ;
; 40.682 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_data_state                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.150     ; 2.020      ;
; 40.699 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4]                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.146     ; 2.007      ;
; 40.823 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[0]                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.145     ; 1.884      ;
; 40.845 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_seq_data_state                                                               ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.142     ; 1.865      ;
; 40.895 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C4_data_state                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.150     ; 1.807      ;
; 41.008 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[0]                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.146     ; 1.698      ;
; 41.169 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.141     ; 1.542      ;
; 41.199 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|configupdate2_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|configupdate3_state ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.017     ; 0.437      ;
; 41.199 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|configupdate2_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|configupdate3_state                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.017     ; 0.437      ;
; 78.949 ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.021     ; 5.549      ;
; 79.105 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.040     ; 4.175      ;
; 79.124 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.053     ; 4.143      ;
; 79.218 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.053     ; 4.049      ;
; 79.255 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.045     ; 4.020      ;
; 79.283 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.040     ; 3.997      ;
; 79.290 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|areset_init_state_1 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.053     ; 3.977      ;
; 79.295 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.041     ; 3.984      ;
; 79.298 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.045     ; 3.977      ;
; 79.423 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.045     ; 3.852      ;
; 79.424 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.045     ; 3.851      ;
; 79.469 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.045     ; 3.806      ;
; 80.052 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 3.232      ;
; 80.092 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.049     ; 3.179      ;
; 80.142 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.049     ; 3.129      ;
; 80.198 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 3.086      ;
; 80.203 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                                            ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.051     ; 3.066      ;
; 80.232 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|areset_init_state_1 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.049     ; 3.039      ;
; 80.234 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.037     ; 3.049      ;
; 80.235 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.041     ; 3.044      ;
; 80.371 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                                            ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.051     ; 2.898      ;
; 80.372 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                                            ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.051     ; 2.897      ;
; 80.417 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                                            ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.051     ; 2.852      ;
; 80.594 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.023     ; 2.703      ;
; 80.605 ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.054     ; 2.661      ;
; 80.613 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 2.671      ;
; 80.643 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.054     ; 2.623      ;
; 80.689 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 2.595      ;
; 80.709 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.023     ; 2.588      ;
; 80.715 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                                            ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.038     ; 2.567      ;
; 80.721 ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.041     ; 2.558      ;
; 80.721 ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.054     ; 2.545      ;
; 80.728 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 2.556      ;
; 80.736 ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.054     ; 2.530      ;
; 80.742 ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_init_state ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.041     ; 2.537      ;
; 80.745 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.023     ; 2.552      ;
; 80.759 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.041     ; 2.520      ;
; 80.762 ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_init_state                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.054     ; 2.504      ;
; 80.779 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|areset_init_state_1 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 2.505      ;
; 80.780 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_init_state ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.041     ; 2.499      ;
; 80.781 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.024     ; 2.515      ;
; 80.782 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.028     ; 2.510      ;
; 80.800 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_init_state                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.054     ; 2.466      ;
; 80.822 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 2.462      ;
; 80.832 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.038     ; 2.450      ;
; 80.837 ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.041     ; 2.442      ;
; 80.852 ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.041     ; 2.427      ;
; 80.858 ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_init_state ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.041     ; 2.421      ;
; 80.873 ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_init_state ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.041     ; 2.406      ;
; 80.878 ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_init_state                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.054     ; 2.388      ;
; 80.883 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                                            ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.038     ; 2.399      ;
; 80.884 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                                            ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.038     ; 2.398      ;
; 80.885 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.023     ; 2.412      ;
; 80.893 ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_init_state                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.054     ; 2.373      ;
; 80.894 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|areset_init_state_1 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 2.390      ;
; 80.899 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.024     ; 2.397      ;
; 80.902 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.028     ; 2.390      ;
; 80.924 ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[0]                                                                                                                                                                                ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.027     ; 2.369      ;
; 80.929 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                                            ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.038     ; 2.353      ;
; 81.000 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.038     ; 2.282      ;
; 81.001 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.038     ; 2.281      ;
; 81.040 ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 2.244      ;
; 81.043 ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 2.241      ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                  ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.392 ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 1.958        ; -0.961     ; 0.543      ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                  ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 2.829 ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:0:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 4.405        ; -0.961     ; 0.543      ;
; 5.531 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.083     ; 3.136      ;
; 5.542 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.083     ; 3.125      ;
; 5.579 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.075     ; 3.096      ;
; 5.587 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.075     ; 3.088      ;
; 5.622 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.083     ; 3.045      ;
; 5.628 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.083     ; 3.039      ;
; 5.710 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.084     ; 2.956      ;
; 5.724 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.090     ; 2.936      ;
; 5.727 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.075     ; 2.948      ;
; 5.737 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[2]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.094     ; 2.919      ;
; 5.739 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.088     ; 2.923      ;
; 5.753 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.094     ; 2.903      ;
; 5.766 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.090     ; 2.894      ;
; 5.771 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.075     ; 2.904      ;
; 5.771 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[2]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.094     ; 2.885      ;
; 5.777 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.067     ; 2.906      ;
; 5.777 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.089     ; 2.884      ;
; 5.777 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.084     ; 2.889      ;
; 5.779 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.094     ; 2.877      ;
; 5.789 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.094     ; 2.867      ;
; 5.791 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.095     ; 2.864      ;
; 5.792 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.077     ; 2.881      ;
; 5.792 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.094     ; 2.864      ;
; 5.799 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.067     ; 2.884      ;
; 5.805 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.088     ; 2.857      ;
; 5.806 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.084     ; 2.860      ;
; 5.833 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[9]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.090     ; 2.827      ;
; 5.835 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.088     ; 2.827      ;
; 5.840 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.069     ; 2.841      ;
; 5.842 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[9]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.090     ; 2.818      ;
; 5.844 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.089     ; 2.817      ;
; 5.848 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.067     ; 2.835      ;
; 5.859 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.077     ; 2.814      ;
; 5.869 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.037     ; 2.891      ;
; 5.873 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.089     ; 2.788      ;
; 5.877 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.084     ; 2.789      ;
; 5.887 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.061     ; 2.802      ;
; 5.889 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.077     ; 2.784      ;
; 5.890 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.091     ; 2.769      ;
; 5.893 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.067     ; 2.790      ;
; 5.893 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.085     ; 2.772      ;
; 5.895 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.095     ; 2.760      ;
; 5.901 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.067     ; 2.782      ;
; 5.905 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.069     ; 2.776      ;
; 5.906 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.088     ; 2.756      ;
; 5.906 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.085     ; 2.759      ;
; 5.907 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.091     ; 2.752      ;
; 5.909 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.083     ; 2.758      ;
; 5.913 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.067     ; 2.770      ;
; 5.913 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.067     ; 2.770      ;
; 5.932 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.090     ; 2.728      ;
; 5.933 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.078     ; 2.727      ;
; 5.933 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.078     ; 2.727      ;
; 5.938 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.062     ; 2.750      ;
; 5.940 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.077     ; 2.733      ;
; 5.944 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[13]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.082     ; 2.724      ;
; 5.944 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.089     ; 2.717      ;
; 5.949 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.031     ; 2.817      ;
; 5.952 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.068     ; 2.730      ;
; 5.954 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.061     ; 2.735      ;
; 5.956 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[13]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.082     ; 2.712      ;
; 5.957 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.075     ; 2.718      ;
; 5.961 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.094     ; 2.695      ;
; 5.973 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.077     ; 2.700      ;
; 5.978 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.084     ; 2.688      ;
; 5.983 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.061     ; 2.706      ;
; 5.987 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.090     ; 2.673      ;
; 5.988 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.069     ; 2.693      ;
; 5.989 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.085     ; 2.676      ;
; 5.991 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.031     ; 2.775      ;
; 5.992 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.062     ; 2.696      ;
; 5.992 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.090     ; 2.668      ;
; 5.993 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.090     ; 2.667      ;
; 5.996 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.067     ; 2.687      ;
; 6.005 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.062     ; 2.683      ;
; 6.006 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.083     ; 2.661      ;
; 6.006 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.068     ; 2.676      ;
; 6.011 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.067     ; 2.672      ;
; 6.015 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[1]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.102     ; 2.633      ;
; 6.017 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.067     ; 2.666      ;
; 6.018 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.077     ; 2.655      ;
; 6.019 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.084     ; 2.647      ;
; 6.020 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.069     ; 2.661      ;
; 6.025 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.084     ; 2.641      ;
; 6.032 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[2]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.088     ; 2.630      ;
; 6.034 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[1]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.102     ; 2.614      ;
; 6.034 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.062     ; 2.654      ;
; 6.038 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.061     ; 2.651      ;
; 6.041 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.078     ; 2.619      ;
; 6.041 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.078     ; 2.619      ;
; 6.043 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.078     ; 2.617      ;
; 6.043 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.078     ; 2.617      ;
; 6.043 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.068     ; 2.639      ;
; 6.045 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.084     ; 2.621      ;
; 6.048 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.088     ; 2.614      ;
; 6.051 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[10]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.063     ; 2.636      ;
; 6.053 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.088     ; 2.609      ;
; 6.054 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.061     ; 2.635      ;
; 6.054 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.088     ; 2.608      ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]'                                                                                                                                                                                                                                                                                                                      ;
+-----------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack     ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-----------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 13.668    ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 15.493       ; -0.961     ; 0.792      ;
; 88103.192 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 2.397      ;
; 88103.213 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 2.376      ;
; 88103.450 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 2.139      ;
; 88103.462 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 2.127      ;
; 88103.490 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 2.099      ;
; 88103.537 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 2.052      ;
; 88103.544 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 2.045      ;
; 88103.568 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 2.021      ;
; 88103.585 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 2.004      ;
; 88103.618 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 1.971      ;
; 88103.688 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 1.900      ;
; 88103.693 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 1.895      ;
; 88103.700 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 1.889      ;
; 88103.747 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 1.842      ;
; 88103.754 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 1.835      ;
; 88103.757 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 1.832      ;
; 88103.766 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 1.823      ;
; 88103.830 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 1.759      ;
; 88103.894 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 1.695      ;
; 88103.915 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 1.673      ;
; 88103.920 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 1.668      ;
; 88103.940 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 1.648      ;
; 88104.114 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_r_inc                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 1.475      ;
; 88104.114 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 1.475      ;
; 88104.160 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 1.428      ;
; 88104.175 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 1.414      ;
; 88104.175 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 1.414      ;
; 88104.175 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 1.414      ;
; 88104.175 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 1.414      ;
; 88104.175 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 1.414      ;
; 88104.175 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 1.414      ;
; 88104.175 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 1.414      ;
; 88104.175 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 1.414      ;
; 88104.240 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 1.349      ;
; 88104.240 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 1.349      ;
; 88104.240 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 1.349      ;
; 88104.240 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 1.349      ;
; 88104.240 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 1.349      ;
; 88104.240 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 1.349      ;
; 88104.240 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 1.349      ;
; 88104.240 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 1.349      ;
; 88104.259 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 1.330      ;
; 88104.259 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 1.330      ;
; 88104.259 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 1.330      ;
; 88104.259 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 1.330      ;
; 88104.259 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 1.330      ;
; 88104.259 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 1.330      ;
; 88104.259 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 1.330      ;
; 88104.259 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 1.330      ;
; 88104.276 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 1.312      ;
; 88104.334 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_r_inc                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 1.255      ;
; 88104.339 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 1.249      ;
; 88104.348 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 1.240      ;
; 88104.355 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 1.233      ;
; 88104.360 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 1.228      ;
; 88104.365 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 1.224      ;
; 88104.365 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 1.224      ;
; 88104.365 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 1.224      ;
; 88104.365 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 1.224      ;
; 88104.365 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 1.224      ;
; 88104.365 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 1.224      ;
; 88104.365 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 1.224      ;
; 88104.365 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 1.224      ;
; 88104.412 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 1.177      ;
; 88104.412 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 1.177      ;
; 88104.412 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 1.177      ;
; 88104.412 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 1.177      ;
; 88104.412 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 1.177      ;
; 88104.412 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 1.177      ;
; 88104.412 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 1.177      ;
; 88104.412 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 1.177      ;
; 88104.427 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 1.161      ;
; 88104.430 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 1.158      ;
; 88104.473 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 1.115      ;
; 88104.490 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 1.099      ;
; 88104.490 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 1.098      ;
; 88104.493 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 1.095      ;
; 88104.496 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 1.092      ;
; 88104.499 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 1.089      ;
; 88104.502 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 1.086      ;
; 88104.530 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 1.058      ;
; 88104.535 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 1.053      ;
; 88104.647 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 0.941      ;
; 88104.650 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 0.938      ;
; 88104.693 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 0.895      ;
; 88104.702 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_state[3]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 0.886      ;
; 88104.713 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 0.876      ;
; 88104.713 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 0.876      ;
; 88104.713 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 0.876      ;
; 88104.713 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 0.876      ;
; 88104.713 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 0.876      ;
; 88104.713 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 0.876      ;
; 88104.713 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 0.876      ;
; 88104.713 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 0.876      ;
; 88104.713 ; user_io:my_user_io|ps2_kbd_data                                             ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 0.875      ;
; 88104.738 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 0.851      ;
; 88104.750 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_r_inc                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.036     ; 0.839      ;
; 88104.771 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_state[3]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 0.817      ;
; 88104.784 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_state[3]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 0.804      ;
+-----------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'CLOCK_27[0]'                                                                                                                                                            ;
+--------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                 ; To Node                                                   ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 35.609 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 1.378      ;
; 35.638 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 1.349      ;
; 35.676 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 1.311      ;
; 35.679 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 1.308      ;
; 35.682 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 1.305      ;
; 35.746 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 1.241      ;
; 35.750 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 1.237      ;
; 35.753 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 1.234      ;
; 35.761 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 1.226      ;
; 35.782 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 1.205      ;
; 35.794 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 1.193      ;
; 35.813 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 1.174      ;
; 35.816 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 1.171      ;
; 35.817 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 1.170      ;
; 35.826 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 1.161      ;
; 35.828 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 1.159      ;
; 35.831 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 1.156      ;
; 35.866 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 1.121      ;
; 35.898 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 1.089      ;
; 35.898 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 1.089      ;
; 35.922 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.036     ; 1.066      ;
; 36.011 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.036     ; 0.977      ;
; 36.011 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.036     ; 0.977      ;
; 36.019 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.036     ; 0.969      ;
; 36.045 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.942      ;
; 36.065 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.922      ;
; 36.065 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.922      ;
; 36.066 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.921      ;
; 36.066 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.921      ;
; 36.070 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.917      ;
; 36.083 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.904      ;
; 36.084 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.903      ;
; 36.089 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.898      ;
; 36.093 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.036     ; 0.895      ;
; 36.098 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.036     ; 0.890      ;
; 36.120 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.867      ;
; 36.148 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.839      ;
; 36.151 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.836      ;
; 36.153 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.834      ;
; 36.160 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.827      ;
; 36.168 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.819      ;
; 36.168 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.819      ;
; 36.171 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.036     ; 0.817      ;
; 36.171 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.036     ; 0.817      ;
; 36.181 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.806      ;
; 36.201 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.786      ;
; 36.225 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.762      ;
; 36.226 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.761      ;
; 36.230 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.757      ;
; 36.231 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.756      ;
; 36.235 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.752      ;
; 36.250 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.737      ;
; 36.260 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.727      ;
; 36.328 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.659      ;
; 36.333 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.654      ;
; 36.336 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.651      ;
; 36.442 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.545      ;
; 36.444 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.543      ;
; 36.455 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.532      ;
; 36.628 ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.359      ;
+--------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                                   ; To Node                                                                                                                                                                                                                                             ; Launch Clock                                                          ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; -1.078 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.017        ; 1.305      ; 0.498      ;
; 0.186  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C2_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C2_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C4_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C4_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                               ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                                                       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                               ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                                       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                               ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                                                       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C2_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C2_data_state                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C1_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C1_data_state                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C3_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C3_data_state                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C0_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C0_data_state                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C4_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C4_data_state                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_seq_data_state                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_seq_data_state                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_seq_data_state                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_seq_data_state                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.194  ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[1]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[0]                                                                                                                                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
; 0.196  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|configupdate_state                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|configupdate2_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.317      ;
; 0.197  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.317      ;
; 0.197  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5]                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.317      ;
; 0.197  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|configupdate_state                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|configupdate2_state                                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.318      ;
; 0.198  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C3_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C2_ena_state                                                                                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.318      ;
; 0.198  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.318      ;
; 0.199  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C1_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C0_ena_state                                                                                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.319      ;
; 0.199  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C1_ena_state                                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C1_data_state                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.319      ;
; 0.200  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C2_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C1_ena_state                                                                                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.320      ;
; 0.204  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reset_state                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.324      ;
; 0.205  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[24]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[24]                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.325      ;
; 0.205  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_counter_state                                                        ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|tmp_seq_ena_state                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.325      ;
; 0.210  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_init_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.330      ;
; 0.211  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C3_ena_state                                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C3_data_state                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.331      ;
; 0.231  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[1]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|altsyncram:altsyncram4|altsyncram_72m3:auto_generated|ram_block1a0~porta_address_reg0                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.222      ; 0.557      ;
; 0.256  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C2_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_ena_state                                                                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.377      ;
; 0.257  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|tmp_seq_ena_state                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.378      ;
; 0.257  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C0_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|tmp_seq_ena_state                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.377      ;
; 0.262  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C4_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C3_ena_state                                                                                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.382      ;
; 0.262  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C4_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_counter_state                                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.382      ;
; 0.271  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_init_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_counter_state                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.391      ;
; 0.271  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|tmp_seq_ena_state                                                             ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_seq_ena_state                                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.391      ;
; 0.272  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_init_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C4_ena_state                                                                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.392      ;
; 0.291  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[9]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[9]                                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.412      ;
; 0.291  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[11]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[11]                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.412      ;
; 0.292  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.413      ;
; 0.292  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.413      ;
; 0.293  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.414      ;
; 0.293  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.414      ;
; 0.293  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.414      ;
; 0.293  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[15]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[15]                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.413      ;
; 0.293  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[7] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|altsyncram:altsyncram4|altsyncram_cul3:auto_generated|ram_block1a0~porta_address_reg0 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.229      ; 0.626      ;
; 0.294  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.415      ;
; 0.294  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.415      ;
; 0.294  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[8]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[8]                                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.415      ;
; 0.294  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[10]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[10]                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.415      ;
; 0.294  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[12]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[12]                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.414      ;
; 0.294  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[13]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[13]                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.414      ;
; 0.294  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[17]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[17]                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.414      ;
; 0.294  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[23]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[23]                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.414      ;
; 0.294  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[3]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|altsyncram:altsyncram4|altsyncram_72m3:auto_generated|ram_block1a0~porta_address_reg0                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.222      ; 0.620      ;
; 0.295  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[14]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[14]                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.295  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[18]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[18]                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.295  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[19]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[19]                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.295  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[21]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[21]                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.295  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|areset_init_state_1                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.296  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[16]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[16]                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.416      ;
; 0.296  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[20]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[20]                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.416      ;
; 0.296  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[22]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[22]                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.416      ;
; 0.296  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[6] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|altsyncram:altsyncram4|altsyncram_cul3:auto_generated|ram_block1a0~porta_address_reg0 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.229      ; 0.629      ;
; 0.297  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1]                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.418      ;
; 0.297  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.417      ;
; 0.297  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_ena_state                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.418      ;
; 0.298  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.418      ;
; 0.298  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3]                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.419      ;
; 0.298  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.418      ;
; 0.298  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[4] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.418      ;
; 0.298  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[7] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[7]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.418      ;
; 0.299  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.419      ;
; 0.299  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2]                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.420      ;
; 0.299  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1]                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.419      ;
; 0.299  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.419      ;
; 0.299  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[5] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[5]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.419      ;
; 0.299  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[6] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[6]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.419      ;
; 0.300  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4]                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.421      ;
; 0.300  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[4]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[4]                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.420      ;
; 0.300  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.420      ;
; 0.300  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.420      ;
; 0.301  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2]                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.421      ;
; 0.301  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.421      ;
; 0.302  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_ena_state                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.423      ;
; 0.303  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_seq_ena_state                                        ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.423      ;
; 0.303  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1]                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.424      ;
; 0.303  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[3]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[3]                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.424      ;
; 0.304  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_init_state                                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.424      ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                     ; To Node                                                                                                                                                                                                                                 ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.136 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[6]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a8~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.463      ;
; 0.138 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_snap_reg[5]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a8~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.465      ;
; 0.139 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[1]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.467      ;
; 0.140 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[7]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.467      ;
; 0.140 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[3]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.469      ;
; 0.142 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[7]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.470      ;
; 0.142 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[5]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.469      ;
; 0.145 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp3_snap_reg[1]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a8~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.472      ;
; 0.145 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[2]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.472      ;
; 0.147 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_snap_reg[6]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a8~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.472      ;
; 0.147 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp3_snap_reg[6]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a8~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.474      ;
; 0.147 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[3]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.475      ;
; 0.148 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[4]                                                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|altsyncram_aj81:FIFOram|ram_block1a0~porta_datain_reg0           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.477      ;
; 0.148 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[4]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a8~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.475      ;
; 0.148 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[2]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.473      ;
; 0.149 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_rj31:auto_generated|a_dpfifo_2q31:dpfifo|cntr_o8b:wr_ptr|counter_reg_bit[5]   ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_rj31:auto_generated|a_dpfifo_2q31:dpfifo|altsyncram_eg81:FIFOram|ram_block1a0~porta_address_reg0        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.222      ; 0.475      ;
; 0.149 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[5]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a8~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.472      ;
; 0.149 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[2]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a8~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.476      ;
; 0.149 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp3_snap_reg[4]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a8~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.476      ;
; 0.150 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[2]                                                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|altsyncram_aj81:FIFOram|ram_block1a0~porta_datain_reg0           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.479      ;
; 0.150 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_snap_reg[2]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a8~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.475      ;
; 0.151 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[4]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.479      ;
; 0.151 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[4]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.478      ;
; 0.151 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[1]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.478      ;
; 0.152 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp3_snap_reg[2]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a8~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.479      ;
; 0.153 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[0]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.481      ;
; 0.153 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[0]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.478      ;
; 0.154 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|cntr_o8b:wr_ptr|counter_reg_bit[6]     ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|altsyncram_aj81:FIFOram|ram_block1a0~porta_address_reg0          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.481      ;
; 0.154 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[1]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a8~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.481      ;
; 0.154 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_snap_reg[3]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a8~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.479      ;
; 0.154 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[6]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.482      ;
; 0.156 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|cntr_o8b:wr_ptr|counter_reg_bit[3]     ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|altsyncram_aj81:FIFOram|ram_block1a0~porta_address_reg0          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.483      ;
; 0.156 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_snap_reg[1]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a8~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.483      ;
; 0.157 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_snap_reg[7]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a8~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.484      ;
; 0.158 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp3_snap_reg[0]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a8~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.485      ;
; 0.158 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[7]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.487      ;
; 0.159 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|cntr_o8b:wr_ptr|counter_reg_bit[1]     ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|altsyncram_aj81:FIFOram|ram_block1a0~porta_address_reg0          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.486      ;
; 0.159 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[1]                                                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|altsyncram_aj81:FIFOram|ram_block1a0~porta_datain_reg0           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.488      ;
; 0.159 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|cntr_8rf:cntr1|counter_reg_bit[6]                                                                 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|altsyncram_v6b1:altsyncram2|ram_block5a0~portb_address_reg0                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.488      ;
; 0.160 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|cntr_8rf:cntr1|counter_reg_bit[6]                                                                 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|altsyncram_v6b1:altsyncram2|ram_block5a0~porta_address_reg0                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.487      ;
; 0.161 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[0]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a8~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.484      ;
; 0.161 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_snap_reg[4]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a8~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.488      ;
; 0.162 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[2]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.490      ;
; 0.162 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[6]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.489      ;
; 0.162 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|cntr_8rf:cntr1|counter_reg_bit[5]                                                                 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|altsyncram_v6b1:altsyncram2|ram_block5a0~portb_address_reg0                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.491      ;
; 0.163 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|cntr_8rf:cntr1|counter_reg_bit[5]                                                                 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|altsyncram_v6b1:altsyncram2|ram_block5a0~porta_address_reg0                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.490      ;
; 0.164 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe3a[0]                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a8~portb_address_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.488      ;
; 0.164 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|cntr_8rf:cntr1|counter_reg_bit[2]                                                                 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|altsyncram_v6b1:altsyncram2|ram_block5a0~portb_address_reg0                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.493      ;
; 0.165 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp3_snap_reg[7]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a8~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.492      ;
; 0.165 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|cntr_8rf:cntr1|counter_reg_bit[2]                                                                 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|altsyncram_v6b1:altsyncram2|ram_block5a0~porta_address_reg0                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.492      ;
; 0.166 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_rj31:auto_generated|a_dpfifo_2q31:dpfifo|cntr_o8b:wr_ptr|counter_reg_bit[1]   ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_rj31:auto_generated|a_dpfifo_2q31:dpfifo|altsyncram_eg81:FIFOram|ram_block1a0~porta_address_reg0        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.222      ; 0.492      ;
; 0.168 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_rj31:auto_generated|a_dpfifo_2q31:dpfifo|cntr_o8b:wr_ptr|counter_reg_bit[0]   ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_rj31:auto_generated|a_dpfifo_2q31:dpfifo|altsyncram_eg81:FIFOram|ram_block1a0~porta_address_reg0        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.222      ; 0.494      ;
; 0.168 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[0]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.495      ;
; 0.169 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|cntr_o8b:wr_ptr|counter_reg_bit[4]     ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|altsyncram_aj81:FIFOram|ram_block1a0~porta_address_reg0          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.496      ;
; 0.169 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|cntr_o8b:wr_ptr|counter_reg_bit[7]     ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|altsyncram_aj81:FIFOram|ram_block1a0~porta_address_reg0          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.496      ;
; 0.170 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_rj31:auto_generated|a_dpfifo_2q31:dpfifo|cntr_o8b:wr_ptr|counter_reg_bit[4]   ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_rj31:auto_generated|a_dpfifo_2q31:dpfifo|altsyncram_eg81:FIFOram|ram_block1a0~porta_address_reg0        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.222      ; 0.496      ;
; 0.171 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[6]                                                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|altsyncram_aj81:FIFOram|ram_block1a0~porta_datain_reg0           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.500      ;
; 0.171 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|cntr_tnf:cntr1|counter_reg_bit[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a8~porta_address_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.218      ; 0.493      ;
; 0.172 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[0]                                                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|altsyncram_aj81:FIFOram|ram_block1a0~porta_datain_reg0           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.501      ;
; 0.173 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[5]                                                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|altsyncram_aj81:FIFOram|ram_block1a0~porta_datain_reg0           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.502      ;
; 0.176 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[3]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a8~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.501      ;
; 0.177 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_rj31:auto_generated|a_dpfifo_2q31:dpfifo|cntr_o8b:wr_ptr|counter_reg_bit[3]   ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_rj31:auto_generated|a_dpfifo_2q31:dpfifo|altsyncram_eg81:FIFOram|ram_block1a0~porta_address_reg0        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.222      ; 0.503      ;
; 0.178 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cyclePreRead                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cyclePreRead                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.045      ; 0.307      ;
; 0.178 ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[7]                                                                                                                                                   ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_fi41:auto_generated|ram_block1a2~porta_address_reg0                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.503      ;
; 0.178 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_rj31:auto_generated|a_dpfifo_2q31:dpfifo|cntr_o8b:wr_ptr|counter_reg_bit[7]   ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_rj31:auto_generated|a_dpfifo_2q31:dpfifo|altsyncram_eg81:FIFOram|ram_block1a0~porta_address_reg0        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.222      ; 0.504      ;
; 0.179 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cycleBranchTaken                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cycleBranchTaken                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.307      ;
; 0.179 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Creg                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Creg                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.307      ;
; 0.179 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[16]                                                                                                                                                 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[16]                                                                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.307      ;
; 0.179 ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[6]                                                                                                                                                   ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_fi41:auto_generated|ram_block1a2~porta_address_reg0                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.506      ;
; 0.179 ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[12]                                                                                                                                                  ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_fi41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.222      ; 0.505      ;
; 0.179 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[6]                                                                                                                                     ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[6]                                                                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.307      ;
; 0.179 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[7]                                                                                                                                     ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[7]                                                                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.307      ;
; 0.179 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[0]                                                                                                                                     ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[0]                                                                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.307      ;
; 0.179 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[3]                                                                                                                                     ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[3]                                                                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.307      ;
; 0.179 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[7]                                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[7]                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.307      ;
; 0.179 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[0]_OTERM269                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[0]_OTERM269                                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.307      ;
; 0.179 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[7]                                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[7]                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.307      ;
; 0.179 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[7]                                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[7]                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.307      ;
; 0.179 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[7]                                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[7]                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.307      ;
; 0.180 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[68]                                                                                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[68]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.043      ; 0.307      ;
; 0.185 ; sdram_statemachine:sdram_adaptor|data_out_reg[24]                                                                                                                                                             ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[24]                                                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 0.387      ;
; 0.185 ; sdram_statemachine:sdram_adaptor|data_out_reg[16]                                                                                                                                                             ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[16]                                                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 0.387      ;
; 0.185 ; sdram_statemachine:sdram_adaptor|sdram_request_reg                                                                                                                                                            ; sdram_statemachine:sdram_adaptor|sdram_request_reg                                                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.038      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]                                                                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]                                                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[3]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[3]                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[6]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[6]                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[7]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[7]                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[8]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[8]                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[9]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[9]                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[9]                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[9]                                                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cyclePreIndirect                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cyclePreIndirect                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Vreg                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Vreg                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vblank_reg                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vblank_reg                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dli_nmi_reg                                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dli_nmi_reg                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vbi_nmi_reg                                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vbi_nmi_reg                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[10]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[10]                                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|use_status_as_ram_address                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|use_status_as_ram_address                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|porta_control_reg[4]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|porta_control_reg[4]                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|cb2_edge_reg                                                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|cb2_edge_reg                                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_shift_reg[9]                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_shift_reg[9]                                                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'CLOCK_27[0]'                                                                                                                                                            ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                 ; To Node                                                   ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.194 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.036      ; 0.314      ;
; 0.297 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.418      ;
; 0.298 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.419      ;
; 0.299 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.420      ;
; 0.431 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.552      ;
; 0.431 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.552      ;
; 0.434 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.555      ;
; 0.436 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.557      ;
; 0.438 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.559      ;
; 0.441 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.562      ;
; 0.445 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.566      ;
; 0.450 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.571      ;
; 0.458 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.579      ;
; 0.461 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.582      ;
; 0.477 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.598      ;
; 0.485 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.606      ;
; 0.490 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.611      ;
; 0.490 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.611      ;
; 0.493 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.614      ;
; 0.497 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.618      ;
; 0.497 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.618      ;
; 0.500 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.621      ;
; 0.508 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.629      ;
; 0.510 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.631      ;
; 0.513 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.634      ;
; 0.538 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.659      ;
; 0.539 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.036      ; 0.659      ;
; 0.541 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.662      ;
; 0.546 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.667      ;
; 0.551 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.672      ;
; 0.552 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.673      ;
; 0.553 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.674      ;
; 0.555 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.676      ;
; 0.557 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.678      ;
; 0.566 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.687      ;
; 0.566 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.687      ;
; 0.569 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.690      ;
; 0.569 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.690      ;
; 0.574 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.695      ;
; 0.576 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.697      ;
; 0.577 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.698      ;
; 0.605 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.036      ; 0.725      ;
; 0.608 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.036      ; 0.728      ;
; 0.616 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.737      ;
; 0.616 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.737      ;
; 0.618 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.739      ;
; 0.618 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.739      ;
; 0.621 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.742      ;
; 0.623 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.744      ;
; 0.646 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.767      ;
; 0.648 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.036      ; 0.768      ;
; 0.648 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.036      ; 0.768      ;
; 0.649 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.770      ;
; 0.651 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.036      ; 0.771      ;
; 0.655 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.036      ; 0.775      ;
; 0.658 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.036      ; 0.778      ;
; 0.692 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.813      ;
; 0.693 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.814      ;
; 0.696 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.817      ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                             ;
+-------+---------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                     ; To Node                                                       ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.186 ; sdram_statemachine:sdram_adaptor|reply_reg                    ; sdram_statemachine:sdram_adaptor|reply_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.205 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.325      ;
; 0.242 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.363      ;
; 0.244 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.365      ;
; 0.293 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.414      ;
; 0.293 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.414      ;
; 0.294 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.415      ;
; 0.294 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.415      ;
; 0.295 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.416      ;
; 0.295 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.416      ;
; 0.295 ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.416      ;
; 0.298 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.418      ;
; 0.298 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.418      ;
; 0.298 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.418      ;
; 0.299 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.419      ;
; 0.299 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.419      ;
; 0.300 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.420      ;
; 0.300 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.420      ;
; 0.300 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.420      ;
; 0.300 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.420      ;
; 0.302 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.423      ;
; 0.303 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.424      ;
; 0.303 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.424      ;
; 0.303 ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.424      ;
; 0.304 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.425      ;
; 0.309 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.429      ;
; 0.309 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.430      ;
; 0.310 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.431      ;
; 0.311 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.432      ;
; 0.311 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.432      ;
; 0.312 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.433      ;
; 0.313 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.434      ;
; 0.315 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.436      ;
; 0.317 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.438      ;
; 0.321 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.442      ;
; 0.324 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.445      ;
; 0.333 ; sdram_statemachine:sdram_adaptor|request_sreg                 ; sdram_statemachine:sdram_adaptor|reply_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 0.522      ;
; 0.375 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.496      ;
; 0.375 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.496      ;
; 0.378 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.499      ;
; 0.378 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.499      ;
; 0.393 ; sdram_statemachine:sdram_adaptor|dqm_mask_sreg[0]             ; sdram_statemachine:sdram_adaptor|data_out_reg[1]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 0.582      ;
; 0.395 ; sdram_statemachine:sdram_adaptor|dqm_mask_sreg[0]             ; sdram_statemachine:sdram_adaptor|data_out_reg[4]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 0.584      ;
; 0.418 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.539      ;
; 0.442 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.563      ;
; 0.443 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.564      ;
; 0.443 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.564      ;
; 0.447 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.567      ;
; 0.447 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.567      ;
; 0.447 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.567      ;
; 0.448 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.568      ;
; 0.449 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.569      ;
; 0.451 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.572      ;
; 0.453 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.574      ;
; 0.453 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.574      ;
; 0.453 ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.574      ;
; 0.453 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.574      ;
; 0.454 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.575      ;
; 0.456 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.576      ;
; 0.456 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.577      ;
; 0.456 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.577      ;
; 0.457 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.577      ;
; 0.458 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.578      ;
; 0.458 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.578      ;
; 0.458 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.578      ;
; 0.459 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.579      ;
; 0.459 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.580      ;
; 0.459 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.580      ;
; 0.460 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.580      ;
; 0.461 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.581      ;
; 0.461 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.581      ;
; 0.461 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.581      ;
; 0.461 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.582      ;
; 0.461 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.582      ;
; 0.462 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.583      ;
; 0.462 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.583      ;
; 0.464 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.585      ;
; 0.468 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.589      ;
; 0.468 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.589      ;
; 0.469 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.590      ;
; 0.471 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.592      ;
; 0.471 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.592      ;
; 0.471 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.592      ;
; 0.472 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.593      ;
; 0.473 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.594      ;
; 0.474 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.595      ;
; 0.475 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.596      ;
; 0.476 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.597      ;
; 0.478 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.599      ;
; 0.505 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.626      ;
; 0.506 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.627      ;
; 0.506 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.627      ;
; 0.509 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.630      ;
; 0.509 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.630      ;
; 0.510 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.630      ;
; 0.510 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.630      ;
; 0.510 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.630      ;
+-------+---------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]'                                                                                                                                                                       ;
+-------+------------------------------------+------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                          ; To Node                            ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------+------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.186 ; user_io:my_user_io|ps2_tx_state[1] ; user_io:my_user_io|ps2_tx_state[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_tx_state[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.307      ;
; 0.187 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_rptr[0]     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; user_io:my_user_io|ps2_rptr[1]     ; user_io:my_user_io|ps2_rptr[1]     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_rptr[2]     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; user_io:my_user_io|ps2_tx_byte[7]  ; user_io:my_user_io|ps2_tx_byte[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; user_io:my_user_io|ps2_parity      ; user_io:my_user_io|ps2_parity      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.307      ;
; 0.202 ; user_io:my_user_io|ps2_r_inc       ; user_io:my_user_io|ps2_rptr[0]     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.322      ;
; 0.202 ; user_io:my_user_io|ps2_r_inc       ; user_io:my_user_io|ps2_rptr[1]     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.322      ;
; 0.205 ; user_io:my_user_io|ps2_tx_byte[0]  ; user_io:my_user_io|ps2_parity      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.325      ;
; 0.212 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_rptr[2]     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.332      ;
; 0.216 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_state[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.337      ;
; 0.226 ; user_io:my_user_io|ps2_tx_state[0] ; user_io:my_user_io|ps2_tx_state[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.347      ;
; 0.236 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_tx_byte[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.356      ;
; 0.237 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_tx_byte[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.357      ;
; 0.237 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_tx_byte[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.357      ;
; 0.268 ; user_io:my_user_io|ps2_tx_byte[4]  ; user_io:my_user_io|ps2_tx_byte[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.388      ;
; 0.268 ; user_io:my_user_io|ps2_tx_byte[3]  ; user_io:my_user_io|ps2_tx_byte[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.388      ;
; 0.269 ; user_io:my_user_io|ps2_tx_byte[5]  ; user_io:my_user_io|ps2_tx_byte[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.389      ;
; 0.269 ; user_io:my_user_io|ps2_tx_byte[2]  ; user_io:my_user_io|ps2_tx_byte[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.389      ;
; 0.269 ; user_io:my_user_io|ps2_tx_byte[1]  ; user_io:my_user_io|ps2_tx_byte[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.389      ;
; 0.270 ; user_io:my_user_io|ps2_tx_byte[6]  ; user_io:my_user_io|ps2_tx_byte[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.390      ;
; 0.271 ; user_io:my_user_io|ps2_parity      ; user_io:my_user_io|ps2_kbd_data    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.391      ;
; 0.302 ; user_io:my_user_io|ps2_r_inc       ; user_io:my_user_io|ps2_rptr[2]     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.422      ;
; 0.307 ; user_io:my_user_io|ps2_rptr[1]     ; user_io:my_user_io|ps2_rptr[2]     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.427      ;
; 0.313 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_rptr[1]     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.433      ;
; 0.334 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_state[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.455      ;
; 0.335 ; user_io:my_user_io|ps2_tx_byte[7]  ; user_io:my_user_io|ps2_tx_byte[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.455      ;
; 0.346 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_tx_byte[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.466      ;
; 0.347 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_tx_byte[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.467      ;
; 0.348 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_tx_byte[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.468      ;
; 0.354 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_tx_byte[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.474      ;
; 0.362 ; user_io:my_user_io|ps2_tx_state[0] ; user_io:my_user_io|ps2_tx_state[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.483      ;
; 0.367 ; user_io:my_user_io|Equal5~0_OTERM1 ; user_io:my_user_io|Equal5~0_OTERM1 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.488      ;
; 0.370 ; user_io:my_user_io|Equal5~0_OTERM1 ; user_io:my_user_io|ps2_tx_state[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.491      ;
; 0.397 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|Equal5~0_OTERM1 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.518      ;
; 0.405 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_r_inc       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.525      ;
; 0.406 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_tx_byte[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.526      ;
; 0.407 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_tx_state[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.528      ;
; 0.412 ; user_io:my_user_io|ps2_tx_state[1] ; user_io:my_user_io|ps2_tx_state[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.533      ;
; 0.412 ; user_io:my_user_io|Equal5~0_OTERM1 ; user_io:my_user_io|ps2_parity      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.533      ;
; 0.444 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_state[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.565      ;
; 0.450 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|Equal5~0_OTERM1 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.571      ;
; 0.453 ; user_io:my_user_io|ps2_kbd_data    ; user_io:my_user_io|ps2_kbd_data    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.574      ;
; 0.455 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_kbd_data    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.576      ;
; 0.476 ; user_io:my_user_io|ps2_tx_state[1] ; user_io:my_user_io|Equal5~0_OTERM1 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.597      ;
; 0.497 ; user_io:my_user_io|Equal5~0_OTERM1 ; user_io:my_user_io|ps2_tx_byte[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.618      ;
; 0.497 ; user_io:my_user_io|Equal5~0_OTERM1 ; user_io:my_user_io|ps2_tx_byte[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.618      ;
; 0.497 ; user_io:my_user_io|Equal5~0_OTERM1 ; user_io:my_user_io|ps2_tx_byte[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.618      ;
; 0.497 ; user_io:my_user_io|Equal5~0_OTERM1 ; user_io:my_user_io|ps2_tx_byte[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.618      ;
; 0.497 ; user_io:my_user_io|Equal5~0_OTERM1 ; user_io:my_user_io|ps2_tx_byte[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.618      ;
; 0.497 ; user_io:my_user_io|Equal5~0_OTERM1 ; user_io:my_user_io|ps2_tx_byte[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.618      ;
; 0.497 ; user_io:my_user_io|Equal5~0_OTERM1 ; user_io:my_user_io|ps2_tx_byte[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.618      ;
; 0.501 ; user_io:my_user_io|ps2_tx_state[0] ; user_io:my_user_io|Equal5~0_OTERM1 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.622      ;
; 0.505 ; user_io:my_user_io|ps2_tx_state[0] ; user_io:my_user_io|ps2_tx_state[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.626      ;
; 0.526 ; user_io:my_user_io|ps2_tx_byte[0]  ; user_io:my_user_io|ps2_kbd_data    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.646      ;
; 0.539 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_tx_byte[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.659      ;
; 0.553 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_kbd_data    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.674      ;
; 0.567 ; user_io:my_user_io|Equal5~0_OTERM1 ; user_io:my_user_io|ps2_kbd_data    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.688      ;
; 0.574 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_tx_state[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.695      ;
; 0.575 ; user_io:my_user_io|ps2_tx_state[0] ; user_io:my_user_io|ps2_kbd_data    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.696      ;
; 0.579 ; user_io:my_user_io|ps2_tx_state[0] ; user_io:my_user_io|ps2_tx_state[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.700      ;
; 0.593 ; user_io:my_user_io|ps2_tx_state[1] ; user_io:my_user_io|ps2_kbd_data    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.714      ;
; 0.595 ; user_io:my_user_io|Equal5~0_OTERM1 ; user_io:my_user_io|ps2_tx_byte[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.716      ;
; 0.596 ; user_io:my_user_io|Equal5~0_OTERM1 ; user_io:my_user_io|ps2_r_inc       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.717      ;
; 0.634 ; user_io:my_user_io|ps2_tx_state[1] ; user_io:my_user_io|ps2_tx_state[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.755      ;
; 0.652 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_tx_byte[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.772      ;
; 0.652 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_tx_byte[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.772      ;
; 0.666 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_tx_byte[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.786      ;
; 0.679 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_tx_byte[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.799      ;
; 0.721 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_state[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.842      ;
; 0.741 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|Equal5~0_OTERM1 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.861      ;
; 0.744 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_tx_state[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.864      ;
; 0.756 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_tx_byte[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.876      ;
; 0.759 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_tx_byte[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.879      ;
; 0.847 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_tx_state[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.968      ;
; 0.869 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_kbd_data    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.989      ;
; 0.888 ; user_io:my_user_io|ps2_rptr[1]     ; user_io:my_user_io|ps2_tx_byte[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 1.008      ;
; 0.891 ; user_io:my_user_io|ps2_tx_state[1] ; user_io:my_user_io|ps2_tx_state[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 1.012      ;
; 0.937 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_tx_byte[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 1.057      ;
; 0.985 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_byte[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 1.106      ;
; 0.985 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_byte[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 1.106      ;
; 0.985 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_byte[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 1.106      ;
; 0.985 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_byte[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 1.106      ;
; 0.985 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_byte[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 1.106      ;
; 0.985 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_byte[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 1.106      ;
; 0.985 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_tx_byte[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 1.106      ;
; 0.985 ; user_io:my_user_io|ps2_tx_state[3] ; user_io:my_user_io|ps2_parity      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 1.106      ;
; 0.997 ; user_io:my_user_io|ps2_rptr[1]     ; user_io:my_user_io|ps2_tx_byte[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 1.117      ;
; 1.017 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_r_inc       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 1.137      ;
; 1.024 ; user_io:my_user_io|ps2_rptr[2]     ; user_io:my_user_io|ps2_parity      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 1.144      ;
; 1.055 ; user_io:my_user_io|ps2_rptr[1]     ; user_io:my_user_io|ps2_tx_byte[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 1.175      ;
; 1.081 ; user_io:my_user_io|ps2_rptr[0]     ; user_io:my_user_io|ps2_kbd_data    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 1.201      ;
; 1.089 ; user_io:my_user_io|ps2_rptr[1]     ; user_io:my_user_io|ps2_tx_byte[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 1.209      ;
; 1.105 ; user_io:my_user_io|ps2_rptr[1]     ; user_io:my_user_io|ps2_tx_byte[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 1.225      ;
; 1.111 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_tx_byte[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 1.232      ;
; 1.111 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_tx_byte[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 1.232      ;
; 1.111 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_tx_byte[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 1.232      ;
; 1.111 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_tx_byte[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 1.232      ;
; 1.111 ; user_io:my_user_io|ps2_tx_state[2] ; user_io:my_user_io|ps2_tx_byte[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 1.232      ;
+-------+------------------------------------+------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                   ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 8.109 ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -6.853       ; -0.824     ; 0.499      ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: 'CLOCK_27[0]'                                                                                                                                                                                                                               ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------+-----------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                              ; To Node                                                   ; Launch Clock                                                          ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------+-----------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.426 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 1.755      ; 2.237      ;
; -0.426 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 1.755      ; 2.237      ;
; -0.426 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 1.755      ; 2.237      ;
; -0.426 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 1.755      ; 2.237      ;
; -0.426 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 1.756      ; 2.238      ;
; -0.426 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 1.755      ; 2.237      ;
; -0.426 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 1.755      ; 2.237      ;
; -0.426 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 1.755      ; 2.237      ;
; -0.426 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 1.755      ; 2.237      ;
; -0.370 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 1.752      ; 2.178      ;
; -0.370 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 1.752      ; 2.178      ;
; -0.370 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 1.752      ; 2.178      ;
; -0.370 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 1.752      ; 2.178      ;
; -0.370 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 1.753      ; 2.179      ;
; -0.370 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 1.752      ; 2.178      ;
; -0.370 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 1.752      ; 2.178      ;
; -0.370 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 1.752      ; 2.178      ;
; -0.370 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 1.752      ; 2.178      ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------+-----------------------------------------------------------------------+-------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                  ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                              ; To Node                                                       ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 5.725 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[9]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.133     ; 2.892      ;
; 5.733 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[4]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.129     ; 2.888      ;
; 5.733 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[5]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.131     ; 2.886      ;
; 5.733 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[6]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.137     ; 2.880      ;
; 5.733 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[7]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.132     ; 2.885      ;
; 5.733 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[8]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.132     ; 2.885      ;
; 5.734 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[11]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.136     ; 2.880      ;
; 5.735 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[1]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.144     ; 2.871      ;
; 5.735 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|udqm_reg                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.138     ; 2.877      ;
; 5.737 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.198     ; 2.813      ;
; 5.740 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.132     ; 2.878      ;
; 5.740 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[9]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.132     ; 2.878      ;
; 5.741 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.134     ; 2.875      ;
; 5.741 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[13]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.134     ; 2.875      ;
; 5.741 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.135     ; 2.874      ;
; 5.741 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.135     ; 2.874      ;
; 5.742 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.186     ; 2.820      ;
; 5.742 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.186     ; 2.820      ;
; 5.743 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.188     ; 2.817      ;
; 5.743 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.188     ; 2.817      ;
; 5.743 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[15]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.189     ; 2.816      ;
; 5.743 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[14]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.189     ; 2.816      ;
; 5.743 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[0]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.141     ; 2.866      ;
; 5.745 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[0]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.195     ; 2.808      ;
; 5.747 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.127     ; 2.876      ;
; 5.747 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.127     ; 2.876      ;
; 5.749 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.181     ; 2.818      ;
; 5.749 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.181     ; 2.818      ;
; 5.750 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.136     ; 2.864      ;
; 5.750 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.136     ; 2.864      ;
; 5.752 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.190     ; 2.806      ;
; 5.752 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.190     ; 2.806      ;
; 5.762 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.109     ; 2.879      ;
; 5.762 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.109     ; 2.879      ;
; 5.762 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ba_reg[0]                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.113     ; 2.875      ;
; 5.762 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|we_n_reg                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.110     ; 2.878      ;
; 5.762 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ldqm_reg                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.110     ; 2.878      ;
; 5.763 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.109     ; 2.878      ;
; 5.763 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.109     ; 2.878      ;
; 5.763 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ba_reg[1]                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.111     ; 2.876      ;
; 5.763 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ras_n_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.113     ; 2.874      ;
; 5.763 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cas_n_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.112     ; 2.875      ;
; 5.763 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[0]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.111     ; 2.876      ;
; 5.763 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[1]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.110     ; 2.877      ;
; 5.763 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[2]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.110     ; 2.877      ;
; 5.763 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[3]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.109     ; 2.878      ;
; 5.763 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[10]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.111     ; 2.876      ;
; 5.764 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.163     ; 2.821      ;
; 5.764 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.163     ; 2.821      ;
; 5.765 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.163     ; 2.820      ;
; 5.765 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.163     ; 2.820      ;
; 5.835 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.153     ; 2.750      ;
; 5.840 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.141     ; 2.757      ;
; 5.840 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.141     ; 2.757      ;
; 5.841 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.143     ; 2.754      ;
; 5.841 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.143     ; 2.754      ;
; 5.841 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.144     ; 2.753      ;
; 5.841 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.144     ; 2.753      ;
; 5.843 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.150     ; 2.745      ;
; 5.847 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.136     ; 2.755      ;
; 5.847 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.136     ; 2.755      ;
; 5.850 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.145     ; 2.743      ;
; 5.850 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.145     ; 2.743      ;
; 5.862 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.118     ; 2.758      ;
; 5.862 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_5   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.118     ; 2.758      ;
; 5.863 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_6   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.118     ; 2.757      ;
; 5.863 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_7   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.118     ; 2.757      ;
; 5.974 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.100     ; 2.723      ;
; 5.974 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.100     ; 2.723      ;
; 5.974 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.100     ; 2.723      ;
; 5.974 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.100     ; 2.723      ;
; 5.974 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.100     ; 2.723      ;
; 5.974 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.100     ; 2.723      ;
; 5.974 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.100     ; 2.723      ;
; 5.974 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.100     ; 2.723      ;
; 5.974 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.100     ; 2.723      ;
; 5.974 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.100     ; 2.723      ;
; 5.974 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.100     ; 2.723      ;
; 5.978 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[28]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.096     ; 2.723      ;
; 5.978 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[31]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.096     ; 2.723      ;
; 5.978 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[26]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.096     ; 2.723      ;
; 5.978 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[27]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.096     ; 2.723      ;
; 5.979 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[20]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.098     ; 2.720      ;
; 5.979 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[0]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.095     ; 2.723      ;
; 5.979 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[3]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.095     ; 2.723      ;
; 5.979 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[1]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.095     ; 2.723      ;
; 5.979 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[4]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.095     ; 2.723      ;
; 5.979 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[5]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.095     ; 2.723      ;
; 5.979 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[7]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.095     ; 2.723      ;
; 5.979 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[2]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.095     ; 2.723      ;
; 5.979 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[6]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.095     ; 2.723      ;
; 5.979 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[15]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.095     ; 2.723      ;
; 5.979 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[13]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.095     ; 2.723      ;
; 5.979 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[10]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.095     ; 2.723      ;
; 5.979 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[21]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.098     ; 2.720      ;
; 5.979 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[8]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.095     ; 2.723      ;
; 5.979 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[14]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.095     ; 2.723      ;
; 5.979 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[18]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.098     ; 2.720      ;
; 5.979 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[12]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.095     ; 2.723      ;
; 5.979 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[19]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.098     ; 2.720      ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                           ;
+--------+------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                              ; To Node                                                                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 14.146 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[3]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.036     ; 3.426      ;
; 14.146 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[0]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.036     ; 3.426      ;
; 14.146 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_input_reg[7]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.036     ; 3.426      ;
; 14.146 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[4]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.036     ; 3.426      ;
; 14.153 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|keycode_latch_reg[4] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.029     ; 3.426      ;
; 14.163 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[14]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.045     ; 3.400      ;
; 14.163 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[22]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.045     ; 3.400      ;
; 14.163 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[15]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.045     ; 3.400      ;
; 14.163 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[23]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.045     ; 3.400      ;
; 14.163 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[30]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.045     ; 3.400      ;
; 14.163 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[31]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.045     ; 3.400      ;
; 14.178 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[3]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.095     ; 3.335      ;
; 14.178 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[0]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.095     ; 3.335      ;
; 14.178 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_input_reg[7]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.095     ; 3.335      ;
; 14.178 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[4]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.095     ; 3.335      ;
; 14.179 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.023     ; 3.406      ;
; 14.179 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[2]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.023     ; 3.406      ;
; 14.179 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[13]                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.023     ; 3.406      ;
; 14.179 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[15]                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.023     ; 3.406      ;
; 14.179 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[14]                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.023     ; 3.406      ;
; 14.179 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.023     ; 3.406      ;
; 14.179 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.023     ; 3.406      ;
; 14.179 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.023     ; 3.406      ;
; 14.185 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|keycode_latch_reg[4] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.088     ; 3.335      ;
; 14.205 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[14]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.094     ; 3.309      ;
; 14.205 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[22]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.094     ; 3.309      ;
; 14.205 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[15]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.094     ; 3.309      ;
; 14.205 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[23]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.094     ; 3.309      ;
; 14.205 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[30]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.094     ; 3.309      ;
; 14.205 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[31]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.094     ; 3.309      ;
; 14.211 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.315      ;
; 14.211 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[2]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.315      ;
; 14.211 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[13]                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.315      ;
; 14.211 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[15]                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.315      ;
; 14.211 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[14]                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.315      ;
; 14.211 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.315      ;
; 14.211 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.315      ;
; 14.211 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.315      ;
; 14.237 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[3]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.037     ; 3.334      ;
; 14.237 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[0]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.037     ; 3.334      ;
; 14.237 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_input_reg[7]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.037     ; 3.334      ;
; 14.237 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[4]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.037     ; 3.334      ;
; 14.244 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|keycode_latch_reg[4] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.030     ; 3.334      ;
; 14.254 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[14]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.046     ; 3.308      ;
; 14.254 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[22]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.046     ; 3.308      ;
; 14.254 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[15]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.046     ; 3.308      ;
; 14.254 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[23]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.046     ; 3.308      ;
; 14.254 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[30]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.046     ; 3.308      ;
; 14.254 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[31]                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.046     ; 3.308      ;
; 14.270 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.024     ; 3.314      ;
; 14.270 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[2]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.024     ; 3.314      ;
; 14.270 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[13]                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.024     ; 3.314      ;
; 14.270 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[15]                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.024     ; 3.314      ;
; 14.270 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[14]                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.024     ; 3.314      ;
; 14.270 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.024     ; 3.314      ;
; 14.270 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.024     ; 3.314      ;
; 14.270 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.024     ; 3.314      ;
; 14.341 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|porta_control_reg[2]                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.051     ; 3.216      ;
; 14.341 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|porta_control_reg[4]                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.051     ; 3.216      ;
; 14.341 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|cb2_edge_reg                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.051     ; 3.216      ;
; 14.341 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot2_reg[4]                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.051     ; 3.216      ;
; 14.341 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot3_reg[4]                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.054     ; 3.213      ;
; 14.341 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot1_reg[4]                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.051     ; 3.216      ;
; 14.341 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot0_reg[4]                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.051     ; 3.216      ;
; 14.341 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|skctl_reg[7]                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.048     ; 3.219      ;
; 14.341 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_holding_reg[0]                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.049     ; 3.218      ;
; 14.341 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_holding_reg[1]                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.049     ; 3.218      ;
; 14.341 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_holding_reg[2]                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.049     ; 3.218      ;
; 14.341 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_holding_reg[3]                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.049     ; 3.218      ;
; 14.341 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_holding_reg[4]                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.049     ; 3.218      ;
; 14.341 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_holding_reg[5]                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.049     ; 3.218      ;
; 14.341 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_holding_reg[6]                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.049     ; 3.218      ;
; 14.341 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_shift_reg[9]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.048     ; 3.219      ;
; 14.341 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_holding_reg[7]                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.049     ; 3.218      ;
; 14.341 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_shift_reg[8]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.049     ; 3.218      ;
; 14.341 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_shift_reg[7]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.049     ; 3.218      ;
; 14.341 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_shift_reg[6]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.049     ; 3.218      ;
; 14.341 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_shift_reg[5]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.049     ; 3.218      ;
; 14.341 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_shift_reg[4]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.049     ; 3.218      ;
; 14.341 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_shift_reg[3]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.049     ; 3.218      ;
; 14.341 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_shift_reg[2]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.049     ; 3.218      ;
; 14.341 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_shift_reg[1]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.049     ; 3.218      ;
; 14.341 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_active_reg                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.048     ; 3.219      ;
; 14.341 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serial_out_reg                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.048     ; 3.219      ;
; 14.341 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_clock_last_reg                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.048     ; 3.219      ;
; 14.341 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_holding_full_reg                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.048     ; 3.219      ;
; 14.341 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|irqst_reg[4]                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.048     ; 3.219      ;
; 14.341 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|porta_control_reg[1]                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.051     ; 3.216      ;
; 14.341 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|irqa_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.051     ; 3.216      ;
; 14.341 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_control_reg[1]                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.051     ; 3.216      ;
; 14.341 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|irqb_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.051     ; 3.216      ;
; 14.341 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot3_reg[3]                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.054     ; 3.213      ;
; 14.341 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|porta_control_reg[3]                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.051     ; 3.216      ;
; 14.341 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_control_reg[3]                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.051     ; 3.216      ;
; 14.341 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|serial_ip_overrun_reg                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.051     ; 3.216      ;
; 14.341 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_control_reg[5]                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.051     ; 3.216      ;
; 14.341 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|porta_control_reg[5]                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.051     ; 3.216      ;
; 14.341 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot2_reg[5]                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.051     ; 3.216      ;
; 14.341 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot3_reg[5]                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.054     ; 3.213      ;
; 14.341 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot1_reg[5]                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.051     ; 3.216      ;
+--------+------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: 'CLOCK_27[0]'                                                                                                                                                                                                                                ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------+-----------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                              ; To Node                                                   ; Launch Clock                                                          ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------+-----------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.363 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 2.202      ; 2.042      ;
; -0.363 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 2.202      ; 2.042      ;
; -0.363 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 2.202      ; 2.042      ;
; -0.363 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 2.202      ; 2.042      ;
; -0.363 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 2.202      ; 2.042      ;
; -0.363 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 2.202      ; 2.042      ;
; -0.363 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 2.202      ; 2.042      ;
; -0.363 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 2.202      ; 2.042      ;
; -0.362 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 2.202      ; 2.043      ;
; -0.317 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 2.205      ; 2.091      ;
; -0.317 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 2.205      ; 2.091      ;
; -0.317 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 2.205      ; 2.091      ;
; -0.317 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 2.205      ; 2.091      ;
; -0.317 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 2.205      ; 2.091      ;
; -0.317 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 2.205      ; 2.091      ;
; -0.317 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 2.205      ; 2.091      ;
; -0.317 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 2.205      ; 2.091      ;
; -0.316 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 2.205      ; 2.092      ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------+-----------------------------------------------------------------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                         ; To Node                                                                                                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.727 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|dffe4                                                                 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|altsyncram_v6b1:altsyncram2|ram_block5a0                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.205      ; 1.022      ;
; 0.880 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a55 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.150      ;
; 0.880 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a54 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.150      ;
; 0.880 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a53 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.150      ;
; 0.880 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a52 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.150      ;
; 0.880 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a51 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.150      ;
; 0.880 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a50 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.150      ;
; 0.880 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a49 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.150      ;
; 0.880 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a48 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.150      ;
; 0.880 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a39 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.150      ;
; 0.880 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a38 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.150      ;
; 0.880 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a37 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.150      ;
; 0.880 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a36 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.150      ;
; 0.880 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a35 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.150      ;
; 0.880 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a34 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.150      ;
; 0.880 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a33 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.150      ;
; 0.880 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a32 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.150      ;
; 0.880 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a31 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.150      ;
; 0.880 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a30 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.150      ;
; 0.880 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a29 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.150      ;
; 0.880 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a28 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.150      ;
; 0.880 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a23 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.150      ;
; 0.880 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a22 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.150      ;
; 0.880 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a21 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.150      ;
; 0.880 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a20 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.150      ;
; 0.880 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a19 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.150      ;
; 0.880 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a18 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.150      ;
; 0.880 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a17 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.150      ;
; 0.880 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a16 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.150      ;
; 0.880 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a7  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.150      ;
; 0.880 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a6  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.150      ;
; 0.880 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a5  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.150      ;
; 0.880 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a4  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.150      ;
; 0.880 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a3  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.150      ;
; 0.880 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a2  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.150      ;
; 0.880 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a1  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.150      ;
; 0.880 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.150      ;
; 1.034 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a63 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 1.300      ;
; 1.034 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a62 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 1.300      ;
; 1.034 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a61 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 1.300      ;
; 1.034 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a60 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 1.300      ;
; 1.034 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a59 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 1.300      ;
; 1.034 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a58 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 1.300      ;
; 1.034 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a57 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 1.300      ;
; 1.034 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a56 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 1.300      ;
; 1.034 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a47 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 1.300      ;
; 1.034 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a46 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 1.300      ;
; 1.034 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a45 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 1.300      ;
; 1.034 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a44 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 1.300      ;
; 1.034 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a43 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 1.300      ;
; 1.034 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a42 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 1.300      ;
; 1.034 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a41 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 1.300      ;
; 1.034 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a40 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 1.300      ;
; 1.034 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a27 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 1.300      ;
; 1.034 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a26 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 1.300      ;
; 1.034 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a25 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 1.300      ;
; 1.034 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a24 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 1.300      ;
; 1.034 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a15 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 1.300      ;
; 1.034 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a14 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 1.300      ;
; 1.034 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a13 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 1.300      ;
; 1.034 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a12 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 1.300      ;
; 1.034 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a11 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 1.300      ;
; 1.034 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a10 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 1.300      ;
; 1.034 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a9  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 1.300      ;
; 1.034 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a8  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 1.300      ;
; 1.653 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[1]                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.290      ; 2.027      ;
; 1.653 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[25]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.292      ; 2.029      ;
; 1.666 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[21]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.283      ; 2.033      ;
; 1.666 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[18]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.283      ; 2.033      ;
; 1.666 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[22]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.283      ; 2.033      ;
; 1.669 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[6]                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.281      ; 2.034      ;
; 1.671 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[15]                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.285      ; 2.040      ;
; 1.680 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[10]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.268      ; 2.032      ;
; 1.680 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[13]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.271      ; 2.035      ;
; 1.680 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[23]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.270      ; 2.034      ;
; 1.680 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[14]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.268      ; 2.032      ;
; 1.680 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[11]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.271      ; 2.035      ;
; 1.689 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[0]                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.268      ; 2.041      ;
; 1.690 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[13]                                                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.264      ; 2.038      ;
; 1.690 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[15]                                                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.264      ; 2.038      ;
; 1.690 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[14]                                                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.264      ; 2.038      ;
; 1.697 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[0]                                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.257      ; 2.038      ;
; 1.744 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[25]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.250      ; 2.078      ;
; 1.754 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[1]                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.238      ; 2.076      ;
; 1.767 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[21]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.231      ; 2.082      ;
; 1.767 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[18]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.231      ; 2.082      ;
; 1.767 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[22]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.231      ; 2.082      ;
; 1.770 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[6]                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.229      ; 2.083      ;
; 1.772 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[15]                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.233      ; 2.089      ;
; 1.781 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[10]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.216      ; 2.081      ;
; 1.781 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[13]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 2.084      ;
; 1.781 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[23]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.218      ; 2.083      ;
; 1.781 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[14]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.216      ; 2.081      ;
; 1.781 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[11]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 2.084      ;
; 1.781 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[13]                                                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.222      ; 2.087      ;
; 1.781 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[15]                                                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.222      ; 2.087      ;
; 1.781 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[14]                                                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.222      ; 2.087      ;
; 1.788 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[0]                                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.215      ; 2.087      ;
; 1.790 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                                                                  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[0]                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.216      ; 2.090      ;
; 1.844 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[20]                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.280      ; 2.208      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                   ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                              ; To Node                                                       ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 2.227 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|reply_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.095      ; 2.425      ;
; 2.227 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.095      ; 2.425      ;
; 2.227 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.095      ; 2.425      ;
; 2.227 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.095      ; 2.425      ;
; 2.228 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.094      ; 2.425      ;
; 2.228 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.094      ; 2.425      ;
; 2.228 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.094      ; 2.425      ;
; 2.228 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.094      ; 2.425      ;
; 2.228 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.094      ; 2.425      ;
; 2.228 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.094      ; 2.425      ;
; 2.228 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.094      ; 2.425      ;
; 2.228 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.094      ; 2.425      ;
; 2.228 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.094      ; 2.425      ;
; 2.228 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.094      ; 2.425      ;
; 2.228 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.094      ; 2.425      ;
; 2.228 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.094      ; 2.425      ;
; 2.228 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cke_reg                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 2.420      ;
; 2.234 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 2.426      ;
; 2.234 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 2.426      ;
; 2.234 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 2.426      ;
; 2.234 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 2.426      ;
; 2.234 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 2.426      ;
; 2.234 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 2.426      ;
; 2.234 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 2.426      ;
; 2.234 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 2.426      ;
; 2.234 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 2.426      ;
; 2.234 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 2.426      ;
; 2.234 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 2.426      ;
; 2.234 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 2.426      ;
; 2.234 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 2.426      ;
; 2.234 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 2.426      ;
; 2.235 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[23]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 2.417      ;
; 2.235 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[28]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.088      ; 2.426      ;
; 2.235 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[25]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 2.417      ;
; 2.235 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[0]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 2.427      ;
; 2.235 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[3]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 2.427      ;
; 2.235 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[1]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 2.427      ;
; 2.235 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[4]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 2.427      ;
; 2.235 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[5]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 2.427      ;
; 2.235 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[7]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 2.427      ;
; 2.235 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[2]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 2.427      ;
; 2.235 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[6]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 2.427      ;
; 2.235 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[15]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 2.427      ;
; 2.235 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[13]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 2.427      ;
; 2.235 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[30]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 2.417      ;
; 2.235 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[10]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 2.427      ;
; 2.235 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[24]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 2.417      ;
; 2.235 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[31]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.088      ; 2.426      ;
; 2.235 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[8]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 2.427      ;
; 2.235 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[14]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 2.427      ;
; 2.235 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[26]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.088      ; 2.426      ;
; 2.235 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[22]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.076      ; 2.414      ;
; 2.235 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[27]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.088      ; 2.426      ;
; 2.235 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[12]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 2.427      ;
; 2.235 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[29]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 2.417      ;
; 2.235 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[16]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.076      ; 2.414      ;
; 2.235 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[9]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 2.427      ;
; 2.235 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[17]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.076      ; 2.414      ;
; 2.235 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[11]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 2.427      ;
; 2.236 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[20]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.085      ; 2.424      ;
; 2.236 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[21]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.085      ; 2.424      ;
; 2.236 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[18]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.085      ; 2.424      ;
; 2.236 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[19]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.085      ; 2.424      ;
; 2.241 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 2.427      ;
; 2.241 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 2.427      ;
; 2.241 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 2.427      ;
; 2.241 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 2.427      ;
; 2.241 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 2.427      ;
; 2.241 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 2.427      ;
; 2.241 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 2.427      ;
; 2.241 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 2.427      ;
; 2.241 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 2.427      ;
; 2.241 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 2.427      ;
; 2.241 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 2.427      ;
; 2.314 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.071      ; 2.468      ;
; 2.314 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_5   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.071      ; 2.468      ;
; 2.315 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_6   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.070      ; 2.468      ;
; 2.315 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_7   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.070      ; 2.468      ;
; 2.332 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.042      ; 2.457      ;
; 2.332 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.042      ; 2.457      ;
; 2.332 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.051      ; 2.466      ;
; 2.332 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.051      ; 2.466      ;
; 2.337 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.043      ; 2.463      ;
; 2.337 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.043      ; 2.463      ;
; 2.338 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.044      ; 2.465      ;
; 2.338 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.044      ; 2.465      ;
; 2.339 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.037      ; 2.459      ;
; 2.339 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.046      ; 2.468      ;
; 2.339 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.046      ; 2.468      ;
; 2.344 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.034      ; 2.461      ;
; 2.435 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 2.591      ;
; 2.435 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 2.591      ;
; 2.435 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ba_reg[0]                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 2.587      ;
; 2.435 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|we_n_reg                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 2.590      ;
; 2.435 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ldqm_reg                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 2.590      ;
; 2.435 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[0]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.076      ; 2.588      ;
; 2.435 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[3]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 2.590      ;
; 2.436 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 2.591      ;
; 2.436 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 2.591      ;
; 2.436 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ba_reg[1]                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.076      ; 2.589      ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                             ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                 ; Clock Edge ; Target                                                        ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------+
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[16]             ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[17]             ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[22]             ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[23]             ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[24]             ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[25]             ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[29]             ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[30]             ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cke_reg                      ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|reply_reg                    ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[0]              ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[10]             ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[11]             ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[12]             ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[13]             ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[14]             ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[15]             ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[18]             ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[19]             ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[1]              ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[20]             ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[21]             ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[2]              ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[3]              ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[4]              ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[5]              ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[6]              ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[7]              ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[8]              ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[9]              ;
; 4.190 ; 4.406        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[26]             ;
; 4.190 ; 4.406        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[27]             ;
; 4.190 ; 4.406        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[28]             ;
; 4.190 ; 4.406        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[31]             ;
; 4.190 ; 4.345        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10  ;
; 4.190 ; 4.345        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11  ;
; 4.190 ; 4.345        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4   ;
; 4.190 ; 4.345        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_5   ;
; 4.190 ; 4.345        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_6   ;
; 4.190 ; 4.345        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_7   ;
; 4.190 ; 4.345        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8   ;
; 4.190 ; 4.345        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9   ;
; 4.192 ; 4.347        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg                ;
; 4.192 ; 4.347        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1   ;
; 4.193 ; 4.348        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12  ;
; 4.193 ; 4.348        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13  ;
; 4.193 ; 4.348        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14  ;
; 4.193 ; 4.348        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15  ;
; 4.193 ; 4.348        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2   ;
; 4.193 ; 4.348        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3   ;
; 4.195 ; 4.350        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[10]                ;
; 4.195 ; 4.350        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[11]                ;
; 4.195 ; 4.350        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[4]                 ;
; 4.195 ; 4.350        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[5]                 ;
; 4.195 ; 4.350        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[6]                 ;
; 4.195 ; 4.350        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[7]                 ;
; 4.195 ; 4.350        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[8]                 ;
; 4.195 ; 4.350        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[9]                 ;
; 4.197 ; 4.352        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[0]                 ;
; 4.197 ; 4.352        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[1]                 ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                     ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                 ; Clock Edge ; Target                                                                                                                                ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+
; 4.331 ; 4.400        ; 0.069          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 4.357 ; 4.410        ; 0.053          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 4.400 ; 4.400        ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 4.410 ; 4.410        ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                         ;
+-------+--------------+----------------+-----------------+-----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type            ; Clock                                                                 ; Clock Edge ; Target                                                                                                                                                                                                                                     ;
+-------+--------------+----------------+-----------------+-----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|generic_ram_infer:freezer_bram|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_address_reg0 ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|generic_ram_infer:freezer_bram|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_we_reg       ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|altsyncram_v6b1:altsyncram2|ram_block5a0~porta_address_reg0                                                                    ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_0h81:auto_generated|ram_block1a0~porta_address_reg0                                                                                              ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_0h81:auto_generated|ram_block1a0~porta_we_reg                                                                                                    ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a13~porta_address_reg0                                                                                                                           ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a17~porta_address_reg0                                                                                                                           ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_fi41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                           ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_fi41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                 ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_address_reg0    ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|altsyncram_v6b1:altsyncram2|ram_block5a0                                                                                       ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|altsyncram_v6b1:altsyncram2|ram_block5a0~portb_address_reg0                                                                    ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_0h81:auto_generated|ram_block1a4~porta_address_reg0                                                                                              ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_0h81:auto_generated|ram_block1a4~porta_we_reg                                                                                                    ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_0h81:auto_generated|ram_block1a4~porta_address_reg0                                                                                              ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_0h81:auto_generated|ram_block1a4~porta_we_reg                                                                                                    ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a10~porta_address_reg0                                                                                                                           ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a11~porta_address_reg0                                                                                                                           ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a15~porta_address_reg0                                                                                                                           ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a19~porta_address_reg0                                                                                                                           ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a22~porta_address_reg0                                                                                                                           ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a25~porta_address_reg0                                                                                                                           ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a27~porta_address_reg0                                                                                                                           ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a28~porta_address_reg0                                                                                                                           ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a31~porta_address_reg0                                                                                                                           ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a5~porta_address_reg0                                                                                                                            ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a7~porta_address_reg0                                                                                                                            ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a8~porta_address_reg0                                                                                                                            ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_fi41:auto_generated|ram_block1a2~porta_address_reg0                                                                                                           ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_fi41:auto_generated|ram_block1a2~porta_we_reg                                                                                                                 ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_fi41:auto_generated|ram_block1a2~porta_address_reg0                                                                                                           ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_fi41:auto_generated|ram_block1a2~porta_we_reg                                                                                                                 ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_fi41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                            ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_fi41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                  ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_fi41:auto_generated|ram_block1a2~porta_address_reg0                                                                                                            ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_fi41:auto_generated|ram_block1a2~porta_we_reg                                                                                                                  ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|altsyncram_aj81:FIFOram|ram_block1a0~porta_address_reg0             ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|altsyncram_aj81:FIFOram|ram_block1a0~porta_we_reg                   ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_rj31:auto_generated|a_dpfifo_2q31:dpfifo|altsyncram_eg81:FIFOram|ram_block1a0~porta_address_reg0           ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_rj31:auto_generated|a_dpfifo_2q31:dpfifo|altsyncram_eg81:FIFOram|ram_block1a0~porta_we_reg                 ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|generic_ram_infer:freezer_bram|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~portb_address_reg0    ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|altsyncram_v6b1:altsyncram2|ram_block5a0~porta_datain_reg0                                                                     ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_0h81:auto_generated|ram_block1a0~porta_address_reg0                                                                                              ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_0h81:auto_generated|ram_block1a0~porta_we_reg                                                                                                    ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_0h81:auto_generated|ram_block1a0~porta_datain_reg0                                                                                               ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a12~porta_address_reg0                                                                                                                           ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a20~porta_address_reg0                                                                                                                           ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a9~porta_address_reg0                                                                                                                            ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_fi41:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                            ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_fi41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                          ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_fi41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_fi41:auto_generated|ram_block1a2~porta_address_reg0                                                                                                          ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_fi41:auto_generated|ram_block1a2~porta_we_reg                                                                                                                ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|generic_ram_infer:reg_file1|altsyncram:ram_block_rtl_0|altsyncram_jf41:auto_generated|ram_block1a0~porta_address_reg0                                 ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|generic_ram_infer:reg_file1|altsyncram:ram_block_rtl_0|altsyncram_jf41:auto_generated|ram_block1a0~porta_we_reg                                       ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0                       ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0     ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a1                       ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a16                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a17                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a18                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a19                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a2                       ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a20                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a21                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a22                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a23                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a28                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a29                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a3                       ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a30                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a31                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a32                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a33                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a34                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a35                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a36                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a37                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a38                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a39                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a4                       ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a48                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a49                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a5                       ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a50                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a51                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a52                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a53                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a54                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a55                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a6                       ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a7                       ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|gtia_palette:palette4|altsyncram:Mux21_rtl_0|altsyncram_tt01:auto_generated|ram_block1a0~porta_address_reg0                                                                                                       ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_0h81:auto_generated|ram_block1a4~porta_datain_reg0                                                                                               ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_0h81:auto_generated|ram_block1a4~porta_datain_reg0                                                                                               ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a18~porta_address_reg0                                                                                                                           ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a24~porta_address_reg0                                                                                                                           ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a29~porta_address_reg0                                                                                                                           ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a3~porta_address_reg0                                                                                                                            ;
+-------+--------------+----------------+-----------------+-----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                           ;
+--------+--------------+----------------+------------------+----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                ; Clock Edge ; Target                                                                                     ;
+--------+--------------+----------------+------------------+----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------+
; 16.300 ; 16.300       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 16.300 ; 16.300       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 16.300 ; 16.300       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 16.300 ; 16.300       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]                      ;
; 16.300 ; 16.300       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 16.310 ; 16.310       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 16.310 ; 16.310       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 16.314 ; 16.314       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 16.316 ; 16.316       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 16.321 ; 16.321       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 16.321 ; 16.321       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 16.331 ; 16.331       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 16.331 ; 16.331       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 16.331 ; 16.331       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 16.331 ; 16.331       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]                      ;
; 16.331 ; 16.331       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
+--------+--------------+----------------+------------------+----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK_27[0]'                                                                                                               ;
+--------+--------------+----------------+------------------+-------------+------------+--------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock       ; Clock Edge ; Target                                                                         ;
+--------+--------------+----------------+------------------+-------------+------------+--------------------------------------------------------------------------------+
; 17.784 ; 17.968       ; 0.184          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                      ;
; 17.784 ; 17.968       ; 0.184          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                      ;
; 17.784 ; 17.968       ; 0.184          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                      ;
; 17.784 ; 17.968       ; 0.184          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                      ;
; 17.784 ; 17.968       ; 0.184          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                      ;
; 17.784 ; 17.968       ; 0.184          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                      ;
; 17.784 ; 17.968       ; 0.184          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                      ;
; 17.784 ; 17.968       ; 0.184          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                      ;
; 17.784 ; 17.968       ; 0.184          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                        ;
; 17.928 ; 17.928       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 17.928 ; 17.928       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 17.929 ; 17.929       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                       ;
; 17.929 ; 17.929       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|observablevcoout             ;
; 17.960 ; 17.960       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~input|o                                                            ;
; 17.964 ; 17.964       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[0]|clk                                          ;
; 17.964 ; 17.964       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[1]|clk                                          ;
; 17.964 ; 17.964       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[2]|clk                                          ;
; 17.964 ; 17.964       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[3]|clk                                          ;
; 17.964 ; 17.964       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[4]|clk                                          ;
; 17.964 ; 17.964       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[5]|clk                                          ;
; 17.964 ; 17.964       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[6]|clk                                          ;
; 17.964 ; 17.964       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[7]|clk                                          ;
; 17.964 ; 17.964       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_toggle_reg|clk                                            ;
; 17.970 ; 17.970       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 17.971 ; 17.971       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|inclk[0]                     ;
; 17.972 ; 17.972       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~inputclkctrl|inclk[0]                                              ;
; 17.972 ; 17.972       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~inputclkctrl|outclk                                                ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~input|i                                                            ;
; 18.519 ; 18.519       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~input|i                                                            ;
; 18.851 ; 19.067       ; 0.216          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                      ;
; 18.851 ; 19.067       ; 0.216          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                      ;
; 18.851 ; 19.067       ; 0.216          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                      ;
; 18.851 ; 19.067       ; 0.216          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                      ;
; 18.851 ; 19.067       ; 0.216          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                      ;
; 18.851 ; 19.067       ; 0.216          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                      ;
; 18.851 ; 19.067       ; 0.216          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                      ;
; 18.851 ; 19.067       ; 0.216          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                      ;
; 18.851 ; 19.067       ; 0.216          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                        ;
; 19.064 ; 19.064       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~inputclkctrl|inclk[0]                                              ;
; 19.064 ; 19.064       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~inputclkctrl|outclk                                                ;
; 19.066 ; 19.066       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|inclk[0]                     ;
; 19.067 ; 19.067       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 19.073 ; 19.073       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[0]|clk                                          ;
; 19.073 ; 19.073       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[1]|clk                                          ;
; 19.073 ; 19.073       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[2]|clk                                          ;
; 19.073 ; 19.073       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[3]|clk                                          ;
; 19.073 ; 19.073       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[4]|clk                                          ;
; 19.073 ; 19.073       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[5]|clk                                          ;
; 19.073 ; 19.073       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[6]|clk                                          ;
; 19.073 ; 19.073       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[7]|clk                                          ;
; 19.073 ; 19.073       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_toggle_reg|clk                                            ;
; 19.077 ; 19.077       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~input|o                                                            ;
; 19.107 ; 19.107       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                       ;
; 19.107 ; 19.107       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|observablevcoout             ;
; 19.108 ; 19.108       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 19.108 ; 19.108       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 33.037 ; 37.037       ; 4.000          ; Port Rate        ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]                                                                    ;
; 35.037 ; 37.037       ; 2.000          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                      ;
; 35.037 ; 37.037       ; 2.000          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                      ;
; 35.037 ; 37.037       ; 2.000          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                      ;
; 35.037 ; 37.037       ; 2.000          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                      ;
; 35.037 ; 37.037       ; 2.000          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                      ;
; 35.037 ; 37.037       ; 2.000          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                      ;
; 35.037 ; 37.037       ; 2.000          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                      ;
; 35.037 ; 37.037       ; 2.000          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                      ;
; 35.037 ; 37.037       ; 2.000          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                        ;
+--------+--------------+----------------+------------------+-------------+------------+--------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                    ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                                                                                                                                                                                                                              ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 40.631 ; 41.641       ; 1.010          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                                       ;
; 40.680 ; 41.690       ; 1.010          ; Low Pulse Width  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                                       ;
; 41.415 ; 41.645       ; 0.230          ; Low Pulse Width  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|altsyncram:altsyncram4|altsyncram_72m3:auto_generated|ram_block1a0~porta_address_reg0                 ;
; 41.415 ; 41.645       ; 0.230          ; Low Pulse Width  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|altsyncram:altsyncram4|altsyncram_cul3:auto_generated|ram_block1a0~porta_address_reg0 ;
; 41.417 ; 41.647       ; 0.230          ; Low Pulse Width  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|altsyncram:altsyncram4|altsyncram_72m3:auto_generated|ram_block1a0~porta_datain_reg0                  ;
; 41.417 ; 41.647       ; 0.230          ; Low Pulse Width  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|altsyncram:altsyncram4|altsyncram_cul3:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 41.437 ; 41.653       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|configupdate3_state                                                                                   ;
; 41.437 ; 41.653       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|configupdate3_state                                                                   ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                                                                                                                                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[0]                                                                                                                                                                                               ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[10]                                                                                                                                                                                              ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[11]                                                                                                                                                                                              ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[12]                                                                                                                                                                                              ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[13]                                                                                                                                                                                              ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[14]                                                                                                                                                                                              ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[15]                                                                                                                                                                                              ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[16]                                                                                                                                                                                              ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[17]                                                                                                                                                                                              ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[18]                                                                                                                                                                                              ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[19]                                                                                                                                                                                              ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                                                               ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[20]                                                                                                                                                                                              ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[21]                                                                                                                                                                                              ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[22]                                                                                                                                                                                              ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[23]                                                                                                                                                                                              ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[24]                                                                                                                                                                                              ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                                                               ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                                                               ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                                                               ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                                                               ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                                                               ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                                                               ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[8]                                                                                                                                                                                               ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[9]                                                                                                                                                                                               ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                                       ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                                                       ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                                                       ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                                       ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|reset_n_reg                                                                                                                                                                                                            ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                                                                                ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C4_ena_state                                                                                          ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                                            ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_init_state                                                                                   ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reset_state                                                                                           ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|areset_init_state_1                                                                   ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[0]                                                                                                                                                                                ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[1]                                                                                                                                                                                ;
; 41.451 ; 41.667       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[0]                                         ;
; 41.451 ; 41.667       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[1]                                         ;
; 41.451 ; 41.667       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[2]                                         ;
; 41.451 ; 41.667       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[3]                                         ;
; 41.451 ; 41.667       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[4]                                         ;
; 41.451 ; 41.667       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[5]                                         ;
; 41.451 ; 41.667       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[6]                                         ;
; 41.451 ; 41.667       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[7]                                         ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C0_data_state                                                                                         ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C0_ena_state                                                                                          ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C1_data_state                                                                                         ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C1_ena_state                                                                                          ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C2_data_state                                                                                         ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C2_ena_state                                                                                          ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C3_data_state                                                                                         ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C3_ena_state                                                                                          ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C4_data_state                                                                                         ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|configupdate2_state                                                                                   ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|configupdate_state                                                                                    ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[0]                                         ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1]                                         ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2]                                         ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3]                                         ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[4]                                         ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5]                                         ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[0]                                         ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1]                                         ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2]                                         ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3]                                         ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4]                                         ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0]                                         ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1]                                         ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[2]                                         ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[3]                                         ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[4]                                         ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[5]                                         ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[6]                                         ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[7]                                         ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_counter_state                                                                                ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                                                   ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_seq_data_state                                                                               ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_seq_ena_state                                                                                ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|tmp_seq_ena_state                                                                                     ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_data_state                                                                         ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_ena_state                                                                          ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_data_state                                                                         ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_ena_state                                                                          ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C2_data_state                                                                         ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C2_ena_state                                                                          ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_data_state                                                                         ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]'                                                                                                                                                                         ;
+-----------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+
; Slack     ; Actual Width ; Required Width ; Type             ; Clock                                                                 ; Clock Edge ; Target                                                                                                                                ;
+-----------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+
; 44052.600 ; 44052.816    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_parity                                                                                                         ;
; 44052.600 ; 44052.816    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_r_inc                                                                                                          ;
; 44052.600 ; 44052.816    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[0]                                                                                                        ;
; 44052.600 ; 44052.816    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[1]                                                                                                        ;
; 44052.600 ; 44052.816    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[2]                                                                                                        ;
; 44052.600 ; 44052.816    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ;
; 44052.600 ; 44052.816    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ;
; 44052.600 ; 44052.816    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ;
; 44052.600 ; 44052.816    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ;
; 44052.600 ; 44052.816    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ;
; 44052.600 ; 44052.816    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ;
; 44052.600 ; 44052.816    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ;
; 44052.600 ; 44052.816    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ;
; 44052.601 ; 44052.817    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ;
; 44052.601 ; 44052.817    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_kbd_data                                                                                                       ;
; 44052.601 ; 44052.817    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ;
; 44052.601 ; 44052.817    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[1]                                                                                                    ;
; 44052.601 ; 44052.817    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[2]                                                                                                    ;
; 44052.601 ; 44052.817    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[3]                                                                                                    ;
; 44052.635 ; 44052.819    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_parity                                                                                                         ;
; 44052.635 ; 44052.819    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_r_inc                                                                                                          ;
; 44052.635 ; 44052.819    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[0]                                                                                                        ;
; 44052.635 ; 44052.819    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[1]                                                                                                        ;
; 44052.635 ; 44052.819    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[2]                                                                                                        ;
; 44052.635 ; 44052.819    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ;
; 44052.635 ; 44052.819    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ;
; 44052.635 ; 44052.819    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ;
; 44052.635 ; 44052.819    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ;
; 44052.635 ; 44052.819    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ;
; 44052.635 ; 44052.819    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ;
; 44052.635 ; 44052.819    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ;
; 44052.635 ; 44052.819    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ;
; 44052.636 ; 44052.820    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ;
; 44052.636 ; 44052.820    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_kbd_data                                                                                                       ;
; 44052.636 ; 44052.820    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ;
; 44052.636 ; 44052.820    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[1]                                                                                                    ;
; 44052.636 ; 44052.820    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[2]                                                                                                    ;
; 44052.636 ; 44052.820    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[3]                                                                                                    ;
; 44052.745 ; 44052.814    ; 0.069          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Fall       ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 44052.771 ; 44052.824    ; 0.053          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Fall       ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 44052.814 ; 44052.814    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; pll_switcher|\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 44052.814 ; 44052.814    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; pll_switcher|\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|outclk                                                 ;
; 44052.815 ; 44052.815    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|Equal5~0_NEW_REG0|clk                                                                                                      ;
; 44052.815 ; 44052.815    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_kbd_data|clk                                                                                                           ;
; 44052.815 ; 44052.815    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_parity|clk                                                                                                             ;
; 44052.815 ; 44052.815    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_r_inc|clk                                                                                                              ;
; 44052.815 ; 44052.815    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_rptr[0]|clk                                                                                                            ;
; 44052.815 ; 44052.815    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_rptr[1]|clk                                                                                                            ;
; 44052.815 ; 44052.815    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_rptr[2]|clk                                                                                                            ;
; 44052.815 ; 44052.815    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[0]|clk                                                                                                         ;
; 44052.815 ; 44052.815    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[1]|clk                                                                                                         ;
; 44052.815 ; 44052.815    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[2]|clk                                                                                                         ;
; 44052.815 ; 44052.815    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[3]|clk                                                                                                         ;
; 44052.815 ; 44052.815    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[4]|clk                                                                                                         ;
; 44052.815 ; 44052.815    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[5]|clk                                                                                                         ;
; 44052.815 ; 44052.815    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[6]|clk                                                                                                         ;
; 44052.815 ; 44052.815    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[7]|clk                                                                                                         ;
; 44052.815 ; 44052.815    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[0]|clk                                                                                                        ;
; 44052.815 ; 44052.815    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[1]|clk                                                                                                        ;
; 44052.815 ; 44052.815    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[2]|clk                                                                                                        ;
; 44052.815 ; 44052.815    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[3]|clk                                                                                                        ;
; 44052.822 ; 44052.822    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|Equal5~0_NEW_REG0|clk                                                                                                      ;
; 44052.822 ; 44052.822    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_kbd_data|clk                                                                                                           ;
; 44052.822 ; 44052.822    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_parity|clk                                                                                                             ;
; 44052.822 ; 44052.822    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_r_inc|clk                                                                                                              ;
; 44052.822 ; 44052.822    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_rptr[0]|clk                                                                                                            ;
; 44052.822 ; 44052.822    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_rptr[1]|clk                                                                                                            ;
; 44052.822 ; 44052.822    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_rptr[2]|clk                                                                                                            ;
; 44052.822 ; 44052.822    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[0]|clk                                                                                                         ;
; 44052.822 ; 44052.822    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[1]|clk                                                                                                         ;
; 44052.822 ; 44052.822    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[2]|clk                                                                                                         ;
; 44052.822 ; 44052.822    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[3]|clk                                                                                                         ;
; 44052.822 ; 44052.822    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[4]|clk                                                                                                         ;
; 44052.822 ; 44052.822    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[5]|clk                                                                                                         ;
; 44052.822 ; 44052.822    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[6]|clk                                                                                                         ;
; 44052.822 ; 44052.822    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[7]|clk                                                                                                         ;
; 44052.822 ; 44052.822    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[0]|clk                                                                                                        ;
; 44052.822 ; 44052.822    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[1]|clk                                                                                                        ;
; 44052.822 ; 44052.822    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[2]|clk                                                                                                        ;
; 44052.822 ; 44052.822    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[3]|clk                                                                                                        ;
; 44052.824 ; 44052.824    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; pll_switcher|\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 44052.824 ; 44052.824    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; pll_switcher|\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|outclk                                                 ;
; 88103.638 ; 88105.638    ; 2.000          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ;
; 88103.638 ; 88105.638    ; 2.000          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_kbd_data                                                                                                       ;
; 88103.638 ; 88105.638    ; 2.000          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_parity                                                                                                         ;
; 88103.638 ; 88105.638    ; 2.000          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_r_inc                                                                                                          ;
; 88103.638 ; 88105.638    ; 2.000          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[0]                                                                                                        ;
; 88103.638 ; 88105.638    ; 2.000          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[1]                                                                                                        ;
; 88103.638 ; 88105.638    ; 2.000          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[2]                                                                                                        ;
; 88103.638 ; 88105.638    ; 2.000          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ;
; 88103.638 ; 88105.638    ; 2.000          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ;
; 88103.638 ; 88105.638    ; 2.000          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ;
; 88103.638 ; 88105.638    ; 2.000          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ;
; 88103.638 ; 88105.638    ; 2.000          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ;
; 88103.638 ; 88105.638    ; 2.000          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ;
; 88103.638 ; 88105.638    ; 2.000          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ;
; 88103.638 ; 88105.638    ; 2.000          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ;
; 88103.638 ; 88105.638    ; 2.000          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ;
; 88103.638 ; 88105.638    ; 2.000          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[1]                                                                                                    ;
; 88103.638 ; 88105.638    ; 2.000          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[2]                                                                                                    ;
+-----------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                      ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 1.472 ; 2.024 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 1.467 ; 2.019 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 1.470 ; 2.022 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 1.472 ; 2.024 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 1.472 ; 2.024 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 1.448 ; 2.006 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 1.458 ; 2.016 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 1.448 ; 2.006 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 1.448 ; 2.006 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 1.448 ; 2.000 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 1.448 ; 2.000 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 1.453 ; 2.005 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 1.453 ; 2.005 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 1.460 ; 2.012 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 1.460 ; 2.012 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 1.471 ; 2.023 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 1.471 ; 2.023 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                         ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; SDRAM_DQ[*]   ; CLOCK_27[0] ; -0.970 ; -1.524 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; -0.991 ; -1.543 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; -0.994 ; -1.546 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; -0.996 ; -1.548 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; -0.996 ; -1.548 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; -0.970 ; -1.528 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; -0.980 ; -1.538 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; -0.971 ; -1.529 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; -0.971 ; -1.529 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; -0.972 ; -1.524 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; -0.972 ; -1.524 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; -0.977 ; -1.529 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; -0.977 ; -1.529 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; -0.984 ; -1.536 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; -0.984 ; -1.536 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; -0.995 ; -1.547 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; -0.995 ; -1.547 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                              ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; SDRAM_A[*]    ; CLOCK_27[0] ; 1.291  ; 1.162  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; CLOCK_27[0] ; 1.164  ; 1.008  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; CLOCK_27[0] ; 1.165  ; 1.009  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; CLOCK_27[0] ; 1.165  ; 1.009  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; CLOCK_27[0] ; 1.176  ; 1.020  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; CLOCK_27[0] ; 1.124  ; 0.985  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; CLOCK_27[0] ; 1.291  ; 1.162  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; CLOCK_27[0] ; 1.276  ; 1.147  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; CLOCK_27[0] ; 1.280  ; 1.151  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; CLOCK_27[0] ; 1.280  ; 1.151  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; CLOCK_27[0] ; 1.279  ; 1.150  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; CLOCK_27[0] ; 1.164  ; 1.008  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; CLOCK_27[0] ; 1.286  ; 1.157  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; CLOCK_27[0] ; 1.163  ; 1.007  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; CLOCK_27[0] ; 1.163  ; 1.007  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; CLOCK_27[0] ; 1.154  ; 0.998  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CKE     ; CLOCK_27[0] ; 1.239  ; 1.151  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 1.287  ; 1.158  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 1.271  ; 1.142  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 1.268  ; 1.139  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 1.116  ; 0.977  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 1.116  ; 0.977  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 1.177  ; 1.021  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 1.187  ; 1.031  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 1.176  ; 1.020  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 1.176  ; 1.020  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 1.270  ; 1.141  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 1.270  ; 1.141  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 1.285  ; 1.156  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 1.285  ; 1.156  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 1.108  ; 0.969  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 1.278  ; 1.149  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 1.287  ; 1.158  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 1.117  ; 0.978  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH    ; CLOCK_27[0] ; 1.264  ; 1.135  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML    ; CLOCK_27[0] ; 1.176  ; 1.020  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nCAS    ; CLOCK_27[0] ; 1.163  ; 1.007  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nRAS    ; CLOCK_27[0] ; 1.162  ; 1.006  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nWE     ; CLOCK_27[0] ; 1.176  ; 1.020  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L       ; CLOCK_27[0] ; 2.887  ; 2.673  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R       ; CLOCK_27[0] ; 2.967  ; 2.799  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; LED           ; CLOCK_27[0] ; 3.142  ; 3.297  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]      ; CLOCK_27[0] ; 11.227 ; 11.227 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; CLOCK_27[0] ; 10.924 ; 10.932 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; CLOCK_27[0] ; 11.227 ; 11.227 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; CLOCK_27[0] ; 10.885 ; 10.866 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; CLOCK_27[0] ; 10.091 ; 9.978  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[4]     ; CLOCK_27[0] ; 10.357 ; 10.384 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[5]     ; CLOCK_27[0] ; 10.339 ; 10.312 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; CLOCK_27[0] ; 11.418 ; 11.397 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; CLOCK_27[0] ; 11.418 ; 11.397 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; CLOCK_27[0] ; 11.403 ; 11.385 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; CLOCK_27[0] ; 11.289 ; 11.265 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; CLOCK_27[0] ; 11.070 ; 10.976 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[4]     ; CLOCK_27[0] ; 10.400 ; 10.377 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[5]     ; CLOCK_27[0] ; 8.190  ; 8.185  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS        ; CLOCK_27[0] ; 3.271  ; 3.090  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]      ; CLOCK_27[0] ; 12.972 ; 13.033 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]     ; CLOCK_27[0] ; 12.316 ; 12.391 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]     ; CLOCK_27[0] ; 12.616 ; 12.651 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]     ; CLOCK_27[0] ; 12.972 ; 13.033 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]     ; CLOCK_27[0] ; 12.261 ; 12.233 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[4]     ; CLOCK_27[0] ; 11.913 ; 12.006 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[5]     ; CLOCK_27[0] ; 11.870 ; 11.895 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS        ; CLOCK_27[0] ; 3.247  ; 3.099  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; CLOCK_27[0] ; -1.618 ;        ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; CLOCK_27[0] ;        ; -1.735 ; Fall       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                      ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; SDRAM_A[*]    ; CLOCK_27[0] ; 0.718  ; 0.579  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; CLOCK_27[0] ; 0.758  ; 0.602  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; CLOCK_27[0] ; 0.759  ; 0.603  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; CLOCK_27[0] ; 0.759  ; 0.603  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; CLOCK_27[0] ; 0.770  ; 0.614  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; CLOCK_27[0] ; 0.718  ; 0.579  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; CLOCK_27[0] ; 0.886  ; 0.757  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; CLOCK_27[0] ; 0.870  ; 0.741  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; CLOCK_27[0] ; 0.875  ; 0.746  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; CLOCK_27[0] ; 0.875  ; 0.746  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; CLOCK_27[0] ; 0.874  ; 0.745  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; CLOCK_27[0] ; 0.758  ; 0.602  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; CLOCK_27[0] ; 0.881  ; 0.752  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; CLOCK_27[0] ; 0.748  ; 0.592  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; CLOCK_27[0] ; 0.756  ; 0.600  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; CLOCK_27[0] ; 0.748  ; 0.592  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CKE     ; CLOCK_27[0] ; 0.832  ; 0.743  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 0.703  ; 0.564  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 0.866  ; 0.737  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 0.863  ; 0.734  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 0.711  ; 0.572  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 0.711  ; 0.572  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 0.770  ; 0.614  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 0.780  ; 0.624  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 0.770  ; 0.614  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 0.770  ; 0.614  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 0.865  ; 0.736  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 0.865  ; 0.736  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 0.880  ; 0.751  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 0.880  ; 0.751  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 0.703  ; 0.564  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 0.873  ; 0.744  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 0.882  ; 0.753  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 0.712  ; 0.573  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH    ; CLOCK_27[0] ; 0.859  ; 0.730  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML    ; CLOCK_27[0] ; 0.769  ; 0.613  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nCAS    ; CLOCK_27[0] ; 0.757  ; 0.601  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nRAS    ; CLOCK_27[0] ; 0.756  ; 0.600  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nWE     ; CLOCK_27[0] ; 0.769  ; 0.613  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L       ; CLOCK_27[0] ; 2.470  ; 2.253  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R       ; CLOCK_27[0] ; 2.545  ; 2.372  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; LED           ; CLOCK_27[0] ; 2.703  ; 2.862  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]      ; CLOCK_27[0] ; 1.952  ; 1.808  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; CLOCK_27[0] ; 2.100  ; 2.010  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; CLOCK_27[0] ; 2.148  ; 2.101  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; CLOCK_27[0] ; 1.952  ; 1.808  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; CLOCK_27[0] ; 2.216  ; 2.110  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[4]     ; CLOCK_27[0] ; 2.296  ; 2.281  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[5]     ; CLOCK_27[0] ; 2.259  ; 2.275  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; CLOCK_27[0] ; 2.341  ; 2.257  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; CLOCK_27[0] ; 2.345  ; 2.289  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; CLOCK_27[0] ; 2.358  ; 2.276  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; CLOCK_27[0] ; 2.364  ; 2.386  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; CLOCK_27[0] ; 2.342  ; 2.257  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[4]     ; CLOCK_27[0] ; 2.341  ; 2.370  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[5]     ; CLOCK_27[0] ; 2.370  ; 2.351  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS        ; CLOCK_27[0] ; 2.838  ; 2.652  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]      ; CLOCK_27[0] ; 1.863  ; 1.835  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]     ; CLOCK_27[0] ; 1.863  ; 1.835  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]     ; CLOCK_27[0] ; 2.116  ; 2.096  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]     ; CLOCK_27[0] ; 2.779  ; 2.759  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]     ; CLOCK_27[0] ; 2.943  ; 2.928  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[4]     ; CLOCK_27[0] ; 2.352  ; 2.373  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[5]     ; CLOCK_27[0] ; 2.545  ; 2.569  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS        ; CLOCK_27[0] ; 2.816  ; 2.662  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; CLOCK_27[0] ; -2.001 ;        ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; CLOCK_27[0] ;        ; -2.119 ; Fall       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+


+----------------------------------------------------------+
; Propagation Delay                                        ;
+------------+-------------+-------+-------+-------+-------+
; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
+------------+-------------+-------+-------+-------+-------+
; CONF_DATA0 ; SPI_DO      ; 5.458 ; 5.458 ; 6.204 ; 6.177 ;
+------------+-------------+-------+-------+-------+-------+


+----------------------------------------------------------+
; Minimum Propagation Delay                                ;
+------------+-------------+-------+-------+-------+-------+
; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
+------------+-------------+-------+-------+-------+-------+
; CONF_DATA0 ; SPI_DO      ; 4.553 ; 4.436 ; 5.176 ; 5.176 ;
+------------+-------------+-------+-------+-------+-------+


+----------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                              ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 1.936 ; 1.981 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 1.939 ; 1.984 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 1.936 ; 1.981 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 1.954 ; 1.999 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 1.954 ; 1.999 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 1.947 ; 1.999 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 1.957 ; 2.009 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 1.946 ; 1.998 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 1.946 ; 1.998 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 1.938 ; 1.983 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 1.938 ; 1.983 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 1.953 ; 1.998 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 1.953 ; 1.998 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 1.946 ; 1.991 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 1.946 ; 1.991 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 1.955 ; 2.000 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 1.955 ; 2.000 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                      ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 0.730 ; 0.730 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 0.733 ; 0.733 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 0.730 ; 0.730 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 0.748 ; 0.748 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 0.748 ; 0.748 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 0.780 ; 0.780 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 0.790 ; 0.790 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 0.780 ; 0.780 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 0.780 ; 0.780 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 0.732 ; 0.732 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 0.732 ; 0.732 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 0.747 ; 0.747 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 0.747 ; 0.747 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 0.740 ; 0.740 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 0.740 ; 0.740 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 0.749 ; 0.749 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 0.749 ; 0.749 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                     ;
+---------------+-------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 2.013     ; 2.013     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 2.016     ; 2.016     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 2.013     ; 2.013     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 2.031     ; 2.031     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 2.031     ; 2.031     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 2.031     ; 2.031     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 2.041     ; 2.041     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 2.030     ; 2.030     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 2.030     ; 2.030     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 2.015     ; 2.015     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 2.015     ; 2.015     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 2.030     ; 2.030     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 2.030     ; 2.030     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 2.023     ; 2.023     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 2.023     ; 2.023     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 2.032     ; 2.032     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 2.032     ; 2.032     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+-------------+-----------+-----------+------------+-----------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                             ;
+---------------+-------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 0.761     ; 0.989     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 0.764     ; 0.992     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 0.761     ; 0.989     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 0.779     ; 1.007     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 0.779     ; 1.007     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 0.811     ; 1.055     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 0.821     ; 1.065     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 0.811     ; 1.055     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 0.811     ; 1.055     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 0.763     ; 0.991     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 0.763     ; 0.991     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 0.778     ; 1.006     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 0.778     ; 1.006     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 0.771     ; 0.999     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 0.771     ; 0.999     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 0.780     ; 1.008     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 0.780     ; 1.008     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+-------------+-----------+-----------+------------+-----------------------------------------------------------------------+


---------------------------------------------
; Fast 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+--------------------------------------------------------------------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary                                                                                                  ;
+------------------------------------------------------------------------+---------+--------+----------+---------+---------------------+
; Clock                                                                  ; Setup   ; Hold   ; Recovery ; Removal ; Minimum Pulse Width ;
+------------------------------------------------------------------------+---------+--------+----------+---------+---------------------+
; Worst-case Slack                                                       ; -4.849  ; -1.838 ; -1.292   ; -0.423  ; 4.093               ;
;  CLOCK_27[0]                                                           ; 33.660  ; 0.186  ; -1.292   ; -0.423  ; 17.784              ;
;  pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.890   ; 0.186  ; 2.099    ; 2.227   ; 4.093               ;
;  pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; -4.849  ; 0.136  ; 10.098   ; 0.727   ; 8.373               ;
;  pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -1.547  ; 8.109  ; N/A      ; N/A     ; 4.224               ;
;  pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 11.442  ; 0.186  ; N/A      ; N/A     ; 44052.506           ;
;  pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; N/A     ; N/A    ; N/A      ; N/A     ; 16.275              ;
;  reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 0.069   ; -1.838 ; N/A      ; N/A     ; 40.596              ;
; Design-wide TNS                                                        ; -12.235 ; -1.838 ; -11.62   ; -3.806  ; 0.0                 ;
;  CLOCK_27[0]                                                           ; 0.000   ; 0.000  ; -11.620  ; -3.806  ; 0.000               ;
;  pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000   ; 0.000  ; 0.000    ; 0.000   ; 0.000               ;
;  pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; -10.688 ; 0.000  ; 0.000    ; 0.000   ; 0.000               ;
;  pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -1.547  ; 0.000  ; N/A      ; N/A     ; 0.000               ;
;  pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000   ; 0.000  ; N/A      ; N/A     ; 0.000               ;
;  pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; N/A     ; N/A    ; N/A      ; N/A     ; 0.000               ;
;  reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 0.000   ; -1.838 ; N/A      ; N/A     ; 0.000               ;
+------------------------------------------------------------------------+---------+--------+----------+---------+---------------------+


+----------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                      ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 3.029 ; 3.142 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 3.024 ; 3.137 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 3.027 ; 3.140 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 3.029 ; 3.142 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 3.029 ; 3.142 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 2.966 ; 3.083 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 2.976 ; 3.093 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 2.966 ; 3.083 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 2.967 ; 3.084 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 2.998 ; 3.111 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 2.998 ; 3.111 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 3.001 ; 3.114 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 3.001 ; 3.114 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 3.014 ; 3.127 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 3.014 ; 3.127 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 3.025 ; 3.138 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 3.025 ; 3.138 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                         ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; SDRAM_DQ[*]   ; CLOCK_27[0] ; -0.970 ; -1.524 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; -0.991 ; -1.543 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; -0.994 ; -1.546 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; -0.996 ; -1.548 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; -0.996 ; -1.548 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; -0.970 ; -1.528 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; -0.980 ; -1.538 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; -0.971 ; -1.529 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; -0.971 ; -1.529 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; -0.972 ; -1.524 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; -0.972 ; -1.524 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; -0.977 ; -1.529 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; -0.977 ; -1.529 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; -0.984 ; -1.536 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; -0.984 ; -1.536 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; -0.995 ; -1.547 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; -0.995 ; -1.547 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                              ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; SDRAM_A[*]    ; CLOCK_27[0] ; 2.750  ; 2.412  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; CLOCK_27[0] ; 2.525  ; 2.238  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; CLOCK_27[0] ; 2.527  ; 2.240  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; CLOCK_27[0] ; 2.527  ; 2.240  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; CLOCK_27[0] ; 2.538  ; 2.251  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; CLOCK_27[0] ; 2.449  ; 2.188  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; CLOCK_27[0] ; 2.750  ; 2.412  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; CLOCK_27[0] ; 2.734  ; 2.396  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; CLOCK_27[0] ; 2.739  ; 2.401  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; CLOCK_27[0] ; 2.739  ; 2.401  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; CLOCK_27[0] ; 2.735  ; 2.397  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; CLOCK_27[0] ; 2.526  ; 2.239  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; CLOCK_27[0] ; 2.742  ; 2.404  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; CLOCK_27[0] ; 2.525  ; 2.238  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; CLOCK_27[0] ; 2.525  ; 2.238  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; CLOCK_27[0] ; 2.516  ; 2.229  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CKE     ; CLOCK_27[0] ; 2.786  ; 2.519  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 2.742  ; 2.404  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 2.723  ; 2.385  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 2.719  ; 2.381  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 2.434  ; 2.173  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 2.434  ; 2.173  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 2.539  ; 2.252  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 2.549  ; 2.262  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 2.538  ; 2.251  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 2.538  ; 2.251  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 2.724  ; 2.386  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 2.724  ; 2.386  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 2.742  ; 2.404  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 2.742  ; 2.404  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 2.430  ; 2.169  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 2.733  ; 2.395  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 2.742  ; 2.404  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 2.439  ; 2.178  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH    ; CLOCK_27[0] ; 2.715  ; 2.377  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML    ; CLOCK_27[0] ; 2.538  ; 2.251  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nCAS    ; CLOCK_27[0] ; 2.525  ; 2.238  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nRAS    ; CLOCK_27[0] ; 2.525  ; 2.238  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nWE     ; CLOCK_27[0] ; 2.538  ; 2.251  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L       ; CLOCK_27[0] ; 5.351  ; 4.759  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R       ; CLOCK_27[0] ; 5.612  ; 4.985  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; LED           ; CLOCK_27[0] ; 5.636  ; 6.466  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]      ; CLOCK_27[0] ; 26.804 ; 26.232 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; CLOCK_27[0] ; 26.060 ; 25.577 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; CLOCK_27[0] ; 26.804 ; 26.232 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; CLOCK_27[0] ; 26.009 ; 25.605 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; CLOCK_27[0] ; 23.902 ; 23.523 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[4]     ; CLOCK_27[0] ; 24.734 ; 24.270 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[5]     ; CLOCK_27[0] ; 24.671 ; 24.187 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; CLOCK_27[0] ; 26.391 ; 26.002 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; CLOCK_27[0] ; 26.377 ; 25.839 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; CLOCK_27[0] ; 26.391 ; 26.002 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; CLOCK_27[0] ; 26.194 ; 25.623 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; CLOCK_27[0] ; 25.511 ; 25.044 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[4]     ; CLOCK_27[0] ; 24.018 ; 23.617 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[5]     ; CLOCK_27[0] ; 19.143 ; 18.492 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS        ; CLOCK_27[0] ; 6.308  ; 5.483  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]      ; CLOCK_27[0] ; 30.761 ; 30.248 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]     ; CLOCK_27[0] ; 29.276 ; 28.789 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]     ; CLOCK_27[0] ; 29.871 ; 29.608 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]     ; CLOCK_27[0] ; 30.761 ; 30.248 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]     ; CLOCK_27[0] ; 28.876 ; 28.425 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[4]     ; CLOCK_27[0] ; 28.321 ; 27.935 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[5]     ; CLOCK_27[0] ; 28.117 ; 27.625 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS        ; CLOCK_27[0] ; 6.036  ; 5.459  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; CLOCK_27[0] ; -0.537 ;        ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; CLOCK_27[0] ;        ; -0.929 ; Fall       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                      ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; SDRAM_A[*]    ; CLOCK_27[0] ; 0.718  ; 0.579  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; CLOCK_27[0] ; 0.758  ; 0.602  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; CLOCK_27[0] ; 0.759  ; 0.603  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; CLOCK_27[0] ; 0.759  ; 0.603  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; CLOCK_27[0] ; 0.770  ; 0.614  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; CLOCK_27[0] ; 0.718  ; 0.579  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; CLOCK_27[0] ; 0.886  ; 0.757  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; CLOCK_27[0] ; 0.870  ; 0.741  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; CLOCK_27[0] ; 0.875  ; 0.746  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; CLOCK_27[0] ; 0.875  ; 0.746  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; CLOCK_27[0] ; 0.874  ; 0.745  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; CLOCK_27[0] ; 0.758  ; 0.602  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; CLOCK_27[0] ; 0.881  ; 0.752  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; CLOCK_27[0] ; 0.748  ; 0.592  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; CLOCK_27[0] ; 0.756  ; 0.600  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; CLOCK_27[0] ; 0.748  ; 0.592  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CKE     ; CLOCK_27[0] ; 0.832  ; 0.743  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 0.703  ; 0.564  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 0.866  ; 0.737  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 0.863  ; 0.734  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 0.711  ; 0.572  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 0.711  ; 0.572  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 0.770  ; 0.614  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 0.780  ; 0.624  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 0.770  ; 0.614  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 0.770  ; 0.614  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 0.865  ; 0.736  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 0.865  ; 0.736  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 0.880  ; 0.751  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 0.880  ; 0.751  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 0.703  ; 0.564  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 0.873  ; 0.744  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 0.882  ; 0.753  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 0.712  ; 0.573  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH    ; CLOCK_27[0] ; 0.859  ; 0.730  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML    ; CLOCK_27[0] ; 0.769  ; 0.613  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nCAS    ; CLOCK_27[0] ; 0.757  ; 0.601  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nRAS    ; CLOCK_27[0] ; 0.756  ; 0.600  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nWE     ; CLOCK_27[0] ; 0.769  ; 0.613  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L       ; CLOCK_27[0] ; 2.470  ; 2.253  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R       ; CLOCK_27[0] ; 2.545  ; 2.372  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; LED           ; CLOCK_27[0] ; 2.703  ; 2.862  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]      ; CLOCK_27[0] ; 1.952  ; 1.808  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; CLOCK_27[0] ; 2.100  ; 2.010  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; CLOCK_27[0] ; 2.148  ; 2.101  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; CLOCK_27[0] ; 1.952  ; 1.808  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; CLOCK_27[0] ; 2.216  ; 2.110  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[4]     ; CLOCK_27[0] ; 2.296  ; 2.281  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[5]     ; CLOCK_27[0] ; 2.259  ; 2.275  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; CLOCK_27[0] ; 2.341  ; 2.257  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; CLOCK_27[0] ; 2.345  ; 2.289  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; CLOCK_27[0] ; 2.358  ; 2.276  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; CLOCK_27[0] ; 2.364  ; 2.386  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; CLOCK_27[0] ; 2.342  ; 2.257  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[4]     ; CLOCK_27[0] ; 2.341  ; 2.370  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[5]     ; CLOCK_27[0] ; 2.370  ; 2.351  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS        ; CLOCK_27[0] ; 2.838  ; 2.652  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]      ; CLOCK_27[0] ; 1.863  ; 1.835  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]     ; CLOCK_27[0] ; 1.863  ; 1.835  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]     ; CLOCK_27[0] ; 2.116  ; 2.096  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]     ; CLOCK_27[0] ; 2.779  ; 2.759  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]     ; CLOCK_27[0] ; 2.943  ; 2.928  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[4]     ; CLOCK_27[0] ; 2.352  ; 2.373  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[5]     ; CLOCK_27[0] ; 2.545  ; 2.569  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS        ; CLOCK_27[0] ; 2.816  ; 2.662  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; CLOCK_27[0] ; -2.001 ;        ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; CLOCK_27[0] ;        ; -2.119 ; Fall       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+


+------------------------------------------------------------+
; Progagation Delay                                          ;
+------------+-------------+-------+-------+--------+--------+
; Input Port ; Output Port ; RR    ; RF    ; FR     ; FF     ;
+------------+-------------+-------+-------+--------+--------+
; CONF_DATA0 ; SPI_DO      ; 9.760 ; 9.520 ; 10.233 ; 10.233 ;
+------------+-------------+-------+-------+--------+--------+


+----------------------------------------------------------+
; Minimum Progagation Delay                                ;
+------------+-------------+-------+-------+-------+-------+
; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
+------------+-------------+-------+-------+-------+-------+
; CONF_DATA0 ; SPI_DO      ; 4.553 ; 4.436 ; 5.176 ; 5.176 ;
+------------+-------------+-------+-------+-------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                   ;
+--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; Pin          ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
+--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; VGA_VS       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_HS       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[0]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[1]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[2]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[3]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[4]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[5]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[0]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[1]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[2]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[3]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[4]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[5]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[0]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[1]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[2]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[3]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[4]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[5]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; AUDIO_L      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; AUDIO_R      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_BA[0]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_BA[1]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_nCS    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_nRAS   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_nCAS   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_nWE    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQMH   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQML   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_CLK    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_CKE    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[0]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[1]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[2]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[3]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[4]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[5]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[6]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[7]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[8]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[9]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[10]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[11]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[12]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; LED          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; UART_TX      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[0]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[1]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[2]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[3]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[4]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[5]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[6]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[7]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[8]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[9]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[10] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[11] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[12] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[13] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[14] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[15] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SPI_DO       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+


+------------------------------------------------------------------+
; Input Transition Times                                           ;
+---------------+--------------+-----------------+-----------------+
; Pin           ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+---------------+--------------+-----------------+-----------------+
; CLOCK_27[1]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; UART_RX       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SPI_SS2       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SPI_SS3       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SPI_SS4       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[0]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[1]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[2]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[3]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[4]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[5]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[6]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[7]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[8]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[9]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[10]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[11]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[12]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[13]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[14]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[15]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SPI_DO        ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SPI_DI        ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; CONF_DATA0    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; CLOCK_27[0]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SPI_SCK       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; ~ALTERA_DCLK~ ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+---------------+--------------+-----------------+-----------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin          ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; VGA_VS       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.08 V              ; -0.00526 V          ; 0.185 V                              ; 0.249 V                              ; 5.8e-09 s                   ; 4.45e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.47e-07 V                  ; 3.08 V             ; -0.00526 V         ; 0.185 V                             ; 0.249 V                             ; 5.8e-09 s                  ; 4.45e-09 s                 ; Yes                       ; Yes                       ;
; VGA_HS       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.08 V              ; -0.00526 V          ; 0.185 V                              ; 0.249 V                              ; 5.8e-09 s                   ; 4.45e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.47e-07 V                  ; 3.08 V             ; -0.00526 V         ; 0.185 V                             ; 0.249 V                             ; 5.8e-09 s                  ; 4.45e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; VGA_G[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.08 V              ; -0.0119 V           ; 0.025 V                              ; 0.13 V                               ; 2.17e-09 s                  ; 1.47e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.08 V             ; -0.0119 V          ; 0.025 V                             ; 0.13 V                              ; 2.17e-09 s                 ; 1.47e-09 s                 ; Yes                       ; Yes                       ;
; VGA_G[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; VGA_G[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; VGA_G[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; VGA_G[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; VGA_G[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; VGA_R[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; VGA_R[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; VGA_R[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; VGA_R[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; VGA_R[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; VGA_R[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; AUDIO_L      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.08 V              ; -0.00526 V          ; 0.185 V                              ; 0.249 V                              ; 5.8e-09 s                   ; 4.45e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.47e-07 V                  ; 3.08 V             ; -0.00526 V         ; 0.185 V                             ; 0.249 V                             ; 5.8e-09 s                  ; 4.45e-09 s                 ; Yes                       ; Yes                       ;
; AUDIO_R      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.08 V              ; -0.00545 V          ; 0.234 V                              ; 0.291 V                              ; 5.77e-09 s                  ; 4.44e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 5.01e-07 V                  ; 3.08 V             ; -0.00545 V         ; 0.234 V                             ; 0.291 V                             ; 5.77e-09 s                 ; 4.44e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_BA[0]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_BA[1]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_nCS    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_nRAS   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_nCAS   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_nWE    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQMH   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.08 V              ; -0.0119 V           ; 0.025 V                              ; 0.13 V                               ; 2.17e-09 s                  ; 1.47e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.08 V             ; -0.0119 V          ; 0.025 V                             ; 0.13 V                              ; 2.17e-09 s                 ; 1.47e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQML   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_CLK    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_CKE    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.09 V              ; -0.0131 V           ; 0.022 V                              ; 0.093 V                              ; 1.48e-09 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.09 V             ; -0.0131 V          ; 0.022 V                             ; 0.093 V                             ; 1.48e-09 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[0]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[1]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[2]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[3]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[4]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.09 V              ; -0.0131 V           ; 0.022 V                              ; 0.093 V                              ; 1.48e-09 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.09 V             ; -0.0131 V          ; 0.022 V                             ; 0.093 V                             ; 1.48e-09 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[5]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.08 V              ; -0.0119 V           ; 0.025 V                              ; 0.13 V                               ; 2.17e-09 s                  ; 1.47e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.08 V             ; -0.0119 V          ; 0.025 V                             ; 0.13 V                              ; 2.17e-09 s                 ; 1.47e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[6]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.08 V              ; -0.0119 V           ; 0.025 V                              ; 0.13 V                               ; 2.17e-09 s                  ; 1.47e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.08 V             ; -0.0119 V          ; 0.025 V                             ; 0.13 V                              ; 2.17e-09 s                 ; 1.47e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[7]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.08 V              ; -0.0119 V           ; 0.025 V                              ; 0.13 V                               ; 2.17e-09 s                  ; 1.47e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.08 V             ; -0.0119 V          ; 0.025 V                             ; 0.13 V                              ; 2.17e-09 s                 ; 1.47e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[8]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.08 V              ; -0.0119 V           ; 0.025 V                              ; 0.13 V                               ; 2.17e-09 s                  ; 1.47e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.08 V             ; -0.0119 V          ; 0.025 V                             ; 0.13 V                              ; 2.17e-09 s                 ; 1.47e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[9]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.08 V              ; -0.0119 V           ; 0.025 V                              ; 0.13 V                               ; 2.17e-09 s                  ; 1.47e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.08 V             ; -0.0119 V          ; 0.025 V                             ; 0.13 V                              ; 2.17e-09 s                 ; 1.47e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[10]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[11]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.08 V              ; -0.0119 V           ; 0.025 V                              ; 0.13 V                               ; 2.17e-09 s                  ; 1.47e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.08 V             ; -0.0119 V          ; 0.025 V                             ; 0.13 V                              ; 2.17e-09 s                 ; 1.47e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[12]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.09 V              ; -0.0131 V           ; 0.022 V                              ; 0.093 V                              ; 1.48e-09 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.09 V             ; -0.0131 V          ; 0.022 V                             ; 0.093 V                             ; 1.48e-09 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; LED          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.08 V              ; -0.00545 V          ; 0.234 V                              ; 0.291 V                              ; 5.77e-09 s                  ; 4.44e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 5.01e-07 V                  ; 3.08 V             ; -0.00545 V         ; 0.234 V                             ; 0.291 V                             ; 5.77e-09 s                 ; 4.44e-09 s                 ; Yes                       ; Yes                       ;
; UART_TX      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.08 V              ; -0.00526 V          ; 0.185 V                              ; 0.249 V                              ; 5.8e-09 s                   ; 4.45e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.47e-07 V                  ; 3.08 V             ; -0.00526 V         ; 0.185 V                             ; 0.249 V                             ; 5.8e-09 s                  ; 4.45e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[0]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.08 V              ; -0.0119 V           ; 0.025 V                              ; 0.13 V                               ; 2.17e-09 s                  ; 1.47e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.08 V             ; -0.0119 V          ; 0.025 V                             ; 0.13 V                              ; 2.17e-09 s                 ; 1.47e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[1]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.08 V              ; -0.0119 V           ; 0.025 V                              ; 0.13 V                               ; 2.17e-09 s                  ; 1.47e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.08 V             ; -0.0119 V          ; 0.025 V                             ; 0.13 V                              ; 2.17e-09 s                 ; 1.47e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[2]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.09 V              ; -0.0131 V           ; 0.022 V                              ; 0.093 V                              ; 1.48e-09 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.09 V             ; -0.0131 V          ; 0.022 V                             ; 0.093 V                             ; 1.48e-09 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[3]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.09 V              ; -0.0131 V           ; 0.022 V                              ; 0.093 V                              ; 1.48e-09 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.09 V             ; -0.0131 V          ; 0.022 V                             ; 0.093 V                             ; 1.48e-09 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[4]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[5]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[6]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[7]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[8]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.08 V              ; -0.0119 V           ; 0.025 V                              ; 0.13 V                               ; 2.17e-09 s                  ; 1.47e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.08 V             ; -0.0119 V          ; 0.025 V                             ; 0.13 V                              ; 2.17e-09 s                 ; 1.47e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[9]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.08 V              ; -0.0119 V           ; 0.025 V                              ; 0.13 V                               ; 2.17e-09 s                  ; 1.47e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.08 V             ; -0.0119 V          ; 0.025 V                             ; 0.13 V                              ; 2.17e-09 s                 ; 1.47e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[10] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.08 V              ; -0.0119 V           ; 0.025 V                              ; 0.13 V                               ; 2.17e-09 s                  ; 1.47e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.08 V             ; -0.0119 V          ; 0.025 V                             ; 0.13 V                              ; 2.17e-09 s                 ; 1.47e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[11] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.08 V              ; -0.0119 V           ; 0.025 V                              ; 0.13 V                               ; 2.17e-09 s                  ; 1.47e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.08 V             ; -0.0119 V          ; 0.025 V                             ; 0.13 V                              ; 2.17e-09 s                 ; 1.47e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[12] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.09 V              ; -0.0131 V           ; 0.022 V                              ; 0.093 V                              ; 1.48e-09 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.09 V             ; -0.0131 V          ; 0.022 V                             ; 0.093 V                             ; 1.48e-09 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[13] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.08 V              ; -0.0119 V           ; 0.025 V                              ; 0.13 V                               ; 2.17e-09 s                  ; 1.47e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.08 V             ; -0.0119 V          ; 0.025 V                             ; 0.13 V                              ; 2.17e-09 s                 ; 1.47e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[14] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.08 V              ; -0.0119 V           ; 0.025 V                              ; 0.13 V                               ; 2.17e-09 s                  ; 1.47e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.08 V             ; -0.0119 V          ; 0.025 V                             ; 0.13 V                              ; 2.17e-09 s                 ; 1.47e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[15] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.09 V              ; -0.0131 V           ; 0.022 V                              ; 0.093 V                              ; 1.48e-09 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.09 V             ; -0.0131 V          ; 0.022 V                             ; 0.093 V                             ; 1.48e-09 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; SPI_DO       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.08 V              ; -0.00545 V          ; 0.234 V                              ; 0.291 V                              ; 5.77e-09 s                  ; 4.44e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 5.01e-07 V                  ; 3.08 V             ; -0.00545 V         ; 0.234 V                             ; 0.291 V                             ; 5.77e-09 s                 ; 4.44e-09 s                 ; Yes                       ; Yes                       ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin          ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; VGA_VS       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.48 V              ; -0.0176 V           ; 0.357 V                              ; 0.323 V                              ; 3.9e-09 s                   ; 3.06e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.48 V             ; -0.0176 V          ; 0.357 V                             ; 0.323 V                             ; 3.9e-09 s                  ; 3.06e-09 s                 ; No                        ; No                        ;
; VGA_HS       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.48 V              ; -0.0176 V           ; 0.357 V                              ; 0.323 V                              ; 3.9e-09 s                   ; 3.06e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.48 V             ; -0.0176 V          ; 0.357 V                             ; 0.323 V                             ; 3.9e-09 s                  ; 3.06e-09 s                 ; No                        ; No                        ;
; VGA_B[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; VGA_B[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; VGA_B[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; VGA_B[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; VGA_B[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; VGA_B[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; VGA_G[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.49 V              ; -0.0449 V           ; 0.354 V                              ; 0.204 V                              ; 1.36e-09 s                  ; 1.05e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.22e-07 V                  ; 3.49 V             ; -0.0449 V          ; 0.354 V                             ; 0.204 V                             ; 1.36e-09 s                 ; 1.05e-09 s                 ; No                        ; No                        ;
; VGA_G[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; VGA_G[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; VGA_G[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; VGA_G[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; VGA_G[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; VGA_R[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; VGA_R[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; VGA_R[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; VGA_R[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; VGA_R[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; VGA_R[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; AUDIO_L      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.48 V              ; -0.0176 V           ; 0.357 V                              ; 0.323 V                              ; 3.9e-09 s                   ; 3.06e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.48 V             ; -0.0176 V          ; 0.357 V                             ; 0.323 V                             ; 3.9e-09 s                  ; 3.06e-09 s                 ; No                        ; No                        ;
; AUDIO_R      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.48 V              ; -0.0164 V           ; 0.353 V                              ; 0.315 V                              ; 3.88e-09 s                  ; 3.06e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.48 V             ; -0.0164 V          ; 0.353 V                             ; 0.315 V                             ; 3.88e-09 s                 ; 3.06e-09 s                 ; No                        ; No                        ;
; SDRAM_BA[0]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; SDRAM_BA[1]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; SDRAM_nCS    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; SDRAM_nRAS   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; SDRAM_nCAS   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; SDRAM_nWE    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQMH   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.49 V              ; -0.0449 V           ; 0.354 V                              ; 0.204 V                              ; 1.36e-09 s                  ; 1.05e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.22e-07 V                  ; 3.49 V             ; -0.0449 V          ; 0.354 V                             ; 0.204 V                             ; 1.36e-09 s                 ; 1.05e-09 s                 ; No                        ; No                        ;
; SDRAM_DQML   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; SDRAM_CLK    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; SDRAM_CKE    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.5 V               ; -0.0534 V           ; 0.346 V                              ; 0.247 V                              ; 9.06e-10 s                  ; 6.55e-10 s                  ; Yes                        ; Yes                        ; 3.46 V                      ; 2.22e-07 V                  ; 3.5 V              ; -0.0534 V          ; 0.346 V                             ; 0.247 V                             ; 9.06e-10 s                 ; 6.55e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[0]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[1]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[2]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[3]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[4]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.5 V               ; -0.0534 V           ; 0.346 V                              ; 0.247 V                              ; 9.06e-10 s                  ; 6.55e-10 s                  ; Yes                        ; Yes                        ; 3.46 V                      ; 2.22e-07 V                  ; 3.5 V              ; -0.0534 V          ; 0.346 V                             ; 0.247 V                             ; 9.06e-10 s                 ; 6.55e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[5]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.49 V              ; -0.0449 V           ; 0.354 V                              ; 0.204 V                              ; 1.36e-09 s                  ; 1.05e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.22e-07 V                  ; 3.49 V             ; -0.0449 V          ; 0.354 V                             ; 0.204 V                             ; 1.36e-09 s                 ; 1.05e-09 s                 ; No                        ; No                        ;
; SDRAM_A[6]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.49 V              ; -0.0449 V           ; 0.354 V                              ; 0.204 V                              ; 1.36e-09 s                  ; 1.05e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.22e-07 V                  ; 3.49 V             ; -0.0449 V          ; 0.354 V                             ; 0.204 V                             ; 1.36e-09 s                 ; 1.05e-09 s                 ; No                        ; No                        ;
; SDRAM_A[7]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.49 V              ; -0.0449 V           ; 0.354 V                              ; 0.204 V                              ; 1.36e-09 s                  ; 1.05e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.22e-07 V                  ; 3.49 V             ; -0.0449 V          ; 0.354 V                             ; 0.204 V                             ; 1.36e-09 s                 ; 1.05e-09 s                 ; No                        ; No                        ;
; SDRAM_A[8]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.49 V              ; -0.0449 V           ; 0.354 V                              ; 0.204 V                              ; 1.36e-09 s                  ; 1.05e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.22e-07 V                  ; 3.49 V             ; -0.0449 V          ; 0.354 V                             ; 0.204 V                             ; 1.36e-09 s                 ; 1.05e-09 s                 ; No                        ; No                        ;
; SDRAM_A[9]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.49 V              ; -0.0449 V           ; 0.354 V                              ; 0.204 V                              ; 1.36e-09 s                  ; 1.05e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.22e-07 V                  ; 3.49 V             ; -0.0449 V          ; 0.354 V                             ; 0.204 V                             ; 1.36e-09 s                 ; 1.05e-09 s                 ; No                        ; No                        ;
; SDRAM_A[10]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[11]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.49 V              ; -0.0449 V           ; 0.354 V                              ; 0.204 V                              ; 1.36e-09 s                  ; 1.05e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.22e-07 V                  ; 3.49 V             ; -0.0449 V          ; 0.354 V                             ; 0.204 V                             ; 1.36e-09 s                 ; 1.05e-09 s                 ; No                        ; No                        ;
; SDRAM_A[12]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.5 V               ; -0.0534 V           ; 0.346 V                              ; 0.247 V                              ; 9.06e-10 s                  ; 6.55e-10 s                  ; Yes                        ; Yes                        ; 3.46 V                      ; 2.22e-07 V                  ; 3.5 V              ; -0.0534 V          ; 0.346 V                             ; 0.247 V                             ; 9.06e-10 s                 ; 6.55e-10 s                 ; Yes                       ; Yes                       ;
; LED          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.48 V              ; -0.0164 V           ; 0.353 V                              ; 0.315 V                              ; 3.88e-09 s                  ; 3.06e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.48 V             ; -0.0164 V          ; 0.353 V                             ; 0.315 V                             ; 3.88e-09 s                 ; 3.06e-09 s                 ; No                        ; No                        ;
; UART_TX      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.48 V              ; -0.0176 V           ; 0.357 V                              ; 0.323 V                              ; 3.9e-09 s                   ; 3.06e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.48 V             ; -0.0176 V          ; 0.357 V                             ; 0.323 V                             ; 3.9e-09 s                  ; 3.06e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[0]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.49 V              ; -0.0449 V           ; 0.354 V                              ; 0.204 V                              ; 1.36e-09 s                  ; 1.05e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.22e-07 V                  ; 3.49 V             ; -0.0449 V          ; 0.354 V                             ; 0.204 V                             ; 1.36e-09 s                 ; 1.05e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[1]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.49 V              ; -0.0449 V           ; 0.354 V                              ; 0.204 V                              ; 1.36e-09 s                  ; 1.05e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.22e-07 V                  ; 3.49 V             ; -0.0449 V          ; 0.354 V                             ; 0.204 V                             ; 1.36e-09 s                 ; 1.05e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[2]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.5 V               ; -0.0534 V           ; 0.346 V                              ; 0.247 V                              ; 9.06e-10 s                  ; 6.55e-10 s                  ; Yes                        ; Yes                        ; 3.46 V                      ; 2.22e-07 V                  ; 3.5 V              ; -0.0534 V          ; 0.346 V                             ; 0.247 V                             ; 9.06e-10 s                 ; 6.55e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[3]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.5 V               ; -0.0534 V           ; 0.346 V                              ; 0.247 V                              ; 9.06e-10 s                  ; 6.55e-10 s                  ; Yes                        ; Yes                        ; 3.46 V                      ; 2.22e-07 V                  ; 3.5 V              ; -0.0534 V          ; 0.346 V                             ; 0.247 V                             ; 9.06e-10 s                 ; 6.55e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[4]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[5]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[6]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[7]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[8]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.49 V              ; -0.0449 V           ; 0.354 V                              ; 0.204 V                              ; 1.36e-09 s                  ; 1.05e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.22e-07 V                  ; 3.49 V             ; -0.0449 V          ; 0.354 V                             ; 0.204 V                             ; 1.36e-09 s                 ; 1.05e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[9]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.49 V              ; -0.0449 V           ; 0.354 V                              ; 0.204 V                              ; 1.36e-09 s                  ; 1.05e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.22e-07 V                  ; 3.49 V             ; -0.0449 V          ; 0.354 V                             ; 0.204 V                             ; 1.36e-09 s                 ; 1.05e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[10] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.49 V              ; -0.0449 V           ; 0.354 V                              ; 0.204 V                              ; 1.36e-09 s                  ; 1.05e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.22e-07 V                  ; 3.49 V             ; -0.0449 V          ; 0.354 V                             ; 0.204 V                             ; 1.36e-09 s                 ; 1.05e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[11] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.49 V              ; -0.0449 V           ; 0.354 V                              ; 0.204 V                              ; 1.36e-09 s                  ; 1.05e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.22e-07 V                  ; 3.49 V             ; -0.0449 V          ; 0.354 V                             ; 0.204 V                             ; 1.36e-09 s                 ; 1.05e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[12] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.5 V               ; -0.0534 V           ; 0.346 V                              ; 0.247 V                              ; 9.06e-10 s                  ; 6.55e-10 s                  ; Yes                        ; Yes                        ; 3.46 V                      ; 2.22e-07 V                  ; 3.5 V              ; -0.0534 V          ; 0.346 V                             ; 0.247 V                             ; 9.06e-10 s                 ; 6.55e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[13] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.49 V              ; -0.0449 V           ; 0.354 V                              ; 0.204 V                              ; 1.36e-09 s                  ; 1.05e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.22e-07 V                  ; 3.49 V             ; -0.0449 V          ; 0.354 V                             ; 0.204 V                             ; 1.36e-09 s                 ; 1.05e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[14] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.49 V              ; -0.0449 V           ; 0.354 V                              ; 0.204 V                              ; 1.36e-09 s                  ; 1.05e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.22e-07 V                  ; 3.49 V             ; -0.0449 V          ; 0.354 V                             ; 0.204 V                             ; 1.36e-09 s                 ; 1.05e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[15] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.5 V               ; -0.0534 V           ; 0.346 V                              ; 0.247 V                              ; 9.06e-10 s                  ; 6.55e-10 s                  ; Yes                        ; Yes                        ; 3.46 V                      ; 2.22e-07 V                  ; 3.5 V              ; -0.0534 V          ; 0.346 V                             ; 0.247 V                             ; 9.06e-10 s                 ; 6.55e-10 s                 ; Yes                       ; Yes                       ;
; SPI_DO       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.48 V              ; -0.0164 V           ; 0.353 V                              ; 0.315 V                              ; 3.88e-09 s                  ; 3.06e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.48 V             ; -0.0164 V          ; 0.353 V                             ; 0.315 V                             ; 3.88e-09 s                 ; 3.06e-09 s                 ; No                        ; No                        ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Transfers                                                                                                                                                                           ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                            ; To Clock                                                              ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+----------+----------+----------+----------+
; CLOCK_27[0]                                                           ; CLOCK_27[0]                                                           ; 85       ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 2473     ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 120      ; 0        ; 1        ; 0        ;
; CLOCK_27[0]                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 1        ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 39       ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 24933819 ; 0        ; 1        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 3        ; 1        ; 0        ; 0        ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 2        ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 0        ; 0        ; 1        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0        ; 0        ; 1        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 219      ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 1        ; 0        ; 0        ; 0        ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 2115     ; 7        ; 42       ; 1        ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Transfers                                                                                                                                                                            ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                            ; To Clock                                                              ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+----------+----------+----------+----------+
; CLOCK_27[0]                                                           ; CLOCK_27[0]                                                           ; 85       ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 2473     ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 120      ; 0        ; 1        ; 0        ;
; CLOCK_27[0]                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 1        ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 39       ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 24933819 ; 0        ; 1        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 3        ; 1        ; 0        ; 0        ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 2        ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 0        ; 0        ; 1        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0        ; 0        ; 1        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 219      ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 1        ; 0        ; 0        ; 0        ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 2115     ; 7        ; 42       ; 1        ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Recovery Transfers                                                                                                                                                                        ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                            ; To Clock                                                              ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+----------+----------+----------+----------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0]                                                           ; 18       ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 141      ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8052     ; 0        ; 0        ; 0        ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Removal Transfers                                                                                                                                                                         ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                            ; To Clock                                                              ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+----------+----------+----------+----------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0]                                                           ; 18       ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 141      ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8052     ; 0        ; 0        ; 0        ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design


---------------
; Report RSKM ;
---------------
No dedicated SERDES Receiver circuitry present in device or used in design


+------------------------------------------------+
; Unconstrained Paths                            ;
+---------------------------------+-------+------+
; Property                        ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks                  ; 0     ; 0    ;
; Unconstrained Clocks            ; 6     ; 6    ;
; Unconstrained Input Ports       ; 18    ; 18   ;
; Unconstrained Input Port Paths  ; 194   ; 194  ;
; Unconstrained Output Ports      ; 61    ; 61   ;
; Unconstrained Output Port Paths ; 152   ; 152  ;
+---------------------------------+-------+------+


+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II 32-bit TimeQuest Timing Analyzer
    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
    Info: Processing started: Mon Jun  1 15:43:26 2020
Info: Command: quartus_sta atari800core -c atari800core
Info: qsta_default_script.tcl version: #1
Info (11104): Parallel Compilation has detected 12 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 6 of the 6 physical processors detected instead.
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (332104): Reading SDC File: 'atari800core.sdc'
Info (332110): Deriving PLL clocks
    Info (332110): create_generated_clock -source {pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 200 -multiply_by 227 -duty_cycle 50.00 -name {pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]} {pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]}
    Info (332110): create_generated_clock -source {reconfig_pll|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 9 -multiply_by 4 -duty_cycle 50.00 -name {reconfig_pll|altpll_component|auto_generated|pll1|clk[0]} {reconfig_pll|altpll_component|auto_generated|pll1|clk[0]}
    Info (332110): create_generated_clock -source {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 27 -multiply_by 100 -duty_cycle 50.00 -name {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]} {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]}
    Info (332110): create_generated_clock -source {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 27 -multiply_by 50 -duty_cycle 50.00 -name {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]} {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]}
    Info (332110): create_generated_clock -source {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 27 -multiply_by 100 -phase -100.00 -duty_cycle 50.00 -name {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]} {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]}
    Info (332110): create_generated_clock -source {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 2700 -phase -0.01 -duty_cycle 50.00 -name {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]} {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]}
Warning (332174): Ignored filter at atari800core.sdc(3): clock|altpll_component|auto_generated|pll1|clk[2] could not be matched with a pin
Warning (332049): Ignored create_generated_clock at atari800core.sdc(3): Argument -source is an empty collection
    Info (332050): create_generated_clock -name sdclk_pin -source [get_pins {clock|altpll_component|auto_generated|pll1|clk[2]}] [get_ports {SDRAM_CLK}]
Info (332151): Clock uncertainty is not calculated until you update the timing netlist.
Warning (332174): Ignored filter at atari800core.sdc(5): sdclk_pin could not be matched with a clock
Warning (332049): Ignored set_input_delay at atari800core.sdc(5): Argument -clock is not an object ID
    Info (332050): set_input_delay -clock sdclk_pin -max 6.4 [get_ports SDRAM_DQ*]
Warning (332049): Ignored set_input_delay at atari800core.sdc(6): Argument -clock is not an object ID
    Info (332050): set_input_delay -clock sdclk_pin -min 3.2 [get_ports SDRAM_DQ*]
Warning (332049): Ignored set_output_delay at atari800core.sdc(7): Argument -clock is not an object ID
    Info (332050): set_output_delay -clock sdclk_pin -max 1.5 [get_ports SDRAM_*]
Warning (332049): Ignored set_output_delay at atari800core.sdc(8): Argument -clock is not an object ID
    Info (332050): set_output_delay -clock sdclk_pin -min -0.8 [get_ports SDRAM_*]
Warning (332174): Ignored filter at atari800core.sdc(9): clock|altpll_component|auto_generated|pll1|clk[0] could not be matched with a clock
Warning (332049): Ignored set_multicycle_path at atari800core.sdc(9): Argument <from> is an empty collection
    Info (332050): set_multicycle_path -from [get_clocks {sdclk_pin}] -to [get_clocks {clock|altpll_component|auto_generated|pll1|clk[0]}] -setup -end 2
Warning (332049): Ignored set_multicycle_path at atari800core.sdc(9): Argument <to> is an empty collection
Warning (332125): Found combinational loop of 4 nodes
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqb_next[0]~6|combout"
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqb_next[0]~4|datab"
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqb_next[0]~4|combout"
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqb_next[0]~6|dataa"
Warning (332125): Found combinational loop of 4 nodes
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqa_next[0]~6|combout"
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqa_next[0]~4|datad"
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqa_next[0]~4|combout"
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqa_next[0]~6|datab"
Warning (332125): Found combinational loop of 4 nodes
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqb_next[1]~8|combout"
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqb_next[1]~7|dataa"
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqb_next[1]~7|combout"
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqb_next[1]~8|dataa"
Warning (332125): Found combinational loop of 4 nodes
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqa_next[1]~9|combout"
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqa_next[1]~7|datad"
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqa_next[1]~7|combout"
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqa_next[1]~9|datab"
Warning (332125): Found combinational loop of 2 nodes
    Warning (332126): Node "my_user_io|spi_sck~0|combout"
    Warning (332126): Node "my_user_io|spi_sck~0|datab"
Warning (332060): Node: SPI_SCK was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|sclk was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: user_io:my_user_io|sd_ack was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: sd_card:my_sd_card|read_state.RD_STATE_IDLE was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: user_io:my_user_io|sd_dout_strobe was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: sd_card:my_sd_card|write_state.WR_STATE_BUSY was determined to be a clock but was found without an associated clock assignment.
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Analyzing Slow 1200mV 85C Model
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -4.849
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -4.849       -10.688 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    -1.547        -1.547 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     0.123         0.000 reconfig_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.890         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    11.442         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] 
    Info (332119):    33.660         0.000 CLOCK_27[0] 
Info (332146): Worst-case hold slack is -1.838
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -1.838        -1.838 reconfig_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.393         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.453         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.454         0.000 CLOCK_27[0] 
    Info (332119):     0.454         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] 
    Info (332119):     9.627         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
Info (332146): Worst-case recovery slack is -1.239
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -1.239       -11.151 CLOCK_27[0] 
    Info (332119):     2.099         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    10.098         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
Info (332146): Worst-case removal slack is -0.423
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -0.423        -3.806 CLOCK_27[0] 
    Info (332119):     1.688         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     4.888         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case minimum pulse width slack is 4.093
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     4.093         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     4.224         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     8.373         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    16.275         0.000 pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    18.274         0.000 CLOCK_27[0] 
    Info (332119):    40.596         0.000 reconfig_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119): 44052.506         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] 
Info: Analyzing Slow 1200mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Warning (332060): Node: SPI_SCK was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|sclk was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: user_io:my_user_io|sd_ack was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: sd_card:my_sd_card|read_state.RD_STATE_IDLE was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: user_io:my_user_io|sd_dout_strobe was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: sd_card:my_sd_card|write_state.WR_STATE_BUSY was determined to be a clock but was found without an associated clock assignment.
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -4.207
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -4.207        -9.258 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    -1.241        -1.241 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     0.069         0.000 reconfig_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     1.197         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    11.785         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] 
    Info (332119):    33.949         0.000 CLOCK_27[0] 
Info (332146): Worst-case hold slack is -1.629
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -1.629        -1.629 reconfig_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.383         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.402         0.000 CLOCK_27[0] 
    Info (332119):     0.402         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.403         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] 
    Info (332119):     9.341         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
Info (332146): Worst-case recovery slack is -1.292
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -1.292       -11.620 CLOCK_27[0] 
    Info (332119):     2.515         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    10.529         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
Info (332146): Worst-case removal slack is -0.277
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -0.277        -2.492 CLOCK_27[0] 
    Info (332119):     1.542         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     4.359         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case minimum pulse width slack is 4.097
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     4.097         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     4.243         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     8.406         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    16.279         0.000 pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    18.273         0.000 CLOCK_27[0] 
    Info (332119):    40.596         0.000 reconfig_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119): 44052.511         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] 
Info: Analyzing Fast 1200mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Warning (332060): Node: SPI_SCK was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|sclk was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: user_io:my_user_io|sd_ack was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: sd_card:my_sd_card|read_state.RD_STATE_IDLE was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: user_io:my_user_io|sd_dout_strobe was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: sd_card:my_sd_card|write_state.WR_STATE_BUSY was determined to be a clock but was found without an associated clock assignment.
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -2.320
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -2.320        -4.912 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.213         0.000 reconfig_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.392         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     2.829         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    13.668         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] 
    Info (332119):    35.609         0.000 CLOCK_27[0] 
Info (332146): Worst-case hold slack is -1.078
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -1.078        -1.078 reconfig_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.136         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.186         0.000 CLOCK_27[0] 
    Info (332119):     0.186         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.186         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] 
    Info (332119):     8.109         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
Info (332146): Worst-case recovery slack is -0.426
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -0.426        -3.834 CLOCK_27[0] 
    Info (332119):     5.725         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    14.146         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
Info (332146): Worst-case removal slack is -0.363
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -0.363        -3.266 CLOCK_27[0] 
    Info (332119):     0.727         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     2.227         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case minimum pulse width slack is 4.186
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     4.186         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     4.331         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     8.560         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    16.300         0.000 pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    17.784         0.000 CLOCK_27[0] 
    Info (332119):    40.631         0.000 reconfig_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119): 44052.600         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] 
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 54 warnings
    Info: Peak virtual memory: 582 megabytes
    Info: Processing ended: Mon Jun  1 15:43:36 2020
    Info: Elapsed time: 00:00:10
    Info: Total CPU time (on all processors): 00:00:13


