TimeQuest Timing Analyzer report for atari800core
Sun Mar 24 14:03:53 2024
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. Parallel Compilation
  4. SDC File List
  5. Clocks
  6. Slow 1200mV 85C Model Fmax Summary
  7. Timing Closure Recommendations
  8. Slow 1200mV 85C Model Setup Summary
  9. Slow 1200mV 85C Model Hold Summary
 10. Slow 1200mV 85C Model Recovery Summary
 11. Slow 1200mV 85C Model Removal Summary
 12. Slow 1200mV 85C Model Minimum Pulse Width Summary
 13. Slow 1200mV 85C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 14. Slow 1200mV 85C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 15. Slow 1200mV 85C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 16. Slow 1200mV 85C Model Setup: 'SPI_SCK'
 17. Slow 1200mV 85C Model Setup: 'clk_27'
 18. Slow 1200mV 85C Model Setup: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'
 19. Slow 1200mV 85C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 20. Slow 1200mV 85C Model Hold: 'SPI_SCK'
 21. Slow 1200mV 85C Model Hold: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'
 22. Slow 1200mV 85C Model Hold: 'clk_27'
 23. Slow 1200mV 85C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 24. Slow 1200mV 85C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 25. Slow 1200mV 85C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 26. Slow 1200mV 85C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 27. Slow 1200mV 85C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 28. Slow 1200mV 85C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 29. Slow 1200mV 85C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 30. Slow 1200mV 85C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 31. Slow 1200mV 85C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 32. Slow 1200mV 85C Model Minimum Pulse Width: 'pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'
 33. Slow 1200mV 85C Model Minimum Pulse Width: 'clk_27'
 34. Slow 1200mV 85C Model Minimum Pulse Width: 'SPI_SCK'
 35. Slow 1200mV 85C Model Minimum Pulse Width: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'
 36. Setup Times
 37. Hold Times
 38. Clock to Output Times
 39. Minimum Clock to Output Times
 40. Propagation Delay
 41. Minimum Propagation Delay
 42. Output Enable Times
 43. Minimum Output Enable Times
 44. Output Disable Times
 45. Minimum Output Disable Times
 46. Slow 1200mV 85C Model Metastability Report
 47. Slow 1200mV 0C Model Fmax Summary
 48. Slow 1200mV 0C Model Setup Summary
 49. Slow 1200mV 0C Model Hold Summary
 50. Slow 1200mV 0C Model Recovery Summary
 51. Slow 1200mV 0C Model Removal Summary
 52. Slow 1200mV 0C Model Minimum Pulse Width Summary
 53. Slow 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 54. Slow 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 55. Slow 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 56. Slow 1200mV 0C Model Setup: 'SPI_SCK'
 57. Slow 1200mV 0C Model Setup: 'clk_27'
 58. Slow 1200mV 0C Model Setup: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'
 59. Slow 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 60. Slow 1200mV 0C Model Hold: 'SPI_SCK'
 61. Slow 1200mV 0C Model Hold: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'
 62. Slow 1200mV 0C Model Hold: 'clk_27'
 63. Slow 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 64. Slow 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 65. Slow 1200mV 0C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 66. Slow 1200mV 0C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 67. Slow 1200mV 0C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 68. Slow 1200mV 0C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 69. Slow 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 70. Slow 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 71. Slow 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 72. Slow 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'
 73. Slow 1200mV 0C Model Minimum Pulse Width: 'clk_27'
 74. Slow 1200mV 0C Model Minimum Pulse Width: 'SPI_SCK'
 75. Slow 1200mV 0C Model Minimum Pulse Width: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'
 76. Setup Times
 77. Hold Times
 78. Clock to Output Times
 79. Minimum Clock to Output Times
 80. Propagation Delay
 81. Minimum Propagation Delay
 82. Output Enable Times
 83. Minimum Output Enable Times
 84. Output Disable Times
 85. Minimum Output Disable Times
 86. Slow 1200mV 0C Model Metastability Report
 87. Fast 1200mV 0C Model Setup Summary
 88. Fast 1200mV 0C Model Hold Summary
 89. Fast 1200mV 0C Model Recovery Summary
 90. Fast 1200mV 0C Model Removal Summary
 91. Fast 1200mV 0C Model Minimum Pulse Width Summary
 92. Fast 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 93. Fast 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 94. Fast 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 95. Fast 1200mV 0C Model Setup: 'SPI_SCK'
 96. Fast 1200mV 0C Model Setup: 'clk_27'
 97. Fast 1200mV 0C Model Setup: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'
 98. Fast 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 99. Fast 1200mV 0C Model Hold: 'SPI_SCK'
100. Fast 1200mV 0C Model Hold: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'
101. Fast 1200mV 0C Model Hold: 'clk_27'
102. Fast 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
103. Fast 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
104. Fast 1200mV 0C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
105. Fast 1200mV 0C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
106. Fast 1200mV 0C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
107. Fast 1200mV 0C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
108. Fast 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
109. Fast 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
110. Fast 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
111. Fast 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'
112. Fast 1200mV 0C Model Minimum Pulse Width: 'clk_27'
113. Fast 1200mV 0C Model Minimum Pulse Width: 'SPI_SCK'
114. Fast 1200mV 0C Model Minimum Pulse Width: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'
115. Setup Times
116. Hold Times
117. Clock to Output Times
118. Minimum Clock to Output Times
119. Propagation Delay
120. Minimum Propagation Delay
121. Output Enable Times
122. Minimum Output Enable Times
123. Output Disable Times
124. Minimum Output Disable Times
125. Fast 1200mV 0C Model Metastability Report
126. Multicorner Timing Analysis Summary
127. Setup Times
128. Hold Times
129. Clock to Output Times
130. Minimum Clock to Output Times
131. Progagation Delay
132. Minimum Progagation Delay
133. Board Trace Model Assignments
134. Input Transition Times
135. Slow Corner Signal Integrity Metrics
136. Fast Corner Signal Integrity Metrics
137. Setup Transfers
138. Hold Transfers
139. Recovery Transfers
140. Removal Transfers
141. Report TCCS
142. Report RSKM
143. Unconstrained Paths
144. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
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to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                                      ;
+--------------------+-------------------------------------------------------------------+
; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition ;
; Revision Name      ; atari800core                                                      ;
; Device Family      ; Cyclone III                                                       ;
; Device Name        ; EP3C25E144C8                                                      ;
; Timing Models      ; Final                                                             ;
; Delay Model        ; Combined                                                          ;
; Rise/Fall Delays   ; Enabled                                                           ;
+--------------------+-------------------------------------------------------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 8           ;
; Maximum allowed            ; 4           ;
;                            ;             ;
; Average used               ; 2.67        ;
; Maximum used               ; 4           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processor 2            ;  66.7%      ;
;     Processors 3-4         ;  50.0%      ;
;     Processors 5-8         ;   0.0%      ;
+----------------------------+-------------+


+------------------------------------------------------+
; SDC File List                                        ;
+------------------+--------+--------------------------+
; SDC File Path    ; Status ; Read at                  ;
+------------------+--------+--------------------------+
; atari800core.sdc ; OK     ; Sun Mar 24 14:03:47 2024 ;
+------------------+--------+--------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                                                                                                                                                                                                                                                                                              ;
+-----------------------------------------------------------------------+-----------+--------+------------+--------+--------+------------+-----------+-------------+--------+--------+-----------+------------+----------+----------------------------------------------------------------------+-------------------------------------------------------------------------+---------------------------------------------------------------------------+
; Clock Name                                                            ; Type      ; Period ; Frequency  ; Rise   ; Fall   ; Duty Cycle ; Divide by ; Multiply by ; Phase  ; Offset ; Edge List ; Edge Shift ; Inverted ; Master                                                               ; Source                                                                  ; Targets                                                                   ;
+-----------------------------------------------------------------------+-----------+--------+------------+--------+--------+------------+-----------+-------------+--------+--------+-----------+------------+----------+----------------------------------------------------------------------+-------------------------------------------------------------------------+---------------------------------------------------------------------------+
; clk_27                                                                ; Base      ; 37.037 ; 27.0 MHz   ; 0.000  ; 18.518 ;            ;           ;             ;        ;        ;           ;            ;          ;                                                                      ;                                                                         ; { CLOCK_27[0] }                                                           ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Generated ; 8.810  ; 113.51 MHz ; 0.000  ; 4.405  ; 50.00      ; 27        ; 100         ;        ;        ;           ;            ; false    ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] } ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Generated ; 17.621 ; 56.75 MHz  ; 0.000  ; 8.810  ; 50.00      ; 27        ; 50          ;        ;        ;           ;            ; false    ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] } ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Generated ; 8.810  ; 113.51 MHz ; -2.447 ; 1.958  ; 50.00      ; 27        ; 100         ; -100.0 ;        ;           ;            ; false    ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] } ;
; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; Generated ; 32.631 ; 30.65 MHz  ; 0.000  ; 16.315 ; 50.00      ; 200       ; 227         ;        ;        ;           ;            ; false    ; clk_27                                                               ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]  ; { pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] }  ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; Generated ; 83.333 ; 12.0 MHz   ; 0.000  ; 41.666 ; 50.00      ; 9         ; 4           ;        ;        ;           ;            ; false    ; clk_27                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|inclk[0]              ; { reconfig_pll|altpll_component|auto_generated|pll1|clk[0] }              ;
; SPI_SCK                                                               ; Base      ; 41.666 ; 24.0 MHz   ; 20.800 ; 41.666 ;            ;           ;             ;        ;        ;           ;            ;          ;                                                                      ;                                                                         ; { SPI_SCK }                                                               ;
+-----------------------------------------------------------------------+-----------+--------+------------+--------+--------+------------+-----------+-------------+--------+--------+-----------+------------+----------+----------------------------------------------------------------------+-------------------------------------------------------------------------+---------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Fmax Summary                                                                                                                                   ;
+------------+-----------------+-----------------------------------------------------------------------+---------------------------------------------------------------+
; Fmax       ; Restricted Fmax ; Clock Name                                                            ; Note                                                          ;
+------------+-----------------+-----------------------------------------------------------------------+---------------------------------------------------------------+
; 58.73 MHz  ; 58.73 MHz       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;                                                               ;
; 84.7 MHz   ; 84.7 MHz        ; SPI_SCK                                                               ;                                                               ;
; 103.9 MHz  ; 100.0 MHz       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; limit due to minimum period restriction (tmin)                ;
; 138.81 MHz ; 138.81 MHz      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;                                                               ;
; 342.35 MHz ; 250.0 MHz       ; clk_27                                                                ; limit due to minimum period restriction (max I/O toggle rate) ;
+------------+-----------------+-----------------------------------------------------------------------+---------------------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


----------------------------------
; Timing Closure Recommendations ;
----------------------------------
HTML report is unavailable in plain text report export.


+------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup Summary                                                            ;
+-----------------------------------------------------------------------+--------+---------------+
; Clock                                                                 ; Slack  ; End Point TNS ;
+-----------------------------------------------------------------------+--------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -1.593 ; -1.593        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.593  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.945  ; 0.000         ;
; SPI_SCK                                                               ; 14.954 ; 0.000         ;
; clk_27                                                                ; 34.116 ; 0.000         ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 36.854 ; 0.000         ;
+-----------------------------------------------------------------------+--------+---------------+


+-----------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold Summary                                                            ;
+-----------------------------------------------------------------------+-------+---------------+
; Clock                                                                 ; Slack ; End Point TNS ;
+-----------------------------------------------------------------------+-------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.406 ; 0.000         ;
; SPI_SCK                                                               ; 0.419 ; 0.000         ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 0.453 ; 0.000         ;
; clk_27                                                                ; 0.455 ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.455 ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 2.208 ; 0.000         ;
+-----------------------------------------------------------------------+-------+---------------+


+-----------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery Summary                                                        ;
+-----------------------------------------------------------------------+-------+---------------+
; Clock                                                                 ; Slack ; End Point TNS ;
+-----------------------------------------------------------------------+-------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 2.684 ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 9.374 ; 0.000         ;
+-----------------------------------------------------------------------+-------+---------------+


+-----------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal Summary                                                         ;
+-----------------------------------------------------------------------+-------+---------------+
; Clock                                                                 ; Slack ; End Point TNS ;
+-----------------------------------------------------------------------+-------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 1.592 ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 4.459 ; 0.000         ;
+-----------------------------------------------------------------------+-------+---------------+


+------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width Summary                                              ;
+-----------------------------------------------------------------------+--------+---------------+
; Clock                                                                 ; Slack  ; End Point TNS ;
+-----------------------------------------------------------------------+--------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 4.093  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 4.194  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.379  ; 0.000         ;
; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; 16.275 ; 0.000         ;
; clk_27                                                                ; 18.275 ; 0.000         ;
; SPI_SCK                                                               ; 20.416 ; 0.000         ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 40.596 ; 0.000         ;
+-----------------------------------------------------------------------+--------+---------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                  ;
+--------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; -1.593 ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 1.958        ; -2.033     ; 1.286      ;
; 2.571  ; sdram_statemachine:sdram_adaptor|addr_reg[5]                                ; SDRAM_A[5]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.930      ; 4.112      ;
; 2.579  ; sdram_statemachine:sdram_adaptor|addr_reg[11]                               ; SDRAM_A[11]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.938      ; 4.112      ;
; 2.581  ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                             ; SDRAM_DQ[14]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.940      ; 4.112      ;
; 2.583  ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                ; SDRAM_A[7]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.932      ; 4.102      ;
; 2.583  ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                ; SDRAM_A[8]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.932      ; 4.102      ;
; 2.585  ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                ; SDRAM_A[9]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.934      ; 4.102      ;
; 2.588  ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]                             ; SDRAM_DQ[11]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.937      ; 4.102      ;
; 2.588  ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                ; SDRAM_A[6]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.937      ; 4.102      ;
; 2.588  ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                             ; SDRAM_DQ[10]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.937      ; 4.102      ;
; 2.590  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_5                 ; SDRAM_DQ[5]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.898      ; 4.061      ;
; 2.590  ; sdram_statemachine:sdram_adaptor|dq_out_reg[13]                             ; SDRAM_DQ[13]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.939      ; 4.102      ;
; 2.600  ; sdram_statemachine:sdram_adaptor|dq_out_reg[0]                              ; SDRAM_DQ[0]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.949      ; 4.102      ;
; 2.600  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4                 ; SDRAM_DQ[4]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.898      ; 4.051      ;
; 2.601  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_6                 ; SDRAM_DQ[6]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.899      ; 4.051      ;
; 2.602  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_7                 ; SDRAM_DQ[7]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.900      ; 4.051      ;
; 2.603  ; sdram_statemachine:sdram_adaptor|dq_out_reg[1]                              ; SDRAM_DQ[1]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.952      ; 4.102      ;
; 2.606  ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]                              ; SDRAM_DQ[8]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.945      ; 4.092      ;
; 2.606  ; sdram_statemachine:sdram_adaptor|dq_out_reg[9]                              ; SDRAM_DQ[9]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.945      ; 4.092      ;
; 2.607  ; sdram_statemachine:sdram_adaptor|udqm_reg                                   ; SDRAM_DQMH                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.946      ; 4.092      ;
; 2.611  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3                 ; SDRAM_DQ[3]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.947      ; 4.089      ;
; 2.611  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2                 ; SDRAM_DQ[2]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.947      ; 4.089      ;
; 2.620  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15                ; SDRAM_DQ[15]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.956      ; 4.089      ;
; 2.620  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14                ; SDRAM_DQ[14]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.956      ; 4.089      ;
; 2.627  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11                ; SDRAM_DQ[11]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.953      ; 4.079      ;
; 2.627  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10                ; SDRAM_DQ[10]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.953      ; 4.079      ;
; 2.629  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12                ; SDRAM_DQ[12]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.955      ; 4.079      ;
; 2.629  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13                ; SDRAM_DQ[13]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.955      ; 4.079      ;
; 2.639  ; sdram_statemachine:sdram_adaptor|dq_output_reg                              ; SDRAM_DQ[0]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.965      ; 4.079      ;
; 2.642  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1                 ; SDRAM_DQ[1]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.968      ; 4.079      ;
; 2.645  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8                 ; SDRAM_DQ[8]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.961      ; 4.069      ;
; 2.645  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9                 ; SDRAM_DQ[9]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.961      ; 4.069      ;
; 2.707  ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]                              ; SDRAM_DQ[5]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.882      ; 3.928      ;
; 2.717  ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]                              ; SDRAM_DQ[4]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.882      ; 3.918      ;
; 2.718  ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                ; SDRAM_A[3]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.883      ; 3.918      ;
; 2.718  ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                              ; SDRAM_DQ[6]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.883      ; 3.918      ;
; 2.719  ; sdram_statemachine:sdram_adaptor|we_n_reg                                   ; SDRAM_nWE                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.884      ; 3.918      ;
; 2.719  ; sdram_statemachine:sdram_adaptor|ldqm_reg                                   ; SDRAM_DQML                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.884      ; 3.918      ;
; 2.719  ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                              ; SDRAM_DQ[7]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.884      ; 3.918      ;
; 2.728  ; sdram_statemachine:sdram_adaptor|addr_reg[4]                                ; SDRAM_A[4]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.928      ; 3.953      ;
; 2.729  ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                ; SDRAM_A[1]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.884      ; 3.908      ;
; 2.729  ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                ; SDRAM_A[2]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.884      ; 3.908      ;
; 2.731  ; sdram_statemachine:sdram_adaptor|addr_reg[0]                                ; SDRAM_A[0]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.886      ; 3.908      ;
; 2.731  ; sdram_statemachine:sdram_adaptor|addr_reg[10]                               ; SDRAM_A[10]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.886      ; 3.908      ;
; 2.731  ; sdram_statemachine:sdram_adaptor|ba_reg[0]                                  ; SDRAM_BA[0]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.886      ; 3.908      ;
; 2.731  ; sdram_statemachine:sdram_adaptor|cas_n_reg                                  ; SDRAM_nCAS                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.886      ; 3.908      ;
; 2.731  ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                              ; SDRAM_DQ[3]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.931      ; 3.953      ;
; 2.731  ; sdram_statemachine:sdram_adaptor|dq_out_reg[2]                              ; SDRAM_DQ[2]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.931      ; 3.953      ;
; 2.732  ; sdram_statemachine:sdram_adaptor|ras_n_reg                                  ; SDRAM_nRAS                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.887      ; 3.908      ;
; 2.740  ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                             ; SDRAM_DQ[15]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.940      ; 3.953      ;
; 2.741  ; sdram_statemachine:sdram_adaptor|ba_reg[1]                                  ; SDRAM_BA[1]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.886      ; 3.898      ;
; 2.749  ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]                             ; SDRAM_DQ[12]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.939      ; 3.943      ;
; 3.618  ; sdram_statemachine:sdram_adaptor|cke_reg                                    ; SDRAM_CKE                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.877      ; 3.012      ;
+--------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                    ;
+-------+-----------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                             ; To Node                                                                                                                        ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.593 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.117     ; 16.912     ;
; 0.612 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.089     ; 16.921     ;
; 0.744 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.176     ; 16.702     ;
; 0.820 ; ioctl_state.IOCTL_IDLE~_Duplicate_7                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.538     ; 16.264     ;
; 0.899 ; user_io:my_user_io|status[1]                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.089     ; 16.634     ;
; 0.905 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.117     ; 16.600     ;
; 0.958 ; DMA_16BIT_WRITE_ENABLE_IOCTL~_Duplicate_1                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.078     ; 16.586     ;
; 0.959 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.088     ; 16.575     ;
; 0.975 ; DMA_16BIT_WRITE_ENABLE_IOCTL                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.088     ; 16.559     ;
; 1.016 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.115     ; 16.491     ;
; 1.031 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.353      ; 16.944     ;
; 1.041 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[0]~_Duplicate_30 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.111     ; 16.470     ;
; 1.050 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.381      ; 16.953     ;
; 1.052 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.349      ; 16.919     ;
; 1.059 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[7]~_Duplicate_31 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.114     ; 16.449     ;
; 1.060 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[0]~_Duplicate_30 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.083     ; 16.479     ;
; 1.067 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[37]        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.386      ; 16.941     ;
; 1.071 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.377      ; 16.928     ;
; 1.076 ; cart_type_byte[4]~_Duplicate_10                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.078     ; 16.468     ;
; 1.078 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[7]~_Duplicate_31 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.086     ; 16.458     ;
; 1.081 ; ioctl_state.IOCTL_IDLE                                                                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.089     ; 16.452     ;
; 1.089 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.115     ; 16.418     ;
; 1.096 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg               ; ioctl_state.IOCTL_IDLE~_Duplicate_1                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 16.444     ;
; 1.104 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.359      ; 16.877     ;
; 1.104 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.359      ; 16.877     ;
; 1.104 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[4]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.359      ; 16.877     ;
; 1.104 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.359      ; 16.877     ;
; 1.112 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.358      ; 16.868     ;
; 1.115 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                   ; ioctl_state.IOCTL_IDLE~_Duplicate_1                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.054     ; 16.453     ;
; 1.123 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.387      ; 16.886     ;
; 1.123 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.387      ; 16.886     ;
; 1.123 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[4]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.387      ; 16.886     ;
; 1.123 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.387      ; 16.886     ;
; 1.128 ; ioctl_state.IOCTL_IDLE~_Duplicate_1                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.115     ; 16.379     ;
; 1.147 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.115     ; 16.360     ;
; 1.153 ; cart_type_byte[3]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.080     ; 16.389     ;
; 1.158 ; user_io:my_user_io|but_sw[1]                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 16.382     ;
; 1.173 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[0]~_Duplicate_30 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.189     ; 16.260     ;
; 1.174 ; cart_type_byte[7]~_Duplicate_8                                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.078     ; 16.370     ;
; 1.182 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.294      ; 16.734     ;
; 1.184 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Y[0]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.119     ; 16.319     ;
; 1.184 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.271      ; 16.709     ;
; 1.185 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[37]        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.414      ; 16.851     ;
; 1.185 ; cart_type_byte[5]~_Duplicate_9                                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.078     ; 16.359     ;
; 1.191 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[7]~_Duplicate_31 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.192     ; 16.239     ;
; 1.201 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_reg[0]                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.107     ; 16.314     ;
; 1.203 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Y[0]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.091     ; 16.328     ;
; 1.217 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg               ; ioctl_state.IOCTL_IDLE~_Duplicate_9                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.115     ; 16.290     ;
; 1.220 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg~_Duplicate_1            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.107     ; 16.295     ;
; 1.220 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_reg[0]                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.079     ; 16.323     ;
; 1.221 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.575     ; 15.826     ;
; 1.228 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                ; ioctl_state.IOCTL_IDLE~_Duplicate_1                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.160     ; 16.234     ;
; 1.230 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.386      ; 16.778     ;
; 1.231 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[9]               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.086     ; 16.305     ;
; 1.233 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.081     ; 16.308     ;
; 1.233 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[11]                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.081     ; 16.308     ;
; 1.233 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.081     ; 16.308     ;
; 1.233 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[12]                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.081     ; 16.308     ;
; 1.233 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[13]                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.081     ; 16.308     ;
; 1.236 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                   ; ioctl_state.IOCTL_IDLE~_Duplicate_9                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.087     ; 16.299     ;
; 1.236 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.281      ; 16.667     ;
; 1.236 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.281      ; 16.667     ;
; 1.236 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[4]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.281      ; 16.667     ;
; 1.236 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.281      ; 16.667     ;
; 1.239 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg~_Duplicate_1            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.079     ; 16.304     ;
; 1.252 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.053     ; 16.317     ;
; 1.252 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[11]                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.053     ; 16.317     ;
; 1.252 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.053     ; 16.317     ;
; 1.252 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[12]                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.053     ; 16.317     ;
; 1.252 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[13]                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.053     ; 16.317     ;
; 1.252 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[9] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.080     ; 16.290     ;
; 1.258 ; ioctl_state.IOCTL_IDLE~_Duplicate_7                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.068     ; 16.296     ;
; 1.258 ; cart_type_byte[3]~_Duplicate_12                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.078     ; 16.286     ;
; 1.267 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[6]          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.107     ; 16.248     ;
; 1.267 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[3]          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.107     ; 16.248     ;
; 1.268 ; ioctl_state.IOCTL_IDLE~_Duplicate_7                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[0]~_Duplicate_30 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.532     ; 15.822     ;
; 1.279 ; ioctl_state.IOCTL_IDLE~_Duplicate_7                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.072     ; 16.271     ;
; 1.286 ; ioctl_state.IOCTL_IDLE~_Duplicate_7                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[7]~_Duplicate_31 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.535     ; 15.801     ;
; 1.286 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[6]          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.079     ; 16.257     ;
; 1.286 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[3]          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.079     ; 16.257     ;
; 1.295 ; cart_type_byte[0]~_Duplicate_11                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.078     ; 16.249     ;
; 1.298 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[37]        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.308      ; 16.632     ;
; 1.308 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg               ; ioctl_state.IOCTL_IDLE~_Duplicate_7                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.324      ; 16.638     ;
; 1.316 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Y[0]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.197     ; 16.109     ;
; 1.321 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg~_Duplicate_1  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.088     ; 16.213     ;
; 1.323 ; ioctl_state.IOCTL_IDLE~_Duplicate_7                                                                                   ; ioctl_state.IOCTL_IDLE~_Duplicate_1                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.503     ; 15.796     ;
; 1.327 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                   ; ioctl_state.IOCTL_IDLE~_Duplicate_7                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.352      ; 16.647     ;
; 1.331 ; ioctl_state.IOCTL_IDLE~_Duplicate_7                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.062     ; 16.229     ;
; 1.331 ; ioctl_state.IOCTL_IDLE~_Duplicate_7                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.062     ; 16.229     ;
; 1.331 ; ioctl_state.IOCTL_IDLE~_Duplicate_7                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[4]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.062     ; 16.229     ;
; 1.331 ; ioctl_state.IOCTL_IDLE~_Duplicate_7                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.062     ; 16.229     ;
; 1.332 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg~_Duplicate_1   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.089     ; 16.201     ;
; 1.333 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_reg[0]                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.185     ; 16.104     ;
; 1.337 ; user_io:my_user_io|status[1]                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.381      ; 16.666     ;
; 1.343 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.353      ; 16.632     ;
; 1.343 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.280      ; 16.559     ;
; 1.347 ; user_io:my_user_io|status[1]                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[0]~_Duplicate_30 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.083     ; 16.192     ;
; 1.349 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                ; ioctl_state.IOCTL_IDLE~_Duplicate_9                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.193     ; 16.080     ;
; 1.352 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg~_Duplicate_1            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.185     ; 16.085     ;
; 1.353 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[0]~_Duplicate_30 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.111     ; 16.158     ;
+-------+-----------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                 ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.945 ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:0:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 4.405        ; -2.032     ; 1.286      ;
; 0.959 ; SDRAM_DQ[1]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[1]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.436     ; 1.231      ;
; 0.961 ; SDRAM_DQ[14]                                                                ; sdram_statemachine:sdram_adaptor|dq_in_reg[14]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.424     ; 1.241      ;
; 0.961 ; SDRAM_DQ[15]                                                                ; sdram_statemachine:sdram_adaptor|dq_in_reg[15]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.424     ; 1.241      ;
; 0.963 ; SDRAM_DQ[0]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[0]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.432     ; 1.231      ;
; 0.969 ; SDRAM_DQ[2]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[2]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.416     ; 1.241      ;
; 0.969 ; SDRAM_DQ[3]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[3]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.416     ; 1.241      ;
; 0.973 ; SDRAM_DQ[13]                                                                ; sdram_statemachine:sdram_adaptor|dq_in_reg[13]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.422     ; 1.231      ;
; 0.973 ; SDRAM_DQ[12]                                                                ; sdram_statemachine:sdram_adaptor|dq_in_reg[12]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.422     ; 1.231      ;
; 0.974 ; SDRAM_DQ[11]                                                                ; sdram_statemachine:sdram_adaptor|dq_in_reg[11]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.421     ; 1.231      ;
; 0.974 ; SDRAM_DQ[10]                                                                ; sdram_statemachine:sdram_adaptor|dq_in_reg[10]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.421     ; 1.231      ;
; 0.976 ; SDRAM_DQ[9]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[9]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.429     ; 1.221      ;
; 0.976 ; SDRAM_DQ[8]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[8]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.429     ; 1.221      ;
; 1.006 ; SDRAM_DQ[5]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[5]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.369     ; 1.251      ;
; 1.015 ; SDRAM_DQ[7]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[7]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.370     ; 1.241      ;
; 1.016 ; SDRAM_DQ[4]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[4]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.369     ; 1.241      ;
; 1.016 ; SDRAM_DQ[6]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[6]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.369     ; 1.241      ;
; 1.606 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.144     ; 6.931      ;
; 1.681 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.144     ; 6.856      ;
; 1.850 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.144     ; 6.687      ;
; 1.885 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.096     ; 6.700      ;
; 1.934 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.096     ; 6.651      ;
; 1.938 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.095     ; 6.648      ;
; 1.946 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.142     ; 6.593      ;
; 1.946 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.061     ; 6.804      ;
; 1.946 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.061     ; 6.804      ;
; 1.946 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.061     ; 6.804      ;
; 1.946 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.061     ; 6.804      ;
; 1.946 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.061     ; 6.804      ;
; 1.946 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.061     ; 6.804      ;
; 1.946 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.061     ; 6.804      ;
; 1.946 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.061     ; 6.804      ;
; 1.946 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.061     ; 6.804      ;
; 1.946 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.061     ; 6.804      ;
; 1.946 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.061     ; 6.804      ;
; 1.946 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.061     ; 6.804      ;
; 1.957 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.142     ; 6.582      ;
; 1.970 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.142     ; 6.569      ;
; 1.972 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.142     ; 6.567      ;
; 1.974 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.061     ; 6.776      ;
; 1.974 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.061     ; 6.776      ;
; 1.974 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.061     ; 6.776      ;
; 1.974 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.061     ; 6.776      ;
; 1.974 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.061     ; 6.776      ;
; 1.974 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.061     ; 6.776      ;
; 1.974 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.061     ; 6.776      ;
; 1.974 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.061     ; 6.776      ;
; 1.974 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.061     ; 6.776      ;
; 1.974 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.061     ; 6.776      ;
; 1.974 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.061     ; 6.776      ;
; 1.974 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.061     ; 6.776      ;
; 1.993 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.095     ; 6.593      ;
; 2.023 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.144     ; 6.514      ;
; 2.060 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.146     ; 6.475      ;
; 2.085 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.148     ; 6.448      ;
; 2.129 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.096     ; 6.456      ;
; 2.135 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.146     ; 6.400      ;
; 2.136 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.148     ; 6.397      ;
; 2.149 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.061     ; 6.601      ;
; 2.149 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.061     ; 6.601      ;
; 2.149 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.061     ; 6.601      ;
; 2.149 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.061     ; 6.601      ;
; 2.149 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.061     ; 6.601      ;
; 2.149 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.061     ; 6.601      ;
; 2.149 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.061     ; 6.601      ;
; 2.149 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.061     ; 6.601      ;
; 2.149 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.061     ; 6.601      ;
; 2.149 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.061     ; 6.601      ;
; 2.149 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.061     ; 6.601      ;
; 2.149 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.061     ; 6.601      ;
; 2.156 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.142     ; 6.383      ;
; 2.159 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.144     ; 6.378      ;
; 2.171 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.142     ; 6.368      ;
; 2.182 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.095     ; 6.404      ;
; 2.248 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.096     ; 6.337      ;
; 2.261 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.061     ; 6.489      ;
; 2.261 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.061     ; 6.489      ;
; 2.261 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.061     ; 6.489      ;
; 2.261 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.061     ; 6.489      ;
; 2.261 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.061     ; 6.489      ;
; 2.261 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.061     ; 6.489      ;
; 2.261 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.061     ; 6.489      ;
; 2.261 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.061     ; 6.489      ;
; 2.261 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.061     ; 6.489      ;
; 2.261 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.061     ; 6.489      ;
; 2.261 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.061     ; 6.489      ;
; 2.261 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.061     ; 6.489      ;
; 2.282 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.096     ; 6.303      ;
; 2.302 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.096     ; 6.283      ;
; 2.304 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.146     ; 6.231      ;
; 2.329 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.148     ; 6.204      ;
; 2.355 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.095     ; 6.231      ;
; 2.361 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[5]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.140     ; 6.180      ;
; 2.363 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.142     ; 6.176      ;
; 2.365 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.142     ; 6.174      ;
; 2.394 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.144     ; 6.143      ;
; 2.476 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.146     ; 6.059      ;
; 2.477 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.146     ; 6.058      ;
; 2.480 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[10]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.098     ; 6.103      ;
; 2.481 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.096     ; 6.104      ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'SPI_SCK'                                                                                                                       ;
+--------+---------------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                             ; To Node                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+
; 14.954 ; user_io:my_user_io|byte_cnt[8]        ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 5.927      ;
; 14.954 ; user_io:my_user_io|byte_cnt[8]        ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 5.927      ;
; 14.954 ; user_io:my_user_io|byte_cnt[8]        ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 5.927      ;
; 14.954 ; user_io:my_user_io|byte_cnt[8]        ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 5.927      ;
; 14.954 ; user_io:my_user_io|byte_cnt[8]        ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 5.927      ;
; 15.140 ; user_io:my_user_io|byte_cnt[7]        ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 5.741      ;
; 15.140 ; user_io:my_user_io|byte_cnt[7]        ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 5.741      ;
; 15.140 ; user_io:my_user_io|byte_cnt[7]        ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 5.741      ;
; 15.140 ; user_io:my_user_io|byte_cnt[7]        ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 5.741      ;
; 15.140 ; user_io:my_user_io|byte_cnt[7]        ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 5.741      ;
; 15.397 ; user_io:my_user_io|byte_cnt[5]        ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 5.484      ;
; 15.397 ; user_io:my_user_io|byte_cnt[5]        ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 5.484      ;
; 15.397 ; user_io:my_user_io|byte_cnt[5]        ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 5.484      ;
; 15.397 ; user_io:my_user_io|byte_cnt[5]        ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 5.484      ;
; 15.397 ; user_io:my_user_io|byte_cnt[5]        ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 5.484      ;
; 15.445 ; user_io:my_user_io|byte_cnt[8]        ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 5.436      ;
; 15.534 ; user_io:my_user_io|byte_cnt[6]        ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 5.347      ;
; 15.534 ; user_io:my_user_io|byte_cnt[6]        ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 5.347      ;
; 15.534 ; user_io:my_user_io|byte_cnt[6]        ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 5.347      ;
; 15.534 ; user_io:my_user_io|byte_cnt[6]        ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 5.347      ;
; 15.534 ; user_io:my_user_io|byte_cnt[6]        ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 5.347      ;
; 15.631 ; user_io:my_user_io|byte_cnt[7]        ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 5.250      ;
; 15.662 ; user_io:my_user_io|byte_cnt[3]        ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 5.219      ;
; 15.662 ; user_io:my_user_io|byte_cnt[3]        ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 5.219      ;
; 15.662 ; user_io:my_user_io|byte_cnt[3]        ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 5.219      ;
; 15.662 ; user_io:my_user_io|byte_cnt[3]        ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 5.219      ;
; 15.662 ; user_io:my_user_io|byte_cnt[3]        ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 5.219      ;
; 15.888 ; user_io:my_user_io|byte_cnt[5]        ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 4.993      ;
; 16.025 ; user_io:my_user_io|byte_cnt[6]        ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 4.856      ;
; 16.114 ; user_io:my_user_io|byte_cnt[9]        ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 4.767      ;
; 16.114 ; user_io:my_user_io|byte_cnt[9]        ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 4.767      ;
; 16.114 ; user_io:my_user_io|byte_cnt[9]        ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 4.767      ;
; 16.114 ; user_io:my_user_io|byte_cnt[9]        ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 4.767      ;
; 16.114 ; user_io:my_user_io|byte_cnt[9]        ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 4.767      ;
; 16.153 ; user_io:my_user_io|byte_cnt[3]        ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 4.728      ;
; 16.468 ; user_io:my_user_io|bit_cnt[0]         ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.012      ; 4.411      ;
; 16.468 ; user_io:my_user_io|bit_cnt[0]         ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.012      ; 4.411      ;
; 16.468 ; user_io:my_user_io|bit_cnt[0]         ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.012      ; 4.411      ;
; 16.468 ; user_io:my_user_io|bit_cnt[0]         ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.012      ; 4.411      ;
; 16.468 ; user_io:my_user_io|bit_cnt[0]         ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.012      ; 4.411      ;
; 16.482 ; user_io:my_user_io|byte_cnt[4]        ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 4.399      ;
; 16.482 ; user_io:my_user_io|byte_cnt[4]        ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 4.399      ;
; 16.482 ; user_io:my_user_io|byte_cnt[4]        ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 4.399      ;
; 16.482 ; user_io:my_user_io|byte_cnt[4]        ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 4.399      ;
; 16.482 ; user_io:my_user_io|byte_cnt[4]        ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 4.399      ;
; 16.563 ; user_io:my_user_io|byte_cnt[2]        ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 4.318      ;
; 16.563 ; user_io:my_user_io|byte_cnt[2]        ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 4.318      ;
; 16.563 ; user_io:my_user_io|byte_cnt[2]        ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 4.318      ;
; 16.563 ; user_io:my_user_io|byte_cnt[2]        ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 4.318      ;
; 16.563 ; user_io:my_user_io|byte_cnt[2]        ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 4.318      ;
; 16.605 ; user_io:my_user_io|byte_cnt[9]        ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 4.276      ;
; 16.846 ; user_io:my_user_io|bit_cnt[2]         ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.012      ; 4.033      ;
; 16.846 ; user_io:my_user_io|bit_cnt[2]         ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.012      ; 4.033      ;
; 16.846 ; user_io:my_user_io|bit_cnt[2]         ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.012      ; 4.033      ;
; 16.846 ; user_io:my_user_io|bit_cnt[2]         ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.012      ; 4.033      ;
; 16.846 ; user_io:my_user_io|bit_cnt[2]         ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.012      ; 4.033      ;
; 16.865 ; user_io:my_user_io|byte_cnt[1]        ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 4.016      ;
; 16.865 ; user_io:my_user_io|byte_cnt[1]        ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 4.016      ;
; 16.865 ; user_io:my_user_io|byte_cnt[1]        ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 4.016      ;
; 16.865 ; user_io:my_user_io|byte_cnt[1]        ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 4.016      ;
; 16.865 ; user_io:my_user_io|byte_cnt[1]        ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 4.016      ;
; 16.942 ; user_io:my_user_io|cmd[3]             ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.004      ; 3.929      ;
; 16.942 ; user_io:my_user_io|cmd[3]             ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.004      ; 3.929      ;
; 16.942 ; user_io:my_user_io|cmd[3]             ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.004      ; 3.929      ;
; 16.942 ; user_io:my_user_io|cmd[3]             ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.004      ; 3.929      ;
; 16.942 ; user_io:my_user_io|cmd[3]             ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.004      ; 3.929      ;
; 16.973 ; user_io:my_user_io|byte_cnt[4]        ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 3.908      ;
; 16.979 ; user_io:my_user_io|bit_cnt[1]         ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.012      ; 3.900      ;
; 16.979 ; user_io:my_user_io|bit_cnt[1]         ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.012      ; 3.900      ;
; 16.979 ; user_io:my_user_io|bit_cnt[1]         ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.012      ; 3.900      ;
; 16.979 ; user_io:my_user_io|bit_cnt[1]         ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.012      ; 3.900      ;
; 16.979 ; user_io:my_user_io|bit_cnt[1]         ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.012      ; 3.900      ;
; 16.992 ; user_io:my_user_io|bit_cnt[0]         ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.012      ; 3.887      ;
; 17.021 ; user_io:my_user_io|byte_cnt[0]        ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 3.860      ;
; 17.021 ; user_io:my_user_io|byte_cnt[0]        ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 3.860      ;
; 17.021 ; user_io:my_user_io|byte_cnt[0]        ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 3.860      ;
; 17.021 ; user_io:my_user_io|byte_cnt[0]        ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 3.860      ;
; 17.021 ; user_io:my_user_io|byte_cnt[0]        ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 3.860      ;
; 17.087 ; user_io:my_user_io|byte_cnt[2]        ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 3.794      ;
; 17.209 ; user_io:my_user_io|cmd[5]             ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.016      ; 3.674      ;
; 17.209 ; user_io:my_user_io|cmd[5]             ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.016      ; 3.674      ;
; 17.209 ; user_io:my_user_io|cmd[5]             ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.016      ; 3.674      ;
; 17.209 ; user_io:my_user_io|cmd[5]             ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.016      ; 3.674      ;
; 17.209 ; user_io:my_user_io|cmd[5]             ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.016      ; 3.674      ;
; 17.215 ; user_io:my_user_io|cmd[7]             ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.016      ; 3.668      ;
; 17.215 ; user_io:my_user_io|cmd[7]             ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.016      ; 3.668      ;
; 17.215 ; user_io:my_user_io|cmd[7]             ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.016      ; 3.668      ;
; 17.215 ; user_io:my_user_io|cmd[7]             ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.016      ; 3.668      ;
; 17.215 ; user_io:my_user_io|cmd[7]             ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.016      ; 3.668      ;
; 17.267 ; user_io:my_user_io|serial_out_rptr[0] ; user_io:my_user_io|spi_byte_out[0]    ; SPI_SCK      ; SPI_SCK     ; 20.800       ; -0.174     ; 3.360      ;
; 17.278 ; user_io:my_user_io|serial_out_rptr[2] ; user_io:my_user_io|spi_byte_out[0]    ; SPI_SCK      ; SPI_SCK     ; 20.800       ; -0.174     ; 3.349      ;
; 17.356 ; user_io:my_user_io|cmd[6]             ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.016      ; 3.527      ;
; 17.356 ; user_io:my_user_io|cmd[6]             ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.016      ; 3.527      ;
; 17.356 ; user_io:my_user_io|cmd[6]             ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.016      ; 3.527      ;
; 17.356 ; user_io:my_user_io|cmd[6]             ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.016      ; 3.527      ;
; 17.356 ; user_io:my_user_io|cmd[6]             ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.016      ; 3.527      ;
; 17.365 ; user_io:my_user_io|byte_cnt[1]        ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.014      ; 3.516      ;
; 17.370 ; user_io:my_user_io|bit_cnt[2]         ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.012      ; 3.509      ;
; 17.430 ; user_io:my_user_io|cmd[1]             ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.004      ; 3.441      ;
; 17.430 ; user_io:my_user_io|cmd[1]             ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.004      ; 3.441      ;
+--------+---------------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'clk_27'                                                                                                                                                                ;
+--------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                 ; To Node                                                   ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 34.116 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.843      ;
; 34.159 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.800      ;
; 34.264 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.695      ;
; 34.266 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.693      ;
; 34.294 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.665      ;
; 34.303 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.656      ;
; 34.307 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.652      ;
; 34.394 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.565      ;
; 34.409 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.550      ;
; 34.414 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.545      ;
; 34.438 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.521      ;
; 34.451 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.508      ;
; 34.452 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.507      ;
; 34.529 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.430      ;
; 34.552 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.407      ;
; 34.557 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.402      ;
; 34.587 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.372      ;
; 34.588 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.371      ;
; 34.681 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.278      ;
; 34.688 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.271      ;
; 34.825 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.134      ;
; 34.832 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.127      ;
; 34.837 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.122      ;
; 34.844 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.115      ;
; 34.857 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.102      ;
; 34.922 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.037      ;
; 34.936 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.023      ;
; 34.957 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 2.002      ;
; 34.976 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.983      ;
; 35.001 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.958      ;
; 35.014 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.945      ;
; 35.021 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.938      ;
; 35.033 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.926      ;
; 35.033 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.926      ;
; 35.045 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.914      ;
; 35.092 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.867      ;
; 35.108 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.851      ;
; 35.109 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.850      ;
; 35.117 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.842      ;
; 35.122 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.837      ;
; 35.126 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.833      ;
; 35.195 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.764      ;
; 35.202 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.757      ;
; 35.208 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.751      ;
; 35.222 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.737      ;
; 35.222 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.737      ;
; 35.236 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.723      ;
; 35.294 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.665      ;
; 35.295 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.664      ;
; 35.395 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.564      ;
; 35.409 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.550      ;
; 35.409 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.550      ;
; 35.481 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.478      ;
; 35.581 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.378      ;
; 35.595 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.364      ;
; 35.595 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.364      ;
; 35.679 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.280      ;
; 35.681 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.278      ;
; 35.720 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 1.239      ;
; 36.101 ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.079     ; 0.858      ;
+--------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                         ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                                       ; To Node                                                                                                                                                                                                                               ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 36.854 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_we_reg ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.803     ; 6.401      ;
; 37.374 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|idle_state                                                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 4.111      ; 8.405      ;
; 38.959 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 4.109      ; 6.818      ;
; 39.285 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 4.109      ; 6.492      ;
; 39.311 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_data_state                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.401     ; 4.346      ;
; 39.318 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_data_state                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.401     ; 4.339      ;
; 39.416 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_init_state_1                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 4.105      ; 6.357      ;
; 39.519 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_data_state                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.401     ; 4.138      ;
; 39.653 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_data_state                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.401     ; 4.004      ;
; 39.927 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_data_state                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.401     ; 3.730      ;
; 40.323 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_seq_data_state                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.406     ; 3.329      ;
; 40.392 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[1]                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.402     ; 3.264      ;
; 40.393 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[3]                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.402     ; 3.263      ;
; 40.453 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate2_state                                                             ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate3_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.122     ; 1.092      ;
; 40.579 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[2]                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.402     ; 3.077      ;
; 40.726 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[4]                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.402     ; 2.930      ;
; 41.171 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                                             ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.406     ; 2.481      ;
; 41.289 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[0]                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.402     ; 2.367      ;
; 75.340 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                             ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|idle_state                                                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.078     ; 7.916      ;
; 76.314 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|idle_state                                                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.074     ; 6.946      ;
; 76.877 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                             ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.080     ; 6.377      ;
; 77.220 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                             ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.080     ; 6.034      ;
; 77.349 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                             ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_init_state_1                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.084     ; 5.901      ;
; 77.727 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_second_state                                                                ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.318      ; 5.972      ;
; 77.727 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_second_state                                                                ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.318      ; 5.972      ;
; 77.851 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.076     ; 5.407      ;
; 78.192 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[2]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.319      ; 5.508      ;
; 78.192 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[2]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.319      ; 5.508      ;
; 78.194 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.076     ; 5.064      ;
; 78.323 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_init_state_1                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.080     ; 4.931      ;
; 78.330 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_first_state                                                                 ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.318      ; 5.369      ;
; 78.330 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_first_state                                                                 ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.318      ; 5.369      ;
; 78.379 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.076     ; 4.879      ;
; 78.379 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.076     ; 4.879      ;
; 78.379 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.076     ; 4.879      ;
; 78.379 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.076     ; 4.879      ;
; 78.379 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.076     ; 4.879      ;
; 78.379 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[5]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.076     ; 4.879      ;
; 78.379 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[6]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.076     ; 4.879      ;
; 78.379 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[7]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.076     ; 4.879      ;
; 78.427 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[1]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.319      ; 5.273      ;
; 78.427 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[1]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.319      ; 5.273      ;
; 78.451 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.812      ;
; 78.499 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.764      ;
; 78.557 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.076     ; 4.701      ;
; 78.557 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.076     ; 4.701      ;
; 78.557 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.076     ; 4.701      ;
; 78.557 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.076     ; 4.701      ;
; 78.557 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.076     ; 4.701      ;
; 78.557 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[5]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.076     ; 4.701      ;
; 78.557 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[6]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.076     ; 4.701      ;
; 78.557 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[7]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.076     ; 4.701      ;
; 78.588 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                   ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.081     ; 4.665      ;
; 78.597 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.666      ;
; 78.612 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[3]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.319      ; 5.088      ;
; 78.612 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[3]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.319      ; 5.088      ;
; 78.636 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                   ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.081     ; 4.617      ;
; 78.671 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_data_state                                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_address_reg0 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.318      ; 5.028      ;
; 78.708 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[5]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.319      ; 4.992      ;
; 78.708 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[5]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.319      ; 4.992      ;
; 78.709 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[6]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.319      ; 4.991      ;
; 78.709 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[6]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.319      ; 4.991      ;
; 78.734 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                   ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.081     ; 4.519      ;
; 78.762 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[0]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.319      ; 4.938      ;
; 78.762 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[0]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.319      ; 4.938      ;
; 78.807 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.077     ; 4.450      ;
; 78.826 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                   ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[0]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.081     ; 4.427      ;
; 78.826 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                   ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.081     ; 4.427      ;
; 78.826 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                   ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.081     ; 4.427      ;
; 78.826 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                   ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.081     ; 4.427      ;
; 78.826 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                   ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.081     ; 4.427      ;
; 78.826 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                   ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.081     ; 4.427      ;
; 78.826 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                   ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.081     ; 4.427      ;
; 78.826 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                   ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.081     ; 4.427      ;
; 78.876 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_second_last_state                                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_address_reg0 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.320      ; 4.825      ;
; 78.885 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.077     ; 4.372      ;
; 78.891 ; rom_loaded                                                                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.077     ; 4.366      ;
; 78.894 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[7]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.319      ; 4.806      ;
; 78.894 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[7]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.319      ; 4.806      ;
; 78.912 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[0]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.351      ;
; 78.912 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.351      ;
; 78.912 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.351      ;
; 78.912 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.351      ;
; 78.912 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.351      ;
; 78.912 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.351      ;
; 78.912 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.351      ;
; 78.912 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.351      ;
; 78.966 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.076     ; 4.292      ;
; 78.966 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.076     ; 4.292      ;
; 78.966 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.076     ; 4.292      ;
; 78.966 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.076     ; 4.292      ;
; 78.966 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.076     ; 4.292      ;
; 78.966 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[5]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.076     ; 4.292      ;
; 78.966 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[6]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.076     ; 4.292      ;
; 78.966 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[7]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.076     ; 4.292      ;
; 78.969 ; rom_loaded                                                                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.077     ; 4.288      ;
; 79.023 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.076     ; 4.235      ;
; 79.028 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_last_state                                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_address_reg0 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.319      ; 4.672      ;
; 79.034 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.079     ; 4.221      ;
; 79.034 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.079     ; 4.221      ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                     ; To Node                                                                                                                                                                                                                                 ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.406 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_snap_reg[4]                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.480      ; 1.140      ;
; 0.408 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[0]                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.480      ; 1.142      ;
; 0.409 ; user_io:my_user_io|sd_dout[6]                                                                                                                 ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.478      ; 1.141      ;
; 0.413 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_snap_reg[0]                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.480      ; 1.147      ;
; 0.414 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[3]                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.480      ; 1.148      ;
; 0.414 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp3_snap_reg[5]                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.480      ; 1.148      ;
; 0.416 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[0]                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.479      ; 1.149      ;
; 0.416 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_snap_reg[6]                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.479      ; 1.149      ;
; 0.420 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[0]                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.480      ; 1.154      ;
; 0.421 ; user_io:my_user_io|sd_dout[5]                                                                                                                 ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.478      ; 1.153      ;
; 0.422 ; user_io:my_user_io|sd_dout[1]                                                                                                                 ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.478      ; 1.154      ;
; 0.424 ; user_io:my_user_io|sd_dout[3]                                                                                                                 ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.478      ; 1.156      ;
; 0.427 ; user_io:my_user_io|sd_dout[4]                                                                                                                 ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.478      ; 1.159      ;
; 0.429 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[6]                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.480      ; 1.163      ;
; 0.430 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[7]                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.480      ; 1.164      ;
; 0.431 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[5]                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.480      ; 1.165      ;
; 0.434 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|state[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|state[1]                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 0.746      ;
; 0.435 ; user_io:my_user_io|sd_buff_addr[1]                                                                                                            ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.474      ; 1.163      ;
; 0.435 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|irqb_reg[1]                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|irqb_reg[1]                                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.099      ; 0.746      ;
; 0.435 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|irqa_reg[1]                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|irqa_reg[1]                                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.099      ; 0.746      ;
; 0.436 ; user_io:my_user_io|sd_dout[0]                                                                                                                 ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.478      ; 1.168      ;
; 0.436 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_snap_reg[1]                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.480      ; 1.170      ;
; 0.439 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[2]                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.480      ; 1.173      ;
; 0.440 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_snap_reg[7]                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.480      ; 1.174      ;
; 0.442 ; user_io:my_user_io|sd_buff_addr[3]                                                                                                            ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.474      ; 1.170      ;
; 0.442 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[3]                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.483      ; 1.179      ;
; 0.443 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[2]                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.479      ; 1.176      ;
; 0.445 ; user_io:my_user_io|sd_buff_addr[6]                                                                                                            ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.474      ; 1.173      ;
; 0.445 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[7]                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.480      ; 1.179      ;
; 0.445 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_snap_reg[5]                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.480      ; 1.179      ;
; 0.446 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[5]                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.480      ; 1.180      ;
; 0.452 ; user_io:my_user_io|sd_dout[2]                                                                                                                 ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.478      ; 1.184      ;
; 0.452 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[1]                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.479      ; 1.185      ;
; 0.453 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|cntr_8rf:cntr1|counter_reg_bit[1] ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|altsyncram_14b1:altsyncram2|ram_block5a0~portb_address_reg0                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.475      ; 1.182      ;
; 0.453 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|cntr_8rf:cntr1|counter_reg_bit[1] ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|altsyncram_14b1:altsyncram2|ram_block5a0~porta_address_reg0                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.474      ; 1.181      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.454 ; user_io:my_user_io|ps2_kbd_tx_state[3]                                                                                                        ; user_io:my_user_io|ps2_kbd_tx_state[3]                                                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; user_io:my_user_io|ps2_kbd_tx_state[1]                                                                                                        ; user_io:my_user_io|ps2_kbd_tx_state[1]                                                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; user_io:my_user_io|ps2_kbd_tx_state[2]                                                                                                        ; user_io:my_user_io|ps2_kbd_tx_state[2]                                                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; user_io:my_user_io|ps2_kbd_tx_byte[7]                                                                                                         ; user_io:my_user_io|ps2_kbd_tx_byte[7]                                                                                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; user_io:my_user_io|ps2_kbd_parity                                                                                                             ; user_io:my_user_io|ps2_kbd_parity                                                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; user_io:my_user_io|ps2_kbd_data                                                                                                               ; user_io:my_user_io|ps2_kbd_data                                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[1]                                                                  ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[1]                                                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[2]                                                                  ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[2]                                                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[3]                                                                  ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[3]                                                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|pending_extended_reg                                                         ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|pending_extended_reg                                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|pending_keyup_reg                                                            ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|pending_keyup_reg                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[120]                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[120]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[9]                                                                                                 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[9]                                                                                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[91]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[91]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[21]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[21]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[88]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[88]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[46]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[46]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[27]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[27]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[51]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[51]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[44]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[44]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[6]                                                                                                 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[6]                                                                                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[66]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[66]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[67]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[67]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[93]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[93]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[82]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[82]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[76]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[76]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[85]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[85]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[78]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[78]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[273]                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[273]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[29]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[29]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[26]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[26]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[34]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[34]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[59]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[59]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[3]                                                                                                 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[3]                                                                                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[37]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[37]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[43]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[43]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[68]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[68]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[70]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[70]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[75]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[75]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[65]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[65]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[69]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[69]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[35]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[35]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[33]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[33]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[38]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[38]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[4]                                                                                                 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[4]                                                                                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[36]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[36]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[53]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[53]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[5]                                                                                                 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[5]                                                                                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[89]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[89]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[18]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[18]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[369]                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[369]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[10]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[10]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[1]                                                                                                 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[1]                                                                                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[11]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[11]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|count[0]                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|count[0]                                                                                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[370]                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[370]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[373]                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[373]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|stretch                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|stretch                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; data_io:mist_data_io|abyte_cnt[1]                                                                                                             ; data_io:mist_data_io|abyte_cnt[1]                                                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; data_io:mist_data_io|abyte_cnt[2]                                                                                                             ; data_io:mist_data_io|abyte_cnt[2]                                                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; data_io:mist_data_io|abyte_cnt[0]                                                                                                             ; data_io:mist_data_io|abyte_cnt[0]                                                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; data_io:mist_data_io|hi                                                                                                                       ; data_io:mist_data_io|hi                                                                                                                                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; data_io:mist_data_io|wr_int                                                                                                                   ; data_io:mist_data_io|wr_int                                                                                                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]                                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'SPI_SCK'                                                                                                                                                                                              ;
+-------+--------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                                  ; To Node                                                                                                 ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.419 ; osd:osd_inst|sbuf[1]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.484      ; 1.157      ;
; 0.431 ; osd:osd_inst|sbuf[5]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.480      ; 1.165      ;
; 0.437 ; osd:osd_inst|sbuf[3]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.480      ; 1.171      ;
; 0.453 ; osd:osd_inst|sbuf[4]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.480      ; 1.187      ;
; 0.453 ; osd:osd_inst|sbuf[6]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.480      ; 1.187      ;
; 0.454 ; osd:osd_inst|osd_enable                    ; osd:osd_inst|osd_enable                                                                                 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; user_io:my_user_io|bit_cnt[1]              ; user_io:my_user_io|bit_cnt[1]                                                                           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; user_io:my_user_io|bit_cnt[2]              ; user_io:my_user_io|bit_cnt[2]                                                                           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; user_io:my_user_io|byte_cnt[0]             ; user_io:my_user_io|byte_cnt[0]                                                                          ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; user_io:my_user_io|cmd[0]                  ; user_io:my_user_io|cmd[0]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; user_io:my_user_io|cmd[2]                  ; user_io:my_user_io|cmd[2]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; user_io:my_user_io|cmd[1]                  ; user_io:my_user_io|cmd[1]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; user_io:my_user_io|cmd[3]                  ; user_io:my_user_io|cmd[3]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 0.746      ;
; 0.455 ; data_io:mist_data_io|bit_cnt[1]            ; data_io:mist_data_io|bit_cnt[1]                                                                         ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; data_io:mist_data_io|bit_cnt[2]            ; data_io:mist_data_io|bit_cnt[2]                                                                         ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; user_io:my_user_io|serial_out_rptr[0]      ; user_io:my_user_io|serial_out_rptr[0]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.746      ;
; 0.457 ; osd:osd_inst|bcnt[1]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.476      ; 1.187      ;
; 0.458 ; osd:osd_inst|bcnt[7]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.477      ; 1.189      ;
; 0.466 ; data_io:mist_data_io|spi_receiver_strobe_r ; data_io:mist_data_io|spi_receiver_strobe_r                                                              ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 0.758      ;
; 0.466 ; user_io:my_user_io|bit_cnt[0]              ; user_io:my_user_io|bit_cnt[0]                                                                           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 0.758      ;
; 0.467 ; user_io:my_user_io|spi_receiver_strobe_r   ; user_io:my_user_io|spi_receiver_strobe_r                                                                ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.758      ;
; 0.467 ; data_io:mist_data_io|bit_cnt[0]            ; data_io:mist_data_io|bit_cnt[0]                                                                         ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.758      ;
; 0.475 ; osd:osd_inst|bcnt[4]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.477      ; 1.206      ;
; 0.475 ; osd:osd_inst|sbuf[2]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.481      ; 1.210      ;
; 0.480 ; osd:osd_inst|bcnt[2]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.476      ; 1.210      ;
; 0.488 ; osd:osd_inst|bcnt[8]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.476      ; 1.218      ;
; 0.501 ; osd:osd_inst|bcnt[4]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.476      ; 1.231      ;
; 0.504 ; data_io:mist_data_io|sbuf[6]               ; data_io:mist_data_io|spi_byte_in[7]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 0.796      ;
; 0.506 ; osd:osd_inst|bcnt[6]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.477      ; 1.237      ;
; 0.509 ; data_io:mist_data_io|sbuf[5]               ; data_io:mist_data_io|sbuf[6]                                                                            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 0.801      ;
; 0.509 ; osd:osd_inst|bcnt[10]                      ; osd:osd_inst|bcnt[10]                                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 0.801      ;
; 0.509 ; data_io:mist_data_io|bit_cnt[0]            ; data_io:mist_data_io|bit_cnt[2]                                                                         ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.800      ;
; 0.510 ; data_io:mist_data_io|sbuf[3]               ; data_io:mist_data_io|sbuf[4]                                                                            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 0.802      ;
; 0.510 ; data_io:mist_data_io|sbuf[3]               ; data_io:mist_data_io|spi_byte_in[4]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 0.802      ;
; 0.511 ; data_io:mist_data_io|sbuf[0]               ; data_io:mist_data_io|spi_byte_in[1]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 0.803      ;
; 0.511 ; data_io:mist_data_io|bit_cnt[0]            ; data_io:mist_data_io|bit_cnt[1]                                                                         ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.802      ;
; 0.512 ; data_io:mist_data_io|sbuf[0]               ; data_io:mist_data_io|sbuf[1]                                                                            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 0.804      ;
; 0.512 ; data_io:mist_data_io|sbuf[5]               ; data_io:mist_data_io|spi_byte_in[6]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 0.804      ;
; 0.513 ; user_io:my_user_io|sbuf[6]                 ; user_io:my_user_io|spi_byte_in[7]                                                                       ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.804      ;
; 0.519 ; user_io:my_user_io|sbuf[5]                 ; user_io:my_user_io|sbuf[6]                                                                              ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.810      ;
; 0.519 ; user_io:my_user_io|sbuf[4]                 ; user_io:my_user_io|spi_byte_in[5]                                                                       ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.810      ;
; 0.520 ; user_io:my_user_io|sbuf[3]                 ; user_io:my_user_io|sbuf[4]                                                                              ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.811      ;
; 0.520 ; user_io:my_user_io|sbuf[4]                 ; user_io:my_user_io|sbuf[5]                                                                              ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.811      ;
; 0.520 ; user_io:my_user_io|sbuf[5]                 ; user_io:my_user_io|spi_byte_in[6]                                                                       ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.811      ;
; 0.520 ; user_io:my_user_io|sbuf[3]                 ; user_io:my_user_io|spi_byte_in[4]                                                                       ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 0.811      ;
; 0.531 ; osd:osd_inst|bcnt[9]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.476      ; 1.261      ;
; 0.536 ; osd:osd_inst|sbuf[2]                       ; osd:osd_inst|sbuf[3]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 0.828      ;
; 0.536 ; osd:osd_inst|sbuf[2]                       ; osd:osd_inst|cmd[3]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 0.828      ;
; 0.542 ; user_io:my_user_io|sbuf[2]                 ; user_io:my_user_io|spi_byte_in[3]                                                                       ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 0.834      ;
; 0.697 ; osd:osd_inst|bcnt[3]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.477      ; 1.428      ;
; 0.698 ; osd:osd_inst|bcnt[0]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.476      ; 1.428      ;
; 0.707 ; data_io:mist_data_io|sbuf[2]               ; data_io:mist_data_io|sbuf[3]                                                                            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 0.999      ;
; 0.708 ; data_io:mist_data_io|sbuf[1]               ; data_io:mist_data_io|spi_byte_in[2]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.000      ;
; 0.708 ; data_io:mist_data_io|sbuf[2]               ; data_io:mist_data_io|spi_byte_in[3]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.000      ;
; 0.708 ; data_io:mist_data_io|sbuf[4]               ; data_io:mist_data_io|spi_byte_in[5]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.000      ;
; 0.710 ; data_io:mist_data_io|sbuf[1]               ; data_io:mist_data_io|sbuf[2]                                                                            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.002      ;
; 0.710 ; data_io:mist_data_io|sbuf[4]               ; data_io:mist_data_io|sbuf[5]                                                                            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.002      ;
; 0.719 ; user_io:my_user_io|sbuf[1]                 ; user_io:my_user_io|spi_byte_in[2]                                                                       ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.011      ;
; 0.724 ; user_io:my_user_io|sbuf[1]                 ; user_io:my_user_io|sbuf[2]                                                                              ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.016      ;
; 0.724 ; user_io:my_user_io|sbuf[1]                 ; user_io:my_user_io|cmd[2]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.016      ;
; 0.728 ; osd:osd_inst|bcnt[5]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.477      ; 1.459      ;
; 0.732 ; user_io:my_user_io|sbuf[0]                 ; user_io:my_user_io|cmd[1]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.024      ;
; 0.733 ; osd:osd_inst|sbuf[5]                       ; osd:osd_inst|sbuf[6]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.025      ;
; 0.733 ; osd:osd_inst|sbuf[5]                       ; osd:osd_inst|cmd[6]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.025      ;
; 0.740 ; osd:osd_inst|bcnt[5]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.476      ; 1.470      ;
; 0.741 ; osd:osd_inst|sbuf[4]                       ; osd:osd_inst|sbuf[5]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.033      ;
; 0.741 ; osd:osd_inst|sbuf[4]                       ; osd:osd_inst|cmd[5]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.033      ;
; 0.743 ; osd:osd_inst|sbuf[3]                       ; osd:osd_inst|sbuf[4]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.035      ;
; 0.743 ; osd:osd_inst|sbuf[3]                       ; osd:osd_inst|cmd[4]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.035      ;
; 0.747 ; osd:osd_inst|sbuf[0]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.484      ; 1.485      ;
; 0.749 ; user_io:my_user_io|serial_out_rptr[4]      ; user_io:my_user_io|serial_out_rptr[4]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 1.040      ;
; 0.750 ; user_io:my_user_io|serial_out_rptr[2]      ; user_io:my_user_io|serial_out_rptr[2]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 1.041      ;
; 0.751 ; user_io:my_user_io|serial_out_rptr[5]      ; user_io:my_user_io|serial_out_rptr[5]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 1.042      ;
; 0.752 ; user_io:my_user_io|serial_out_rptr[3]      ; user_io:my_user_io|serial_out_rptr[3]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 1.043      ;
; 0.756 ; user_io:my_user_io|sbuf[0]                 ; user_io:my_user_io|spi_byte_in[1]                                                                       ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.048      ;
; 0.759 ; user_io:my_user_io|sbuf[0]                 ; user_io:my_user_io|sbuf[1]                                                                              ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.051      ;
; 0.761 ; osd:osd_inst|bcnt[7]                       ; osd:osd_inst|bcnt[7]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.053      ;
; 0.762 ; osd:osd_inst|bcnt[1]                       ; osd:osd_inst|bcnt[1]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.054      ;
; 0.762 ; osd:osd_inst|bcnt[9]                       ; osd:osd_inst|bcnt[9]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.054      ;
; 0.762 ; data_io:mist_data_io|bit_cnt[1]            ; data_io:mist_data_io|bit_cnt[2]                                                                         ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 1.053      ;
; 0.764 ; osd:osd_inst|bcnt[2]                       ; osd:osd_inst|bcnt[2]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.056      ;
; 0.764 ; osd:osd_inst|bcnt[5]                       ; osd:osd_inst|bcnt[5]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.056      ;
; 0.765 ; osd:osd_inst|bcnt[8]                       ; osd:osd_inst|bcnt[8]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.057      ;
; 0.766 ; osd:osd_inst|bcnt[6]                       ; osd:osd_inst|bcnt[6]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.058      ;
; 0.767 ; osd:osd_inst|bcnt[1]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.477      ; 1.498      ;
; 0.769 ; osd:osd_inst|bcnt[7]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.476      ; 1.499      ;
; 0.769 ; user_io:my_user_io|serial_out_rptr[0]      ; user_io:my_user_io|serial_out_rptr[1]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 1.060      ;
; 0.770 ; osd:osd_inst|bcnt[9]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.477      ; 1.501      ;
; 0.770 ; user_io:my_user_io|serial_out_rptr[1]      ; user_io:my_user_io|serial_out_rptr[1]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.079      ; 1.061      ;
; 0.771 ; osd:osd_inst|cnt[1]                        ; osd:osd_inst|cnt[1]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.063      ;
; 0.771 ; osd:osd_inst|cnt[3]                        ; osd:osd_inst|cnt[3]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.063      ;
; 0.772 ; user_io:my_user_io|bit_cnt[1]              ; user_io:my_user_io|bit_cnt[2]                                                                           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.064      ;
; 0.773 ; user_io:my_user_io|byte_cnt[3]             ; user_io:my_user_io|byte_cnt[3]                                                                          ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.065      ;
; 0.773 ; user_io:my_user_io|byte_cnt[8]             ; user_io:my_user_io|byte_cnt[8]                                                                          ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.065      ;
; 0.774 ; osd:osd_inst|cnt[2]                        ; osd:osd_inst|cnt[2]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.066      ;
; 0.774 ; user_io:my_user_io|byte_cnt[6]             ; user_io:my_user_io|byte_cnt[6]                                                                          ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.066      ;
; 0.775 ; user_io:my_user_io|byte_cnt[5]             ; user_io:my_user_io|byte_cnt[5]                                                                          ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.067      ;
; 0.775 ; user_io:my_user_io|byte_cnt[7]             ; user_io:my_user_io|byte_cnt[7]                                                                          ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.067      ;
; 0.775 ; user_io:my_user_io|byte_cnt[9]             ; user_io:my_user_io|byte_cnt[9]                                                                          ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.067      ;
; 0.777 ; osd:osd_inst|cnt[4]                        ; osd:osd_inst|cnt[4]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.080      ; 1.069      ;
+-------+--------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                     ; To Node                                                                                                                                                                                                       ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 0.453 ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                                                                                                                   ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                                                                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.454 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_seq_data_state                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_seq_data_state                                       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                              ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; rom_loaded                                                                                                                                                                                                    ; rom_loaded                                                                                                                                                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_data_state                                                ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_data_state                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.466 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reset_state                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reset_state                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.758      ;
; 0.493 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[4] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[4] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.785      ;
; 0.494 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.786      ;
; 0.494 ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[0]                                                                                                                                          ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.786      ;
; 0.502 ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[1]                                                                                                                                          ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[0]                                                                                                                                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.794      ;
; 0.504 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|tmp_seq_ena_state                                             ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_seq_ena_state                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.796      ;
; 0.505 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_init_state_1                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.797      ;
; 0.509 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate_state                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate2_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.801      ;
; 0.510 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[16]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[16]                                                                                                                                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.802      ;
; 0.529 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.821      ;
; 0.544 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[3]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[3]                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.836      ;
; 0.544 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[0]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[0]                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.836      ;
; 0.546 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[6]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[6]                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.838      ;
; 0.557 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 0.850      ;
; 0.559 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 0.852      ;
; 0.561 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|idle_state                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_init_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.853      ;
; 0.564 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|idle_state                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_init_state                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.856      ;
; 0.653 ; switch_pal_ntsc:pll_switcher|pll_reconfig_write_from_rom                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_init_state                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.945      ;
; 0.684 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[7]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[7]                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.976      ;
; 0.684 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[5]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[5]                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.976      ;
; 0.698 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.990      ;
; 0.699 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[2]                                              ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[2]                                             ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.991      ;
; 0.701 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[1]                                              ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[1]                                             ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.992      ;
; 0.721 ; rom_loaded                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|reset_n_reg                                                                                                                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.013      ;
; 0.727 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_init_state                                                ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_first_state                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.019      ;
; 0.727 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate_state                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.019      ;
; 0.736 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.028      ;
; 0.736 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.028      ;
; 0.736 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.028      ;
; 0.737 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[11]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[11]                                                                                                                                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.029      ;
; 0.738 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[9]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[9]                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.030      ;
; 0.738 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[13]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[13]                                                                                                                                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.030      ;
; 0.739 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.031      ;
; 0.739 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[8]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[8]                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.031      ;
; 0.740 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.032      ;
; 0.740 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.032      ;
; 0.740 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[10]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[10]                                                                                                                                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.032      ;
; 0.740 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[14]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[14]                                                                                                                                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.032      ;
; 0.740 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[1]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[1]                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.030      ;
; 0.741 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.033      ;
; 0.741 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[12]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[12]                                                                                                                                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.033      ;
; 0.741 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[15]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[15]                                                                                                                                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.033      ;
; 0.745 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[3] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.037      ;
; 0.746 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[5] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[5] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.038      ;
; 0.746 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[3] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.038      ;
; 0.747 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.039      ;
; 0.747 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[7] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[7] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.039      ;
; 0.747 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.039      ;
; 0.748 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.040      ;
; 0.748 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.040      ;
; 0.748 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.040      ;
; 0.748 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[4] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[4] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.040      ;
; 0.748 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[7] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[7] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.040      ;
; 0.749 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[6] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[6] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.041      ;
; 0.749 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[3] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.041      ;
; 0.749 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.041      ;
; 0.750 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[4] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[4] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.042      ;
; 0.751 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[2] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.043      ;
; 0.761 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.053      ;
; 0.763 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[5] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[5] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.054      ;
; 0.763 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[7] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[7] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.054      ;
; 0.764 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[0]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[0]                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.056      ;
; 0.764 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[5] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[5] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.056      ;
; 0.764 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[3] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.055      ;
; 0.764 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.056      ;
; 0.765 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.056      ;
; 0.765 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_ena_state                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.057      ;
; 0.766 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[2] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.058      ;
; 0.766 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[6] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[6] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.058      ;
; 0.766 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[2] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.057      ;
; 0.771 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.063      ;
; 0.772 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[0] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.064      ;
; 0.773 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[1]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[1]  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.065      ;
; 0.774 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[4]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[4]  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.066      ;
; 0.774 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[0] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.066      ;
; 0.775 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[2]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[2]  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.067      ;
; 0.779 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[5]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[5]  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.071      ;
; 0.780 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[6]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[6]  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.072      ;
; 0.781 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[7]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[7]  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.073      ;
; 0.782 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[3]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[3]  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.074      ;
; 0.787 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_counter_state                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.079      ;
; 0.790 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[0] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.082      ;
; 0.799 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[0]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[0]  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.091      ;
; 0.801 ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.094      ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'clk_27'                                                                                                                                                                ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                 ; To Node                                                   ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 0.746      ;
; 0.467 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 0.758      ;
; 0.748 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.039      ;
; 0.751 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.042      ;
; 0.751 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.042      ;
; 0.940 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.231      ;
; 0.958 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.249      ;
; 0.959 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.250      ;
; 0.960 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.251      ;
; 1.082 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.373      ;
; 1.091 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.382      ;
; 1.097 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.388      ;
; 1.100 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.391      ;
; 1.101 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.392      ;
; 1.102 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.393      ;
; 1.103 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.394      ;
; 1.110 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.401      ;
; 1.112 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.403      ;
; 1.119 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.410      ;
; 1.146 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.437      ;
; 1.151 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.442      ;
; 1.195 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.486      ;
; 1.200 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.491      ;
; 1.232 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.523      ;
; 1.234 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.525      ;
; 1.238 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.529      ;
; 1.243 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.534      ;
; 1.243 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.534      ;
; 1.244 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.535      ;
; 1.245 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.536      ;
; 1.252 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.543      ;
; 1.259 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.550      ;
; 1.261 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.552      ;
; 1.262 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.553      ;
; 1.277 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.568      ;
; 1.278 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.569      ;
; 1.279 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.570      ;
; 1.280 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.571      ;
; 1.281 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.572      ;
; 1.282 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.573      ;
; 1.337 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.628      ;
; 1.384 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.675      ;
; 1.385 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.676      ;
; 1.386 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.677      ;
; 1.402 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.693      ;
; 1.411 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.702      ;
; 1.417 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.708      ;
; 1.420 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.711      ;
; 1.504 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.795      ;
; 1.514 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.805      ;
; 1.517 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.808      ;
; 1.519 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.810      ;
; 1.563 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.854      ;
; 1.564 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.855      ;
; 1.565 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.856      ;
; 1.566 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.857      ;
; 1.567 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.858      ;
; 1.568 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.859      ;
; 1.581 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.872      ;
; 1.584 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.079      ; 1.875      ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                            ;
+-------+---------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                     ; To Node                                                       ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.455 ; sdram_statemachine:sdram_adaptor|reply_reg                    ; sdram_statemachine:sdram_adaptor|reply_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.467 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.758      ;
; 0.492 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.784      ;
; 0.510 ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.801      ;
; 0.687 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.979      ;
; 0.740 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.031      ;
; 0.740 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.031      ;
; 0.740 ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.031      ;
; 0.741 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.032      ;
; 0.741 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.032      ;
; 0.743 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.034      ;
; 0.743 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.034      ;
; 0.746 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.038      ;
; 0.746 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.038      ;
; 0.746 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.038      ;
; 0.748 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.040      ;
; 0.748 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.040      ;
; 0.749 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.041      ;
; 0.750 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.042      ;
; 0.751 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.043      ;
; 0.755 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.047      ;
; 0.755 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.047      ;
; 0.756 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.048      ;
; 0.756 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.048      ;
; 0.756 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.048      ;
; 0.757 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.049      ;
; 0.759 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.051      ;
; 0.764 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.056      ;
; 0.765 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.057      ;
; 0.766 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.058      ;
; 0.767 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.059      ;
; 0.772 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.064      ;
; 0.780 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.071      ;
; 0.780 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.072      ;
; 0.782 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.073      ;
; 0.787 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.078      ;
; 0.788 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.079      ;
; 0.805 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.096      ;
; 0.829 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.120      ;
; 0.857 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.148      ;
; 1.071 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.362      ;
; 1.094 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.385      ;
; 1.095 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.386      ;
; 1.095 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.386      ;
; 1.101 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.393      ;
; 1.101 ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.392      ;
; 1.101 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.393      ;
; 1.101 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.393      ;
; 1.101 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.392      ;
; 1.102 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.394      ;
; 1.102 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.394      ;
; 1.104 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.395      ;
; 1.104 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.395      ;
; 1.108 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.400      ;
; 1.109 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.401      ;
; 1.110 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.402      ;
; 1.110 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.402      ;
; 1.110 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.402      ;
; 1.110 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.401      ;
; 1.111 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.403      ;
; 1.111 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.403      ;
; 1.112 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.404      ;
; 1.113 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.404      ;
; 1.113 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.404      ;
; 1.118 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.410      ;
; 1.118 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.410      ;
; 1.118 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.410      ;
; 1.119 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.411      ;
; 1.119 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.411      ;
; 1.119 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.411      ;
; 1.119 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.411      ;
; 1.120 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.412      ;
; 1.121 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.413      ;
; 1.127 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.419      ;
; 1.127 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.419      ;
; 1.127 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.419      ;
; 1.127 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.419      ;
; 1.127 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.419      ;
; 1.128 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.420      ;
; 1.128 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.420      ;
; 1.135 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.426      ;
; 1.136 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.428      ;
; 1.137 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.429      ;
; 1.141 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.432      ;
; 1.143 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.434      ;
; 1.144 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.435      ;
; 1.149 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.440      ;
; 1.152 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.443      ;
; 1.158 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.449      ;
; 1.159 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.450      ;
; 1.167 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.458      ;
; 1.176 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.467      ;
; 1.225 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.516      ;
; 1.226 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.517      ;
; 1.226 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.517      ;
; 1.232 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.524      ;
; 1.232 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.524      ;
; 1.233 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.525      ;
; 1.233 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.525      ;
+-------+---------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                  ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 2.208 ; sdram_statemachine:sdram_adaptor|cke_reg                                    ; SDRAM_CKE                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.231      ; 2.902      ;
; 2.583 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8                 ; SDRAM_DQ[8]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.318      ; 3.364      ;
; 2.583 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9                 ; SDRAM_DQ[9]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.318      ; 3.364      ;
; 2.586 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1                 ; SDRAM_DQ[1]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.325      ; 3.374      ;
; 2.590 ; sdram_statemachine:sdram_adaptor|dq_output_reg                              ; SDRAM_DQ[0]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.321      ; 3.374      ;
; 2.600 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12                ; SDRAM_DQ[12]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.311      ; 3.374      ;
; 2.600 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13                ; SDRAM_DQ[13]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.311      ; 3.374      ;
; 2.601 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11                ; SDRAM_DQ[11]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.310      ; 3.374      ;
; 2.601 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10                ; SDRAM_DQ[10]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.310      ; 3.374      ;
; 2.608 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14                ; SDRAM_DQ[14]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.313      ; 3.384      ;
; 2.608 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15                ; SDRAM_DQ[15]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.313      ; 3.384      ;
; 2.616 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3                 ; SDRAM_DQ[3]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.305      ; 3.384      ;
; 2.616 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2                 ; SDRAM_DQ[2]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.305      ; 3.384      ;
; 2.617 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_7                 ; SDRAM_DQ[7]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.259      ; 3.339      ;
; 2.618 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4                 ; SDRAM_DQ[4]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.258      ; 3.339      ;
; 2.618 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_6                 ; SDRAM_DQ[6]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.258      ; 3.339      ;
; 2.628 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_5                 ; SDRAM_DQ[5]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.258      ; 3.349      ;
; 2.893 ; sdram_statemachine:sdram_adaptor|ba_reg[1]                                  ; SDRAM_BA[1]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.245      ; 3.601      ;
; 2.901 ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]                             ; SDRAM_DQ[12]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.295      ; 3.659      ;
; 2.903 ; sdram_statemachine:sdram_adaptor|addr_reg[0]                                ; SDRAM_A[0]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.245      ; 3.611      ;
; 2.903 ; sdram_statemachine:sdram_adaptor|addr_reg[10]                               ; SDRAM_A[10]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.245      ; 3.611      ;
; 2.903 ; sdram_statemachine:sdram_adaptor|ba_reg[0]                                  ; SDRAM_BA[0]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.245      ; 3.611      ;
; 2.903 ; sdram_statemachine:sdram_adaptor|ras_n_reg                                  ; SDRAM_nRAS                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.245      ; 3.611      ;
; 2.903 ; sdram_statemachine:sdram_adaptor|cas_n_reg                                  ; SDRAM_nCAS                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.245      ; 3.611      ;
; 2.905 ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                ; SDRAM_A[1]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.243      ; 3.611      ;
; 2.905 ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                ; SDRAM_A[2]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.243      ; 3.611      ;
; 2.909 ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                             ; SDRAM_DQ[15]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.297      ; 3.669      ;
; 2.915 ; sdram_statemachine:sdram_adaptor|we_n_reg                                   ; SDRAM_nWE                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.243      ; 3.621      ;
; 2.915 ; sdram_statemachine:sdram_adaptor|ldqm_reg                                   ; SDRAM_DQML                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.243      ; 3.621      ;
; 2.915 ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                              ; SDRAM_DQ[7]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.243      ; 3.621      ;
; 2.916 ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                ; SDRAM_A[3]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.242      ; 3.621      ;
; 2.916 ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]                              ; SDRAM_DQ[4]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.242      ; 3.621      ;
; 2.916 ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                              ; SDRAM_DQ[6]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.242      ; 3.621      ;
; 2.917 ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                              ; SDRAM_DQ[3]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.289      ; 3.669      ;
; 2.917 ; sdram_statemachine:sdram_adaptor|dq_out_reg[2]                              ; SDRAM_DQ[2]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.289      ; 3.669      ;
; 2.920 ; sdram_statemachine:sdram_adaptor|addr_reg[4]                                ; SDRAM_A[4]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.286      ; 3.669      ;
; 2.926 ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]                              ; SDRAM_DQ[5]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.242      ; 3.631      ;
; 3.029 ; sdram_statemachine:sdram_adaptor|udqm_reg                                   ; SDRAM_DQMH                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.303      ; 3.795      ;
; 3.030 ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]                              ; SDRAM_DQ[8]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.302      ; 3.795      ;
; 3.030 ; sdram_statemachine:sdram_adaptor|dq_out_reg[9]                              ; SDRAM_DQ[9]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.302      ; 3.795      ;
; 3.033 ; sdram_statemachine:sdram_adaptor|dq_out_reg[1]                              ; SDRAM_DQ[1]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.309      ; 3.805      ;
; 3.037 ; sdram_statemachine:sdram_adaptor|dq_out_reg[0]                              ; SDRAM_DQ[0]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.305      ; 3.805      ;
; 3.047 ; sdram_statemachine:sdram_adaptor|dq_out_reg[13]                             ; SDRAM_DQ[13]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.295      ; 3.805      ;
; 3.048 ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]                             ; SDRAM_DQ[11]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.294      ; 3.805      ;
; 3.048 ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                             ; SDRAM_DQ[10]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.294      ; 3.805      ;
; 3.049 ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                ; SDRAM_A[6]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.293      ; 3.805      ;
; 3.051 ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                ; SDRAM_A[9]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.291      ; 3.805      ;
; 3.053 ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                ; SDRAM_A[7]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.289      ; 3.805      ;
; 3.053 ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                ; SDRAM_A[8]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.289      ; 3.805      ;
; 3.055 ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                             ; SDRAM_DQ[14]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.297      ; 3.815      ;
; 3.057 ; sdram_statemachine:sdram_adaptor|addr_reg[11]                               ; SDRAM_A[11]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.295      ; 3.815      ;
; 3.064 ; sdram_statemachine:sdram_adaptor|addr_reg[5]                                ; SDRAM_A[5]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.288      ; 3.815      ;
; 9.468 ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -6.853       ; -1.748     ; 1.078      ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                ;
+-------+------------------------------------------------------------------------+--------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                              ; To Node                                                      ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------+--------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 2.684 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[0]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.384     ; 5.601      ;
; 2.691 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.321     ; 5.657      ;
; 2.691 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[7]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.322     ; 5.656      ;
; 2.691 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.321     ; 5.657      ;
; 2.692 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.321     ; 5.656      ;
; 2.694 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[9]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.381     ; 5.594      ;
; 2.694 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[8]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.381     ; 5.594      ;
; 2.705 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.243     ; 5.733      ;
; 2.707 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[1]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.388     ; 5.574      ;
; 2.713 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[14]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.376     ; 5.580      ;
; 2.713 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[15]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.376     ; 5.580      ;
; 2.714 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[11]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.373     ; 5.582      ;
; 2.714 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[13]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.374     ; 5.581      ;
; 2.714 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[12]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.374     ; 5.581      ;
; 2.714 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.368     ; 5.587      ;
; 2.714 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[10]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.373     ; 5.582      ;
; 2.714 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[3]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.368     ; 5.587      ;
; 2.716 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|udqm_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.255     ; 5.710      ;
; 2.717 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[0]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.257     ; 5.707      ;
; 2.717 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.240     ; 5.724      ;
; 2.717 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.245     ; 5.719      ;
; 2.717 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.247     ; 5.717      ;
; 2.724 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.194     ; 5.763      ;
; 2.724 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.194     ; 5.763      ;
; 2.724 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.195     ; 5.762      ;
; 2.724 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.241     ; 5.716      ;
; 2.724 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.241     ; 5.716      ;
; 2.725 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.194     ; 5.762      ;
; 2.725 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ba_reg[0]                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.197     ; 5.759      ;
; 2.725 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ba_reg[1]                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.197     ; 5.759      ;
; 2.725 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ras_n_reg                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.197     ; 5.759      ;
; 2.725 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cas_n_reg                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.197     ; 5.759      ;
; 2.725 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|we_n_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.195     ; 5.761      ;
; 2.725 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ldqm_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.195     ; 5.761      ;
; 2.725 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[0]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.197     ; 5.759      ;
; 2.725 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.195     ; 5.761      ;
; 2.725 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.195     ; 5.761      ;
; 2.725 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.194     ; 5.762      ;
; 2.725 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.197     ; 5.759      ;
; 2.727 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.254     ; 5.700      ;
; 2.727 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[9]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.254     ; 5.700      ;
; 2.735 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.238     ; 5.708      ;
; 2.740 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[1]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.261     ; 5.680      ;
; 2.746 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.249     ; 5.686      ;
; 2.746 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.249     ; 5.686      ;
; 2.747 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[2]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.241     ; 5.693      ;
; 2.747 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.241     ; 5.693      ;
; 2.747 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.246     ; 5.688      ;
; 2.747 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.246     ; 5.688      ;
; 2.747 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.247     ; 5.687      ;
; 2.747 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[13]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.247     ; 5.687      ;
; 2.919 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.273     ; 5.453      ;
; 2.926 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.210     ; 5.509      ;
; 2.926 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_5  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.210     ; 5.509      ;
; 2.926 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_7  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.211     ; 5.508      ;
; 2.927 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_6  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.210     ; 5.508      ;
; 2.929 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.270     ; 5.446      ;
; 2.929 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.270     ; 5.446      ;
; 2.942 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.277     ; 5.426      ;
; 2.948 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.265     ; 5.432      ;
; 2.948 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.265     ; 5.432      ;
; 2.949 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.257     ; 5.439      ;
; 2.949 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.257     ; 5.439      ;
; 2.949 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.262     ; 5.434      ;
; 2.949 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.262     ; 5.434      ;
; 2.949 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.263     ; 5.433      ;
; 2.949 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.263     ; 5.433      ;
; 3.244 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[31]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.195     ; 5.372      ;
; 3.244 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[8]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.195     ; 5.372      ;
; 3.244 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[23]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.195     ; 5.372      ;
; 3.244 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[15]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.195     ; 5.372      ;
; 3.244 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[19]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.195     ; 5.372      ;
; 3.244 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[24]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.195     ; 5.372      ;
; 3.244 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[16]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.195     ; 5.372      ;
; 3.245 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[5]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.201     ; 5.365      ;
; 3.245 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[7]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.201     ; 5.365      ;
; 3.245 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[4]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.201     ; 5.365      ;
; 3.245 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[6]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.201     ; 5.365      ;
; 3.245 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[1]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.201     ; 5.365      ;
; 3.245 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[2]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.201     ; 5.365      ;
; 3.245 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[3]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.201     ; 5.365      ;
; 3.245 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[0]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.201     ; 5.365      ;
; 3.246 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[25]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.192     ; 5.373      ;
; 3.246 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[27]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.192     ; 5.373      ;
; 3.246 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[30]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.192     ; 5.373      ;
; 3.246 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[29]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.192     ; 5.373      ;
; 3.246 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[28]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.192     ; 5.373      ;
; 3.246 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[9]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.192     ; 5.373      ;
; 3.246 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[11]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.192     ; 5.373      ;
; 3.246 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[13]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.192     ; 5.373      ;
; 3.246 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[22]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.192     ; 5.373      ;
; 3.246 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[14]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.192     ; 5.373      ;
; 3.246 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[12]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.192     ; 5.373      ;
; 3.246 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[26]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.192     ; 5.373      ;
; 3.246 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[17]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.192     ; 5.373      ;
; 3.246 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[21]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.192     ; 5.373      ;
; 3.246 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[10]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.192     ; 5.373      ;
; 3.246 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[18]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.192     ; 5.373      ;
; 3.246 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[20]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.192     ; 5.373      ;
; 3.247 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.198     ; 5.366      ;
+-------+------------------------------------------------------------------------+--------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                 ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                              ; To Node                                                                                                                                                                                                       ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 9.374 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[28]                                                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.192     ; 8.056      ;
; 9.374 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[26]                                                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.192     ; 8.056      ;
; 9.374 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[16]                                                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.192     ; 8.056      ;
; 9.374 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[18]                                                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.192     ; 8.056      ;
; 9.379 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[0]                                                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.178     ; 8.065      ;
; 9.379 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg~_Duplicate_3                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.178     ; 8.065      ;
; 9.403 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[1]                                                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.176     ; 8.043      ;
; 9.415 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.185     ; 8.022      ;
; 9.415 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.185     ; 8.022      ;
; 9.422 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg~_Duplicate_1                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.185     ; 8.015      ;
; 9.422 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]                                                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.185     ; 8.015      ;
; 9.422 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]~_Duplicate_8                                                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.185     ; 8.015      ;
; 9.422 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[5]~_Duplicate_4                                                                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.185     ; 8.015      ;
; 9.447 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[2]~_Duplicate_1                                                                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.159     ; 8.016      ;
; 9.466 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[7]                                                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.191     ; 7.965      ;
; 9.518 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|compare_latch_reg[5]                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.190     ; 7.914      ;
; 9.518 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|keycode_latch_reg[5]                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.190     ; 7.914      ;
; 9.518 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|keycode_latch_reg[6]                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.190     ; 7.914      ;
; 9.518 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|compare_latch_reg[4]                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.190     ; 7.914      ;
; 9.518 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|keycode_latch_reg[4]                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.190     ; 7.914      ;
; 9.518 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|compare_latch_reg[0]                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.190     ; 7.914      ;
; 9.518 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|compare_latch_reg[2]                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.190     ; 7.914      ;
; 9.518 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|compare_latch_reg[3]                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.190     ; 7.914      ;
; 9.518 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|compare_latch_reg[1]                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.190     ; 7.914      ;
; 9.518 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|keycode_latch_reg[3]                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.190     ; 7.914      ;
; 9.518 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|keycode_latch_reg[0]                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.190     ; 7.914      ;
; 9.519 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[6]                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.188     ; 7.915      ;
; 9.519 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[2]                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.188     ; 7.915      ;
; 9.519 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[2]                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.188     ; 7.915      ;
; 9.519 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[3]                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.188     ; 7.915      ;
; 9.519 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[3]                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.188     ; 7.915      ;
; 9.519 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[5]                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.188     ; 7.915      ;
; 9.519 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[5]                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.188     ; 7.915      ;
; 9.519 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[7]                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.188     ; 7.915      ;
; 9.519 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[7]                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.188     ; 7.915      ;
; 9.519 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|cntr_g7h:cntr5|counter_reg_bit[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.194     ; 7.909      ;
; 9.519 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[4]                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.188     ; 7.915      ;
; 9.520 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|last_bus_reg[0]                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.202     ; 7.900      ;
; 9.525 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|serin_bitcount_reg[0]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.190     ; 7.907      ;
; 9.525 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|serin_bitcount_reg[2]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.190     ; 7.907      ;
; 9.525 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|serin_bitcount_reg[1]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.190     ; 7.907      ;
; 9.525 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|serin_bitcount_reg[3]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.190     ; 7.907      ;
; 9.525 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vscrol_raw_reg[0]                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.184     ; 7.913      ;
; 9.525 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vscrol_raw_reg[1]                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.184     ; 7.913      ;
; 9.525 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|last_bus_reg[7]                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.190     ; 7.907      ;
; 9.525 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pot0_reg[5]                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.188     ; 7.909      ;
; 9.525 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|serin_reg[5]                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.188     ; 7.909      ;
; 9.525 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vscrol_raw_reg[2]                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.184     ; 7.913      ;
; 9.525 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|serin_reg[4]                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.188     ; 7.909      ;
; 9.525 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pot0_reg[4]                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.188     ; 7.909      ;
; 9.525 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|keycode_latch_reg[1]                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.194     ; 7.903      ;
; 9.525 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pot0_reg[1]                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.194     ; 7.903      ;
; 9.525 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vscrol_raw_reg[3]                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.184     ; 7.913      ;
; 9.525 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|shift_reg[1][6]                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.184     ; 7.913      ;
; 9.525 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|shift_reg[0][6]                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.184     ; 7.913      ;
; 9.525 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|count_reg[0]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.184     ; 7.913      ;
; 9.525 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|shift_reg[1][7]                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.184     ; 7.913      ;
; 9.525 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|shift_reg[0][7]                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.184     ; 7.913      ;
; 9.525 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|count_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.184     ; 7.913      ;
; 9.525 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.184     ; 7.913      ;
; 9.525 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pf_reg[1]                                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.185     ; 7.912      ;
; 9.525 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p3pf_reg[1]                                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.185     ; 7.912      ;
; 9.525 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pl_reg[3]                                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.185     ; 7.912      ;
; 9.525 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pl_reg[1]                                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.185     ; 7.912      ;
; 9.525 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pl_reg[1]                                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.185     ; 7.912      ;
; 9.525 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pl_reg[1]                                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.185     ; 7.912      ;
; 9.525 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pf_reg[1]                                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.185     ; 7.912      ;
; 9.525 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pl_reg[1]                                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.185     ; 7.912      ;
; 9.525 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|shift_reg[1][2]                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.184     ; 7.913      ;
; 9.525 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|shift_reg[0][2]                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.184     ; 7.913      ;
; 9.525 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|count_reg[0]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.184     ; 7.913      ;
; 9.525 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|shift_reg[1][3]                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.184     ; 7.913      ;
; 9.525 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|shift_reg[0][3]                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.184     ; 7.913      ;
; 9.525 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|count_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.184     ; 7.913      ;
; 9.525 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|shift_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.184     ; 7.913      ;
; 9.525 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|keycode_latch_reg[2]                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.194     ; 7.903      ;
; 9.525 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pot0_reg[2]                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.194     ; 7.903      ;
; 9.525 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pl_reg[3]                                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.185     ; 7.912      ;
; 9.525 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|serin_reg[3]                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.188     ; 7.909      ;
; 9.525 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pot0_reg[3]                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.188     ; 7.909      ;
; 9.525 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpm0_raw_reg[7]                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.183     ; 7.914      ;
; 9.525 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpf2_snap_reg[6]                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.183     ; 7.914      ;
; 9.525 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpm0_raw_reg[6]                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.183     ; 7.914      ;
; 9.525 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpm0_snap_reg[6]                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.183     ; 7.914      ;
; 9.525 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpf2_snap_reg[5]                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.183     ; 7.914      ;
; 9.525 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpm0_raw_reg[5]                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.183     ; 7.914      ;
; 9.525 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpm0_snap_reg[5]                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.183     ; 7.914      ;
; 9.525 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpm0_raw_reg[4]                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.183     ; 7.914      ;
; 9.525 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpm0_snap_reg[4]                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.183     ; 7.914      ;
; 9.525 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpm0_raw_reg[3]                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.183     ; 7.914      ;
; 9.525 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpm0_raw_reg[1]                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.183     ; 7.914      ;
; 9.526 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[13]                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.189     ; 7.907      ;
; 9.526 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|skctl_reg[2]                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.187     ; 7.909      ;
; 9.526 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|allpot_reg[7]                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.193     ; 7.903      ;
; 9.526 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|serin_shift_reg[9]                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.189     ; 7.907      ;
; 9.526 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|serin_shift_reg[8]                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.189     ; 7.907      ;
; 9.526 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|serin_shift_reg[7]                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.189     ; 7.907      ;
; 9.526 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_poly_17_9:poly_17_19_lfsr|select_9_17_del_reg                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.189     ; 7.907      ;
; 9.526 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[7]                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.189     ; 7.907      ;
; 9.526 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[6]                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.189     ; 7.907      ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                         ; To Node                                                                                                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 1.592 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|dffe4                                                                 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|altsyncram_14b1:altsyncram2|ram_block5a0                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.428      ; 2.231      ;
; 2.212 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a59 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.400      ; 2.823      ;
; 2.212 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a58 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.400      ; 2.823      ;
; 2.212 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a57 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.400      ; 2.823      ;
; 2.212 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a56 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.400      ; 2.823      ;
; 2.212 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a55 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.400      ; 2.823      ;
; 2.212 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a54 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.400      ; 2.823      ;
; 2.212 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a53 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.400      ; 2.823      ;
; 2.212 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a52 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.400      ; 2.823      ;
; 2.212 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a51 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.400      ; 2.823      ;
; 2.212 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a50 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.400      ; 2.823      ;
; 2.212 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a49 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.400      ; 2.823      ;
; 2.212 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a48 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.400      ; 2.823      ;
; 2.212 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a31 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.400      ; 2.823      ;
; 2.212 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a30 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.400      ; 2.823      ;
; 2.212 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a29 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.400      ; 2.823      ;
; 2.212 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a28 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.400      ; 2.823      ;
; 2.212 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a27 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.400      ; 2.823      ;
; 2.212 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a26 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.400      ; 2.823      ;
; 2.212 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a25 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.400      ; 2.823      ;
; 2.212 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a24 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.400      ; 2.823      ;
; 2.212 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a23 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.400      ; 2.823      ;
; 2.212 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a22 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.400      ; 2.823      ;
; 2.212 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a21 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.400      ; 2.823      ;
; 2.212 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a20 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.400      ; 2.823      ;
; 2.212 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a19 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.400      ; 2.823      ;
; 2.212 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a18 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.400      ; 2.823      ;
; 2.212 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a17 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.400      ; 2.823      ;
; 2.212 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.400      ; 2.823      ;
; 2.559 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a63 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 3.166      ;
; 2.559 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a62 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 3.166      ;
; 2.559 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a61 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 3.166      ;
; 2.559 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a60 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 3.166      ;
; 2.559 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a47 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 3.166      ;
; 2.559 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a46 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 3.166      ;
; 2.559 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a45 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 3.166      ;
; 2.559 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a44 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 3.166      ;
; 2.559 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a43 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 3.166      ;
; 2.559 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a42 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 3.166      ;
; 2.559 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a41 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 3.166      ;
; 2.559 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a40 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 3.166      ;
; 2.559 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a39 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 3.166      ;
; 2.559 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a38 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 3.166      ;
; 2.559 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a37 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 3.166      ;
; 2.559 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a36 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 3.166      ;
; 2.559 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a35 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 3.166      ;
; 2.559 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a34 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 3.166      ;
; 2.559 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a33 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 3.166      ;
; 2.559 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a32 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 3.166      ;
; 2.559 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a15 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 3.166      ;
; 2.559 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a14 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 3.166      ;
; 2.559 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a13 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 3.166      ;
; 2.559 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a12 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 3.166      ;
; 2.559 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a11 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 3.166      ;
; 2.559 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a10 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 3.166      ;
; 2.559 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a9  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 3.166      ;
; 2.559 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a8  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 3.166      ;
; 2.559 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a7  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 3.166      ;
; 2.559 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a6  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 3.166      ;
; 2.559 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a5  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 3.166      ;
; 2.559 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a4  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 3.166      ;
; 2.559 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a3  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 3.166      ;
; 2.559 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a2  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 3.166      ;
; 2.559 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a1  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 3.166      ;
; 2.559 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 3.166      ;
; 4.019 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ioctl_state.IOCTL_IDLE~_Duplicate_7                                                                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.648      ; 4.879      ;
; 4.019 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|refresh_sreg                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.648      ; 4.879      ;
; 4.022 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ioctl_state.IOCTL_IDLE~_Duplicate_5                                                                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.661      ; 4.895      ;
; 4.393 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ioctl_state.IOCTL_IDLE~_Duplicate_3                                                                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.696      ; 5.301      ;
; 4.463 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[20]                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.211      ; 4.886      ;
; 4.465 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p1[13]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.202      ; 4.879      ;
; 4.465 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p1[14]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.202      ; 4.879      ;
; 4.465 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p1[15]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.202      ; 4.879      ;
; 4.465 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p1[16]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.202      ; 4.879      ;
; 4.465 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p1[17]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.202      ; 4.879      ;
; 4.465 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p1[18]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.202      ; 4.879      ;
; 4.465 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p2[15]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 4.878      ;
; 4.465 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p1[19]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.202      ; 4.879      ;
; 4.465 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p2[16]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 4.878      ;
; 4.465 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p1[20]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.202      ; 4.879      ;
; 4.465 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p2[17]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 4.878      ;
; 4.465 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p1[21]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.202      ; 4.879      ;
; 4.465 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p2[18]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 4.878      ;
; 4.465 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p1[22]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.202      ; 4.879      ;
; 4.465 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p2[19]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 4.878      ;
; 4.465 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p1[23]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.202      ; 4.879      ;
; 4.465 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p2[20]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 4.878      ;
; 4.465 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p2[21]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 4.878      ;
; 4.465 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p2[22]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 4.878      ;
; 4.465 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p2[14]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 4.878      ;
; 4.465 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p2[13]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 4.878      ;
; 4.465 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p2[12]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 4.878      ;
; 4.465 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p2[23]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 4.878      ;
; 4.465 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|ADDRESS_IN_sreg[13]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.206      ; 4.883      ;
; 4.465 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|ADDRESS_IN_sreg[21]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.206      ; 4.883      ;
; 4.466 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_lpf_p2[14]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 4.879      ;
; 4.466 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_lpf_p2[15]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 4.879      ;
; 4.466 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_lpf_p2[16]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 4.879      ;
; 4.466 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_lpf_p2[17]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 4.879      ;
; 4.466 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_lpf_p2[18]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 4.879      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                  ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                              ; To Node                                                       ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 4.459 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.197      ; 4.887      ;
; 4.459 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.197      ; 4.887      ;
; 4.459 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.197      ; 4.887      ;
; 4.459 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.197      ; 4.887      ;
; 4.459 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.197      ; 4.887      ;
; 4.459 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.197      ; 4.887      ;
; 4.459 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.197      ; 4.887      ;
; 4.459 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.197      ; 4.887      ;
; 4.459 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.197      ; 4.887      ;
; 4.459 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.197      ; 4.887      ;
; 4.459 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.197      ; 4.887      ;
; 4.459 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cke_reg                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.201      ; 4.891      ;
; 4.462 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.206      ; 4.899      ;
; 4.462 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.206      ; 4.899      ;
; 4.462 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.206      ; 4.899      ;
; 4.462 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.206      ; 4.899      ;
; 4.462 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.206      ; 4.899      ;
; 4.462 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.206      ; 4.899      ;
; 4.462 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.206      ; 4.899      ;
; 4.462 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.206      ; 4.899      ;
; 4.462 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.206      ; 4.899      ;
; 4.462 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.206      ; 4.899      ;
; 4.462 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.206      ; 4.899      ;
; 4.462 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.206      ; 4.899      ;
; 4.481 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[25]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.193      ; 4.905      ;
; 4.482 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.187      ; 4.900      ;
; 4.482 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.187      ; 4.900      ;
; 4.482 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.187      ; 4.900      ;
; 4.482 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.187      ; 4.900      ;
; 4.482 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.187      ; 4.900      ;
; 4.482 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.186      ; 4.899      ;
; 4.482 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[27]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.192      ; 4.905      ;
; 4.482 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[30]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.192      ; 4.905      ;
; 4.482 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[29]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.192      ; 4.905      ;
; 4.482 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[28]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.192      ; 4.905      ;
; 4.482 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[31]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.190      ; 4.903      ;
; 4.482 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[9]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.192      ; 4.905      ;
; 4.482 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[11]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.192      ; 4.905      ;
; 4.482 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[8]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.190      ; 4.903      ;
; 4.482 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[23]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.190      ; 4.903      ;
; 4.482 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[13]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.192      ; 4.905      ;
; 4.482 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[15]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.190      ; 4.903      ;
; 4.482 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[22]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.192      ; 4.905      ;
; 4.482 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[14]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.192      ; 4.905      ;
; 4.482 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[12]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.192      ; 4.905      ;
; 4.482 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[26]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.192      ; 4.905      ;
; 4.482 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[19]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.190      ; 4.903      ;
; 4.482 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[17]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.192      ; 4.905      ;
; 4.482 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[21]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.192      ; 4.905      ;
; 4.482 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[24]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.190      ; 4.903      ;
; 4.482 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[16]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.190      ; 4.903      ;
; 4.482 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[10]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.192      ; 4.905      ;
; 4.482 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[18]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.192      ; 4.905      ;
; 4.482 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[20]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.192      ; 4.905      ;
; 4.482 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.186      ; 4.899      ;
; 4.482 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.187      ; 4.900      ;
; 4.482 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.187      ; 4.900      ;
; 4.482 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.187      ; 4.900      ;
; 4.482 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.187      ; 4.900      ;
; 4.482 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.187      ; 4.900      ;
; 4.482 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.187      ; 4.900      ;
; 4.482 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.187      ; 4.900      ;
; 4.482 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.187      ; 4.900      ;
; 4.482 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.187      ; 4.900      ;
; 4.482 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.186      ; 4.899      ;
; 4.483 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[5]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.183      ; 4.897      ;
; 4.483 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[7]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.183      ; 4.897      ;
; 4.483 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[4]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.183      ; 4.897      ;
; 4.483 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[6]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.183      ; 4.897      ;
; 4.483 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[1]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.183      ; 4.897      ;
; 4.483 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[2]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.183      ; 4.897      ;
; 4.483 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[3]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.183      ; 4.897      ;
; 4.483 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[0]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.183      ; 4.897      ;
; 4.483 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|reply_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.182      ; 4.896      ;
; 4.668 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 5.011      ;
; 4.668 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_5   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 5.011      ;
; 4.668 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_6   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 5.010      ;
; 4.669 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_7   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 5.010      ;
; 4.693 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.125      ; 4.981      ;
; 4.693 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.125      ; 4.981      ;
; 4.693 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.122      ; 4.978      ;
; 4.693 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.122      ; 4.978      ;
; 4.694 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.123      ; 4.980      ;
; 4.694 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.123      ; 4.980      ;
; 4.698 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.131      ; 4.992      ;
; 4.698 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.131      ; 4.992      ;
; 4.700 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.110      ; 4.973      ;
; 4.717 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.117      ; 4.997      ;
; 4.717 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.117      ; 4.997      ;
; 4.736 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.113      ; 5.012      ;
; 5.025 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.196      ; 5.366      ;
; 5.025 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.196      ; 5.366      ;
; 5.025 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.195      ; 5.365      ;
; 5.025 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ba_reg[0]                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.192      ; 5.362      ;
; 5.025 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|we_n_reg                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.194      ; 5.364      ;
; 5.025 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ldqm_reg                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.194      ; 5.364      ;
; 5.025 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[0]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.192      ; 5.362      ;
; 5.025 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[1]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.194      ; 5.364      ;
; 5.025 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[3]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.195      ; 5.365      ;
; 5.026 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.194      ; 5.365      ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                            ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                 ; Clock Edge ; Target                                                        ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------+
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cke_reg                      ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[25]             ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|reply_reg                    ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[10]             ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[11]             ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[12]             ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[13]             ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[14]             ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[15]             ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[16]             ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[17]             ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[18]             ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[19]             ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[20]             ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[21]             ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[22]             ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[23]             ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[24]             ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[26]             ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[27]             ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[28]             ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[29]             ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[30]             ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[31]             ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[8]              ;
; 4.095 ; 4.315        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[9]              ;
; 4.096 ; 4.316        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[0]              ;
; 4.096 ; 4.316        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[1]              ;
; 4.096 ; 4.316        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[2]              ;
; 4.096 ; 4.316        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[3]              ;
; 4.096 ; 4.316        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[4]              ;
; 4.096 ; 4.316        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[5]              ;
; 4.096 ; 4.316        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[6]              ;
; 4.096 ; 4.316        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[7]              ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ;
; 4.200 ; 4.358        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[2]                 ;
; 4.200 ; 4.358        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[3]                 ;
; 4.200 ; 4.358        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2   ;
; 4.200 ; 4.358        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3   ;
; 4.204 ; 4.362        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[1]                 ;
; 4.204 ; 4.362        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1   ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[10]                ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[11]                ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[12]                ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[13]                ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[8]                 ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[9]                 ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10  ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11  ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12  ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13  ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8   ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9   ;
; 4.206 ; 4.359        ; 0.153          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[11]                 ;
; 4.206 ; 4.359        ; 0.153          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[5]                  ;
; 4.206 ; 4.359        ; 0.153          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[7]                  ;
; 4.206 ; 4.359        ; 0.153          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[8]                  ;
; 4.206 ; 4.364        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[4]                 ;
; 4.206 ; 4.364        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[5]                 ;
; 4.206 ; 4.364        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[7]                 ;
; 4.206 ; 4.364        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4   ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                    ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                 ; Clock Edge ; Target                                                                                                                                ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+
; 4.194 ; 4.194        ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK                                                                                                                             ;
; 4.194 ; 4.194        ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK~output|o                                                                                                                    ;
; 4.224 ; 4.368        ; 0.144          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 4.313 ; 4.313        ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK~output|i                                                                                                                    ;
; 4.316 ; 4.440        ; 0.124          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 4.329 ; 8.810        ; 4.481          ; Port Rate        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK                                                                                                                             ;
; 4.368 ; 4.368        ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 4.368 ; 4.368        ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|outclk                                                 ;
; 4.440 ; 4.440        ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 4.440 ; 4.440        ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|outclk                                                 ;
; 4.493 ; 4.493        ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK~output|i                                                                                                                    ;
; 4.612 ; 4.612        ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK                                                                                                                             ;
; 4.612 ; 4.612        ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK~output|o                                                                                                                    ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                        ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                 ; Clock Edge ; Target                                                                                                                                                    ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; 8.379 ; 8.780        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[0] ;
; 8.379 ; 8.780        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[1] ;
; 8.379 ; 8.780        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[2] ;
; 8.379 ; 8.780        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[3] ;
; 8.379 ; 8.780        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[4] ;
; 8.379 ; 8.780        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[10]      ;
; 8.379 ; 8.780        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[11]      ;
; 8.379 ; 8.780        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[12]      ;
; 8.379 ; 8.780        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[13]      ;
; 8.379 ; 8.780        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[14]      ;
; 8.379 ; 8.780        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[15]      ;
; 8.379 ; 8.780        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[16]      ;
; 8.379 ; 8.780        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[17]      ;
; 8.379 ; 8.780        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[18]      ;
; 8.379 ; 8.780        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[19]      ;
; 8.379 ; 8.780        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[20]      ;
; 8.379 ; 8.780        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[5]       ;
; 8.379 ; 8.780        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[6]       ;
; 8.379 ; 8.780        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[7]       ;
; 8.379 ; 8.780        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[8]       ;
; 8.379 ; 8.780        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[9]       ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[0] ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[1] ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[2] ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[3] ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[4] ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[10]      ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[11]      ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[12]      ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[13]      ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[14]      ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[15]      ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[16]      ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[17]      ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[18]      ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[19]      ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[20]      ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[5]       ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[6]       ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[7]       ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[8]       ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[9]       ;
; 8.471 ; 8.691        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[0]                                                                                      ;
; 8.471 ; 8.691        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[10]                                                                                     ;
; 8.471 ; 8.691        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[11]                                                                                     ;
; 8.471 ; 8.691        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[12]                                                                                     ;
; 8.471 ; 8.691        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[15]                                                                                     ;
; 8.471 ; 8.691        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[17]                                                                                     ;
; 8.471 ; 8.691        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[1]                                                                                      ;
; 8.471 ; 8.691        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[5]                                                                                      ;
; 8.471 ; 8.691        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[6]                                                                                      ;
; 8.471 ; 8.691        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[7]                                                                                      ;
; 8.474 ; 8.694        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[5]                                                           ;
; 8.474 ; 8.694        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; data_io:mist_data_io|ioctl_wr                                                                                                                             ;
; 8.475 ; 8.695        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[15]                                                                     ;
; 8.477 ; 8.697        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_READ_reg~_Duplicate_1                                                                                               ;
; 8.479 ; 8.699        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_reg[6]                                                     ;
; 8.479 ; 8.699        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_reg[7]                                                     ;
; 8.480 ; 8.700        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[0]                                          ;
; 8.480 ; 8.700        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[1]                                          ;
; 8.480 ; 8.700        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[2]                                          ;
; 8.480 ; 8.700        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[4]~_Duplicate_3                             ;
; 8.480 ; 8.700        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[5]                                          ;
; 8.480 ; 8.700        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[6]                                          ;
; 8.480 ; 8.700        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[7]                                          ;
; 8.480 ; 8.700        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[9]             ;
; 8.481 ; 8.701        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|state[1]                                ;
; 8.481 ; 8.701        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|PC[4]                                         ;
; 8.481 ; 8.701        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|PC[8]                                         ;
; 8.481 ; 8.701        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]~_Duplicate_6                                                                                           ;
; 8.481 ; 8.701        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[13]                                                                                                        ;
; 8.481 ; 8.701        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[4]~_Duplicate_3                                                                                            ;
; 8.481 ; 8.701        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[7]                                                                                                           ;
; 8.482 ; 8.702        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|addr_r[3]~_Duplicate_9                                                                              ;
; 8.482 ; 8.702        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|addr_r[6]~_Duplicate_10                                                                             ;
; 8.483 ; 8.703        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|processInt                                    ;
; 8.483 ; 8.703        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|VOLUME_OUT_R_REG[10]                             ;
; 8.483 ; 8.703        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|VOLUME_OUT_R_REG[11]                             ;
; 8.483 ; 8.703        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|VOLUME_OUT_R_REG[8]                              ;
; 8.483 ; 8.703        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|VOLUME_OUT_R_REG[9]                              ;
; 8.483 ; 8.703        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[3]                                                               ;
; 8.484 ; 8.704        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|PC[0]                                         ;
; 8.484 ; 8.704        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[3]~_Duplicate_50                       ;
; 8.484 ; 8.704        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[30]                                   ;
; 8.484 ; 8.704        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[30]~_Duplicate_8                      ;
; 8.484 ; 8.704        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[31]                                   ;
; 8.484 ; 8.704        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[14]                                                                                                        ;
; 8.484 ; 8.704        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[15]                                                                                                        ;
; 8.485 ; 8.705        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[27]                                   ;
; 8.485 ; 8.705        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[34]                                   ;
; 8.485 ; 8.705        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[40]                                   ;
; 8.485 ; 8.705        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gractl_reg[1]                                                          ;
; 8.485 ; 8.705        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[0]                                                          ;
; 8.485 ; 8.705        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[4]                                                          ;
; 8.485 ; 8.705        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[5]                                                          ;
; 8.485 ; 8.705        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[18]                                                                                                        ;
; 8.485 ; 8.705        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[19]                                                                                                        ;
; 8.485 ; 8.705        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[20]                                                                                                        ;
; 8.485 ; 8.705        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[21]                                                                                                        ;
; 8.485 ; 8.705        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[22]                                                                                                        ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                          ;
+--------+--------------+----------------+------------------+----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                ; Clock Edge ; Target                                                                                     ;
+--------+--------------+----------------+------------------+----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------+
; 16.275 ; 16.275       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 16.279 ; 16.279       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 16.279 ; 16.279       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 16.298 ; 16.298       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 16.298 ; 16.298       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 16.298 ; 16.298       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 16.298 ; 16.298       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 16.331 ; 16.331       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 16.331 ; 16.331       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 16.331 ; 16.331       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 16.331 ; 16.331       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 16.351 ; 16.351       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 16.351 ; 16.351       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 16.355 ; 16.355       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
+--------+--------------+----------------+------------------+----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'clk_27'                                                                                                              ;
+--------+--------------+----------------+------------------+--------+------------+--------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target                                                                         ;
+--------+--------------+----------------+------------------+--------+------------+--------------------------------------------------------------------------------+
; 18.275 ; 18.463       ; 0.188          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                      ;
; 18.275 ; 18.463       ; 0.188          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                      ;
; 18.275 ; 18.463       ; 0.188          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                      ;
; 18.275 ; 18.463       ; 0.188          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                      ;
; 18.275 ; 18.463       ; 0.188          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                      ;
; 18.275 ; 18.463       ; 0.188          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                      ;
; 18.275 ; 18.463       ; 0.188          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                      ;
; 18.275 ; 18.463       ; 0.188          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                      ;
; 18.275 ; 18.463       ; 0.188          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                        ;
; 18.352 ; 18.572       ; 0.220          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                      ;
; 18.352 ; 18.572       ; 0.220          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                      ;
; 18.352 ; 18.572       ; 0.220          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                      ;
; 18.352 ; 18.572       ; 0.220          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                      ;
; 18.352 ; 18.572       ; 0.220          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                      ;
; 18.352 ; 18.572       ; 0.220          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                      ;
; 18.352 ; 18.572       ; 0.220          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                      ;
; 18.352 ; 18.572       ; 0.220          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                      ;
; 18.352 ; 18.572       ; 0.220          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                        ;
; 18.362 ; 18.362       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                       ;
; 18.362 ; 18.362       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|observablevcoout             ;
; 18.366 ; 18.366       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 18.366 ; 18.366       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 18.400 ; 18.400       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; CLOCK_27[0]~input|o                                                            ;
; 18.410 ; 18.410       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; CLOCK_27[0]~inputclkctrl|inclk[0]                                              ;
; 18.410 ; 18.410       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; CLOCK_27[0]~inputclkctrl|outclk                                                ;
; 18.415 ; 18.415       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[0]|clk                                          ;
; 18.415 ; 18.415       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[1]|clk                                          ;
; 18.415 ; 18.415       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[2]|clk                                          ;
; 18.415 ; 18.415       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[3]|clk                                          ;
; 18.415 ; 18.415       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[4]|clk                                          ;
; 18.415 ; 18.415       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[5]|clk                                          ;
; 18.415 ; 18.415       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[6]|clk                                          ;
; 18.415 ; 18.415       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[7]|clk                                          ;
; 18.415 ; 18.415       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_toggle_reg|clk                                            ;
; 18.434 ; 18.434       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|inclk[0]                     ;
; 18.438 ; 18.438       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; CLOCK_27[0]~input|i                                                            ;
; 18.519 ; 18.519       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; CLOCK_27[0]~input|i                                                            ;
; 18.598 ; 18.598       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 18.602 ; 18.602       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|inclk[0]                     ;
; 18.621 ; 18.621       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[0]|clk                                          ;
; 18.621 ; 18.621       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[1]|clk                                          ;
; 18.621 ; 18.621       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[2]|clk                                          ;
; 18.621 ; 18.621       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[3]|clk                                          ;
; 18.621 ; 18.621       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[4]|clk                                          ;
; 18.621 ; 18.621       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[5]|clk                                          ;
; 18.621 ; 18.621       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[6]|clk                                          ;
; 18.621 ; 18.621       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[7]|clk                                          ;
; 18.621 ; 18.621       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_toggle_reg|clk                                            ;
; 18.626 ; 18.626       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; CLOCK_27[0]~inputclkctrl|inclk[0]                                              ;
; 18.626 ; 18.626       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; CLOCK_27[0]~inputclkctrl|outclk                                                ;
; 18.637 ; 18.637       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; CLOCK_27[0]~input|o                                                            ;
; 18.668 ; 18.668       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 18.668 ; 18.668       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 18.672 ; 18.672       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                       ;
; 18.672 ; 18.672       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|observablevcoout             ;
; 33.037 ; 37.037       ; 4.000          ; Port Rate        ; clk_27 ; Rise       ; CLOCK_27[0]                                                                    ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                        ;
+--------+--------------+----------------+------------------+--------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'SPI_SCK'                                                                                                                                       ;
+--------+--------------+----------------+------------------+---------+------------+---------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock   ; Clock Edge ; Target                                                                                                  ;
+--------+--------------+----------------+------------------+---------+------------+---------------------------------------------------------------------------------------------------------+
; 20.416 ; 20.651       ; 0.235          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ;
; 20.416 ; 20.651       ; 0.235          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_we_reg       ;
; 20.417 ; 20.652       ; 0.235          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ;
; 20.417 ; 20.652       ; 0.235          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_we_reg       ;
; 20.418 ; 20.653       ; 0.235          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 20.419 ; 20.654       ; 0.235          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_datain_reg0  ;
; 20.498 ; 20.718       ; 0.220          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[0]                                                                   ;
; 20.498 ; 20.718       ; 0.220          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[1]                                                                   ;
; 20.498 ; 20.718       ; 0.220          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[2]                                                                   ;
; 20.498 ; 20.718       ; 0.220          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[3]                                                                   ;
; 20.498 ; 20.718       ; 0.220          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[4]                                                                   ;
; 20.498 ; 20.718       ; 0.220          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[5]                                                                   ;
; 20.499 ; 20.719       ; 0.220          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|SPI_MISO~en                                                                          ;
; 20.499 ; 20.719       ; 0.220          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|SPI_MISO~reg0                                                                        ;
; 20.552 ; 20.740       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_in[0]                                                                       ;
; 20.552 ; 20.740       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_receiver_strobe_r                                                                ;
; 20.553 ; 20.741       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[0]                                                                               ;
; 20.553 ; 20.741       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[1]                                                                               ;
; 20.553 ; 20.741       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[2]                                                                               ;
; 20.553 ; 20.741       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[3]                                                                               ;
; 20.553 ; 20.741       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|sbuf[0]                                                                              ;
; 20.553 ; 20.741       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|sbuf[1]                                                                              ;
; 20.553 ; 20.741       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|sbuf[2]                                                                              ;
; 20.553 ; 20.741       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_in[1]                                                                       ;
; 20.553 ; 20.741       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_in[2]                                                                       ;
; 20.553 ; 20.741       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_in[3]                                                                       ;
; 20.553 ; 20.741       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[29]                                                         ;
; 20.555 ; 20.743       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[10]                                                         ;
; 20.555 ; 20.743       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[11]                                                         ;
; 20.555 ; 20.743       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[12]                                                         ;
; 20.555 ; 20.743       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[17]                                                         ;
; 20.555 ; 20.743       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[18]                                                         ;
; 20.555 ; 20.743       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[19]                                                         ;
; 20.555 ; 20.743       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[1]                                                          ;
; 20.555 ; 20.743       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[20]                                                         ;
; 20.555 ; 20.743       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[25]                                                         ;
; 20.555 ; 20.743       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[26]                                                         ;
; 20.555 ; 20.743       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[27]                                                         ;
; 20.555 ; 20.743       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[28]                                                         ;
; 20.555 ; 20.743       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[2]                                                          ;
; 20.555 ; 20.743       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[3]                                                          ;
; 20.555 ; 20.743       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[4]                                                          ;
; 20.555 ; 20.743       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[9]                                                          ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|bit_cnt[0]                                                                         ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|bit_cnt[1]                                                                         ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|bit_cnt[2]                                                                         ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|sbuf[0]                                                                            ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|sbuf[1]                                                                            ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|sbuf[2]                                                                            ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|sbuf[3]                                                                            ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|sbuf[4]                                                                            ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|sbuf[5]                                                                            ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|sbuf[6]                                                                            ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[0]                                                                     ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[1]                                                                     ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[2]                                                                     ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[3]                                                                     ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[4]                                                                     ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[5]                                                                     ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[6]                                                                     ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[7]                                                                     ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_receiver_strobe_r                                                              ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_transfer_end_r                                                                 ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[0]                                                                                    ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[10]                                                                                   ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[1]                                                                                    ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[2]                                                                                    ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[3]                                                                                    ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[4]                                                                                    ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[5]                                                                                    ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[6]                                                                                    ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[7]                                                                                    ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[8]                                                                                    ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[9]                                                                                    ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cmd[3]                                                                                     ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cmd[4]                                                                                     ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cmd[5]                                                                                     ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cmd[6]                                                                                     ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cmd[7]                                                                                     ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cnt[0]                                                                                     ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cnt[1]                                                                                     ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cnt[2]                                                                                     ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cnt[3]                                                                                     ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cnt[4]                                                                                     ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|sbuf[0]                                                                                    ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|sbuf[1]                                                                                    ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|sbuf[2]                                                                                    ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|sbuf[3]                                                                                    ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|sbuf[4]                                                                                    ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|sbuf[5]                                                                                    ;
; 20.556 ; 20.744       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|sbuf[6]                                                                                    ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|osd_enable                                                                                 ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[0]                                                                          ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[1]                                                                          ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[2]                                                                          ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[3]                                                                          ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[4]                                                                          ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[5]                                                                          ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[6]                                                                          ;
; 20.557 ; 20.745       ; 0.188          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[7]                                                                          ;
+--------+--------------+----------------+------------------+---------+------------+---------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                             ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                                                                                                                                                                                        ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 40.596 ; 41.626       ; 1.030          ; Low Pulse Width  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                 ;
; 40.674 ; 41.704       ; 1.030          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                 ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                                          ;
; 41.362 ; 41.582       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                                                                                                                   ;
; 41.362 ; 41.582       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                 ;
; 41.362 ; 41.582       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                 ;
; 41.362 ; 41.582       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                 ;
; 41.362 ; 41.582       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                 ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; rom_loaded                                                                                                                                                                                                    ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|rden_a_store                                                                                ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[0]                                                                                                                                                         ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[10]                                                                                                                                                        ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[11]                                                                                                                                                        ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[12]                                                                                                                                                        ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[13]                                                                                                                                                        ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[14]                                                                                                                                                        ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[15]                                                                                                                                                        ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[16]                                                                                                                                                        ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                         ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                         ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                         ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                         ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                         ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                         ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                         ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[8]                                                                                                                                                         ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[9]                                                                                                                                                         ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_reconfig_write_from_rom                                                                                                                                                      ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                              ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|reset_n_reg                                                                                                                                                                      ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[0]                                                                                                                                          ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[1]                                                                                                                                          ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_data_state                                                 ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_ena_state                                                  ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_data_state                                                 ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                  ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_data_state                                                 ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_ena_state                                                  ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_data_state                                                 ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                  ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_data_state                                                 ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_ena_state                                                  ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[0]                                             ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[1]                                             ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[2]                                             ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[3]                                             ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[4]                                             ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[5]                                             ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[6]                                             ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[7]                                             ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[0]                                              ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[1]                                              ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[2]                                              ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[3]                                              ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[4]                                              ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[5]                                              ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[6]                                              ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[7]                                              ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_init_state_1                                           ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                  ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate2_state                                           ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate_state                                            ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|idle_state                                                    ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[0] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[4] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[0] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[1] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[2] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[3] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[4] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[5] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[6] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[7] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[0] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[1] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[2] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[3] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[4] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[3] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[4] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[5] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[6] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[7] ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[0]  ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[1]  ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[2]  ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[3]  ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[4]  ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[5]  ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[6]  ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[7]  ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_counter_state                                        ;
; 41.363 ; 41.583       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_init_state                                           ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                     ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+
; CONF_DATA0    ; SPI_SCK    ; 6.210 ; 6.745 ; Rise       ; SPI_SCK                                                               ;
; SPI_DI        ; SPI_SCK    ; 5.438 ; 5.538 ; Rise       ; SPI_SCK                                                               ;
; SPI_SS2       ; SPI_SCK    ; 1.398 ; 1.677 ; Rise       ; SPI_SCK                                                               ;
; SPI_SS3       ; SPI_SCK    ; 2.185 ; 2.561 ; Rise       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; clk_27     ; 3.025 ; 3.138 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 3.021 ; 3.134 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 3.025 ; 3.138 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 3.015 ; 3.128 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 3.015 ; 3.128 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 2.964 ; 3.081 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 2.974 ; 3.091 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 2.964 ; 3.081 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 2.965 ; 3.082 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 3.008 ; 3.121 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 3.008 ; 3.121 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 3.010 ; 3.123 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 3.010 ; 3.123 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 3.011 ; 3.124 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 3.011 ; 3.124 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 3.023 ; 3.136 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 3.023 ; 3.136 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                        ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; CONF_DATA0    ; SPI_SCK    ; -3.505 ; -3.785 ; Rise       ; SPI_SCK                                                               ;
; SPI_DI        ; SPI_SCK    ; 0.521  ; 0.354  ; Rise       ; SPI_SCK                                                               ;
; SPI_SS2       ; SPI_SCK    ; -1.053 ; -1.315 ; Rise       ; SPI_SCK                                                               ;
; SPI_SS3       ; SPI_SCK    ; -0.160 ; -0.323 ; Rise       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; clk_27     ; -1.948 ; -2.065 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; -2.009 ; -2.122 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; -2.012 ; -2.125 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; -2.001 ; -2.114 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; -2.001 ; -2.114 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; -1.948 ; -2.065 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; -1.958 ; -2.075 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; -1.949 ; -2.066 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; -1.950 ; -2.067 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; -1.995 ; -2.108 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; -1.995 ; -2.108 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; -1.997 ; -2.110 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; -1.997 ; -2.110 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; -1.999 ; -2.112 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; -1.999 ; -2.112 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; -2.010 ; -2.123 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; -2.010 ; -2.123 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                             ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK    ; 10.658 ; 10.161 ; Fall       ; SPI_SCK                                                               ;
; SDRAM_A[*]    ; clk_27     ; 3.296  ; 3.052  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; clk_27     ; 3.136  ; 2.890  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; clk_27     ; 3.138  ; 2.892  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; clk_27     ; 3.138  ; 2.892  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; clk_27     ; 3.149  ; 2.903  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; clk_27     ; 3.139  ; 2.908  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; clk_27     ; 3.296  ; 3.052  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; clk_27     ; 3.279  ; 3.035  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; clk_27     ; 3.284  ; 3.040  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; clk_27     ; 3.284  ; 3.040  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; clk_27     ; 3.282  ; 3.038  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; clk_27     ; 3.136  ; 2.890  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; clk_27     ; 3.288  ; 3.044  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; clk_27     ; 3.136  ; 2.890  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; clk_27     ; 3.136  ; 2.890  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; clk_27     ; 3.126  ; 2.880  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CKE     ; clk_27     ; 2.249  ; 2.160  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; clk_27     ; 3.286  ; 3.042  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 3.267  ; 3.023  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 3.264  ; 3.020  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 3.136  ; 2.905  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 3.136  ; 2.905  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 3.150  ; 2.904  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 3.160  ; 2.914  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 3.149  ; 2.903  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 3.148  ; 2.902  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 3.261  ; 3.017  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 3.261  ; 3.017  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 3.279  ; 3.035  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 3.279  ; 3.035  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 3.118  ; 2.887  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 3.277  ; 3.033  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 3.286  ; 3.042  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 3.127  ; 2.896  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH    ; clk_27     ; 3.260  ; 3.016  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML    ; clk_27     ; 3.148  ; 2.902  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nCAS    ; clk_27     ; 3.136  ; 2.890  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nRAS    ; clk_27     ; 3.135  ; 2.889  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nWE     ; clk_27     ; 3.148  ; 2.902  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; VGA_B[*]      ; clk_27     ; 24.807 ; 24.476 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; clk_27     ; 24.007 ; 23.632 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; clk_27     ; 24.509 ; 24.262 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; clk_27     ; 24.807 ; 24.476 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; clk_27     ; 23.904 ; 23.615 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[4]     ; clk_27     ; 23.746 ; 23.460 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[5]     ; clk_27     ; 23.676 ; 23.244 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; clk_27     ; 22.695 ; 22.283 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; clk_27     ; 22.695 ; 22.283 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; clk_27     ; 22.412 ; 21.985 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; clk_27     ; 22.579 ; 22.020 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; clk_27     ; 21.912 ; 21.538 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[4]     ; clk_27     ; 21.600 ; 21.520 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[5]     ; clk_27     ; 19.417 ; 18.723 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS        ; clk_27     ; 8.292  ; 7.714  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]      ; clk_27     ; 26.090 ; 25.835 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]     ; clk_27     ; 25.847 ; 25.576 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]     ; clk_27     ; 25.963 ; 25.682 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]     ; clk_27     ; 26.090 ; 25.835 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]     ; clk_27     ; 25.481 ; 25.266 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[4]     ; clk_27     ; 25.482 ; 25.289 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[5]     ; clk_27     ; 24.662 ; 24.519 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS        ; clk_27     ; 7.597  ; 6.998  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; clk_27     ; -1.171 ;        ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; clk_27     ;        ; -1.382 ; Fall       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                     ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK    ; 10.437 ; 9.942  ; Fall       ; SPI_SCK                                                               ;
; SDRAM_A[*]    ; clk_27     ; 2.257  ; 2.016  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; clk_27     ; 2.257  ; 2.016  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; clk_27     ; 2.259  ; 2.018  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; clk_27     ; 2.259  ; 2.018  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; clk_27     ; 2.270  ; 2.029  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; clk_27     ; 2.258  ; 2.033  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; clk_27     ; 2.415  ; 2.177  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; clk_27     ; 2.400  ; 2.162  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; clk_27     ; 2.404  ; 2.166  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; clk_27     ; 2.404  ; 2.166  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; clk_27     ; 2.402  ; 2.164  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; clk_27     ; 2.257  ; 2.016  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; clk_27     ; 2.408  ; 2.170  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; clk_27     ; 2.247  ; 2.006  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; clk_27     ; 2.257  ; 2.016  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; clk_27     ; 2.247  ; 2.006  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CKE     ; clk_27     ; 1.411  ; 1.321  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; clk_27     ; 2.239  ; 2.014  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 2.388  ; 2.150  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 2.384  ; 2.146  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 2.255  ; 2.030  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 2.255  ; 2.030  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 2.270  ; 2.029  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 2.280  ; 2.039  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 2.270  ; 2.029  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 2.269  ; 2.028  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 2.381  ; 2.143  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 2.381  ; 2.143  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 2.399  ; 2.161  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 2.399  ; 2.161  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 2.239  ; 2.014  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 2.398  ; 2.160  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 2.406  ; 2.168  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 2.247  ; 2.022  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH    ; clk_27     ; 2.380  ; 2.142  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML    ; clk_27     ; 2.269  ; 2.028  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nCAS    ; clk_27     ; 2.257  ; 2.016  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nRAS    ; clk_27     ; 2.257  ; 2.016  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nWE     ; clk_27     ; 2.269  ; 2.028  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; VGA_B[*]      ; clk_27     ; 6.142  ; 5.776  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; clk_27     ; 6.237  ; 5.921  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; clk_27     ; 6.142  ; 5.776  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; clk_27     ; 6.320  ; 6.045  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; clk_27     ; 6.448  ; 6.098  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[4]     ; clk_27     ; 6.623  ; 6.349  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[5]     ; clk_27     ; 7.138  ; 6.547  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; clk_27     ; 6.599  ; 6.161  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; clk_27     ; 6.859  ; 6.438  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; clk_27     ; 6.659  ; 6.172  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; clk_27     ; 6.924  ; 6.285  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; clk_27     ; 6.599  ; 6.207  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[4]     ; clk_27     ; 6.642  ; 6.161  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[5]     ; clk_27     ; 7.005  ; 6.349  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS        ; clk_27     ; 5.907  ; 5.250  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]      ; clk_27     ; 6.057  ; 5.707  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]     ; clk_27     ; 6.057  ; 5.707  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]     ; clk_27     ; 6.180  ; 5.845  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]     ; clk_27     ; 6.401  ; 6.018  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]     ; clk_27     ; 6.673  ; 6.392  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[4]     ; clk_27     ; 6.329  ; 6.036  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[5]     ; clk_27     ; 6.363  ; 6.075  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS        ; clk_27     ; 5.677  ; 5.061  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; clk_27     ; -1.959 ;        ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; clk_27     ;        ; -2.166 ; Fall       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+


+--------------------------------------------------------------+
; Propagation Delay                                            ;
+------------+-------------+--------+--------+--------+--------+
; Input Port ; Output Port ; RR     ; RF     ; FR     ; FF     ;
+------------+-------------+--------+--------+--------+--------+
; CONF_DATA0 ; SPI_DO      ; 11.002 ; 10.762 ; 11.387 ; 11.387 ;
+------------+-------------+--------+--------+--------+--------+


+--------------------------------------------------------------+
; Minimum Propagation Delay                                    ;
+------------+-------------+--------+--------+--------+--------+
; Input Port ; Output Port ; RR     ; RF     ; FR     ; FF     ;
+------------+-------------+--------+--------+--------+--------+
; CONF_DATA0 ; SPI_DO      ; 10.186 ; 10.186 ; 10.555 ; 10.584 ;
+------------+-------------+--------+--------+--------+--------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                             ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK    ; 9.371 ; 9.371 ; Fall       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; clk_27     ; 3.143 ; 3.039 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 3.149 ; 3.045 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 3.146 ; 3.042 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 3.177 ; 3.073 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 3.177 ; 3.073 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 3.188 ; 3.085 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 3.198 ; 3.095 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 3.187 ; 3.084 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 3.186 ; 3.083 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 3.143 ; 3.039 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 3.143 ; 3.039 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 3.161 ; 3.057 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 3.161 ; 3.057 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 3.159 ; 3.055 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 3.159 ; 3.055 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 3.168 ; 3.064 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 3.168 ; 3.064 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                     ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK    ; 8.618 ; 8.647 ; Fall       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; clk_27     ; 1.767 ; 1.696 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 1.774 ; 1.703 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 1.770 ; 1.699 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 1.800 ; 1.729 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 1.800 ; 1.729 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 1.784 ; 1.731 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 1.794 ; 1.741 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 1.784 ; 1.731 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 1.783 ; 1.730 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 1.767 ; 1.696 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 1.767 ; 1.696 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 1.785 ; 1.714 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 1.785 ; 1.714 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 1.784 ; 1.713 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 1.784 ; 1.713 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 1.792 ; 1.721 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 1.792 ; 1.721 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                    ;
+---------------+------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK    ; 9.008     ; 9.248     ; Fall       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; clk_27     ; 2.878     ; 3.222     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 2.884     ; 3.228     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 2.881     ; 3.225     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 2.912     ; 3.256     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 2.912     ; 3.256     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 2.904     ; 3.267     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 2.914     ; 3.277     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 2.903     ; 3.266     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 2.902     ; 3.265     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 2.878     ; 3.222     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 2.878     ; 3.222     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 2.896     ; 3.240     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 2.896     ; 3.240     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 2.894     ; 3.238     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 2.894     ; 3.238     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 2.903     ; 3.247     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 2.903     ; 3.247     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+-----------+-----------+------------+-----------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                            ;
+---------------+------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK    ; 8.499     ; 8.499     ; Fall       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; clk_27     ; 1.743     ; 1.843     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 1.750     ; 1.850     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 1.746     ; 1.846     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 1.776     ; 1.876     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 1.776     ; 1.876     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 1.761     ; 1.860     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 1.771     ; 1.870     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 1.761     ; 1.860     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 1.760     ; 1.859     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 1.743     ; 1.843     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 1.743     ; 1.843     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 1.761     ; 1.861     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 1.761     ; 1.861     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 1.760     ; 1.860     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 1.760     ; 1.860     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 1.768     ; 1.868     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 1.768     ; 1.868     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+-----------+-----------+------------+-----------------------------------------------------------------------+


----------------------------------------------
; Slow 1200mV 85C Model Metastability Report ;
----------------------------------------------
No synchronizer chains to report.


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Fmax Summary                                                                                                                                    ;
+------------+-----------------+-----------------------------------------------------------------------+---------------------------------------------------------------+
; Fmax       ; Restricted Fmax ; Clock Name                                                            ; Note                                                          ;
+------------+-----------------+-----------------------------------------------------------------------+---------------------------------------------------------------+
; 61.98 MHz  ; 61.98 MHz       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;                                                               ;
; 91.0 MHz   ; 91.0 MHz        ; SPI_SCK                                                               ;                                                               ;
; 109.04 MHz ; 100.0 MHz       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; limit due to minimum period restriction (tmin)                ;
; 148.92 MHz ; 148.92 MHz      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;                                                               ;
; 376.36 MHz ; 250.0 MHz       ; clk_27                                                                ; limit due to minimum period restriction (max I/O toggle rate) ;
+------------+-----------------+-----------------------------------------------------------------------+---------------------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup Summary                                                             ;
+-----------------------------------------------------------------------+--------+---------------+
; Clock                                                                 ; Slack  ; End Point TNS ;
+-----------------------------------------------------------------------+--------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -1.296 ; -1.296        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.981  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 1.488  ; 0.000         ;
; SPI_SCK                                                               ; 15.363 ; 0.000         ;
; clk_27                                                                ; 34.380 ; 0.000         ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 37.081 ; 0.000         ;
+-----------------------------------------------------------------------+--------+---------------+


+-----------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold Summary                                                             ;
+-----------------------------------------------------------------------+-------+---------------+
; Clock                                                                 ; Slack ; End Point TNS ;
+-----------------------------------------------------------------------+-------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.383 ; 0.000         ;
; SPI_SCK                                                               ; 0.397 ; 0.000         ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 0.402 ; 0.000         ;
; clk_27                                                                ; 0.403 ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.403 ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 2.111 ; 0.000         ;
+-----------------------------------------------------------------------+-------+---------------+


+------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery Summary                                                          ;
+-----------------------------------------------------------------------+--------+---------------+
; Clock                                                                 ; Slack  ; End Point TNS ;
+-----------------------------------------------------------------------+--------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 3.126  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 10.072 ; 0.000         ;
+-----------------------------------------------------------------------+--------+---------------+


+-----------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal Summary                                                          ;
+-----------------------------------------------------------------------+-------+---------------+
; Clock                                                                 ; Slack ; End Point TNS ;
+-----------------------------------------------------------------------+-------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 1.443 ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 4.025 ; 0.000         ;
+-----------------------------------------------------------------------+-------+---------------+


+------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width Summary                                               ;
+-----------------------------------------------------------------------+--------+---------------+
; Clock                                                                 ; Slack  ; End Point TNS ;
+-----------------------------------------------------------------------+--------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 4.097  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 4.167  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.400  ; 0.000         ;
; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; 16.280 ; 0.000         ;
; clk_27                                                                ; 18.270 ; 0.000         ;
; SPI_SCK                                                               ; 20.401 ; 0.000         ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 40.596 ; 0.000         ;
+-----------------------------------------------------------------------+--------+---------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                   ;
+--------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; -1.296 ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 1.958        ; -1.816     ; 1.221      ;
; 2.855  ; sdram_statemachine:sdram_adaptor|addr_reg[5]                                ; SDRAM_A[5]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.992      ; 3.890      ;
; 2.864  ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                             ; SDRAM_DQ[14]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.001      ; 3.890      ;
; 2.864  ; sdram_statemachine:sdram_adaptor|addr_reg[11]                               ; SDRAM_A[11]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.001      ; 3.890      ;
; 2.867  ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                ; SDRAM_A[7]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.994      ; 3.880      ;
; 2.867  ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                ; SDRAM_A[8]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.994      ; 3.880      ;
; 2.871  ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                ; SDRAM_A[9]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.998      ; 3.880      ;
; 2.872  ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]                             ; SDRAM_DQ[11]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.999      ; 3.880      ;
; 2.872  ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                ; SDRAM_A[6]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.999      ; 3.880      ;
; 2.872  ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                             ; SDRAM_DQ[10]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.999      ; 3.880      ;
; 2.873  ; sdram_statemachine:sdram_adaptor|dq_out_reg[13]                             ; SDRAM_DQ[13]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.000      ; 3.880      ;
; 2.883  ; sdram_statemachine:sdram_adaptor|dq_out_reg[0]                              ; SDRAM_DQ[0]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.010      ; 3.880      ;
; 2.887  ; sdram_statemachine:sdram_adaptor|dq_out_reg[1]                              ; SDRAM_DQ[1]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.014      ; 3.880      ;
; 2.890  ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]                              ; SDRAM_DQ[8]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.007      ; 3.870      ;
; 2.890  ; sdram_statemachine:sdram_adaptor|udqm_reg                                   ; SDRAM_DQMH                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.007      ; 3.870      ;
; 2.890  ; sdram_statemachine:sdram_adaptor|dq_out_reg[9]                              ; SDRAM_DQ[9]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.007      ; 3.870      ;
; 2.988  ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]                              ; SDRAM_DQ[5]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.951      ; 3.716      ;
; 2.998  ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                              ; SDRAM_DQ[7]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.951      ; 3.706      ;
; 2.998  ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]                              ; SDRAM_DQ[4]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.951      ; 3.706      ;
; 2.998  ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                              ; SDRAM_DQ[6]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.951      ; 3.706      ;
; 2.999  ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                ; SDRAM_A[3]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.952      ; 3.706      ;
; 2.999  ; sdram_statemachine:sdram_adaptor|we_n_reg                                   ; SDRAM_nWE                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.952      ; 3.706      ;
; 2.999  ; sdram_statemachine:sdram_adaptor|ldqm_reg                                   ; SDRAM_DQML                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.952      ; 3.706      ;
; 3.009  ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                ; SDRAM_A[2]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.952      ; 3.696      ;
; 3.010  ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                ; SDRAM_A[1]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.953      ; 3.696      ;
; 3.010  ; sdram_statemachine:sdram_adaptor|addr_reg[10]                               ; SDRAM_A[10]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.953      ; 3.696      ;
; 3.011  ; sdram_statemachine:sdram_adaptor|addr_reg[0]                                ; SDRAM_A[0]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.954      ; 3.696      ;
; 3.011  ; sdram_statemachine:sdram_adaptor|cas_n_reg                                  ; SDRAM_nCAS                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.954      ; 3.696      ;
; 3.012  ; sdram_statemachine:sdram_adaptor|addr_reg[4]                                ; SDRAM_A[4]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.990      ; 3.731      ;
; 3.012  ; sdram_statemachine:sdram_adaptor|ba_reg[0]                                  ; SDRAM_BA[0]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.955      ; 3.696      ;
; 3.012  ; sdram_statemachine:sdram_adaptor|ras_n_reg                                  ; SDRAM_nRAS                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.955      ; 3.696      ;
; 3.019  ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                              ; SDRAM_DQ[3]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.997      ; 3.731      ;
; 3.019  ; sdram_statemachine:sdram_adaptor|dq_out_reg[2]                              ; SDRAM_DQ[2]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.997      ; 3.731      ;
; 3.020  ; sdram_statemachine:sdram_adaptor|ba_reg[1]                                  ; SDRAM_BA[1]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.953      ; 3.686      ;
; 3.023  ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                             ; SDRAM_DQ[15]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.001      ; 3.731      ;
; 3.032  ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]                             ; SDRAM_DQ[12]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.000      ; 3.721      ;
; 3.216  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_5                 ; SDRAM_DQ[5]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.965      ; 3.502      ;
; 3.226  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_7                 ; SDRAM_DQ[7]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.965      ; 3.492      ;
; 3.226  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4                 ; SDRAM_DQ[4]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.965      ; 3.492      ;
; 3.226  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_6                 ; SDRAM_DQ[6]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.965      ; 3.492      ;
; 3.243  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3                 ; SDRAM_DQ[3]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.011      ; 3.521      ;
; 3.243  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2                 ; SDRAM_DQ[2]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.011      ; 3.521      ;
; 3.247  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14                ; SDRAM_DQ[14]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.015      ; 3.521      ;
; 3.247  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15                ; SDRAM_DQ[15]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.015      ; 3.521      ;
; 3.255  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11                ; SDRAM_DQ[11]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.013      ; 3.511      ;
; 3.255  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10                ; SDRAM_DQ[10]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.013      ; 3.511      ;
; 3.256  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13                ; SDRAM_DQ[13]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.014      ; 3.511      ;
; 3.256  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12                ; SDRAM_DQ[12]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.014      ; 3.511      ;
; 3.266  ; sdram_statemachine:sdram_adaptor|dq_output_reg                              ; SDRAM_DQ[0]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.024      ; 3.511      ;
; 3.270  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1                 ; SDRAM_DQ[1]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.028      ; 3.511      ;
; 3.273  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8                 ; SDRAM_DQ[8]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.021      ; 3.501      ;
; 3.273  ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9                 ; SDRAM_DQ[9]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 2.021      ; 3.501      ;
; 3.724  ; sdram_statemachine:sdram_adaptor|cke_reg                                    ; SDRAM_CKE                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.944      ; 2.973      ;
+--------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                  ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.981 ; SDRAM_DQ[1]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[1]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.448     ; 1.203      ;
; 0.983 ; SDRAM_DQ[14]                                                                ; sdram_statemachine:sdram_adaptor|dq_in_reg[14]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.436     ; 1.213      ;
; 0.983 ; SDRAM_DQ[15]                                                                ; sdram_statemachine:sdram_adaptor|dq_in_reg[15]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.436     ; 1.213      ;
; 0.985 ; SDRAM_DQ[0]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[0]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.444     ; 1.203      ;
; 0.987 ; SDRAM_DQ[2]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[2]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.432     ; 1.213      ;
; 0.987 ; SDRAM_DQ[3]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[3]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.432     ; 1.213      ;
; 0.995 ; SDRAM_DQ[11]                                                                ; sdram_statemachine:sdram_adaptor|dq_in_reg[11]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.434     ; 1.203      ;
; 0.995 ; SDRAM_DQ[13]                                                                ; sdram_statemachine:sdram_adaptor|dq_in_reg[13]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.434     ; 1.203      ;
; 0.995 ; SDRAM_DQ[12]                                                                ; sdram_statemachine:sdram_adaptor|dq_in_reg[12]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.434     ; 1.203      ;
; 0.995 ; SDRAM_DQ[10]                                                                ; sdram_statemachine:sdram_adaptor|dq_in_reg[10]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.434     ; 1.203      ;
; 0.998 ; SDRAM_DQ[9]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[9]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.441     ; 1.193      ;
; 0.998 ; SDRAM_DQ[8]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[8]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.441     ; 1.193      ;
; 1.021 ; SDRAM_DQ[5]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[5]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.388     ; 1.223      ;
; 1.031 ; SDRAM_DQ[7]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[7]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.388     ; 1.213      ;
; 1.031 ; SDRAM_DQ[4]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[4]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.388     ; 1.213      ;
; 1.031 ; SDRAM_DQ[6]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[6]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -2.388     ; 1.213      ;
; 1.240 ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:0:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 4.405        ; -1.816     ; 1.222      ;
; 2.095 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.131     ; 6.460      ;
; 2.131 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.131     ; 6.424      ;
; 2.285 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.131     ; 6.270      ;
; 2.329 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 6.426      ;
; 2.329 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 6.426      ;
; 2.329 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 6.426      ;
; 2.329 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 6.426      ;
; 2.329 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 6.426      ;
; 2.329 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 6.426      ;
; 2.329 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 6.426      ;
; 2.329 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 6.426      ;
; 2.329 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 6.426      ;
; 2.329 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 6.426      ;
; 2.329 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 6.426      ;
; 2.329 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 6.426      ;
; 2.353 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 6.402      ;
; 2.353 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 6.402      ;
; 2.353 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 6.402      ;
; 2.353 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 6.402      ;
; 2.353 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 6.402      ;
; 2.353 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 6.402      ;
; 2.353 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 6.402      ;
; 2.353 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 6.402      ;
; 2.353 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 6.402      ;
; 2.353 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 6.402      ;
; 2.353 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 6.402      ;
; 2.353 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 6.402      ;
; 2.367 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.087     ; 6.232      ;
; 2.394 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.127     ; 6.165      ;
; 2.403 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.087     ; 6.196      ;
; 2.405 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.087     ; 6.194      ;
; 2.430 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.127     ; 6.129      ;
; 2.441 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.087     ; 6.158      ;
; 2.445 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.131     ; 6.110      ;
; 2.446 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.127     ; 6.113      ;
; 2.482 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.127     ; 6.077      ;
; 2.497 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.132     ; 6.057      ;
; 2.499 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 6.256      ;
; 2.499 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 6.256      ;
; 2.499 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 6.256      ;
; 2.499 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 6.256      ;
; 2.499 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 6.256      ;
; 2.499 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 6.256      ;
; 2.499 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 6.256      ;
; 2.499 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 6.256      ;
; 2.499 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 6.256      ;
; 2.499 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 6.256      ;
; 2.499 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 6.256      ;
; 2.499 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 6.256      ;
; 2.533 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.132     ; 6.021      ;
; 2.554 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.134     ; 5.998      ;
; 2.557 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.087     ; 6.042      ;
; 2.584 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.127     ; 5.975      ;
; 2.590 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.134     ; 5.962      ;
; 2.595 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.087     ; 6.004      ;
; 2.598 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.131     ; 5.957      ;
; 2.605 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 6.150      ;
; 2.605 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 6.150      ;
; 2.605 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 6.150      ;
; 2.605 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 6.150      ;
; 2.605 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 6.150      ;
; 2.605 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 6.150      ;
; 2.605 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 6.150      ;
; 2.605 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 6.150      ;
; 2.605 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 6.150      ;
; 2.605 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 6.150      ;
; 2.605 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 6.150      ;
; 2.605 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 6.150      ;
; 2.636 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.127     ; 5.923      ;
; 2.687 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.132     ; 5.867      ;
; 2.717 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.087     ; 5.882      ;
; 2.723 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.088     ; 5.875      ;
; 2.744 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.127     ; 5.815      ;
; 2.744 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.134     ; 5.808      ;
; 2.751 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.132     ; 5.803      ;
; 2.755 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.087     ; 5.844      ;
; 2.759 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.088     ; 5.839      ;
; 2.796 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.127     ; 5.763      ;
; 2.821 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.131     ; 5.734      ;
; 2.847 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.132     ; 5.707      ;
; 2.876 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[5]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.125     ; 5.685      ;
; 2.904 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.134     ; 5.648      ;
; 2.904 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.056     ; 5.852      ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                          ;
+-------+-----------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                             ; To Node                                                                                                                             ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 1.488 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.080     ; 16.055     ;
; 1.602 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.155     ; 15.866     ;
; 1.638 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.104     ; 15.881     ;
; 1.666 ; ioctl_state.IOCTL_IDLE~_Duplicate_7                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.506     ; 15.451     ;
; 1.767 ; user_io:my_user_io|status[1]                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.080     ; 15.776     ;
; 1.887 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[0]~_Duplicate_30      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.075     ; 15.661     ;
; 1.893 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.076     ; 15.654     ;
; 1.896 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.102     ; 15.625     ;
; 1.900 ; DMA_16BIT_WRITE_ENABLE_IOCTL                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.076     ; 15.647     ;
; 1.903 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                   ; ioctl_state.IOCTL_IDLE~_Duplicate_1                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.050     ; 15.670     ;
; 1.904 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.371      ; 16.090     ;
; 1.907 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.104     ; 15.612     ;
; 1.909 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[7]~_Duplicate_31      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.077     ; 15.637     ;
; 1.910 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.359      ; 16.072     ;
; 1.941 ; DMA_16BIT_WRITE_ENABLE_IOCTL~_Duplicate_1                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.070     ; 15.612     ;
; 1.957 ; ioctl_state.IOCTL_IDLE                                                                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.077     ; 15.589     ;
; 1.972 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.372      ; 16.023     ;
; 1.972 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.372      ; 16.023     ;
; 1.972 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[4]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.372      ; 16.023     ;
; 1.972 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.372      ; 16.023     ;
; 1.985 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[0]~_Duplicate_30      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.166     ; 15.472     ;
; 2.001 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                ; ioctl_state.IOCTL_IDLE~_Duplicate_1                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.141     ; 15.481     ;
; 2.002 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[37]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.376      ; 15.997     ;
; 2.007 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[7]~_Duplicate_31      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.168     ; 15.448     ;
; 2.008 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.268      ; 15.883     ;
; 2.014 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Y[0]                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 15.527     ;
; 2.014 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.349      ; 15.958     ;
; 2.016 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.102     ; 15.505     ;
; 2.018 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.296      ; 15.901     ;
; 2.020 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                   ; ioctl_state.IOCTL_IDLE~_Duplicate_9                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.078     ; 15.525     ;
; 2.030 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_reg[0]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.072     ; 15.521     ;
; 2.037 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[0]~_Duplicate_30      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.099     ; 15.487     ;
; 2.037 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[37]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.400      ; 15.986     ;
; 2.049 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.373      ; 15.947     ;
; 2.053 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg               ; ioctl_state.IOCTL_IDLE~_Duplicate_1                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.074     ; 15.496     ;
; 2.054 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.347      ; 15.916     ;
; 2.059 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[7]~_Duplicate_31      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.101     ; 15.463     ;
; 2.060 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.335      ; 15.898     ;
; 2.060 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.102     ; 15.461     ;
; 2.065 ; ioctl_state.IOCTL_IDLE~_Duplicate_7                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[0]~_Duplicate_30      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.501     ; 15.057     ;
; 2.069 ; user_io:my_user_io|but_sw[1]                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.074     ; 15.480     ;
; 2.070 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.281      ; 15.834     ;
; 2.070 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.281      ; 15.834     ;
; 2.070 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[4]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.281      ; 15.834     ;
; 2.070 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.281      ; 15.834     ;
; 2.077 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[9] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.070     ; 15.476     ;
; 2.081 ; ioctl_state.IOCTL_IDLE~_Duplicate_7                                                                                   ; ioctl_state.IOCTL_IDLE~_Duplicate_1                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.476     ; 15.066     ;
; 2.082 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg~_Duplicate_1                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.072     ; 15.469     ;
; 2.082 ; ioctl_state.IOCTL_IDLE~_Duplicate_7                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.055     ; 15.486     ;
; 2.087 ; ioctl_state.IOCTL_IDLE~_Duplicate_7                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[7]~_Duplicate_31      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.503     ; 15.033     ;
; 2.088 ; ioctl_state.IOCTL_IDLE~_Duplicate_7                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.067     ; 15.468     ;
; 2.091 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[9]               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.076     ; 15.456     ;
; 2.100 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[6]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.074     ; 15.449     ;
; 2.100 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[3]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.074     ; 15.449     ;
; 2.101 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                   ; ioctl_state.IOCTL_IDLE~_Duplicate_7                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.337      ; 15.859     ;
; 2.106 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.049     ; 15.468     ;
; 2.106 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[11]                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.049     ; 15.468     ;
; 2.106 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.049     ; 15.468     ;
; 2.106 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[12]                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.049     ; 15.468     ;
; 2.106 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[13]                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.049     ; 15.468     ;
; 2.112 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Y[0]                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.173     ; 15.338     ;
; 2.118 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                ; ioctl_state.IOCTL_IDLE~_Duplicate_9                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.169     ; 15.336     ;
; 2.122 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.348      ; 15.849     ;
; 2.122 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.348      ; 15.849     ;
; 2.122 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[4]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.348      ; 15.849     ;
; 2.122 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.348      ; 15.849     ;
; 2.128 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_reg[0]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.163     ; 15.332     ;
; 2.135 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[37]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.309      ; 15.797     ;
; 2.147 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.282      ; 15.758     ;
; 2.150 ; ioctl_state.IOCTL_IDLE~_Duplicate_7                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.054     ; 15.419     ;
; 2.150 ; ioctl_state.IOCTL_IDLE~_Duplicate_7                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.054     ; 15.419     ;
; 2.150 ; ioctl_state.IOCTL_IDLE~_Duplicate_7                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[4]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.054     ; 15.419     ;
; 2.150 ; ioctl_state.IOCTL_IDLE~_Duplicate_7                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.054     ; 15.419     ;
; 2.164 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Y[0]                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.106     ; 15.353     ;
; 2.166 ; user_io:my_user_io|status[1]                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[0]~_Duplicate_30      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.075     ; 15.382     ;
; 2.170 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg               ; ioctl_state.IOCTL_IDLE~_Duplicate_9                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.102     ; 15.351     ;
; 2.171 ; ioctl_state.IOCTL_IDLE~_Duplicate_1                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.102     ; 15.350     ;
; 2.178 ; cart_type_byte[4]~_Duplicate_10                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.068     ; 15.377     ;
; 2.180 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[3]~_Duplicate_50 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.334      ; 15.777     ;
; 2.180 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_reg[0]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.096     ; 15.347     ;
; 2.180 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg~_Duplicate_1                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.163     ; 15.280     ;
; 2.182 ; user_io:my_user_io|status[1]                                                                                          ; ioctl_state.IOCTL_IDLE~_Duplicate_1                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.050     ; 15.391     ;
; 2.183 ; user_io:my_user_io|status[1]                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.371      ; 15.811     ;
; 2.188 ; user_io:my_user_io|status[1]                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[7]~_Duplicate_31      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.077     ; 15.358     ;
; 2.189 ; user_io:my_user_io|status[1]                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.359      ; 15.793     ;
; 2.189 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg~_Duplicate_1   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.080     ; 15.354     ;
; 2.191 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[5]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.307      ; 15.739     ;
; 2.192 ; ioctl_state.IOCTL_IDLE~_Duplicate_7                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Y[0]                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.508     ; 14.923     ;
; 2.198 ; ioctl_state.IOCTL_IDLE~_Duplicate_7                                                                                   ; ioctl_state.IOCTL_IDLE~_Duplicate_9                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.504     ; 14.921     ;
; 2.198 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[6]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.165     ; 15.260     ;
; 2.198 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[3]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.165     ; 15.260     ;
; 2.199 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                ; ioctl_state.IOCTL_IDLE~_Duplicate_7                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.246      ; 15.670     ;
; 2.204 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.140     ; 15.279     ;
; 2.204 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[11]                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.140     ; 15.279     ;
; 2.204 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.140     ; 15.279     ;
; 2.204 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[12]                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.140     ; 15.279     ;
; 2.204 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[13]                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.140     ; 15.279     ;
; 2.208 ; ioctl_state.IOCTL_IDLE~_Duplicate_7                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_reg[0]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.498     ; 14.917     ;
; 2.210 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[0]~_Duplicate_49 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.372      ; 15.785     ;
; 2.214 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg~_Duplicate_1  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.076     ; 15.333     ;
+-------+-----------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'SPI_SCK'                                                                                                                        ;
+--------+---------------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                             ; To Node                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+
; 15.363 ; user_io:my_user_io|byte_cnt[8]        ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.022      ; 5.527      ;
; 15.363 ; user_io:my_user_io|byte_cnt[8]        ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.022      ; 5.527      ;
; 15.363 ; user_io:my_user_io|byte_cnt[8]        ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.022      ; 5.527      ;
; 15.363 ; user_io:my_user_io|byte_cnt[8]        ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.022      ; 5.527      ;
; 15.363 ; user_io:my_user_io|byte_cnt[8]        ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.022      ; 5.527      ;
; 15.536 ; user_io:my_user_io|byte_cnt[7]        ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.022      ; 5.354      ;
; 15.536 ; user_io:my_user_io|byte_cnt[7]        ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.022      ; 5.354      ;
; 15.536 ; user_io:my_user_io|byte_cnt[7]        ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.022      ; 5.354      ;
; 15.536 ; user_io:my_user_io|byte_cnt[7]        ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.022      ; 5.354      ;
; 15.536 ; user_io:my_user_io|byte_cnt[7]        ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.022      ; 5.354      ;
; 15.746 ; user_io:my_user_io|byte_cnt[5]        ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.022      ; 5.144      ;
; 15.746 ; user_io:my_user_io|byte_cnt[5]        ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.022      ; 5.144      ;
; 15.746 ; user_io:my_user_io|byte_cnt[5]        ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.022      ; 5.144      ;
; 15.746 ; user_io:my_user_io|byte_cnt[5]        ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.022      ; 5.144      ;
; 15.746 ; user_io:my_user_io|byte_cnt[5]        ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.022      ; 5.144      ;
; 15.825 ; user_io:my_user_io|byte_cnt[8]        ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.022      ; 5.065      ;
; 15.875 ; user_io:my_user_io|byte_cnt[6]        ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.022      ; 5.015      ;
; 15.875 ; user_io:my_user_io|byte_cnt[6]        ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.022      ; 5.015      ;
; 15.875 ; user_io:my_user_io|byte_cnt[6]        ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.022      ; 5.015      ;
; 15.875 ; user_io:my_user_io|byte_cnt[6]        ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.022      ; 5.015      ;
; 15.875 ; user_io:my_user_io|byte_cnt[6]        ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.022      ; 5.015      ;
; 15.998 ; user_io:my_user_io|byte_cnt[7]        ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.022      ; 4.892      ;
; 16.054 ; user_io:my_user_io|byte_cnt[3]        ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.022      ; 4.836      ;
; 16.054 ; user_io:my_user_io|byte_cnt[3]        ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.022      ; 4.836      ;
; 16.054 ; user_io:my_user_io|byte_cnt[3]        ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.022      ; 4.836      ;
; 16.054 ; user_io:my_user_io|byte_cnt[3]        ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.022      ; 4.836      ;
; 16.054 ; user_io:my_user_io|byte_cnt[3]        ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.022      ; 4.836      ;
; 16.208 ; user_io:my_user_io|byte_cnt[5]        ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.022      ; 4.682      ;
; 16.337 ; user_io:my_user_io|byte_cnt[6]        ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.022      ; 4.553      ;
; 16.448 ; user_io:my_user_io|byte_cnt[9]        ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.022      ; 4.442      ;
; 16.448 ; user_io:my_user_io|byte_cnt[9]        ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.022      ; 4.442      ;
; 16.448 ; user_io:my_user_io|byte_cnt[9]        ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.022      ; 4.442      ;
; 16.448 ; user_io:my_user_io|byte_cnt[9]        ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.022      ; 4.442      ;
; 16.448 ; user_io:my_user_io|byte_cnt[9]        ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.022      ; 4.442      ;
; 16.516 ; user_io:my_user_io|byte_cnt[3]        ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.022      ; 4.374      ;
; 16.724 ; user_io:my_user_io|bit_cnt[0]         ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.020      ; 4.164      ;
; 16.724 ; user_io:my_user_io|bit_cnt[0]         ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.020      ; 4.164      ;
; 16.724 ; user_io:my_user_io|bit_cnt[0]         ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.020      ; 4.164      ;
; 16.724 ; user_io:my_user_io|bit_cnt[0]         ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.020      ; 4.164      ;
; 16.724 ; user_io:my_user_io|bit_cnt[0]         ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.020      ; 4.164      ;
; 16.773 ; user_io:my_user_io|byte_cnt[4]        ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.022      ; 4.117      ;
; 16.773 ; user_io:my_user_io|byte_cnt[4]        ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.022      ; 4.117      ;
; 16.773 ; user_io:my_user_io|byte_cnt[4]        ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.022      ; 4.117      ;
; 16.773 ; user_io:my_user_io|byte_cnt[4]        ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.022      ; 4.117      ;
; 16.773 ; user_io:my_user_io|byte_cnt[4]        ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.022      ; 4.117      ;
; 16.850 ; user_io:my_user_io|byte_cnt[2]        ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.022      ; 4.040      ;
; 16.850 ; user_io:my_user_io|byte_cnt[2]        ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.022      ; 4.040      ;
; 16.850 ; user_io:my_user_io|byte_cnt[2]        ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.022      ; 4.040      ;
; 16.850 ; user_io:my_user_io|byte_cnt[2]        ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.022      ; 4.040      ;
; 16.850 ; user_io:my_user_io|byte_cnt[2]        ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.022      ; 4.040      ;
; 16.910 ; user_io:my_user_io|byte_cnt[9]        ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.022      ; 3.980      ;
; 17.083 ; user_io:my_user_io|bit_cnt[2]         ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.020      ; 3.805      ;
; 17.083 ; user_io:my_user_io|bit_cnt[2]         ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.020      ; 3.805      ;
; 17.083 ; user_io:my_user_io|bit_cnt[2]         ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.020      ; 3.805      ;
; 17.083 ; user_io:my_user_io|bit_cnt[2]         ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.020      ; 3.805      ;
; 17.083 ; user_io:my_user_io|bit_cnt[2]         ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.020      ; 3.805      ;
; 17.140 ; user_io:my_user_io|cmd[3]             ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.012      ; 3.740      ;
; 17.140 ; user_io:my_user_io|cmd[3]             ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.012      ; 3.740      ;
; 17.140 ; user_io:my_user_io|cmd[3]             ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.012      ; 3.740      ;
; 17.140 ; user_io:my_user_io|cmd[3]             ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.012      ; 3.740      ;
; 17.140 ; user_io:my_user_io|cmd[3]             ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.012      ; 3.740      ;
; 17.146 ; user_io:my_user_io|byte_cnt[1]        ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.022      ; 3.744      ;
; 17.146 ; user_io:my_user_io|byte_cnt[1]        ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.022      ; 3.744      ;
; 17.146 ; user_io:my_user_io|byte_cnt[1]        ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.022      ; 3.744      ;
; 17.146 ; user_io:my_user_io|byte_cnt[1]        ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.022      ; 3.744      ;
; 17.146 ; user_io:my_user_io|byte_cnt[1]        ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.022      ; 3.744      ;
; 17.209 ; user_io:my_user_io|bit_cnt[0]         ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.020      ; 3.679      ;
; 17.231 ; user_io:my_user_io|bit_cnt[1]         ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.020      ; 3.657      ;
; 17.231 ; user_io:my_user_io|bit_cnt[1]         ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.020      ; 3.657      ;
; 17.231 ; user_io:my_user_io|bit_cnt[1]         ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.020      ; 3.657      ;
; 17.231 ; user_io:my_user_io|bit_cnt[1]         ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.020      ; 3.657      ;
; 17.231 ; user_io:my_user_io|bit_cnt[1]         ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.020      ; 3.657      ;
; 17.235 ; user_io:my_user_io|byte_cnt[4]        ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.022      ; 3.655      ;
; 17.300 ; user_io:my_user_io|byte_cnt[0]        ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.022      ; 3.590      ;
; 17.300 ; user_io:my_user_io|byte_cnt[0]        ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.022      ; 3.590      ;
; 17.300 ; user_io:my_user_io|byte_cnt[0]        ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.022      ; 3.590      ;
; 17.300 ; user_io:my_user_io|byte_cnt[0]        ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.022      ; 3.590      ;
; 17.300 ; user_io:my_user_io|byte_cnt[0]        ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.022      ; 3.590      ;
; 17.335 ; user_io:my_user_io|byte_cnt[2]        ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.022      ; 3.555      ;
; 17.454 ; user_io:my_user_io|cmd[5]             ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.023      ; 3.437      ;
; 17.454 ; user_io:my_user_io|cmd[5]             ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.023      ; 3.437      ;
; 17.454 ; user_io:my_user_io|cmd[5]             ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.023      ; 3.437      ;
; 17.454 ; user_io:my_user_io|cmd[5]             ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.023      ; 3.437      ;
; 17.454 ; user_io:my_user_io|cmd[5]             ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.023      ; 3.437      ;
; 17.459 ; user_io:my_user_io|cmd[7]             ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.023      ; 3.432      ;
; 17.459 ; user_io:my_user_io|cmd[7]             ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.023      ; 3.432      ;
; 17.459 ; user_io:my_user_io|cmd[7]             ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.023      ; 3.432      ;
; 17.459 ; user_io:my_user_io|cmd[7]             ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.023      ; 3.432      ;
; 17.459 ; user_io:my_user_io|cmd[7]             ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.023      ; 3.432      ;
; 17.468 ; user_io:my_user_io|serial_out_rptr[0] ; user_io:my_user_io|spi_byte_out[0]    ; SPI_SCK      ; SPI_SCK     ; 20.800       ; -0.163     ; 3.171      ;
; 17.468 ; user_io:my_user_io|serial_out_rptr[2] ; user_io:my_user_io|spi_byte_out[0]    ; SPI_SCK      ; SPI_SCK     ; 20.800       ; -0.163     ; 3.171      ;
; 17.568 ; user_io:my_user_io|bit_cnt[2]         ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.020      ; 3.320      ;
; 17.575 ; user_io:my_user_io|cmd[6]             ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.023      ; 3.316      ;
; 17.575 ; user_io:my_user_io|cmd[6]             ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.023      ; 3.316      ;
; 17.575 ; user_io:my_user_io|cmd[6]             ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.023      ; 3.316      ;
; 17.575 ; user_io:my_user_io|cmd[6]             ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.023      ; 3.316      ;
; 17.575 ; user_io:my_user_io|cmd[6]             ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.023      ; 3.316      ;
; 17.609 ; user_io:my_user_io|cmd[1]             ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.012      ; 3.271      ;
; 17.609 ; user_io:my_user_io|cmd[1]             ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.012      ; 3.271      ;
; 17.609 ; user_io:my_user_io|cmd[1]             ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.012      ; 3.271      ;
+--------+---------------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'clk_27'                                                                                                                                                                 ;
+--------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                 ; To Node                                                   ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 34.380 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 2.588      ;
; 34.468 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 2.500      ;
; 34.508 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 2.460      ;
; 34.508 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 2.460      ;
; 34.563 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 2.405      ;
; 34.592 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 2.376      ;
; 34.596 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 2.372      ;
; 34.630 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 2.338      ;
; 34.636 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 2.332      ;
; 34.654 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 2.314      ;
; 34.687 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 2.281      ;
; 34.720 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 2.248      ;
; 34.720 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 2.248      ;
; 34.756 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 2.212      ;
; 34.758 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 2.210      ;
; 34.769 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 2.199      ;
; 34.814 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 2.154      ;
; 34.815 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 2.153      ;
; 34.903 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 2.065      ;
; 34.905 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 2.063      ;
; 35.042 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.926      ;
; 35.050 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.918      ;
; 35.054 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.914      ;
; 35.062 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.906      ;
; 35.083 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.885      ;
; 35.138 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.830      ;
; 35.150 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.818      ;
; 35.165 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.803      ;
; 35.174 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.794      ;
; 35.207 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.761      ;
; 35.211 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.757      ;
; 35.219 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.749      ;
; 35.225 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.743      ;
; 35.237 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.731      ;
; 35.248 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.720      ;
; 35.285 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.683      ;
; 35.289 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.679      ;
; 35.291 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.677      ;
; 35.293 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.675      ;
; 35.305 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.663      ;
; 35.306 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.662      ;
; 35.378 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.590      ;
; 35.386 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.582      ;
; 35.389 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.579      ;
; 35.401 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.567      ;
; 35.406 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.562      ;
; 35.418 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.550      ;
; 35.475 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.493      ;
; 35.476 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.492      ;
; 35.556 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.412      ;
; 35.573 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.395      ;
; 35.576 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.392      ;
; 35.608 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.360      ;
; 35.726 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.242      ;
; 35.743 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.225      ;
; 35.745 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.223      ;
; 35.815 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.153      ;
; 35.817 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.151      ;
; 35.851 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 1.117      ;
; 36.198 ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.071     ; 0.770      ;
+--------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                          ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                                       ; To Node                                                                                                                                                                                                                               ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 37.081 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_we_reg ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.734     ; 5.965      ;
; 37.634 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|idle_state                                                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 3.621      ; 7.656      ;
; 39.174 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 3.619      ; 6.114      ;
; 39.397 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_data_state                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.379     ; 4.004      ;
; 39.403 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_data_state                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.379     ; 3.998      ;
; 39.476 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 3.619      ; 5.812      ;
; 39.571 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_data_state                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.379     ; 3.830      ;
; 39.607 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_init_state_1                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 3.616      ; 5.678      ;
; 39.698 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_data_state                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.379     ; 3.703      ;
; 39.959 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_data_state                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.379     ; 3.442      ;
; 40.220 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_seq_data_state                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.384     ; 3.176      ;
; 40.312 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[1]                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.380     ; 3.088      ;
; 40.312 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[3]                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.380     ; 3.088      ;
; 40.487 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[2]                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.380     ; 2.913      ;
; 40.546 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate2_state                                                             ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate3_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.119     ; 1.003      ;
; 40.625 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[4]                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.380     ; 2.775      ;
; 41.077 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                                             ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.384     ; 2.319      ;
; 41.151 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[0]                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.380     ; 2.249      ;
; 75.975 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                             ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|idle_state                                                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.070     ; 7.290      ;
; 76.908 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|idle_state                                                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.066     ; 6.361      ;
; 77.343 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                             ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.072     ; 5.920      ;
; 77.653 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                             ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.072     ; 5.610      ;
; 77.777 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                             ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_init_state_1                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.075     ; 5.483      ;
; 78.039 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_second_state                                                                ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.282      ; 5.615      ;
; 78.039 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_second_state                                                                ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.282      ; 5.615      ;
; 78.293 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.068     ; 4.974      ;
; 78.442 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[2]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.282      ; 5.212      ;
; 78.442 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[2]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.282      ; 5.212      ;
; 78.603 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.068     ; 4.664      ;
; 78.609 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.068     ; 4.658      ;
; 78.609 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.068     ; 4.658      ;
; 78.609 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.068     ; 4.658      ;
; 78.609 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.068     ; 4.658      ;
; 78.609 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.068     ; 4.658      ;
; 78.609 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[5]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.068     ; 4.658      ;
; 78.609 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[6]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.068     ; 4.658      ;
; 78.609 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[7]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.068     ; 4.658      ;
; 78.623 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_first_state                                                                 ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.281      ; 5.030      ;
; 78.623 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_first_state                                                                 ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.281      ; 5.030      ;
; 78.676 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[1]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.282      ; 4.978      ;
; 78.676 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[1]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.282      ; 4.978      ;
; 78.712 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.062     ; 4.561      ;
; 78.727 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_init_state_1                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.537      ;
; 78.747 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.062     ; 4.526      ;
; 78.780 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.068     ; 4.487      ;
; 78.780 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.068     ; 4.487      ;
; 78.780 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.068     ; 4.487      ;
; 78.780 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.068     ; 4.487      ;
; 78.780 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.068     ; 4.487      ;
; 78.780 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[5]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.068     ; 4.487      ;
; 78.780 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[6]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.068     ; 4.487      ;
; 78.780 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[7]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.068     ; 4.487      ;
; 78.796 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.062     ; 4.477      ;
; 78.830 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_data_state                                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_address_reg0 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.281      ; 4.823      ;
; 78.850 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[3]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.282      ; 4.804      ;
; 78.850 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[3]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.282      ; 4.804      ;
; 78.871 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                   ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.393      ;
; 78.906 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                   ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.358      ;
; 78.955 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                   ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.309      ;
; 78.966 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[5]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.282      ; 4.688      ;
; 78.966 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[5]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.282      ; 4.688      ;
; 78.966 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[6]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.282      ; 4.688      ;
; 78.966 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[6]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.282      ; 4.688      ;
; 78.988 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[0]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.282      ; 4.666      ;
; 78.988 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[0]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.282      ; 4.666      ;
; 79.013 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_second_last_state                                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_address_reg0 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.283      ; 4.642      ;
; 79.108 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                   ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[0]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.072     ; 4.155      ;
; 79.108 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                   ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.072     ; 4.155      ;
; 79.108 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                   ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.072     ; 4.155      ;
; 79.108 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                   ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.072     ; 4.155      ;
; 79.108 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                   ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.072     ; 4.155      ;
; 79.108 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                   ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.072     ; 4.155      ;
; 79.108 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                   ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.072     ; 4.155      ;
; 79.108 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                   ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.072     ; 4.155      ;
; 79.141 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[7]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.282      ; 4.513      ;
; 79.141 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[7]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.282      ; 4.513      ;
; 79.142 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[0]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.063     ; 4.130      ;
; 79.142 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.063     ; 4.130      ;
; 79.142 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.063     ; 4.130      ;
; 79.142 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.063     ; 4.130      ;
; 79.142 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.063     ; 4.130      ;
; 79.142 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.063     ; 4.130      ;
; 79.142 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.063     ; 4.130      ;
; 79.142 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.063     ; 4.130      ;
; 79.157 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.068     ; 4.110      ;
; 79.162 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.068     ; 4.105      ;
; 79.162 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.068     ; 4.105      ;
; 79.162 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.068     ; 4.105      ;
; 79.162 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.068     ; 4.105      ;
; 79.162 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.068     ; 4.105      ;
; 79.162 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[5]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.068     ; 4.105      ;
; 79.162 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[6]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.068     ; 4.105      ;
; 79.162 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[7]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.068     ; 4.105      ;
; 79.181 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_last_state                                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_address_reg0 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.282      ; 4.473      ;
; 79.200 ; rom_loaded                                                                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.068     ; 4.067      ;
; 79.228 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.068     ; 4.039      ;
; 79.255 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.009      ;
; 79.255 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.009      ;
; 79.255 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.009      ;
; 79.255 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.009      ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
+-------+-----------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                   ; To Node                                                                                                                                                                                                                                ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.383 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|state[1]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|state[1]                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.091      ; 0.669      ;
; 0.384 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|irqb_reg[1]                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|irqb_reg[1]                                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.090      ; 0.669      ;
; 0.384 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|irqa_reg[1]                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|irqa_reg[1]                                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.090      ; 0.669      ;
; 0.387 ; user_io:my_user_io|sd_dout[6]                                                                                               ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.423      ; 1.040      ;
; 0.398 ; user_io:my_user_io|sd_dout[5]                                                                                               ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.423      ; 1.051      ;
; 0.400 ; user_io:my_user_io|sd_dout[1]                                                                                               ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.423      ; 1.053      ;
; 0.400 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[0]                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.422      ; 1.052      ;
; 0.400 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_snap_reg[6]                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.422      ; 1.052      ;
; 0.401 ; user_io:my_user_io|sd_dout[3]                                                                                               ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.423      ; 1.054      ;
; 0.401 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|nmiReg          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|nmiReg                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.073      ; 0.669      ;
; 0.401 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.073      ; 0.669      ;
; 0.402 ; user_io:my_user_io|ps2_kbd_tx_state[3]                                                                                      ; user_io:my_user_io|ps2_kbd_tx_state[3]                                                                                                                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; user_io:my_user_io|ps2_kbd_tx_state[1]                                                                                      ; user_io:my_user_io|ps2_kbd_tx_state[1]                                                                                                                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; user_io:my_user_io|ps2_kbd_tx_state[2]                                                                                      ; user_io:my_user_io|ps2_kbd_tx_state[2]                                                                                                                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; user_io:my_user_io|ps2_kbd_data                                                                                             ; user_io:my_user_io|ps2_kbd_data                                                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[1]                                                ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[1]                                                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[2]                                                ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[2]                                                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[3]                                                ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[3]                                                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[0]                                            ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[0]                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[1]                                            ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[1]                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[2]                                            ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[2]                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[3]                                            ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[3]                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|pending_extended_reg                                       ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|pending_extended_reg                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|pending_keyup_reg                                          ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|pending_keyup_reg                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[120]                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[120]                                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|count[0]                                                     ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|count[0]                                                                                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[22]                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[22]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[118]                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[118]                                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[51]                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[51]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[287]                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[287]                                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; paddle_mode_reg                                                                                                             ; paddle_mode_reg                                                                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[102]                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[102]                                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[62]                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[62]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[13]                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[13]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[58]                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[58]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[66]                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[66]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[90]                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[90]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[93]                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[93]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[82]                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[82]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[76]                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[76]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[84]                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[84]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[78]                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[78]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[273]                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[273]                                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[74]                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[74]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[29]                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[29]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[41]                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[41]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[59]                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[59]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[37]                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[37]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[43]                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[43]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[68]                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[68]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[45]                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[45]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[70]                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[70]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[42]                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[42]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[65]                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[65]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[69]                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[69]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[35]                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[35]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[33]                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[33]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[73]                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[73]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[77]                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[77]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[53]                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[53]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[49]                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[49]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[276]                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[276]                                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[18]                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[18]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[369]                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[369]                                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[126]                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[126]                                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[131]                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[131]                                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[10]                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[10]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[1]                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[1]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[5]                                                   ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[5]                                                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|stretch                                                      ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|stretch                                                                                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[7]                                                   ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[7]                                                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[6]                                                   ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[6]                                                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[4]                                                   ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[4]                                                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[3]                                                   ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[3]                                                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[370]                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[370]                                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[1]                                                   ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[1]                                                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[363]                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[363]                                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[2]                                                   ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[2]                                                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[0]                                                   ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[0]                                                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[373]                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[373]                                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_reg                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_reg                                                                                                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.ready                                                  ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.ready                                                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; data_io:mist_data_io|abyte_cnt[1]                                                                                           ; data_io:mist_data_io|abyte_cnt[1]                                                                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; data_io:mist_data_io|abyte_cnt[2]                                                                                           ; data_io:mist_data_io|abyte_cnt[2]                                                                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; data_io:mist_data_io|abyte_cnt[0]                                                                                           ; data_io:mist_data_io|abyte_cnt[0]                                                                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; data_io:mist_data_io|hi                                                                                                     ; data_io:mist_data_io|hi                                                                                                                                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[3]                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[3]                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[4]                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[4]                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[6]                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[6]                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[7]                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[7]                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[9]                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[9]                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_16bit_reg                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_16bit_reg                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|first_line_of_instruction_reg          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|first_line_of_instruction_reg                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[2]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[2]                                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[15]                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[15]                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|vector_a2 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|vector_a2                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[22]                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[22]                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[8]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[8]                                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|cfg_enable  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|cfg_enable                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'SPI_SCK'                                                                                                                                                                                               ;
+-------+--------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                                  ; To Node                                                                                                 ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.397 ; osd:osd_inst|sbuf[1]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.427      ; 1.054      ;
; 0.402 ; osd:osd_inst|osd_enable                    ; osd:osd_inst|osd_enable                                                                                 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; user_io:my_user_io|cmd[0]                  ; user_io:my_user_io|cmd[0]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; user_io:my_user_io|cmd[2]                  ; user_io:my_user_io|cmd[2]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; user_io:my_user_io|cmd[1]                  ; user_io:my_user_io|cmd[1]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; user_io:my_user_io|cmd[3]                  ; user_io:my_user_io|cmd[3]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.669      ;
; 0.403 ; user_io:my_user_io|bit_cnt[1]              ; user_io:my_user_io|bit_cnt[1]                                                                           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; user_io:my_user_io|bit_cnt[2]              ; user_io:my_user_io|bit_cnt[2]                                                                           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; data_io:mist_data_io|bit_cnt[1]            ; data_io:mist_data_io|bit_cnt[1]                                                                         ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; data_io:mist_data_io|bit_cnt[2]            ; data_io:mist_data_io|bit_cnt[2]                                                                         ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; user_io:my_user_io|byte_cnt[0]             ; user_io:my_user_io|byte_cnt[0]                                                                          ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.669      ;
; 0.405 ; user_io:my_user_io|serial_out_rptr[0]      ; user_io:my_user_io|serial_out_rptr[0]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.069      ; 0.669      ;
; 0.417 ; data_io:mist_data_io|spi_receiver_strobe_r ; data_io:mist_data_io|spi_receiver_strobe_r                                                              ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.684      ;
; 0.418 ; user_io:my_user_io|bit_cnt[0]              ; user_io:my_user_io|bit_cnt[0]                                                                           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.684      ;
; 0.418 ; user_io:my_user_io|spi_receiver_strobe_r   ; user_io:my_user_io|spi_receiver_strobe_r                                                                ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.684      ;
; 0.418 ; data_io:mist_data_io|bit_cnt[0]            ; data_io:mist_data_io|bit_cnt[0]                                                                         ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.684      ;
; 0.429 ; osd:osd_inst|bcnt[7]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.421      ; 1.080      ;
; 0.430 ; osd:osd_inst|bcnt[1]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.420      ; 1.080      ;
; 0.432 ; osd:osd_inst|sbuf[5]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.424      ; 1.086      ;
; 0.436 ; osd:osd_inst|sbuf[3]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.424      ; 1.090      ;
; 0.445 ; osd:osd_inst|sbuf[2]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.425      ; 1.100      ;
; 0.446 ; osd:osd_inst|sbuf[4]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.424      ; 1.100      ;
; 0.447 ; osd:osd_inst|bcnt[4]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.421      ; 1.098      ;
; 0.450 ; osd:osd_inst|bcnt[2]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.420      ; 1.100      ;
; 0.451 ; osd:osd_inst|sbuf[6]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.424      ; 1.105      ;
; 0.453 ; osd:osd_inst|bcnt[8]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.420      ; 1.103      ;
; 0.468 ; osd:osd_inst|bcnt[4]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.420      ; 1.118      ;
; 0.469 ; osd:osd_inst|bcnt[10]                      ; osd:osd_inst|bcnt[10]                                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.735      ;
; 0.472 ; data_io:mist_data_io|sbuf[6]               ; data_io:mist_data_io|spi_byte_in[7]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.739      ;
; 0.473 ; osd:osd_inst|bcnt[6]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.421      ; 1.124      ;
; 0.473 ; data_io:mist_data_io|bit_cnt[0]            ; data_io:mist_data_io|bit_cnt[2]                                                                         ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.739      ;
; 0.476 ; data_io:mist_data_io|sbuf[3]               ; data_io:mist_data_io|spi_byte_in[4]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.743      ;
; 0.476 ; data_io:mist_data_io|sbuf[5]               ; data_io:mist_data_io|sbuf[6]                                                                            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.743      ;
; 0.477 ; data_io:mist_data_io|sbuf[3]               ; data_io:mist_data_io|sbuf[4]                                                                            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.744      ;
; 0.477 ; data_io:mist_data_io|bit_cnt[0]            ; data_io:mist_data_io|bit_cnt[1]                                                                         ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.743      ;
; 0.478 ; data_io:mist_data_io|sbuf[0]               ; data_io:mist_data_io|sbuf[1]                                                                            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.745      ;
; 0.478 ; data_io:mist_data_io|sbuf[0]               ; data_io:mist_data_io|spi_byte_in[1]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.745      ;
; 0.478 ; data_io:mist_data_io|sbuf[5]               ; data_io:mist_data_io|spi_byte_in[6]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.745      ;
; 0.479 ; user_io:my_user_io|sbuf[6]                 ; user_io:my_user_io|spi_byte_in[7]                                                                       ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.746      ;
; 0.483 ; user_io:my_user_io|sbuf[5]                 ; user_io:my_user_io|sbuf[6]                                                                              ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.750      ;
; 0.484 ; user_io:my_user_io|sbuf[5]                 ; user_io:my_user_io|spi_byte_in[6]                                                                       ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.751      ;
; 0.487 ; user_io:my_user_io|sbuf[3]                 ; user_io:my_user_io|sbuf[4]                                                                              ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.754      ;
; 0.487 ; user_io:my_user_io|sbuf[4]                 ; user_io:my_user_io|sbuf[5]                                                                              ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.754      ;
; 0.487 ; user_io:my_user_io|sbuf[3]                 ; user_io:my_user_io|spi_byte_in[4]                                                                       ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.754      ;
; 0.488 ; user_io:my_user_io|sbuf[4]                 ; user_io:my_user_io|spi_byte_in[5]                                                                       ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.755      ;
; 0.493 ; osd:osd_inst|bcnt[9]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.420      ; 1.143      ;
; 0.500 ; osd:osd_inst|sbuf[2]                       ; osd:osd_inst|sbuf[3]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.767      ;
; 0.500 ; osd:osd_inst|sbuf[2]                       ; osd:osd_inst|cmd[3]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.767      ;
; 0.509 ; user_io:my_user_io|sbuf[2]                 ; user_io:my_user_io|spi_byte_in[3]                                                                       ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.776      ;
; 0.638 ; user_io:my_user_io|sbuf[1]                 ; user_io:my_user_io|spi_byte_in[2]                                                                       ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.904      ;
; 0.642 ; osd:osd_inst|bcnt[0]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.420      ; 1.292      ;
; 0.643 ; osd:osd_inst|bcnt[3]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.421      ; 1.294      ;
; 0.645 ; user_io:my_user_io|sbuf[1]                 ; user_io:my_user_io|cmd[2]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.912      ;
; 0.653 ; data_io:mist_data_io|sbuf[2]               ; data_io:mist_data_io|sbuf[3]                                                                            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.920      ;
; 0.654 ; data_io:mist_data_io|sbuf[1]               ; data_io:mist_data_io|spi_byte_in[2]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.921      ;
; 0.654 ; data_io:mist_data_io|sbuf[4]               ; data_io:mist_data_io|spi_byte_in[5]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.921      ;
; 0.655 ; user_io:my_user_io|sbuf[0]                 ; user_io:my_user_io|cmd[1]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.922      ;
; 0.656 ; data_io:mist_data_io|sbuf[1]               ; data_io:mist_data_io|sbuf[2]                                                                            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.923      ;
; 0.656 ; data_io:mist_data_io|sbuf[2]               ; data_io:mist_data_io|spi_byte_in[3]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.923      ;
; 0.656 ; data_io:mist_data_io|sbuf[4]               ; data_io:mist_data_io|sbuf[5]                                                                            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.923      ;
; 0.667 ; user_io:my_user_io|sbuf[1]                 ; user_io:my_user_io|sbuf[2]                                                                              ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.934      ;
; 0.668 ; osd:osd_inst|bcnt[5]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.421      ; 1.319      ;
; 0.676 ; osd:osd_inst|sbuf[5]                       ; osd:osd_inst|cmd[6]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.943      ;
; 0.677 ; osd:osd_inst|sbuf[5]                       ; osd:osd_inst|sbuf[6]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.944      ;
; 0.684 ; osd:osd_inst|sbuf[4]                       ; osd:osd_inst|cmd[5]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.951      ;
; 0.685 ; osd:osd_inst|sbuf[4]                       ; osd:osd_inst|sbuf[5]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.952      ;
; 0.686 ; osd:osd_inst|sbuf[3]                       ; osd:osd_inst|sbuf[4]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.953      ;
; 0.687 ; osd:osd_inst|sbuf[3]                       ; osd:osd_inst|cmd[4]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.954      ;
; 0.687 ; osd:osd_inst|sbuf[0]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.427      ; 1.344      ;
; 0.697 ; user_io:my_user_io|sbuf[0]                 ; user_io:my_user_io|spi_byte_in[1]                                                                       ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.964      ;
; 0.698 ; user_io:my_user_io|sbuf[0]                 ; user_io:my_user_io|sbuf[1]                                                                              ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.965      ;
; 0.700 ; osd:osd_inst|bcnt[5]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.420      ; 1.350      ;
; 0.700 ; user_io:my_user_io|serial_out_rptr[2]      ; user_io:my_user_io|serial_out_rptr[2]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.069      ; 0.964      ;
; 0.701 ; user_io:my_user_io|serial_out_rptr[4]      ; user_io:my_user_io|serial_out_rptr[4]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.069      ; 0.965      ;
; 0.701 ; user_io:my_user_io|serial_out_rptr[5]      ; user_io:my_user_io|serial_out_rptr[5]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.069      ; 0.965      ;
; 0.702 ; user_io:my_user_io|serial_out_rptr[3]      ; user_io:my_user_io|serial_out_rptr[3]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.069      ; 0.966      ;
; 0.704 ; osd:osd_inst|bcnt[1]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.421      ; 1.355      ;
; 0.707 ; osd:osd_inst|bcnt[9]                       ; osd:osd_inst|bcnt[9]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.973      ;
; 0.708 ; osd:osd_inst|bcnt[1]                       ; osd:osd_inst|bcnt[1]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.974      ;
; 0.708 ; osd:osd_inst|bcnt[7]                       ; osd:osd_inst|bcnt[7]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.974      ;
; 0.708 ; osd:osd_inst|bcnt[9]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.421      ; 1.359      ;
; 0.708 ; data_io:mist_data_io|bit_cnt[1]            ; data_io:mist_data_io|bit_cnt[2]                                                                         ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.974      ;
; 0.710 ; osd:osd_inst|bcnt[2]                       ; osd:osd_inst|bcnt[2]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.976      ;
; 0.711 ; osd:osd_inst|bcnt[5]                       ; osd:osd_inst|bcnt[5]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.977      ;
; 0.711 ; osd:osd_inst|bcnt[7]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.420      ; 1.361      ;
; 0.713 ; osd:osd_inst|bcnt[8]                       ; osd:osd_inst|bcnt[8]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.979      ;
; 0.714 ; osd:osd_inst|bcnt[6]                       ; osd:osd_inst|bcnt[6]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.980      ;
; 0.716 ; osd:osd_inst|cnt[1]                        ; osd:osd_inst|cnt[1]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.983      ;
; 0.716 ; osd:osd_inst|cnt[3]                        ; osd:osd_inst|cnt[3]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.983      ;
; 0.718 ; user_io:my_user_io|byte_cnt[3]             ; user_io:my_user_io|byte_cnt[3]                                                                          ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.984      ;
; 0.718 ; user_io:my_user_io|bit_cnt[1]              ; user_io:my_user_io|bit_cnt[2]                                                                           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.984      ;
; 0.719 ; user_io:my_user_io|byte_cnt[6]             ; user_io:my_user_io|byte_cnt[6]                                                                          ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.985      ;
; 0.719 ; user_io:my_user_io|byte_cnt[8]             ; user_io:my_user_io|byte_cnt[8]                                                                          ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.985      ;
; 0.720 ; osd:osd_inst|cnt[2]                        ; osd:osd_inst|cnt[2]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.987      ;
; 0.720 ; user_io:my_user_io|byte_cnt[9]             ; user_io:my_user_io|byte_cnt[9]                                                                          ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.986      ;
; 0.722 ; user_io:my_user_io|serial_out_rptr[1]      ; user_io:my_user_io|serial_out_rptr[1]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.069      ; 0.986      ;
; 0.723 ; osd:osd_inst|cnt[4]                        ; osd:osd_inst|cnt[4]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.072      ; 0.990      ;
; 0.723 ; user_io:my_user_io|byte_cnt[5]             ; user_io:my_user_io|byte_cnt[5]                                                                          ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.989      ;
; 0.723 ; user_io:my_user_io|byte_cnt[7]             ; user_io:my_user_io|byte_cnt[7]                                                                          ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.071      ; 0.989      ;
; 0.723 ; user_io:my_user_io|serial_out_rptr[0]      ; user_io:my_user_io|serial_out_rptr[1]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.069      ; 0.987      ;
+-------+--------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                     ; To Node                                                                                                                                                                                                       ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 0.402 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_seq_data_state                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_seq_data_state                                       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                              ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; rom_loaded                                                                                                                                                                                                    ; rom_loaded                                                                                                                                                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_data_state                                                ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_data_state                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.403 ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                                                                                                                   ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                                                                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.417 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reset_state                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reset_state                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.684      ;
; 0.455 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[4] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[4] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.722      ;
; 0.456 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.723      ;
; 0.456 ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[0]                                                                                                                                          ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.723      ;
; 0.470 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[16]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[16]                                                                                                                                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.737      ;
; 0.471 ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[1]                                                                                                                                          ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[0]                                                                                                                                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.738      ;
; 0.473 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|tmp_seq_ena_state                                             ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_seq_ena_state                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.739      ;
; 0.474 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_init_state_1                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.740      ;
; 0.476 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate_state                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate2_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.743      ;
; 0.495 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.761      ;
; 0.508 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[3]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[3]                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.775      ;
; 0.510 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[6]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[6]                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.777      ;
; 0.511 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[0]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[0]                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.778      ;
; 0.518 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.784      ;
; 0.520 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.786      ;
; 0.521 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|idle_state                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_init_state                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.788      ;
; 0.522 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|idle_state                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_init_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.789      ;
; 0.607 ; switch_pal_ntsc:pll_switcher|pll_reconfig_write_from_rom                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_init_state                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.874      ;
; 0.622 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.888      ;
; 0.637 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[7]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[7]                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.904      ;
; 0.640 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[5]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[5]                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.907      ;
; 0.646 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[2]                                              ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[2]                                             ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.912      ;
; 0.647 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[1]                                              ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[1]                                             ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.913      ;
; 0.656 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[1]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[1]                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.921      ;
; 0.670 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_init_state                                                ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_first_state                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.937      ;
; 0.670 ; rom_loaded                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|reset_n_reg                                                                                                                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.937      ;
; 0.674 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate_state                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.941      ;
; 0.683 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.950      ;
; 0.683 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.950      ;
; 0.684 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.951      ;
; 0.685 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[11]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[11]                                                                                                                                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.952      ;
; 0.686 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[9]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[9]                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.953      ;
; 0.686 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[13]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[13]                                                                                                                                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.953      ;
; 0.687 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.954      ;
; 0.688 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[8]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[8]                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.955      ;
; 0.688 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[14]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[14]                                                                                                                                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.955      ;
; 0.689 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.956      ;
; 0.689 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[15]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[15]                                                                                                                                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.956      ;
; 0.690 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.957      ;
; 0.690 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.957      ;
; 0.690 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[10]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[10]                                                                                                                                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.957      ;
; 0.691 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[12]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[12]                                                                                                                                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.958      ;
; 0.694 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[3] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.960      ;
; 0.695 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.962      ;
; 0.695 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[5] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[5] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.961      ;
; 0.695 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[7] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[7] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.961      ;
; 0.695 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.962      ;
; 0.695 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[3] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.962      ;
; 0.696 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.963      ;
; 0.696 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.963      ;
; 0.696 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[4] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[4] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.963      ;
; 0.696 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[7] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[7] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.963      ;
; 0.697 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[3] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.964      ;
; 0.698 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.964      ;
; 0.698 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.965      ;
; 0.699 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[4] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[4] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.965      ;
; 0.700 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[6] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[6] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.966      ;
; 0.700 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[2] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.967      ;
; 0.705 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.972      ;
; 0.707 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[7] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[7] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.974      ;
; 0.708 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[5] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[5] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.975      ;
; 0.709 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[5] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[5] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.976      ;
; 0.709 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.976      ;
; 0.709 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[3] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.976      ;
; 0.711 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.978      ;
; 0.711 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_ena_state                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.977      ;
; 0.712 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[6] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[6] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.979      ;
; 0.712 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[2] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.979      ;
; 0.714 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[0]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[0]                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.981      ;
; 0.714 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[2] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.980      ;
; 0.719 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[1]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[1]  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.986      ;
; 0.720 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[0] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.987      ;
; 0.721 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.988      ;
; 0.722 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[2]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[2]  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.989      ;
; 0.722 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[4]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[4]  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.989      ;
; 0.724 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[5]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[5]  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.991      ;
; 0.724 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[0] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.990      ;
; 0.726 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[3]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[3]  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.993      ;
; 0.726 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[7]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[7]  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.993      ;
; 0.727 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[6]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[6]  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.994      ;
; 0.738 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[0] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.005      ;
; 0.742 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_counter_state                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.008      ;
; 0.748 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[0]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[0]  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.015      ;
; 0.751 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_ena_state                                                  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.017      ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'clk_27'                                                                                                                                                                 ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                 ; To Node                                                   ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 0.669      ;
; 0.418 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 0.684      ;
; 0.698 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 0.964      ;
; 0.700 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 0.966      ;
; 0.701 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 0.967      ;
; 0.883 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.149      ;
; 0.892 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.158      ;
; 0.894 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.160      ;
; 0.895 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.161      ;
; 1.013 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.279      ;
; 1.017 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.283      ;
; 1.018 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.284      ;
; 1.022 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.288      ;
; 1.032 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.298      ;
; 1.034 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.300      ;
; 1.034 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.300      ;
; 1.035 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.301      ;
; 1.036 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.302      ;
; 1.036 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.302      ;
; 1.061 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.327      ;
; 1.066 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.332      ;
; 1.118 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.384      ;
; 1.122 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.388      ;
; 1.122 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.388      ;
; 1.140 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.406      ;
; 1.143 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.409      ;
; 1.155 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.421      ;
; 1.164 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.430      ;
; 1.164 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.430      ;
; 1.172 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.438      ;
; 1.172 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.438      ;
; 1.173 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.439      ;
; 1.180 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.446      ;
; 1.184 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.450      ;
; 1.201 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.467      ;
; 1.201 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.467      ;
; 1.202 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.468      ;
; 1.205 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.471      ;
; 1.205 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.471      ;
; 1.206 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.472      ;
; 1.252 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.518      ;
; 1.300 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.566      ;
; 1.300 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.566      ;
; 1.301 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.567      ;
; 1.314 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.580      ;
; 1.332 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.598      ;
; 1.332 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.598      ;
; 1.335 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.601      ;
; 1.376 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.642      ;
; 1.392 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.658      ;
; 1.419 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.685      ;
; 1.423 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.689      ;
; 1.468 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.734      ;
; 1.468 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.734      ;
; 1.469 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.735      ;
; 1.471 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.737      ;
; 1.471 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.737      ;
; 1.472 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.738      ;
; 1.482 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.748      ;
; 1.485 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.071      ; 1.751      ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                             ;
+-------+---------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                     ; To Node                                                       ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.403 ; sdram_statemachine:sdram_adaptor|reply_reg                    ; sdram_statemachine:sdram_adaptor|reply_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.418 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.684      ;
; 0.455 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.722      ;
; 0.469 ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.735      ;
; 0.623 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.890      ;
; 0.687 ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.953      ;
; 0.688 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.954      ;
; 0.689 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.955      ;
; 0.689 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.955      ;
; 0.689 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.955      ;
; 0.692 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.958      ;
; 0.692 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.958      ;
; 0.693 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.960      ;
; 0.693 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.960      ;
; 0.693 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.960      ;
; 0.697 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.964      ;
; 0.697 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.964      ;
; 0.697 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.964      ;
; 0.698 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.965      ;
; 0.699 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.966      ;
; 0.703 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.970      ;
; 0.703 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.970      ;
; 0.704 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.971      ;
; 0.704 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.971      ;
; 0.705 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.972      ;
; 0.705 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.972      ;
; 0.709 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.976      ;
; 0.710 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.977      ;
; 0.710 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.977      ;
; 0.713 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.980      ;
; 0.713 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.980      ;
; 0.723 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.990      ;
; 0.725 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.991      ;
; 0.726 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.993      ;
; 0.727 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.993      ;
; 0.730 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.996      ;
; 0.731 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.997      ;
; 0.748 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.014      ;
; 0.774 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.040      ;
; 0.813 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.079      ;
; 0.981 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.247      ;
; 1.006 ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.272      ;
; 1.007 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.273      ;
; 1.010 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.276      ;
; 1.010 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.276      ;
; 1.013 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.279      ;
; 1.013 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.279      ;
; 1.013 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.279      ;
; 1.015 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.282      ;
; 1.015 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.282      ;
; 1.015 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.282      ;
; 1.016 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.283      ;
; 1.017 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.284      ;
; 1.018 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.285      ;
; 1.018 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.285      ;
; 1.021 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.288      ;
; 1.021 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.288      ;
; 1.021 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.288      ;
; 1.022 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.288      ;
; 1.023 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.290      ;
; 1.024 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.291      ;
; 1.025 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.292      ;
; 1.026 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.293      ;
; 1.026 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.293      ;
; 1.026 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.293      ;
; 1.026 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.292      ;
; 1.026 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.292      ;
; 1.030 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.297      ;
; 1.030 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.297      ;
; 1.030 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.297      ;
; 1.031 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.298      ;
; 1.031 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.298      ;
; 1.032 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.299      ;
; 1.033 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.300      ;
; 1.033 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.300      ;
; 1.034 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.301      ;
; 1.036 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.303      ;
; 1.040 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.307      ;
; 1.041 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.308      ;
; 1.041 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.308      ;
; 1.044 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.310      ;
; 1.047 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.314      ;
; 1.047 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.314      ;
; 1.049 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.315      ;
; 1.049 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.315      ;
; 1.055 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.321      ;
; 1.059 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.325      ;
; 1.064 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.330      ;
; 1.069 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.335      ;
; 1.070 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.336      ;
; 1.072 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.338      ;
; 1.084 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.350      ;
; 1.107 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.373      ;
; 1.108 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.374      ;
; 1.108 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.374      ;
; 1.111 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.378      ;
; 1.112 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.379      ;
; 1.118 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.385      ;
; 1.118 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.385      ;
+-------+---------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                   ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 2.111 ; sdram_statemachine:sdram_adaptor|cke_reg                                    ; SDRAM_CKE                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.256      ; 2.830      ;
; 2.225 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8                 ; SDRAM_DQ[8]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.334      ; 3.022      ;
; 2.225 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9                 ; SDRAM_DQ[9]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.334      ; 3.022      ;
; 2.228 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1                 ; SDRAM_DQ[1]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.341      ; 3.032      ;
; 2.232 ; sdram_statemachine:sdram_adaptor|dq_output_reg                              ; SDRAM_DQ[0]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.337      ; 3.032      ;
; 2.242 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11                ; SDRAM_DQ[11]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.327      ; 3.032      ;
; 2.242 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10                ; SDRAM_DQ[10]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.327      ; 3.032      ;
; 2.242 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12                ; SDRAM_DQ[12]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.327      ; 3.032      ;
; 2.242 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13                ; SDRAM_DQ[13]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.327      ; 3.032      ;
; 2.248 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_7                 ; SDRAM_DQ[7]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.281      ; 2.992      ;
; 2.248 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4                 ; SDRAM_DQ[4]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.281      ; 2.992      ;
; 2.248 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_6                 ; SDRAM_DQ[6]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.281      ; 2.992      ;
; 2.250 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14                ; SDRAM_DQ[14]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.329      ; 3.042      ;
; 2.250 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15                ; SDRAM_DQ[15]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.329      ; 3.042      ;
; 2.254 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3                 ; SDRAM_DQ[3]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.325      ; 3.042      ;
; 2.254 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2                 ; SDRAM_DQ[2]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.325      ; 3.042      ;
; 2.258 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_5                 ; SDRAM_DQ[5]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.281      ; 3.002      ;
; 2.716 ; sdram_statemachine:sdram_adaptor|ba_reg[1]                                  ; SDRAM_BA[1]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.270      ; 3.449      ;
; 2.720 ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]                             ; SDRAM_DQ[12]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.314      ; 3.497      ;
; 2.724 ; sdram_statemachine:sdram_adaptor|ras_n_reg                                  ; SDRAM_nRAS                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.272      ; 3.459      ;
; 2.725 ; sdram_statemachine:sdram_adaptor|addr_reg[0]                                ; SDRAM_A[0]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.271      ; 3.459      ;
; 2.725 ; sdram_statemachine:sdram_adaptor|ba_reg[0]                                  ; SDRAM_BA[0]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.271      ; 3.459      ;
; 2.725 ; sdram_statemachine:sdram_adaptor|cas_n_reg                                  ; SDRAM_nCAS                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.271      ; 3.459      ;
; 2.726 ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                ; SDRAM_A[1]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.270      ; 3.459      ;
; 2.726 ; sdram_statemachine:sdram_adaptor|addr_reg[10]                               ; SDRAM_A[10]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.270      ; 3.459      ;
; 2.727 ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                ; SDRAM_A[2]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.269      ; 3.459      ;
; 2.728 ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                             ; SDRAM_DQ[15]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.316      ; 3.507      ;
; 2.732 ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                              ; SDRAM_DQ[3]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.312      ; 3.507      ;
; 2.732 ; sdram_statemachine:sdram_adaptor|dq_out_reg[2]                              ; SDRAM_DQ[2]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.312      ; 3.507      ;
; 2.737 ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                ; SDRAM_A[3]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.269      ; 3.469      ;
; 2.737 ; sdram_statemachine:sdram_adaptor|we_n_reg                                   ; SDRAM_nWE                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.269      ; 3.469      ;
; 2.737 ; sdram_statemachine:sdram_adaptor|ldqm_reg                                   ; SDRAM_DQML                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.269      ; 3.469      ;
; 2.738 ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                              ; SDRAM_DQ[7]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.268      ; 3.469      ;
; 2.738 ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]                              ; SDRAM_DQ[4]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.268      ; 3.469      ;
; 2.738 ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                              ; SDRAM_DQ[6]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.268      ; 3.469      ;
; 2.739 ; sdram_statemachine:sdram_adaptor|addr_reg[4]                                ; SDRAM_A[4]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.305      ; 3.507      ;
; 2.748 ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]                              ; SDRAM_DQ[5]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.268      ; 3.479      ;
; 2.848 ; sdram_statemachine:sdram_adaptor|udqm_reg                                   ; SDRAM_DQMH                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.322      ; 3.633      ;
; 2.849 ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]                              ; SDRAM_DQ[8]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.321      ; 3.633      ;
; 2.849 ; sdram_statemachine:sdram_adaptor|dq_out_reg[9]                              ; SDRAM_DQ[9]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.321      ; 3.633      ;
; 2.852 ; sdram_statemachine:sdram_adaptor|dq_out_reg[1]                              ; SDRAM_DQ[1]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.328      ; 3.643      ;
; 2.856 ; sdram_statemachine:sdram_adaptor|dq_out_reg[0]                              ; SDRAM_DQ[0]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.324      ; 3.643      ;
; 2.866 ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                ; SDRAM_A[6]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.314      ; 3.643      ;
; 2.866 ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]                             ; SDRAM_DQ[11]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.314      ; 3.643      ;
; 2.866 ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                             ; SDRAM_DQ[10]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.314      ; 3.643      ;
; 2.866 ; sdram_statemachine:sdram_adaptor|dq_out_reg[13]                             ; SDRAM_DQ[13]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.314      ; 3.643      ;
; 2.867 ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                ; SDRAM_A[9]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.313      ; 3.643      ;
; 2.871 ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                ; SDRAM_A[7]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.309      ; 3.643      ;
; 2.871 ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                ; SDRAM_A[8]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.309      ; 3.643      ;
; 2.874 ; sdram_statemachine:sdram_adaptor|addr_reg[11]                               ; SDRAM_A[11]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.316      ; 3.653      ;
; 2.874 ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                             ; SDRAM_DQ[14]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.316      ; 3.653      ;
; 2.882 ; sdram_statemachine:sdram_adaptor|addr_reg[5]                                ; SDRAM_A[5]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 2.308      ; 3.653      ;
; 9.187 ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -6.853       ; -1.566     ; 0.970      ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                 ;
+-------+------------------------------------------------------------------------+--------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                              ; To Node                                                      ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------+--------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 3.126 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.292     ; 5.257      ;
; 3.126 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[7]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.292     ; 5.257      ;
; 3.126 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.292     ; 5.257      ;
; 3.126 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.292     ; 5.257      ;
; 3.134 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[0]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.348     ; 5.193      ;
; 3.149 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[9]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.345     ; 5.181      ;
; 3.149 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[8]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.345     ; 5.181      ;
; 3.159 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[1]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.352     ; 5.164      ;
; 3.163 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[11]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.338     ; 5.174      ;
; 3.163 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.336     ; 5.176      ;
; 3.163 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[10]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.338     ; 5.174      ;
; 3.163 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[3]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.336     ; 5.176      ;
; 3.163 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.172     ; 5.351      ;
; 3.163 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.172     ; 5.351      ;
; 3.163 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.172     ; 5.351      ;
; 3.163 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.172     ; 5.351      ;
; 3.163 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ba_reg[1]                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.174     ; 5.349      ;
; 3.163 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ras_n_reg                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.176     ; 5.347      ;
; 3.163 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cas_n_reg                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.175     ; 5.348      ;
; 3.163 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|we_n_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.173     ; 5.350      ;
; 3.163 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ldqm_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.173     ; 5.350      ;
; 3.163 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[0]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.175     ; 5.348      ;
; 3.163 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.174     ; 5.349      ;
; 3.163 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.173     ; 5.350      ;
; 3.163 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.173     ; 5.350      ;
; 3.163 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.174     ; 5.349      ;
; 3.164 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[14]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.340     ; 5.171      ;
; 3.164 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[13]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.338     ; 5.173      ;
; 3.164 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[12]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.338     ; 5.173      ;
; 3.164 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[15]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.340     ; 5.171      ;
; 3.164 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ba_reg[0]                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.175     ; 5.347      ;
; 3.168 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.217     ; 5.301      ;
; 3.170 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|udqm_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.226     ; 5.290      ;
; 3.171 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[0]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.228     ; 5.287      ;
; 3.176 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.212     ; 5.298      ;
; 3.176 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.218     ; 5.292      ;
; 3.177 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.220     ; 5.289      ;
; 3.184 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.213     ; 5.289      ;
; 3.184 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.213     ; 5.289      ;
; 3.186 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.225     ; 5.275      ;
; 3.186 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[9]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.225     ; 5.275      ;
; 3.194 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.209     ; 5.283      ;
; 3.196 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[1]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.232     ; 5.258      ;
; 3.200 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[2]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.216     ; 5.270      ;
; 3.200 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.216     ; 5.270      ;
; 3.200 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.218     ; 5.268      ;
; 3.200 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.218     ; 5.268      ;
; 3.201 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.218     ; 5.267      ;
; 3.201 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[13]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.218     ; 5.267      ;
; 3.201 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.220     ; 5.265      ;
; 3.201 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.220     ; 5.265      ;
; 3.350 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.185     ; 5.115      ;
; 3.350 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_5  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.185     ; 5.115      ;
; 3.350 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_6  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.185     ; 5.115      ;
; 3.350 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_7  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.185     ; 5.115      ;
; 3.358 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.241     ; 5.051      ;
; 3.373 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.238     ; 5.039      ;
; 3.373 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.238     ; 5.039      ;
; 3.383 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.245     ; 5.022      ;
; 3.387 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.229     ; 5.034      ;
; 3.387 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.229     ; 5.034      ;
; 3.387 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.231     ; 5.032      ;
; 3.387 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.231     ; 5.032      ;
; 3.388 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.231     ; 5.031      ;
; 3.388 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.231     ; 5.031      ;
; 3.388 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.233     ; 5.029      ;
; 3.388 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.233     ; 5.029      ;
; 3.669 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[1]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.173     ; 4.970      ;
; 3.669 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.173     ; 4.970      ;
; 3.669 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[3]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.173     ; 4.970      ;
; 3.669 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.173     ; 4.970      ;
; 3.669 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.173     ; 4.970      ;
; 3.669 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.174     ; 4.969      ;
; 3.669 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|reply_reg                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.178     ; 4.965      ;
; 3.669 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.174     ; 4.969      ;
; 3.669 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.173     ; 4.970      ;
; 3.669 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[7]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.173     ; 4.970      ;
; 3.669 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[8]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.173     ; 4.970      ;
; 3.669 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[9]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.173     ; 4.970      ;
; 3.669 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[10]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.173     ; 4.970      ;
; 3.669 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[11]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.173     ; 4.970      ;
; 3.669 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[12]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.173     ; 4.970      ;
; 3.669 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[13]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.173     ; 4.970      ;
; 3.669 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[0]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.173     ; 4.970      ;
; 3.669 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.174     ; 4.969      ;
; 3.670 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[25]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.168     ; 4.974      ;
; 3.670 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[27]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.168     ; 4.974      ;
; 3.670 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[30]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.168     ; 4.974      ;
; 3.670 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[29]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.168     ; 4.974      ;
; 3.670 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[28]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.168     ; 4.974      ;
; 3.670 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[31]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.169     ; 4.973      ;
; 3.670 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[5]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.176     ; 4.966      ;
; 3.670 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[7]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.176     ; 4.966      ;
; 3.670 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[4]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.176     ; 4.966      ;
; 3.670 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[6]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.176     ; 4.966      ;
; 3.670 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[1]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.176     ; 4.966      ;
; 3.670 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[2]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.176     ; 4.966      ;
; 3.670 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[3]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.176     ; 4.966      ;
; 3.670 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[9]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.168     ; 4.974      ;
; 3.670 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[11]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.168     ; 4.974      ;
+-------+------------------------------------------------------------------------+--------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                   ;
+--------+------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                              ; To Node                                                                                                                                                                                                       ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 10.072 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[0]                                                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.158     ; 7.393      ;
; 10.072 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg~_Duplicate_3                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.158     ; 7.393      ;
; 10.074 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[28]                                                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.168     ; 7.381      ;
; 10.074 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[26]                                                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.168     ; 7.381      ;
; 10.074 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[16]                                                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.168     ; 7.381      ;
; 10.074 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[18]                                                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.168     ; 7.381      ;
; 10.097 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[1]                                                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.155     ; 7.371      ;
; 10.106 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.163     ; 7.354      ;
; 10.106 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.163     ; 7.354      ;
; 10.111 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg~_Duplicate_1                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.165     ; 7.347      ;
; 10.111 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]                                                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.164     ; 7.348      ;
; 10.111 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]~_Duplicate_8                                                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.164     ; 7.348      ;
; 10.111 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[5]~_Duplicate_4                                                                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.164     ; 7.348      ;
; 10.130 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|compare_latch_reg[5]                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.165     ; 7.328      ;
; 10.130 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|keycode_latch_reg[5]                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.165     ; 7.328      ;
; 10.130 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|keycode_latch_reg[6]                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.165     ; 7.328      ;
; 10.130 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|compare_latch_reg[4]                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.165     ; 7.328      ;
; 10.130 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|keycode_latch_reg[4]                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.165     ; 7.328      ;
; 10.130 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|compare_latch_reg[0]                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.165     ; 7.328      ;
; 10.130 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|compare_latch_reg[2]                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.165     ; 7.328      ;
; 10.130 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|compare_latch_reg[3]                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.165     ; 7.328      ;
; 10.130 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|compare_latch_reg[1]                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.165     ; 7.328      ;
; 10.130 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[6]                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.164     ; 7.329      ;
; 10.130 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[2]                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.164     ; 7.329      ;
; 10.130 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[2]                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.164     ; 7.329      ;
; 10.130 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[3]                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.164     ; 7.329      ;
; 10.130 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[3]                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.164     ; 7.329      ;
; 10.130 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[5]                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.164     ; 7.329      ;
; 10.130 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[5]                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.164     ; 7.329      ;
; 10.130 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[7]                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.164     ; 7.329      ;
; 10.130 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[7]                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.164     ; 7.329      ;
; 10.130 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|cntr_g7h:cntr5|counter_reg_bit[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.170     ; 7.323      ;
; 10.130 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[4]                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.164     ; 7.329      ;
; 10.130 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|keycode_latch_reg[3]                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.165     ; 7.328      ;
; 10.130 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|keycode_latch_reg[0]                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.165     ; 7.328      ;
; 10.130 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|last_bus_reg[0]                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.178     ; 7.315      ;
; 10.135 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[2]~_Duplicate_1                                                                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.140     ; 7.348      ;
; 10.136 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[13]                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.165     ; 7.322      ;
; 10.136 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pot0_reg[5]                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.164     ; 7.323      ;
; 10.136 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|serin_reg[5]                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.164     ; 7.323      ;
; 10.136 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_poly_17_9:poly_17_19_lfsr|select_9_17_del_reg                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.165     ; 7.322      ;
; 10.136 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[7]                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.165     ; 7.322      ;
; 10.136 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[6]                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.165     ; 7.322      ;
; 10.136 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[5]                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.165     ; 7.322      ;
; 10.136 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[4]                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.165     ; 7.322      ;
; 10.136 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[3]                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.165     ; 7.322      ;
; 10.136 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[2]                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.165     ; 7.322      ;
; 10.136 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[1]                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.165     ; 7.322      ;
; 10.136 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[0]                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.165     ; 7.322      ;
; 10.136 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[16]                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.165     ; 7.322      ;
; 10.136 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[14]                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.165     ; 7.322      ;
; 10.136 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|serin_reg[4]                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.164     ; 7.323      ;
; 10.136 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pot0_reg[4]                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.164     ; 7.323      ;
; 10.136 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|shift_reg[1][6]                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.160     ; 7.327      ;
; 10.136 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|shift_reg[0][6]                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.160     ; 7.327      ;
; 10.136 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|count_reg[0]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.160     ; 7.327      ;
; 10.136 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|shift_reg[1][7]                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.160     ; 7.327      ;
; 10.136 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|shift_reg[0][7]                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.160     ; 7.327      ;
; 10.136 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|count_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.160     ; 7.327      ;
; 10.136 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.160     ; 7.327      ;
; 10.136 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|shift_reg[1][2]                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.160     ; 7.327      ;
; 10.136 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|shift_reg[0][2]                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.160     ; 7.327      ;
; 10.136 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|count_reg[0]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.160     ; 7.327      ;
; 10.136 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|shift_reg[1][3]                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.160     ; 7.327      ;
; 10.136 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|shift_reg[0][3]                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.160     ; 7.327      ;
; 10.136 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|count_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.160     ; 7.327      ;
; 10.136 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|shift_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.160     ; 7.327      ;
; 10.136 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|serin_reg[3]                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.164     ; 7.323      ;
; 10.136 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pot0_reg[3]                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.164     ; 7.323      ;
; 10.136 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpm0_raw_reg[7]                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.159     ; 7.328      ;
; 10.136 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpf2_snap_reg[6]                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.159     ; 7.328      ;
; 10.136 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpm0_raw_reg[6]                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.159     ; 7.328      ;
; 10.136 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpm0_snap_reg[6]                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.159     ; 7.328      ;
; 10.136 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpf2_snap_reg[5]                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.159     ; 7.328      ;
; 10.136 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpm0_raw_reg[5]                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.159     ; 7.328      ;
; 10.136 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpm0_snap_reg[5]                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.159     ; 7.328      ;
; 10.136 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpm0_raw_reg[4]                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.159     ; 7.328      ;
; 10.136 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpm0_snap_reg[4]                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.159     ; 7.328      ;
; 10.136 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpm0_raw_reg[3]                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.159     ; 7.328      ;
; 10.136 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpm0_raw_reg[1]                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.159     ; 7.328      ;
; 10.137 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|skctl_reg[2]                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.163     ; 7.323      ;
; 10.137 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|allpot_reg[7]                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.168     ; 7.318      ;
; 10.137 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|serin_bitcount_reg[0]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.165     ; 7.321      ;
; 10.137 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|serin_bitcount_reg[2]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.165     ; 7.321      ;
; 10.137 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|serin_bitcount_reg[1]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.165     ; 7.321      ;
; 10.137 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|serin_bitcount_reg[3]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.165     ; 7.321      ;
; 10.137 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|serin_shift_reg[9]                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.165     ; 7.321      ;
; 10.137 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vscrol_raw_reg[0]                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.159     ; 7.327      ;
; 10.137 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vscrol_raw_reg[1]                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.159     ; 7.327      ;
; 10.137 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audctl_reg[3]                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.171     ; 7.315      ;
; 10.137 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audctl_reg[5]                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.171     ; 7.315      ;
; 10.137 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|wide_delay_line:audctl_delay|shift_reg[0][5]                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.171     ; 7.315      ;
; 10.137 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|wide_delay_line:audf2_delay|shift_reg[0][6]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.171     ; 7.315      ;
; 10.137 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audctl_reg[7]                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.171     ; 7.315      ;
; 10.137 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|wide_delay_line:audctl_delay|shift_reg[0][7]                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.171     ; 7.315      ;
; 10.137 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|last_bus_reg[7]                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.165     ; 7.321      ;
; 10.137 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|serin_shift_reg[8]                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.165     ; 7.321      ;
; 10.137 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|serin_shift_reg[7]                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.165     ; 7.321      ;
; 10.137 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vscrol_raw_reg[2]                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.159     ; 7.327      ;
; 10.137 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|irqst_reg[6]                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.166     ; 7.320      ;
+--------+------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                         ; To Node                                                                                                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 1.443 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|dffe4                                                                 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|altsyncram_14b1:altsyncram2|ram_block5a0                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.379      ; 2.012      ;
; 1.999 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a59 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.351      ; 2.540      ;
; 1.999 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a58 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.351      ; 2.540      ;
; 1.999 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a57 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.351      ; 2.540      ;
; 1.999 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a56 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.351      ; 2.540      ;
; 1.999 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a55 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.351      ; 2.540      ;
; 1.999 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a54 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.351      ; 2.540      ;
; 1.999 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a53 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.351      ; 2.540      ;
; 1.999 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a52 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.351      ; 2.540      ;
; 1.999 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a51 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.351      ; 2.540      ;
; 1.999 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a50 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.351      ; 2.540      ;
; 1.999 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a49 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.351      ; 2.540      ;
; 1.999 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a48 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.351      ; 2.540      ;
; 1.999 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a31 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.351      ; 2.540      ;
; 1.999 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a30 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.351      ; 2.540      ;
; 1.999 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a29 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.351      ; 2.540      ;
; 1.999 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a28 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.351      ; 2.540      ;
; 1.999 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a27 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.351      ; 2.540      ;
; 1.999 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a26 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.351      ; 2.540      ;
; 1.999 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a25 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.351      ; 2.540      ;
; 1.999 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a24 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.351      ; 2.540      ;
; 1.999 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a23 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.351      ; 2.540      ;
; 1.999 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a22 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.351      ; 2.540      ;
; 1.999 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a21 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.351      ; 2.540      ;
; 1.999 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a20 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.351      ; 2.540      ;
; 1.999 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a19 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.351      ; 2.540      ;
; 1.999 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a18 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.351      ; 2.540      ;
; 1.999 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a17 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.351      ; 2.540      ;
; 1.999 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.351      ; 2.540      ;
; 2.321 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a63 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.856      ;
; 2.321 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a62 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.856      ;
; 2.321 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a61 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.856      ;
; 2.321 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a60 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.856      ;
; 2.321 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a47 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.856      ;
; 2.321 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a46 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.856      ;
; 2.321 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a45 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.856      ;
; 2.321 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a44 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.856      ;
; 2.321 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a43 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.856      ;
; 2.321 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a42 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.856      ;
; 2.321 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a41 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.856      ;
; 2.321 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a40 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.856      ;
; 2.321 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a39 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.856      ;
; 2.321 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a38 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.856      ;
; 2.321 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a37 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.856      ;
; 2.321 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a36 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.856      ;
; 2.321 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a35 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.856      ;
; 2.321 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a34 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.856      ;
; 2.321 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a33 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.856      ;
; 2.321 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a32 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.856      ;
; 2.321 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a15 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.856      ;
; 2.321 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a14 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.856      ;
; 2.321 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a13 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.856      ;
; 2.321 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a12 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.856      ;
; 2.321 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a11 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.856      ;
; 2.321 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a10 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.856      ;
; 2.321 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a9  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.856      ;
; 2.321 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a8  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.856      ;
; 2.321 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a7  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.856      ;
; 2.321 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a6  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.856      ;
; 2.321 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a5  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.856      ;
; 2.321 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a4  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.856      ;
; 2.321 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a3  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.856      ;
; 2.321 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a2  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.856      ;
; 2.321 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a1  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.856      ;
; 2.321 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 2.856      ;
; 3.609 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ioctl_state.IOCTL_IDLE~_Duplicate_7                                                                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.602      ; 4.406      ;
; 3.609 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|refresh_sreg                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.602      ; 4.406      ;
; 3.614 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ioctl_state.IOCTL_IDLE~_Duplicate_5                                                                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.612      ; 4.421      ;
; 3.932 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ioctl_state.IOCTL_IDLE~_Duplicate_3                                                                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.651      ; 4.778      ;
; 4.034 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[20]                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.185      ; 4.414      ;
; 4.035 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_lpf_p2[14]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 4.406      ;
; 4.035 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p1[13]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.177      ; 4.407      ;
; 4.035 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p1[14]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.177      ; 4.407      ;
; 4.035 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p1[15]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.177      ; 4.407      ;
; 4.035 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p1[16]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.177      ; 4.407      ;
; 4.035 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p1[17]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.177      ; 4.407      ;
; 4.035 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_lpf_p2[15]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 4.406      ;
; 4.035 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_lpf_p2[16]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 4.406      ;
; 4.035 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p1[18]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.177      ; 4.407      ;
; 4.035 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p2[15]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 4.406      ;
; 4.035 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p1[19]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.177      ; 4.407      ;
; 4.035 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_lpf_p2[17]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 4.406      ;
; 4.035 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p2[16]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 4.406      ;
; 4.035 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p1[20]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.177      ; 4.407      ;
; 4.035 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_lpf_p2[18]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 4.406      ;
; 4.035 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p2[17]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 4.406      ;
; 4.035 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_lpf_p2[19]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 4.406      ;
; 4.035 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p1[21]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.177      ; 4.407      ;
; 4.035 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p2[18]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 4.406      ;
; 4.035 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p1[22]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.177      ; 4.407      ;
; 4.035 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_lpf_p2[20]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 4.406      ;
; 4.035 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p2[19]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 4.406      ;
; 4.035 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_lpf_p2[21]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 4.406      ;
; 4.035 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p1[23]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.177      ; 4.407      ;
; 4.035 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p2[20]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 4.406      ;
; 4.035 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_lpf_p2[22]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 4.406      ;
; 4.035 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p2[21]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 4.406      ;
; 4.035 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_lpf_p2[23]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 4.406      ;
; 4.035 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p2[22]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 4.406      ;
; 4.035 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p2[14]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 4.406      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                   ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                              ; To Node                                                       ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 4.025 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cke_reg                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 4.418      ;
; 4.027 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 4.416      ;
; 4.027 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 4.416      ;
; 4.027 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 4.416      ;
; 4.027 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 4.416      ;
; 4.027 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 4.416      ;
; 4.027 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 4.416      ;
; 4.027 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 4.416      ;
; 4.027 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 4.416      ;
; 4.027 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 4.416      ;
; 4.027 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 4.416      ;
; 4.027 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 4.416      ;
; 4.030 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 4.424      ;
; 4.030 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 4.424      ;
; 4.030 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 4.424      ;
; 4.030 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 4.424      ;
; 4.030 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 4.424      ;
; 4.030 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 4.424      ;
; 4.030 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 4.424      ;
; 4.030 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 4.424      ;
; 4.030 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 4.424      ;
; 4.030 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 4.424      ;
; 4.030 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 4.424      ;
; 4.030 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 4.424      ;
; 4.045 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.165      ; 4.424      ;
; 4.045 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.165      ; 4.424      ;
; 4.045 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.165      ; 4.424      ;
; 4.045 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.165      ; 4.424      ;
; 4.045 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.165      ; 4.424      ;
; 4.045 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.165      ; 4.424      ;
; 4.045 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.165      ; 4.424      ;
; 4.045 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.165      ; 4.424      ;
; 4.045 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.165      ; 4.424      ;
; 4.045 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.165      ; 4.424      ;
; 4.045 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.165      ; 4.424      ;
; 4.045 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.165      ; 4.424      ;
; 4.045 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.165      ; 4.424      ;
; 4.045 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.165      ; 4.424      ;
; 4.046 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.164      ; 4.424      ;
; 4.046 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[25]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 4.431      ;
; 4.046 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|reply_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.160      ; 4.420      ;
; 4.046 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.164      ; 4.424      ;
; 4.046 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.164      ; 4.424      ;
; 4.047 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[27]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.170      ; 4.431      ;
; 4.047 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[30]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.170      ; 4.431      ;
; 4.047 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[29]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.170      ; 4.431      ;
; 4.047 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[28]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.170      ; 4.431      ;
; 4.047 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[31]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 4.430      ;
; 4.047 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[5]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 4.423      ;
; 4.047 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[7]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 4.423      ;
; 4.047 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[4]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 4.423      ;
; 4.047 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[6]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 4.423      ;
; 4.047 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[1]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 4.423      ;
; 4.047 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[2]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 4.423      ;
; 4.047 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[3]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 4.423      ;
; 4.047 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[9]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.170      ; 4.431      ;
; 4.047 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[11]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.170      ; 4.431      ;
; 4.047 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[8]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 4.430      ;
; 4.047 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[23]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 4.430      ;
; 4.047 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[13]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.170      ; 4.431      ;
; 4.047 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[15]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 4.430      ;
; 4.047 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[22]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.170      ; 4.431      ;
; 4.047 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[0]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 4.423      ;
; 4.047 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[14]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.170      ; 4.431      ;
; 4.047 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[12]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.170      ; 4.431      ;
; 4.047 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[26]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.170      ; 4.431      ;
; 4.047 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[19]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 4.430      ;
; 4.047 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[17]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.170      ; 4.431      ;
; 4.047 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[21]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.170      ; 4.431      ;
; 4.047 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[24]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 4.430      ;
; 4.047 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[16]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 4.430      ;
; 4.047 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[10]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.170      ; 4.431      ;
; 4.047 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[18]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.170      ; 4.431      ;
; 4.047 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[20]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.170      ; 4.431      ;
; 4.218 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_6   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 4.524      ;
; 4.218 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_7   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 4.524      ;
; 4.219 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 4.525      ;
; 4.219 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_5   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 4.525      ;
; 4.233 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.108      ; 4.489      ;
; 4.233 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.108      ; 4.489      ;
; 4.236 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.109      ; 4.493      ;
; 4.236 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.109      ; 4.493      ;
; 4.237 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.110      ; 4.495      ;
; 4.237 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.110      ; 4.495      ;
; 4.239 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.112      ; 4.499      ;
; 4.239 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.112      ; 4.499      ;
; 4.241 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.095      ; 4.484      ;
; 4.256 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.102      ; 4.506      ;
; 4.256 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.102      ; 4.506      ;
; 4.274 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.099      ; 4.521      ;
; 4.553 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.172      ; 4.856      ;
; 4.553 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.172      ; 4.856      ;
; 4.553 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ba_reg[1]                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.170      ; 4.854      ;
; 4.553 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ras_n_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 4.852      ;
; 4.553 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cas_n_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 4.853      ;
; 4.553 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[0]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 4.853      ;
; 4.553 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[2]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 4.855      ;
; 4.553 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[10]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.170      ; 4.854      ;
; 4.554 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.172      ; 4.857      ;
; 4.554 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.172      ; 4.857      ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                             ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                 ; Clock Edge ; Target                                                        ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------+
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cke_reg                      ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[0]              ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[15]             ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[16]             ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[19]             ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[1]              ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[23]             ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[24]             ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[25]             ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[2]              ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[31]             ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[3]              ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[4]              ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[5]              ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[6]              ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[7]              ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[8]              ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ;
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[10]             ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[11]             ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[12]             ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[13]             ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[14]             ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[17]             ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[18]             ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[20]             ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[21]             ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[22]             ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[26]             ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[27]             ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[28]             ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[29]             ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[30]             ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[9]              ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|reply_reg                    ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ;
; 4.104 ; 4.320        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ;
; 4.205 ; 4.355        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]               ;
; 4.205 ; 4.355        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]               ;
; 4.206 ; 4.356        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[4]                  ;
; 4.206 ; 4.356        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[5]                  ;
; 4.206 ; 4.356        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[7]                  ;
; 4.206 ; 4.356        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[8]                  ;
; 4.206 ; 4.356        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[0]                ;
; 4.206 ; 4.356        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]               ;
; 4.206 ; 4.356        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]               ;
; 4.206 ; 4.356        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]               ;
; 4.206 ; 4.356        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[13]               ;
; 4.206 ; 4.356        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|udqm_reg                     ;
; 4.207 ; 4.357        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[6]                  ;
; 4.207 ; 4.357        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[1]                ;
; 4.207 ; 4.357        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]                ;
; 4.207 ; 4.357        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[9]                ;
; 4.208 ; 4.358        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[11]                 ;
; 4.208 ; 4.358        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[9]                  ;
; 4.210 ; 4.360        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[0]                  ;
; 4.210 ; 4.360        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[10]                 ;
; 4.210 ; 4.360        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[1]                  ;
; 4.210 ; 4.360        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[2]                  ;
; 4.210 ; 4.360        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[3]                  ;
; 4.210 ; 4.360        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|ba_reg[0]                    ;
; 4.210 ; 4.360        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|ba_reg[1]                    ;
; 4.210 ; 4.360        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cas_n_reg                    ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                     ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                 ; Clock Edge ; Target                                                                                                                                ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+
; 4.167 ; 4.167        ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK                                                                                                                             ;
; 4.167 ; 4.167        ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK~output|o                                                                                                                    ;
; 4.244 ; 4.370        ; 0.126          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 4.286 ; 4.286        ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK~output|i                                                                                                                    ;
; 4.329 ; 8.810        ; 4.481          ; Port Rate        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK                                                                                                                             ;
; 4.330 ; 4.439        ; 0.109          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 4.370 ; 4.370        ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 4.370 ; 4.370        ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|outclk                                                 ;
; 4.439 ; 4.439        ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 4.439 ; 4.439        ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|outclk                                                 ;
; 4.521 ; 4.521        ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK~output|i                                                                                                                    ;
; 4.640 ; 4.640        ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK                                                                                                                             ;
; 4.640 ; 4.640        ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK~output|o                                                                                                                    ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                         ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                 ; Clock Edge ; Target                                                                                                                                                    ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; 8.400 ; 8.782        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[0] ;
; 8.400 ; 8.782        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[1] ;
; 8.400 ; 8.782        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[2] ;
; 8.400 ; 8.782        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[3] ;
; 8.400 ; 8.782        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[4] ;
; 8.400 ; 8.782        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[10]      ;
; 8.400 ; 8.782        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[11]      ;
; 8.400 ; 8.782        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[12]      ;
; 8.400 ; 8.782        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[13]      ;
; 8.400 ; 8.782        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[14]      ;
; 8.400 ; 8.782        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[15]      ;
; 8.400 ; 8.782        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[16]      ;
; 8.400 ; 8.782        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[17]      ;
; 8.400 ; 8.782        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[18]      ;
; 8.400 ; 8.782        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[19]      ;
; 8.400 ; 8.782        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[20]      ;
; 8.400 ; 8.782        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[5]       ;
; 8.400 ; 8.782        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[6]       ;
; 8.400 ; 8.782        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[7]       ;
; 8.400 ; 8.782        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[8]       ;
; 8.400 ; 8.782        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[9]       ;
; 8.443 ; 8.659        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|state[1]                                ;
; 8.443 ; 8.659        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]~_Duplicate_6                                                                                           ;
; 8.443 ; 8.659        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[13]                                                                                                        ;
; 8.443 ; 8.659        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[4]~_Duplicate_3                                                                                            ;
; 8.444 ; 8.826        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[0] ;
; 8.444 ; 8.826        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[1] ;
; 8.444 ; 8.826        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[2] ;
; 8.444 ; 8.826        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[3] ;
; 8.444 ; 8.826        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[4] ;
; 8.444 ; 8.826        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[10]      ;
; 8.444 ; 8.826        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[11]      ;
; 8.444 ; 8.826        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[12]      ;
; 8.444 ; 8.826        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[13]      ;
; 8.444 ; 8.826        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[14]      ;
; 8.444 ; 8.826        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[15]      ;
; 8.444 ; 8.826        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[16]      ;
; 8.444 ; 8.826        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[17]      ;
; 8.444 ; 8.826        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[18]      ;
; 8.444 ; 8.826        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[19]      ;
; 8.444 ; 8.826        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[20]      ;
; 8.444 ; 8.826        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[5]       ;
; 8.444 ; 8.826        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[6]       ;
; 8.444 ; 8.826        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[7]       ;
; 8.444 ; 8.826        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[8]       ;
; 8.444 ; 8.826        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[9]       ;
; 8.447 ; 8.663        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]                                   ;
; 8.448 ; 8.664        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[2]~_Duplicate_8                             ;
; 8.448 ; 8.664        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; data_io:mist_data_io|ioctl_wr                                                                                                                             ;
; 8.449 ; 8.665        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Y[4]                                          ;
; 8.449 ; 8.665        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[29]~_Duplicate_7                      ;
; 8.449 ; 8.665        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[38]                                   ;
; 8.449 ; 8.665        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[5]                                                           ;
; 8.450 ; 8.666        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[27]                                   ;
; 8.450 ; 8.666        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[34]                                   ;
; 8.450 ; 8.666        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[40]                                   ;
; 8.450 ; 8.666        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[0]                                                                                      ;
; 8.450 ; 8.666        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[10]                                                                                     ;
; 8.450 ; 8.666        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[11]                                                                                     ;
; 8.450 ; 8.666        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[12]                                                                                     ;
; 8.450 ; 8.666        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[15]                                                                                     ;
; 8.450 ; 8.666        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[17]                                                                                     ;
; 8.450 ; 8.666        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[1]                                                                                      ;
; 8.450 ; 8.666        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[5]                                                                                      ;
; 8.450 ; 8.666        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[6]                                                                                      ;
; 8.450 ; 8.666        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[7]                                                                                      ;
; 8.452 ; 8.668        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_READ_reg~_Duplicate_1                                                                                               ;
; 8.452 ; 8.668        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[18]                                                                                                        ;
; 8.452 ; 8.668        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[19]                                                                                                        ;
; 8.452 ; 8.668        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[20]                                                                                                        ;
; 8.452 ; 8.668        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[21]                                                                                                        ;
; 8.452 ; 8.668        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[22]                                                                                                        ;
; 8.452 ; 8.668        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[23]                                                                                                        ;
; 8.453 ; 8.669        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_reg[6]                                                     ;
; 8.453 ; 8.669        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_reg[7]                                                     ;
; 8.453 ; 8.669        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[0]                                          ;
; 8.453 ; 8.669        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[1]                                          ;
; 8.453 ; 8.669        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[2]                                          ;
; 8.453 ; 8.669        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[4]~_Duplicate_3                             ;
; 8.453 ; 8.669        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[5]                                          ;
; 8.453 ; 8.669        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[6]                                          ;
; 8.453 ; 8.669        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[7]                                          ;
; 8.453 ; 8.669        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|PC[4]                                         ;
; 8.453 ; 8.669        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|PC[8]                                         ;
; 8.453 ; 8.669        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[0]                                          ;
; 8.453 ; 8.669        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Y[1]                                          ;
; 8.453 ; 8.669        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; user_io:my_user_io|status[5]                                                                                                                              ;
; 8.453 ; 8.669        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[25]                                                                                                      ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]                                                   ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[4]                                                   ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                                                   ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                                                   ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[6]                                          ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[7]~_Duplicate_10                            ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[4]                                          ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[0]                                     ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[4]                                     ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[5]                                     ;
; 8.454 ; 8.670        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|processInt                                    ;
; 8.455 ; 8.671        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|PC[0]                                         ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                           ;
+--------+--------------+----------------+------------------+----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                ; Clock Edge ; Target                                                                                     ;
+--------+--------------+----------------+------------------+----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------+
; 16.280 ; 16.280       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 16.280 ; 16.280       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 16.283 ; 16.283       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 16.294 ; 16.294       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 16.294 ; 16.294       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 16.294 ; 16.294       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 16.294 ; 16.294       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 16.335 ; 16.335       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 16.335 ; 16.335       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 16.335 ; 16.335       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 16.335 ; 16.335       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 16.347 ; 16.347       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 16.350 ; 16.350       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 16.350 ; 16.350       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
+--------+--------------+----------------+------------------+----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'clk_27'                                                                                                               ;
+--------+--------------+----------------+------------------+--------+------------+--------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target                                                                         ;
+--------+--------------+----------------+------------------+--------+------------+--------------------------------------------------------------------------------+
; 18.270 ; 18.454       ; 0.184          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                      ;
; 18.270 ; 18.454       ; 0.184          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                      ;
; 18.270 ; 18.454       ; 0.184          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                      ;
; 18.270 ; 18.454       ; 0.184          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                      ;
; 18.270 ; 18.454       ; 0.184          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                      ;
; 18.270 ; 18.454       ; 0.184          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                      ;
; 18.270 ; 18.454       ; 0.184          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                      ;
; 18.270 ; 18.454       ; 0.184          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                      ;
; 18.270 ; 18.454       ; 0.184          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                        ;
; 18.344 ; 18.344       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                       ;
; 18.344 ; 18.344       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|observablevcoout             ;
; 18.351 ; 18.351       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 18.351 ; 18.351       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 18.364 ; 18.580       ; 0.216          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                      ;
; 18.364 ; 18.580       ; 0.216          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                      ;
; 18.364 ; 18.580       ; 0.216          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                      ;
; 18.364 ; 18.580       ; 0.216          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                      ;
; 18.364 ; 18.580       ; 0.216          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                      ;
; 18.364 ; 18.580       ; 0.216          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                      ;
; 18.364 ; 18.580       ; 0.216          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                      ;
; 18.364 ; 18.580       ; 0.216          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                      ;
; 18.364 ; 18.580       ; 0.216          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                        ;
; 18.400 ; 18.400       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; CLOCK_27[0]~input|o                                                            ;
; 18.403 ; 18.403       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; CLOCK_27[0]~inputclkctrl|inclk[0]                                              ;
; 18.403 ; 18.403       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; CLOCK_27[0]~inputclkctrl|outclk                                                ;
; 18.403 ; 18.403       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[0]|clk                                          ;
; 18.403 ; 18.403       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[1]|clk                                          ;
; 18.403 ; 18.403       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[2]|clk                                          ;
; 18.403 ; 18.403       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[3]|clk                                          ;
; 18.403 ; 18.403       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[4]|clk                                          ;
; 18.403 ; 18.403       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[5]|clk                                          ;
; 18.403 ; 18.403       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[6]|clk                                          ;
; 18.403 ; 18.403       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[7]|clk                                          ;
; 18.403 ; 18.403       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_toggle_reg|clk                                            ;
; 18.423 ; 18.423       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|inclk[0]                     ;
; 18.430 ; 18.430       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; CLOCK_27[0]~input|i                                                            ;
; 18.519 ; 18.519       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; CLOCK_27[0]~input|i                                                            ;
; 18.606 ; 18.606       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 18.613 ; 18.613       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|inclk[0]                     ;
; 18.633 ; 18.633       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; CLOCK_27[0]~inputclkctrl|inclk[0]                                              ;
; 18.633 ; 18.633       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; CLOCK_27[0]~inputclkctrl|outclk                                                ;
; 18.634 ; 18.634       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[0]|clk                                          ;
; 18.634 ; 18.634       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[1]|clk                                          ;
; 18.634 ; 18.634       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[2]|clk                                          ;
; 18.634 ; 18.634       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[3]|clk                                          ;
; 18.634 ; 18.634       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[4]|clk                                          ;
; 18.634 ; 18.634       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[5]|clk                                          ;
; 18.634 ; 18.634       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[6]|clk                                          ;
; 18.634 ; 18.634       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[7]|clk                                          ;
; 18.634 ; 18.634       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_toggle_reg|clk                                            ;
; 18.637 ; 18.637       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; CLOCK_27[0]~input|o                                                            ;
; 18.684 ; 18.684       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 18.684 ; 18.684       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 18.691 ; 18.691       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                       ;
; 18.691 ; 18.691       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|observablevcoout             ;
; 33.037 ; 37.037       ; 4.000          ; Port Rate        ; clk_27 ; Rise       ; CLOCK_27[0]                                                                    ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                        ;
+--------+--------------+----------------+------------------+--------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'SPI_SCK'                                                                                                                                        ;
+--------+--------------+----------------+------------------+---------+------------+---------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock   ; Clock Edge ; Target                                                                                                  ;
+--------+--------------+----------------+------------------+---------+------------+---------------------------------------------------------------------------------------------------------+
; 20.401 ; 20.631       ; 0.230          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ;
; 20.401 ; 20.631       ; 0.230          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_we_reg       ;
; 20.401 ; 20.631       ; 0.230          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ;
; 20.401 ; 20.631       ; 0.230          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_we_reg       ;
; 20.403 ; 20.633       ; 0.230          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 20.403 ; 20.633       ; 0.230          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_datain_reg0  ;
; 20.507 ; 20.723       ; 0.216          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|SPI_MISO~reg0                                                                        ;
; 20.507 ; 20.723       ; 0.216          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[0]                                                                   ;
; 20.507 ; 20.723       ; 0.216          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[1]                                                                   ;
; 20.507 ; 20.723       ; 0.216          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[2]                                                                   ;
; 20.507 ; 20.723       ; 0.216          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[3]                                                                   ;
; 20.507 ; 20.723       ; 0.216          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[4]                                                                   ;
; 20.507 ; 20.723       ; 0.216          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[5]                                                                   ;
; 20.508 ; 20.724       ; 0.216          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|SPI_MISO~en                                                                          ;
; 20.551 ; 20.735       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cmd[3]                                                                                     ;
; 20.551 ; 20.735       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cmd[4]                                                                                     ;
; 20.551 ; 20.735       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cmd[5]                                                                                     ;
; 20.551 ; 20.735       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cmd[6]                                                                                     ;
; 20.551 ; 20.735       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cmd[7]                                                                                     ;
; 20.551 ; 20.735       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|sbuf[2]                                                                                    ;
; 20.551 ; 20.735       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|sbuf[3]                                                                                    ;
; 20.551 ; 20.735       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|sbuf[4]                                                                                    ;
; 20.551 ; 20.735       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|sbuf[5]                                                                                    ;
; 20.551 ; 20.735       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|sbuf[6]                                                                                    ;
; 20.551 ; 20.735       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_in[0]                                                                       ;
; 20.551 ; 20.735       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_receiver_strobe_r                                                                ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|bit_cnt[0]                                                                         ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|bit_cnt[1]                                                                         ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|bit_cnt[2]                                                                         ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_transfer_end_r                                                                 ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[0]                                                                                    ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[10]                                                                                   ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[1]                                                                                    ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[2]                                                                                    ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[3]                                                                                    ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[4]                                                                                    ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[5]                                                                                    ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[6]                                                                                    ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[7]                                                                                    ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[8]                                                                                    ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[9]                                                                                    ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cnt[0]                                                                                     ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cnt[1]                                                                                     ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cnt[2]                                                                                     ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cnt[3]                                                                                     ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cnt[4]                                                                                     ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|osd_enable                                                                                 ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|sbuf[0]                                                                                    ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|sbuf[1]                                                                                    ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[0]                                                                               ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[1]                                                                               ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[2]                                                                               ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[3]                                                                               ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|sbuf[0]                                                                              ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|sbuf[1]                                                                              ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|sbuf[2]                                                                              ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_in[1]                                                                       ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_in[2]                                                                       ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_in[3]                                                                       ;
; 20.552 ; 20.736       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[29]                                                         ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|sbuf[0]                                                                            ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|sbuf[1]                                                                            ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|sbuf[2]                                                                            ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|sbuf[3]                                                                            ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|sbuf[4]                                                                            ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|sbuf[5]                                                                            ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|sbuf[6]                                                                            ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[0]                                                                     ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[1]                                                                     ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[2]                                                                     ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[3]                                                                     ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[4]                                                                     ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[5]                                                                     ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[6]                                                                     ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[7]                                                                     ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_receiver_strobe_r                                                              ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[0]                                                                          ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[1]                                                                          ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[2]                                                                          ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[3]                                                                          ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[4]                                                                          ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[5]                                                                          ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[6]                                                                          ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[7]                                                                          ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[8]                                                                          ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[9]                                                                          ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[4]                                                                               ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[5]                                                                               ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[6]                                                                               ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[7]                                                                               ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|sbuf[3]                                                                              ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|sbuf[4]                                                                              ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|sbuf[5]                                                                              ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|sbuf[6]                                                                              ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_in[4]                                                                       ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_in[5]                                                                       ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_in[6]                                                                       ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_in[7]                                                                       ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_out[0]                                                                      ;
; 20.553 ; 20.737       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_out[1]                                                                      ;
+--------+--------------+----------------+------------------+---------+------------+---------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                              ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                                                                                                                                                                                        ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 40.596 ; 41.606       ; 1.010          ; Low Pulse Width  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                 ;
; 40.713 ; 41.723       ; 1.010          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                 ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                                          ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; rom_loaded                                                                                                                                                                                                    ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|rden_a_store                                                                                ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[10]                                                                                                                                                        ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[11]                                                                                                                                                        ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[12]                                                                                                                                                        ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[13]                                                                                                                                                        ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[14]                                                                                                                                                        ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[15]                                                                                                                                                        ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[16]                                                                                                                                                        ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[8]                                                                                                                                                         ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[9]                                                                                                                                                         ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_reconfig_write_from_rom                                                                                                                                                      ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                              ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|reset_n_reg                                                                                                                                                                      ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[0]                                                                                                                                          ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[1]                                                                                                                                          ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_data_state                                                 ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_ena_state                                                  ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_data_state                                                 ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                  ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_data_state                                                 ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_ena_state                                                  ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_data_state                                                 ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                  ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_data_state                                                 ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_ena_state                                                  ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[0]                                             ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[1]                                             ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[2]                                             ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[3]                                             ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[4]                                             ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[5]                                             ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[6]                                             ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[7]                                             ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[0]                                              ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[1]                                              ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[2]                                              ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[3]                                              ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[4]                                              ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[5]                                              ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[6]                                              ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[7]                                              ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate2_state                                           ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate_state                                            ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|idle_state                                                    ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[0] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[1] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[2] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[3] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[4] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[5] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[6] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[7] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[0] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[4] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[0] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[1] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[2] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[3] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[4] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[5] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[6] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[7] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[0] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[1] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[2] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[3] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[4] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[3] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[4] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[5] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[6] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[7] ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[0]  ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[1]  ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[2]  ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[3]  ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[4]  ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[5]  ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[6]  ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[7]  ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_counter_state                                        ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_init_state                                           ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                           ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_seq_data_state                                       ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_seq_ena_state                                        ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                           ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reset_state                                                   ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_data_state                                                ;
; 41.368 ; 41.584       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_first_state                                               ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                     ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+
; CONF_DATA0    ; SPI_SCK    ; 5.610 ; 6.180 ; Rise       ; SPI_SCK                                                               ;
; SPI_DI        ; SPI_SCK    ; 5.081 ; 5.356 ; Rise       ; SPI_SCK                                                               ;
; SPI_SS2       ; SPI_SCK    ; 1.276 ; 1.746 ; Rise       ; SPI_SCK                                                               ;
; SPI_SS3       ; SPI_SCK    ; 1.999 ; 2.531 ; Rise       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; clk_27     ; 2.634 ; 2.747 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 2.630 ; 2.743 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 2.634 ; 2.747 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 2.628 ; 2.741 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 2.628 ; 2.741 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 2.580 ; 2.697 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 2.590 ; 2.707 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 2.580 ; 2.697 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 2.580 ; 2.697 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 2.617 ; 2.730 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 2.617 ; 2.730 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 2.620 ; 2.733 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 2.620 ; 2.733 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 2.620 ; 2.733 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 2.620 ; 2.733 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 2.632 ; 2.745 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 2.632 ; 2.745 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                        ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; CONF_DATA0    ; SPI_SCK    ; -3.200 ; -3.346 ; Rise       ; SPI_SCK                                                               ;
; SPI_DI        ; SPI_SCK    ; 0.453  ; 0.141  ; Rise       ; SPI_SCK                                                               ;
; SPI_SS2       ; SPI_SCK    ; -0.969 ; -1.391 ; Rise       ; SPI_SCK                                                               ;
; SPI_SS3       ; SPI_SCK    ; -0.181 ; -0.431 ; Rise       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; clk_27     ; -1.684 ; -1.802 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; -1.737 ; -1.851 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; -1.741 ; -1.855 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; -1.734 ; -1.848 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; -1.734 ; -1.848 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; -1.684 ; -1.802 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; -1.694 ; -1.812 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; -1.684 ; -1.802 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; -1.684 ; -1.802 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; -1.724 ; -1.838 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; -1.724 ; -1.838 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; -1.726 ; -1.840 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; -1.726 ; -1.840 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; -1.727 ; -1.841 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; -1.727 ; -1.841 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; -1.738 ; -1.852 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; -1.738 ; -1.852 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                             ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK    ; 10.301 ; 9.612  ; Fall       ; SPI_SCK                                                               ;
; SDRAM_A[*]    ; clk_27     ; 3.319  ; 3.129  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; clk_27     ; 3.163  ; 2.970  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; clk_27     ; 3.164  ; 2.971  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; clk_27     ; 3.165  ; 2.972  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; clk_27     ; 3.175  ; 2.982  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; clk_27     ; 3.162  ; 2.985  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; clk_27     ; 3.319  ; 3.129  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; clk_27     ; 3.302  ; 3.112  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; clk_27     ; 3.307  ; 3.117  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; clk_27     ; 3.307  ; 3.117  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; clk_27     ; 3.303  ; 3.113  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; clk_27     ; 3.164  ; 2.971  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; clk_27     ; 3.310  ; 3.120  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; clk_27     ; 3.162  ; 2.969  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; clk_27     ; 3.162  ; 2.969  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; clk_27     ; 3.154  ; 2.961  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CKE     ; clk_27     ; 2.450  ; 2.326  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; clk_27     ; 3.310  ; 3.120  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 3.291  ; 3.101  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 3.287  ; 3.097  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 3.155  ; 2.978  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 3.155  ; 2.978  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 3.176  ; 2.983  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 3.186  ; 2.993  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 3.176  ; 2.983  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 3.176  ; 2.983  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 3.284  ; 3.094  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 3.284  ; 3.094  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 3.302  ; 3.112  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 3.302  ; 3.112  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 3.142  ; 2.965  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 3.301  ; 3.111  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 3.310  ; 3.120  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 3.151  ; 2.974  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH    ; clk_27     ; 3.284  ; 3.094  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML    ; clk_27     ; 3.175  ; 2.982  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nCAS    ; clk_27     ; 3.163  ; 2.970  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nRAS    ; clk_27     ; 3.162  ; 2.969  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nWE     ; clk_27     ; 3.175  ; 2.982  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; VGA_B[*]      ; clk_27     ; 23.338 ; 22.872 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; clk_27     ; 22.602 ; 22.099 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; clk_27     ; 23.062 ; 22.627 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; clk_27     ; 23.338 ; 22.872 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; clk_27     ; 22.474 ; 22.077 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[4]     ; clk_27     ; 22.357 ; 21.891 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[5]     ; clk_27     ; 22.292 ; 21.648 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; clk_27     ; 21.605 ; 21.035 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; clk_27     ; 21.605 ; 21.035 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; clk_27     ; 21.329 ; 20.749 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; clk_27     ; 21.546 ; 20.808 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; clk_27     ; 20.845 ; 20.381 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[4]     ; clk_27     ; 20.494 ; 20.289 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[5]     ; clk_27     ; 18.569 ; 17.532 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS        ; clk_27     ; 8.335  ; 7.703  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]      ; clk_27     ; 24.519 ; 24.051 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]     ; clk_27     ; 24.276 ; 23.899 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]     ; clk_27     ; 24.335 ; 23.981 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]     ; clk_27     ; 24.519 ; 24.051 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]     ; clk_27     ; 23.908 ; 23.578 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[4]     ; clk_27     ; 23.996 ; 23.576 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[5]     ; clk_27     ; 23.142 ; 22.929 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS        ; clk_27     ; 7.680  ; 6.861  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; clk_27     ; -0.884 ;        ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; clk_27     ;        ; -1.122 ; Fall       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                     ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK    ; 10.098 ; 9.418  ; Fall       ; SPI_SCK                                                               ;
; SDRAM_A[*]    ; clk_27     ; 2.394  ; 2.207  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; clk_27     ; 2.396  ; 2.207  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; clk_27     ; 2.397  ; 2.208  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; clk_27     ; 2.398  ; 2.209  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; clk_27     ; 2.408  ; 2.219  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; clk_27     ; 2.394  ; 2.221  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; clk_27     ; 2.550  ; 2.364  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; clk_27     ; 2.534  ; 2.348  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; clk_27     ; 2.539  ; 2.353  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; clk_27     ; 2.539  ; 2.353  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; clk_27     ; 2.535  ; 2.349  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; clk_27     ; 2.397  ; 2.208  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; clk_27     ; 2.542  ; 2.356  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; clk_27     ; 2.387  ; 2.198  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; clk_27     ; 2.396  ; 2.207  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; clk_27     ; 2.387  ; 2.198  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CKE     ; clk_27     ; 1.717  ; 1.593  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; clk_27     ; 2.375  ; 2.202  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 2.524  ; 2.338  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 2.520  ; 2.334  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 2.387  ; 2.214  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 2.387  ; 2.214  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 2.409  ; 2.220  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 2.419  ; 2.230  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 2.409  ; 2.220  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 2.409  ; 2.220  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 2.517  ; 2.331  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 2.517  ; 2.331  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 2.534  ; 2.348  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 2.534  ; 2.348  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 2.375  ; 2.202  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 2.534  ; 2.348  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 2.542  ; 2.356  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 2.383  ; 2.210  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH    ; clk_27     ; 2.516  ; 2.330  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML    ; clk_27     ; 2.408  ; 2.219  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nCAS    ; clk_27     ; 2.396  ; 2.207  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nRAS    ; clk_27     ; 2.395  ; 2.206  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nWE     ; clk_27     ; 2.408  ; 2.219  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; VGA_B[*]      ; clk_27     ; 6.030  ; 5.575  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; clk_27     ; 6.125  ; 5.711  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; clk_27     ; 6.030  ; 5.575  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; clk_27     ; 6.194  ; 5.819  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; clk_27     ; 6.303  ; 5.867  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[4]     ; clk_27     ; 6.510  ; 6.097  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[5]     ; clk_27     ; 6.982  ; 6.246  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; clk_27     ; 6.507  ; 5.900  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; clk_27     ; 6.727  ; 6.169  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; clk_27     ; 6.538  ; 5.900  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; clk_27     ; 6.843  ; 6.005  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; clk_27     ; 6.507  ; 5.994  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[4]     ; clk_27     ; 6.762  ; 5.944  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[5]     ; clk_27     ; 7.122  ; 6.085  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS        ; clk_27     ; 6.066  ; 5.332  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]      ; clk_27     ; 5.945  ; 5.534  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]     ; clk_27     ; 5.945  ; 5.534  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]     ; clk_27     ; 6.052  ; 5.671  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]     ; clk_27     ; 6.299  ; 5.813  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]     ; clk_27     ; 6.554  ; 6.162  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[4]     ; clk_27     ; 6.215  ; 5.845  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[5]     ; clk_27     ; 6.240  ; 5.866  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS        ; clk_27     ; 5.872  ; 5.155  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; clk_27     ; -1.570 ;        ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; clk_27     ;        ; -1.805 ; Fall       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+


+------------------------------------------------------------+
; Propagation Delay                                          ;
+------------+-------------+-------+-------+--------+--------+
; Input Port ; Output Port ; RR    ; RF    ; FR     ; FF     ;
+------------+-------------+-------+-------+--------+--------+
; CONF_DATA0 ; SPI_DO      ; 9.900 ; 9.829 ; 10.253 ; 10.253 ;
+------------+-------------+-------+-------+--------+--------+


+----------------------------------------------------------+
; Minimum Propagation Delay                                ;
+------------+-------------+-------+-------+-------+-------+
; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
+------------+-------------+-------+-------+-------+-------+
; CONF_DATA0 ; SPI_DO      ; 9.457 ; 9.321 ; 9.662 ; 9.662 ;
+------------+-------------+-------+-------+-------+-------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                             ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK    ; 8.594 ; 8.594 ; Fall       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; clk_27     ; 2.825 ; 2.761 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 2.832 ; 2.768 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 2.828 ; 2.764 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 2.855 ; 2.791 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 2.855 ; 2.791 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 2.872 ; 2.808 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 2.882 ; 2.818 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 2.872 ; 2.808 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 2.872 ; 2.808 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 2.825 ; 2.761 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 2.825 ; 2.761 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 2.843 ; 2.779 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 2.843 ; 2.779 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 2.842 ; 2.778 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 2.842 ; 2.778 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 2.851 ; 2.787 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 2.851 ; 2.787 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                     ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK    ; 8.069 ; 8.069 ; Fall       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; clk_27     ; 1.769 ; 1.707 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 1.776 ; 1.714 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 1.772 ; 1.710 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 1.798 ; 1.736 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 1.798 ; 1.736 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 1.792 ; 1.730 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 1.802 ; 1.740 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 1.792 ; 1.730 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 1.792 ; 1.730 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 1.769 ; 1.707 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 1.769 ; 1.707 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 1.786 ; 1.724 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 1.786 ; 1.724 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 1.786 ; 1.724 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 1.786 ; 1.724 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 1.794 ; 1.732 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 1.794 ; 1.732 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                    ;
+---------------+------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK    ; 8.226     ; 8.297     ; Fall       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; clk_27     ; 2.766     ; 2.901     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 2.773     ; 2.908     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 2.769     ; 2.904     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 2.796     ; 2.931     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 2.796     ; 2.931     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 2.785     ; 2.948     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 2.795     ; 2.958     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 2.785     ; 2.948     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 2.785     ; 2.948     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 2.766     ; 2.901     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 2.766     ; 2.901     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 2.784     ; 2.919     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 2.784     ; 2.919     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 2.783     ; 2.918     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 2.783     ; 2.918     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 2.792     ; 2.927     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 2.792     ; 2.927     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+-----------+-----------+------------+-----------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                            ;
+---------------+------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK    ; 7.783     ; 7.919     ; Fall       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; clk_27     ; 1.780     ; 1.978     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 1.787     ; 1.985     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 1.783     ; 1.981     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 1.809     ; 2.007     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 1.809     ; 2.007     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 1.803     ; 1.996     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 1.813     ; 2.006     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 1.803     ; 1.996     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 1.803     ; 1.996     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 1.780     ; 1.978     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 1.780     ; 1.978     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 1.797     ; 1.995     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 1.797     ; 1.995     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 1.797     ; 1.995     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 1.797     ; 1.995     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 1.805     ; 2.003     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 1.805     ; 2.003     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+-----------+-----------+------------+-----------------------------------------------------------------------+


---------------------------------------------
; Slow 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup Summary                                                             ;
+-----------------------------------------------------------------------+--------+---------------+
; Clock                                                                 ; Slack  ; End Point TNS ;
+-----------------------------------------------------------------------+--------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 0.323  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 2.394  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 6.301  ; 0.000         ;
; SPI_SCK                                                               ; 18.720 ; 0.000         ;
; clk_27                                                                ; 35.771 ; 0.000         ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 39.833 ; 0.000         ;
+-----------------------------------------------------------------------+--------+---------------+


+-----------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold Summary                                                             ;
+-----------------------------------------------------------------------+-------+---------------+
; Clock                                                                 ; Slack ; End Point TNS ;
+-----------------------------------------------------------------------+-------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.139 ; 0.000         ;
; SPI_SCK                                                               ; 0.140 ; 0.000         ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 0.186 ; 0.000         ;
; clk_27                                                                ; 0.187 ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.187 ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 1.850 ; 0.000         ;
+-----------------------------------------------------------------------+-------+---------------+


+------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery Summary                                                          ;
+-----------------------------------------------------------------------+--------+---------------+
; Clock                                                                 ; Slack  ; End Point TNS ;
+-----------------------------------------------------------------------+--------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.945  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 13.807 ; 0.000         ;
+-----------------------------------------------------------------------+--------+---------------+


+-----------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal Summary                                                          ;
+-----------------------------------------------------------------------+-------+---------------+
; Clock                                                                 ; Slack ; End Point TNS ;
+-----------------------------------------------------------------------+-------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.681 ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 2.029 ; 0.000         ;
+-----------------------------------------------------------------------+-------+---------------+


+------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width Summary                                               ;
+-----------------------------------------------------------------------+--------+---------------+
; Clock                                                                 ; Slack  ; End Point TNS ;
+-----------------------------------------------------------------------+--------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 4.186  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 4.331  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.557  ; 0.000         ;
; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; 16.300 ; 0.000         ;
; clk_27                                                                ; 17.784 ; 0.000         ;
; SPI_SCK                                                               ; 20.000 ; 0.000         ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 40.631 ; 0.000         ;
+-----------------------------------------------------------------------+--------+---------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                  ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.323 ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 1.958        ; -0.963     ; 0.510      ;
; 3.000 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3                 ; SDRAM_DQ[3]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.141      ; 2.894      ;
; 3.000 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2                 ; SDRAM_DQ[2]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.141      ; 2.894      ;
; 3.005 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14                ; SDRAM_DQ[14]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.146      ; 2.894      ;
; 3.005 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15                ; SDRAM_DQ[15]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.146      ; 2.894      ;
; 3.012 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11                ; SDRAM_DQ[11]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.143      ; 2.884      ;
; 3.012 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10                ; SDRAM_DQ[10]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.143      ; 2.884      ;
; 3.013 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12                ; SDRAM_DQ[12]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.144      ; 2.884      ;
; 3.013 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13                ; SDRAM_DQ[13]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.144      ; 2.884      ;
; 3.020 ; sdram_statemachine:sdram_adaptor|dq_output_reg                              ; SDRAM_DQ[0]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.151      ; 2.884      ;
; 3.024 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_5                 ; SDRAM_DQ[5]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.118      ; 2.847      ;
; 3.024 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1                 ; SDRAM_DQ[1]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.155      ; 2.884      ;
; 3.027 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8                 ; SDRAM_DQ[8]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.148      ; 2.874      ;
; 3.027 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9                 ; SDRAM_DQ[9]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.148      ; 2.874      ;
; 3.034 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4                 ; SDRAM_DQ[4]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.118      ; 2.837      ;
; 3.035 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_7                 ; SDRAM_DQ[7]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.119      ; 2.837      ;
; 3.035 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_6                 ; SDRAM_DQ[6]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.119      ; 2.837      ;
; 3.701 ; sdram_statemachine:sdram_adaptor|addr_reg[5]                                ; SDRAM_A[5]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.133      ; 2.185      ;
; 3.706 ; sdram_statemachine:sdram_adaptor|addr_reg[11]                               ; SDRAM_A[11]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.138      ; 2.185      ;
; 3.706 ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                             ; SDRAM_DQ[14]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.138      ; 2.185      ;
; 3.713 ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                ; SDRAM_A[7]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.135      ; 2.175      ;
; 3.713 ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                ; SDRAM_A[8]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.135      ; 2.175      ;
; 3.713 ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                ; SDRAM_A[9]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.135      ; 2.175      ;
; 3.713 ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]                             ; SDRAM_DQ[11]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.135      ; 2.175      ;
; 3.713 ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                             ; SDRAM_DQ[10]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.135      ; 2.175      ;
; 3.714 ; sdram_statemachine:sdram_adaptor|dq_out_reg[13]                             ; SDRAM_DQ[13]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.136      ; 2.175      ;
; 3.717 ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                ; SDRAM_A[6]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.139      ; 2.175      ;
; 3.721 ; sdram_statemachine:sdram_adaptor|dq_out_reg[0]                              ; SDRAM_DQ[0]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.143      ; 2.175      ;
; 3.725 ; sdram_statemachine:sdram_adaptor|dq_out_reg[1]                              ; SDRAM_DQ[1]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.147      ; 2.175      ;
; 3.728 ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]                              ; SDRAM_DQ[8]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.140      ; 2.165      ;
; 3.728 ; sdram_statemachine:sdram_adaptor|dq_out_reg[9]                              ; SDRAM_DQ[9]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.140      ; 2.165      ;
; 3.729 ; sdram_statemachine:sdram_adaptor|udqm_reg                                   ; SDRAM_DQMH                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.141      ; 2.165      ;
; 3.759 ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]                              ; SDRAM_DQ[5]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.110      ; 2.104      ;
; 3.769 ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]                              ; SDRAM_DQ[4]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.110      ; 2.094      ;
; 3.770 ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                ; SDRAM_A[3]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.111      ; 2.094      ;
; 3.770 ; sdram_statemachine:sdram_adaptor|we_n_reg                                   ; SDRAM_nWE                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.111      ; 2.094      ;
; 3.770 ; sdram_statemachine:sdram_adaptor|ldqm_reg                                   ; SDRAM_DQML                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.111      ; 2.094      ;
; 3.770 ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                              ; SDRAM_DQ[7]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.111      ; 2.094      ;
; 3.770 ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                              ; SDRAM_DQ[6]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.111      ; 2.094      ;
; 3.777 ; sdram_statemachine:sdram_adaptor|addr_reg[4]                                ; SDRAM_A[4]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.131      ; 2.107      ;
; 3.779 ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                              ; SDRAM_DQ[3]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.133      ; 2.107      ;
; 3.779 ; sdram_statemachine:sdram_adaptor|dq_out_reg[2]                              ; SDRAM_DQ[2]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.133      ; 2.107      ;
; 3.780 ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                ; SDRAM_A[2]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.111      ; 2.084      ;
; 3.781 ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                ; SDRAM_A[1]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.112      ; 2.084      ;
; 3.781 ; sdram_statemachine:sdram_adaptor|addr_reg[10]                               ; SDRAM_A[10]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.112      ; 2.084      ;
; 3.782 ; sdram_statemachine:sdram_adaptor|addr_reg[0]                                ; SDRAM_A[0]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.113      ; 2.084      ;
; 3.782 ; sdram_statemachine:sdram_adaptor|cas_n_reg                                  ; SDRAM_nCAS                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.113      ; 2.084      ;
; 3.783 ; sdram_statemachine:sdram_adaptor|ba_reg[0]                                  ; SDRAM_BA[0]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.114      ; 2.084      ;
; 3.784 ; sdram_statemachine:sdram_adaptor|ras_n_reg                                  ; SDRAM_nRAS                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.115      ; 2.084      ;
; 3.784 ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                             ; SDRAM_DQ[15]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.138      ; 2.107      ;
; 3.791 ; sdram_statemachine:sdram_adaptor|ba_reg[1]                                  ; SDRAM_BA[1]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.112      ; 2.074      ;
; 3.792 ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]                             ; SDRAM_DQ[12]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.136      ; 2.097      ;
; 4.257 ; sdram_statemachine:sdram_adaptor|cke_reg                                    ; SDRAM_CKE                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 6.363        ; 1.100      ; 1.596      ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                  ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 2.394 ; SDRAM_DQ[14]                                                                ; sdram_statemachine:sdram_adaptor|dq_in_reg[14]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -1.362     ; 0.949      ;
; 2.394 ; SDRAM_DQ[15]                                                                ; sdram_statemachine:sdram_adaptor|dq_in_reg[15]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -1.362     ; 0.949      ;
; 2.395 ; SDRAM_DQ[1]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[1]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -1.371     ; 0.939      ;
; 2.399 ; SDRAM_DQ[2]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[2]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -1.357     ; 0.949      ;
; 2.399 ; SDRAM_DQ[3]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[3]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -1.357     ; 0.949      ;
; 2.399 ; SDRAM_DQ[0]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[0]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -1.367     ; 0.939      ;
; 2.402 ; SDRAM_DQ[5]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[5]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -1.335     ; 0.968      ;
; 2.405 ; SDRAM_DQ[13]                                                                ; sdram_statemachine:sdram_adaptor|dq_in_reg[13]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -1.361     ; 0.939      ;
; 2.405 ; SDRAM_DQ[12]                                                                ; sdram_statemachine:sdram_adaptor|dq_in_reg[12]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -1.361     ; 0.939      ;
; 2.406 ; SDRAM_DQ[11]                                                                ; sdram_statemachine:sdram_adaptor|dq_in_reg[11]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -1.360     ; 0.939      ;
; 2.406 ; SDRAM_DQ[10]                                                                ; sdram_statemachine:sdram_adaptor|dq_in_reg[10]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -1.360     ; 0.939      ;
; 2.411 ; SDRAM_DQ[9]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[9]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -1.365     ; 0.929      ;
; 2.411 ; SDRAM_DQ[7]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[7]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -1.336     ; 0.958      ;
; 2.411 ; SDRAM_DQ[6]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[6]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -1.336     ; 0.958      ;
; 2.411 ; SDRAM_DQ[8]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[8]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -1.365     ; 0.929      ;
; 2.412 ; SDRAM_DQ[4]                                                                 ; sdram_statemachine:sdram_adaptor|dq_in_reg[4]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.257       ; -1.335     ; 0.958      ;
; 2.861 ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:0:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 4.405        ; -0.962     ; 0.510      ;
; 5.611 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.075     ; 3.064      ;
; 5.688 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.075     ; 2.987      ;
; 5.707 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.075     ; 2.968      ;
; 5.712 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.052     ; 2.986      ;
; 5.749 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.051     ; 2.950      ;
; 5.756 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.074     ; 2.920      ;
; 5.767 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.074     ; 2.909      ;
; 5.789 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.052     ; 2.909      ;
; 5.793 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.075     ; 2.882      ;
; 5.803 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.078     ; 2.869      ;
; 5.808 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.052     ; 2.890      ;
; 5.826 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.051     ; 2.873      ;
; 5.833 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.074     ; 2.843      ;
; 5.843 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.078     ; 2.829      ;
; 5.844 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.074     ; 2.832      ;
; 5.845 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.051     ; 2.854      ;
; 5.852 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.074     ; 2.824      ;
; 5.857 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.075     ; 2.818      ;
; 5.863 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.074     ; 2.813      ;
; 5.880 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.078     ; 2.792      ;
; 5.894 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.052     ; 2.804      ;
; 5.894 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.025     ; 2.878      ;
; 5.894 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.025     ; 2.878      ;
; 5.894 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.025     ; 2.878      ;
; 5.894 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.025     ; 2.878      ;
; 5.894 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.025     ; 2.878      ;
; 5.894 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.025     ; 2.878      ;
; 5.894 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.025     ; 2.878      ;
; 5.894 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.025     ; 2.878      ;
; 5.894 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.025     ; 2.878      ;
; 5.894 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.025     ; 2.878      ;
; 5.894 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.025     ; 2.878      ;
; 5.894 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.025     ; 2.878      ;
; 5.899 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.078     ; 2.773      ;
; 5.905 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.052     ; 2.793      ;
; 5.906 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.025     ; 2.866      ;
; 5.906 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.025     ; 2.866      ;
; 5.906 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.025     ; 2.866      ;
; 5.906 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.025     ; 2.866      ;
; 5.906 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.025     ; 2.866      ;
; 5.906 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.025     ; 2.866      ;
; 5.906 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.025     ; 2.866      ;
; 5.906 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.025     ; 2.866      ;
; 5.906 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.025     ; 2.866      ;
; 5.906 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.025     ; 2.866      ;
; 5.906 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.025     ; 2.866      ;
; 5.906 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.025     ; 2.866      ;
; 5.920 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.078     ; 2.752      ;
; 5.931 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.051     ; 2.768      ;
; 5.934 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.078     ; 2.738      ;
; 5.938 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.074     ; 2.738      ;
; 5.939 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.078     ; 2.733      ;
; 5.949 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.074     ; 2.727      ;
; 5.951 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.075     ; 2.724      ;
; 5.962 ; sdram_statemachine:sdram_adaptor|ADDRESS_IN_sreg[17]                        ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.137     ; 2.651      ;
; 5.970 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[5]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.073     ; 2.707      ;
; 5.978 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.052     ; 2.720      ;
; 5.981 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.025     ; 2.791      ;
; 5.981 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.025     ; 2.791      ;
; 5.981 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.025     ; 2.791      ;
; 5.981 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.025     ; 2.791      ;
; 5.981 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.025     ; 2.791      ;
; 5.981 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.025     ; 2.791      ;
; 5.981 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.025     ; 2.791      ;
; 5.981 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.025     ; 2.791      ;
; 5.981 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.025     ; 2.791      ;
; 5.981 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.025     ; 2.791      ;
; 5.981 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.025     ; 2.791      ;
; 5.981 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.025     ; 2.791      ;
; 5.985 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.078     ; 2.687      ;
; 6.001 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.052     ; 2.697      ;
; 6.002 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.074     ; 2.674      ;
; 6.025 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.078     ; 2.647      ;
; 6.028 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[10]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.053     ; 2.669      ;
; 6.029 ; sdram_statemachine:sdram_adaptor|ADDRESS_IN_sreg[14]                        ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.120     ; 2.601      ;
; 6.031 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.075     ; 2.644      ;
; 6.035 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.025     ; 2.737      ;
; 6.035 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.025     ; 2.737      ;
; 6.035 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.025     ; 2.737      ;
; 6.035 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.025     ; 2.737      ;
; 6.035 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.025     ; 2.737      ;
; 6.035 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.025     ; 2.737      ;
; 6.035 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.025     ; 2.737      ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                             ;
+--------+-----------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                             ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 6.301  ; user_io:my_user_io|ps2_clk                                                                                            ; user_io:my_user_io|ps2_kbd_tx_byte[6]                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.059     ; 2.438      ;
; 6.301  ; user_io:my_user_io|ps2_clk                                                                                            ; user_io:my_user_io|ps2_kbd_tx_byte[5]                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.059     ; 2.438      ;
; 6.301  ; user_io:my_user_io|ps2_clk                                                                                            ; user_io:my_user_io|ps2_kbd_tx_byte[4]                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.059     ; 2.438      ;
; 6.301  ; user_io:my_user_io|ps2_clk                                                                                            ; user_io:my_user_io|ps2_kbd_tx_byte[3]                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.059     ; 2.438      ;
; 6.301  ; user_io:my_user_io|ps2_clk                                                                                            ; user_io:my_user_io|ps2_kbd_tx_byte[2]                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.059     ; 2.438      ;
; 6.301  ; user_io:my_user_io|ps2_clk                                                                                            ; user_io:my_user_io|ps2_kbd_tx_byte[1]                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.059     ; 2.438      ;
; 6.301  ; user_io:my_user_io|ps2_clk                                                                                            ; user_io:my_user_io|ps2_kbd_tx_byte[0]                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.059     ; 2.438      ;
; 6.444  ; user_io:my_user_io|ps2_clk                                                                                            ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.058     ; 2.296      ;
; 6.509  ; user_io:my_user_io|ps2_clk                                                                                            ; user_io:my_user_io|ps2_kbd_parity                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.059     ; 2.230      ;
; 6.525  ; user_io:my_user_io|ps2_clk                                                                                            ; user_io:my_user_io|ps2_kbd_tx_byte[7]                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.059     ; 2.214      ;
; 6.529  ; user_io:my_user_io|ps2_clk                                                                                            ; user_io:my_user_io|ps2_kbd_tx_state[0]                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.058     ; 2.211      ;
; 6.643  ; user_io:my_user_io|ps2_clk                                                                                            ; user_io:my_user_io|ps2_kbd_tx_state[2]                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.058     ; 2.097      ;
; 6.644  ; user_io:my_user_io|ps2_clk                                                                                            ; user_io:my_user_io|ps2_kbd_tx_state[3]                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.058     ; 2.096      ;
; 6.645  ; user_io:my_user_io|ps2_clk                                                                                            ; user_io:my_user_io|ps2_kbd_tx_state[1]                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.058     ; 2.095      ;
; 6.718  ; user_io:my_user_io|ps2_clk                                                                                            ; user_io:my_user_io|ps2_kbd_rptr[2]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.056     ; 2.024      ;
; 6.756  ; user_io:my_user_io|ps2_clk                                                                                            ; user_io:my_user_io|ps2_kbd_r_inc                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.056     ; 1.986      ;
; 6.991  ; user_io:my_user_io|ps2_clk                                                                                            ; user_io:my_user_io|ps2_kbd_rptr[1]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.056     ; 1.751      ;
; 7.010  ; user_io:my_user_io|ps2_clk                                                                                            ; user_io:my_user_io|ps2_kbd_rptr[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.056     ; 1.732      ;
; 7.176  ; user_io:my_user_io|ps2_clk                                                                                            ; user_io:my_user_io|ps2_kbd.ps2_clkD                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.056     ; 1.566      ;
; 7.183  ; user_io:my_user_io|ps2_clk                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|synchronizer:sync_clk|ff_reg[2]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.056     ; 1.559      ;
; 7.266  ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0]                                           ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:1:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.810        ; -0.962     ; 0.510      ;
; 7.530  ; sdram_statemachine:sdram_adaptor|data_out_reg[23]                                                                     ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[23]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.088     ; 1.180      ;
; 7.591  ; sdram_statemachine:sdram_adaptor|data_out_reg[7]                                                                      ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[7]                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.090     ; 1.117      ;
; 7.689  ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                                                                   ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.085     ; 1.024      ;
; 7.690  ; sdram_statemachine:sdram_adaptor|data_out_reg[8]                                                                      ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[8]                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.083     ; 1.025      ;
; 7.731  ; sdram_statemachine:sdram_adaptor|data_out_reg[19]                                                                     ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[19]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.091     ; 0.976      ;
; 7.780  ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                                                                   ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.085     ; 0.933      ;
; 7.801  ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                                                                   ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.087     ; 0.910      ;
; 7.809  ; sdram_statemachine:sdram_adaptor|data_out_reg[15]                                                                     ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[15]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.079     ; 0.910      ;
; 7.814  ; sdram_statemachine:sdram_adaptor|data_out_reg[22]                                                                     ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[22]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.093     ; 0.891      ;
; 7.814  ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                                                                   ; sdram_statemachine:sdram_adaptor|reset_client_n_reg~_Duplicate_2                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.085     ; 0.899      ;
; 7.855  ; sdram_statemachine:sdram_adaptor|data_out_reg[9]                                                                      ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[9]                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.085     ; 0.858      ;
; 7.861  ; sdram_statemachine:sdram_adaptor|data_out_reg[10]                                                                     ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[10]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.085     ; 0.852      ;
; 7.862  ; sdram_statemachine:sdram_adaptor|data_out_reg[0]                                                                      ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[0]                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.090     ; 0.846      ;
; 7.874  ; sdram_statemachine:sdram_adaptor|data_out_reg[14]                                                                     ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[14]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.085     ; 0.839      ;
; 7.875  ; sdram_statemachine:sdram_adaptor|data_out_reg[13]                                                                     ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[13]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.085     ; 0.838      ;
; 7.886  ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                                                                   ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.087     ; 0.825      ;
; 7.887  ; sdram_statemachine:sdram_adaptor|data_out_reg[11]                                                                     ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[11]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.085     ; 0.826      ;
; 7.891  ; sdram_statemachine:sdram_adaptor|data_out_reg[29]                                                                     ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[29]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.093     ; 0.814      ;
; 7.893  ; sdram_statemachine:sdram_adaptor|data_out_reg[1]                                                                      ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[1]                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.090     ; 0.815      ;
; 7.903  ; sdram_statemachine:sdram_adaptor|reply_reg                                                                            ; sdram_statemachine:sdram_adaptor|reply_sreg                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.091     ; 0.804      ;
; 7.908  ; sdram_statemachine:sdram_adaptor|data_out_reg[4]                                                                      ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[4]                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.088     ; 0.802      ;
; 7.910  ; sdram_statemachine:sdram_adaptor|data_out_reg[21]                                                                     ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[21]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.093     ; 0.795      ;
; 7.926  ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                                                                   ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.087     ; 0.785      ;
; 8.010  ; sdram_statemachine:sdram_adaptor|data_out_reg[16]                                                                     ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[16]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.091     ; 0.697      ;
; 8.011  ; sdram_statemachine:sdram_adaptor|data_out_reg[3]                                                                      ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[3]                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.090     ; 0.697      ;
; 8.057  ; sdram_statemachine:sdram_adaptor|data_out_reg[24]                                                                     ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[24]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.093     ; 0.648      ;
; 8.092  ; sdram_statemachine:sdram_adaptor|data_out_reg[31]                                                                     ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[31]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.093     ; 0.613      ;
; 8.100  ; sdram_statemachine:sdram_adaptor|data_out_reg[27]                                                                     ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[27]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.093     ; 0.605      ;
; 8.167  ; sdram_statemachine:sdram_adaptor|data_out_reg[5]                                                                      ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[5]                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.087     ; 0.544      ;
; 8.167  ; sdram_statemachine:sdram_adaptor|data_out_reg[12]                                                                     ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[12]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.093     ; 0.538      ;
; 8.168  ; sdram_statemachine:sdram_adaptor|data_out_reg[2]                                                                      ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[2]                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.087     ; 0.543      ;
; 8.170  ; sdram_statemachine:sdram_adaptor|data_out_reg[17]                                                                     ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[17]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.093     ; 0.535      ;
; 8.171  ; sdram_statemachine:sdram_adaptor|data_out_reg[30]                                                                     ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[30]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.093     ; 0.534      ;
; 8.191  ; sdram_statemachine:sdram_adaptor|data_out_reg[6]                                                                      ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[6]                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.088     ; 0.519      ;
; 8.236  ; sdram_statemachine:sdram_adaptor|data_out_reg[20]                                                                     ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[20]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.093     ; 0.469      ;
; 8.240  ; sdram_statemachine:sdram_adaptor|data_out_reg[18]                                                                     ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[18]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.093     ; 0.465      ;
; 8.249  ; sdram_statemachine:sdram_adaptor|data_out_reg[26]                                                                     ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[26]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.093     ; 0.456      ;
; 8.252  ; sdram_statemachine:sdram_adaptor|data_out_reg[28]                                                                     ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[28]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.093     ; 0.453      ;
; 8.268  ; sdram_statemachine:sdram_adaptor|data_out_reg[25]                                                                     ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[25]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.093     ; 0.437      ;
; 10.300 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.084     ; 7.224      ;
; 10.313 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.042     ; 7.253      ;
; 10.363 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.055     ; 7.190      ;
; 10.399 ; DMA_16BIT_WRITE_ENABLE_IOCTL                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.040     ; 7.169      ;
; 10.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg~_Duplicate_2       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.040     ; 7.166      ;
; 10.429 ; ioctl_state.IOCTL_IDLE~_Duplicate_7                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.225     ; 6.954      ;
; 10.429 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_reg[0]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.089     ; 7.090      ;
; 10.432 ; DMA_16BIT_WRITE_ENABLE_IOCTL~_Duplicate_1                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.035     ; 7.141      ;
; 10.440 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[7]~_Duplicate_31        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.094     ; 7.074      ;
; 10.452 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_reg[0]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.037     ; 7.119      ;
; 10.456 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.137      ; 7.289      ;
; 10.456 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[0]~_Duplicate_30        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.090     ; 7.062      ;
; 10.457 ; user_io:my_user_io|status[1]                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.042     ; 7.109      ;
; 10.458 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[37]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.152      ; 7.302      ;
; 10.463 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[7]~_Duplicate_31        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.042     ; 7.103      ;
; 10.463 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.054     ; 7.091      ;
; 10.470 ; ioctl_state.IOCTL_IDLE                                                                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.040     ; 7.098      ;
; 10.472 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.106      ; 7.242      ;
; 10.479 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[0]~_Duplicate_30        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.038     ; 7.091      ;
; 10.480 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                ; ioctl_state.IOCTL_IDLE~_Duplicate_1                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.077     ; 7.051      ;
; 10.483 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Y[0]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.094     ; 7.031      ;
; 10.485 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.148      ; 7.271      ;
; 10.490 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.055     ; 7.063      ;
; 10.494 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                ; ioctl_state.IOCTL_IDLE~_Duplicate_9                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.092     ; 7.022      ;
; 10.498 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                ; ioctl_state.IOCTL_IDLE~_Duplicate_7                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.087      ; 7.197      ;
; 10.502 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_reg[0]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.050     ; 7.056      ;
; 10.503 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                   ; ioctl_state.IOCTL_IDLE~_Duplicate_1                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.025     ; 7.080      ;
; 10.504 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.054     ; 7.050      ;
; 10.504 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[9]               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.038     ; 7.066      ;
; 10.505 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.099      ; 7.202      ;
; 10.506 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Y[0]                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.042     ; 7.060      ;
; 10.506 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.098      ; 7.200      ;
; 10.506 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.098      ; 7.200      ;
; 10.506 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[4]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.098      ; 7.200      ;
; 10.506 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.098      ; 7.200      ;
; 10.509 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[9] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.036     ; 7.063      ;
; 10.513 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[7]~_Duplicate_31        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.055     ; 7.040      ;
; 10.517 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                   ; ioctl_state.IOCTL_IDLE~_Duplicate_9                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.040     ; 7.051      ;
; 10.517 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.054     ; 7.037      ;
; 10.518 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg~_Duplicate_1                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.089     ; 7.001      ;
+--------+-----------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'SPI_SCK'                                                                                                                        ;
+--------+---------------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                             ; To Node                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+
; 18.720 ; user_io:my_user_io|serial_out_rptr[0] ; user_io:my_user_io|spi_byte_out[0]    ; SPI_SCK      ; SPI_SCK     ; 20.800       ; -0.606     ; 1.461      ;
; 18.723 ; user_io:my_user_io|serial_out_rptr[2] ; user_io:my_user_io|spi_byte_out[0]    ; SPI_SCK      ; SPI_SCK     ; 20.800       ; -0.606     ; 1.458      ;
; 18.805 ; user_io:my_user_io|serial_out_rptr[1] ; user_io:my_user_io|spi_byte_out[0]    ; SPI_SCK      ; SPI_SCK     ; 20.800       ; -0.606     ; 1.376      ;
; 18.876 ; user_io:my_user_io|serial_out_rptr[3] ; user_io:my_user_io|spi_byte_out[0]    ; SPI_SCK      ; SPI_SCK     ; 20.800       ; -0.606     ; 1.305      ;
; 18.884 ; user_io:my_user_io|serial_out_rptr[4] ; user_io:my_user_io|spi_byte_out[0]    ; SPI_SCK      ; SPI_SCK     ; 20.800       ; -0.606     ; 1.297      ;
; 18.920 ; user_io:my_user_io|byte_cnt[8]        ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.531      ; 2.464      ;
; 18.920 ; user_io:my_user_io|byte_cnt[8]        ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.531      ; 2.464      ;
; 18.920 ; user_io:my_user_io|byte_cnt[8]        ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.531      ; 2.464      ;
; 18.920 ; user_io:my_user_io|byte_cnt[8]        ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.531      ; 2.464      ;
; 18.920 ; user_io:my_user_io|byte_cnt[8]        ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.531      ; 2.464      ;
; 18.979 ; user_io:my_user_io|serial_out_rptr[5] ; user_io:my_user_io|spi_byte_out[0]    ; SPI_SCK      ; SPI_SCK     ; 20.800       ; -0.606     ; 1.202      ;
; 19.007 ; user_io:my_user_io|byte_cnt[7]        ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.531      ; 2.377      ;
; 19.007 ; user_io:my_user_io|byte_cnt[7]        ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.531      ; 2.377      ;
; 19.007 ; user_io:my_user_io|byte_cnt[7]        ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.531      ; 2.377      ;
; 19.007 ; user_io:my_user_io|byte_cnt[7]        ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.531      ; 2.377      ;
; 19.007 ; user_io:my_user_io|byte_cnt[7]        ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.531      ; 2.377      ;
; 19.111 ; user_io:my_user_io|byte_cnt[5]        ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.531      ; 2.273      ;
; 19.111 ; user_io:my_user_io|byte_cnt[5]        ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.531      ; 2.273      ;
; 19.111 ; user_io:my_user_io|byte_cnt[5]        ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.531      ; 2.273      ;
; 19.111 ; user_io:my_user_io|byte_cnt[5]        ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.531      ; 2.273      ;
; 19.111 ; user_io:my_user_io|byte_cnt[5]        ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.531      ; 2.273      ;
; 19.129 ; user_io:my_user_io|byte_cnt[8]        ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.531      ; 2.255      ;
; 19.173 ; user_io:my_user_io|byte_cnt[6]        ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.531      ; 2.211      ;
; 19.173 ; user_io:my_user_io|byte_cnt[6]        ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.531      ; 2.211      ;
; 19.173 ; user_io:my_user_io|byte_cnt[6]        ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.531      ; 2.211      ;
; 19.173 ; user_io:my_user_io|byte_cnt[6]        ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.531      ; 2.211      ;
; 19.173 ; user_io:my_user_io|byte_cnt[6]        ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.531      ; 2.211      ;
; 19.188 ; user_io:my_user_io|byte_cnt[3]        ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.531      ; 2.196      ;
; 19.188 ; user_io:my_user_io|byte_cnt[3]        ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.531      ; 2.196      ;
; 19.188 ; user_io:my_user_io|byte_cnt[3]        ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.531      ; 2.196      ;
; 19.188 ; user_io:my_user_io|byte_cnt[3]        ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.531      ; 2.196      ;
; 19.188 ; user_io:my_user_io|byte_cnt[3]        ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.531      ; 2.196      ;
; 19.218 ; user_io:my_user_io|byte_cnt[7]        ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.531      ; 2.166      ;
; 19.331 ; user_io:my_user_io|byte_cnt[5]        ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.531      ; 2.053      ;
; 19.393 ; user_io:my_user_io|byte_cnt[6]        ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.531      ; 1.991      ;
; 19.397 ; user_io:my_user_io|byte_cnt[3]        ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.531      ; 1.987      ;
; 19.402 ; user_io:my_user_io|byte_cnt[9]        ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.531      ; 1.982      ;
; 19.402 ; user_io:my_user_io|byte_cnt[9]        ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.531      ; 1.982      ;
; 19.402 ; user_io:my_user_io|byte_cnt[9]        ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.531      ; 1.982      ;
; 19.402 ; user_io:my_user_io|byte_cnt[9]        ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.531      ; 1.982      ;
; 19.402 ; user_io:my_user_io|byte_cnt[9]        ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.531      ; 1.982      ;
; 19.442 ; user_io:my_user_io|bit_cnt[0]         ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.530      ; 1.941      ;
; 19.442 ; user_io:my_user_io|bit_cnt[0]         ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.530      ; 1.941      ;
; 19.442 ; user_io:my_user_io|bit_cnt[0]         ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.530      ; 1.941      ;
; 19.442 ; user_io:my_user_io|bit_cnt[0]         ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.530      ; 1.941      ;
; 19.442 ; user_io:my_user_io|bit_cnt[0]         ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.530      ; 1.941      ;
; 19.530 ; user_io:my_user_io|byte_cnt[2]        ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.531      ; 1.854      ;
; 19.530 ; user_io:my_user_io|byte_cnt[2]        ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.531      ; 1.854      ;
; 19.530 ; user_io:my_user_io|byte_cnt[2]        ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.531      ; 1.854      ;
; 19.530 ; user_io:my_user_io|byte_cnt[2]        ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.531      ; 1.854      ;
; 19.530 ; user_io:my_user_io|byte_cnt[2]        ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.531      ; 1.854      ;
; 19.565 ; user_io:my_user_io|byte_cnt[4]        ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.531      ; 1.819      ;
; 19.565 ; user_io:my_user_io|byte_cnt[4]        ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.531      ; 1.819      ;
; 19.565 ; user_io:my_user_io|byte_cnt[4]        ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.531      ; 1.819      ;
; 19.565 ; user_io:my_user_io|byte_cnt[4]        ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.531      ; 1.819      ;
; 19.565 ; user_io:my_user_io|byte_cnt[4]        ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.531      ; 1.819      ;
; 19.611 ; user_io:my_user_io|byte_cnt[9]        ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.531      ; 1.773      ;
; 19.618 ; user_io:my_user_io|bit_cnt[2]         ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.530      ; 1.765      ;
; 19.618 ; user_io:my_user_io|bit_cnt[2]         ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.530      ; 1.765      ;
; 19.618 ; user_io:my_user_io|bit_cnt[2]         ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.530      ; 1.765      ;
; 19.618 ; user_io:my_user_io|bit_cnt[2]         ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.530      ; 1.765      ;
; 19.618 ; user_io:my_user_io|bit_cnt[2]         ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.530      ; 1.765      ;
; 19.651 ; user_io:my_user_io|bit_cnt[0]         ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.530      ; 1.732      ;
; 19.662 ; user_io:my_user_io|byte_cnt[1]        ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.531      ; 1.722      ;
; 19.662 ; user_io:my_user_io|byte_cnt[1]        ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.531      ; 1.722      ;
; 19.662 ; user_io:my_user_io|byte_cnt[1]        ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.531      ; 1.722      ;
; 19.662 ; user_io:my_user_io|byte_cnt[1]        ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.531      ; 1.722      ;
; 19.662 ; user_io:my_user_io|byte_cnt[1]        ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.531      ; 1.722      ;
; 19.679 ; user_io:my_user_io|bit_cnt[1]         ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.530      ; 1.704      ;
; 19.679 ; user_io:my_user_io|bit_cnt[1]         ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.530      ; 1.704      ;
; 19.679 ; user_io:my_user_io|bit_cnt[1]         ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.530      ; 1.704      ;
; 19.679 ; user_io:my_user_io|bit_cnt[1]         ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.530      ; 1.704      ;
; 19.679 ; user_io:my_user_io|bit_cnt[1]         ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.530      ; 1.704      ;
; 19.685 ; user_io:my_user_io|cmd[3]             ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.527      ; 1.695      ;
; 19.685 ; user_io:my_user_io|cmd[3]             ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.527      ; 1.695      ;
; 19.685 ; user_io:my_user_io|cmd[3]             ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.527      ; 1.695      ;
; 19.685 ; user_io:my_user_io|cmd[3]             ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.527      ; 1.695      ;
; 19.685 ; user_io:my_user_io|cmd[3]             ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.527      ; 1.695      ;
; 19.739 ; user_io:my_user_io|byte_cnt[2]        ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.531      ; 1.645      ;
; 19.750 ; user_io:my_user_io|byte_cnt[0]        ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.531      ; 1.634      ;
; 19.750 ; user_io:my_user_io|byte_cnt[0]        ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.531      ; 1.634      ;
; 19.750 ; user_io:my_user_io|byte_cnt[0]        ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.531      ; 1.634      ;
; 19.750 ; user_io:my_user_io|byte_cnt[0]        ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.531      ; 1.634      ;
; 19.750 ; user_io:my_user_io|byte_cnt[0]        ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.531      ; 1.634      ;
; 19.774 ; user_io:my_user_io|byte_cnt[4]        ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.531      ; 1.610      ;
; 19.827 ; user_io:my_user_io|bit_cnt[2]         ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.530      ; 1.556      ;
; 19.871 ; user_io:my_user_io|byte_cnt[1]        ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.531      ; 1.513      ;
; 19.872 ; user_io:my_user_io|cmd[7]             ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.532      ; 1.513      ;
; 19.872 ; user_io:my_user_io|cmd[7]             ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.532      ; 1.513      ;
; 19.872 ; user_io:my_user_io|cmd[7]             ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.532      ; 1.513      ;
; 19.872 ; user_io:my_user_io|cmd[7]             ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.532      ; 1.513      ;
; 19.872 ; user_io:my_user_io|cmd[7]             ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.532      ; 1.513      ;
; 19.873 ; user_io:my_user_io|cmd[5]             ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.532      ; 1.512      ;
; 19.873 ; user_io:my_user_io|cmd[5]             ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.532      ; 1.512      ;
; 19.873 ; user_io:my_user_io|cmd[5]             ; user_io:my_user_io|serial_out_rptr[4] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.532      ; 1.512      ;
; 19.873 ; user_io:my_user_io|cmd[5]             ; user_io:my_user_io|serial_out_rptr[5] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.532      ; 1.512      ;
; 19.873 ; user_io:my_user_io|cmd[5]             ; user_io:my_user_io|serial_out_rptr[1] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.532      ; 1.512      ;
; 19.888 ; user_io:my_user_io|bit_cnt[1]         ; user_io:my_user_io|serial_out_rptr[0] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.530      ; 1.495      ;
; 19.891 ; user_io:my_user_io|cmd[1]             ; user_io:my_user_io|serial_out_rptr[2] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.527      ; 1.489      ;
; 19.891 ; user_io:my_user_io|cmd[1]             ; user_io:my_user_io|serial_out_rptr[3] ; SPI_SCK      ; SPI_SCK     ; 20.866       ; 0.527      ; 1.489      ;
+--------+---------------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'clk_27'                                                                                                                                                                 ;
+--------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                 ; To Node                                                   ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 35.771 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 1.217      ;
; 35.786 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 1.202      ;
; 35.838 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 1.150      ;
; 35.841 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 1.147      ;
; 35.850 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 1.138      ;
; 35.854 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 1.134      ;
; 35.856 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 1.132      ;
; 35.897 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 1.091      ;
; 35.907 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 1.081      ;
; 35.908 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 1.080      ;
; 35.917 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 1.071      ;
; 35.922 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 1.066      ;
; 35.924 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 1.064      ;
; 35.964 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 1.024      ;
; 35.986 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 1.002      ;
; 35.987 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 1.001      ;
; 35.987 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 1.001      ;
; 35.992 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.996      ;
; 36.033 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.955      ;
; 36.034 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.954      ;
; 36.059 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.929      ;
; 36.062 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.926      ;
; 36.069 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.919      ;
; 36.072 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.916      ;
; 36.090 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.898      ;
; 36.101 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.887      ;
; 36.110 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.878      ;
; 36.137 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.851      ;
; 36.146 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.842      ;
; 36.149 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.839      ;
; 36.154 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.834      ;
; 36.157 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.831      ;
; 36.158 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.830      ;
; 36.168 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.820      ;
; 36.169 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.819      ;
; 36.186 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.802      ;
; 36.186 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.802      ;
; 36.204 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.784      ;
; 36.218 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.770      ;
; 36.220 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.768      ;
; 36.221 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.767      ;
; 36.237 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.751      ;
; 36.237 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.751      ;
; 36.237 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.751      ;
; 36.240 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.748      ;
; 36.246 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.742      ;
; 36.249 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.739      ;
; 36.261 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.727      ;
; 36.261 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.727      ;
; 36.322 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.666      ;
; 36.324 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.664      ;
; 36.325 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.663      ;
; 36.359 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.629      ;
; 36.397 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.591      ;
; 36.399 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.589      ;
; 36.400 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.588      ;
; 36.442 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.546      ;
; 36.443 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.545      ;
; 36.455 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.533      ;
; 36.629 ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 37.037       ; -0.036     ; 0.359      ;
+--------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                          ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                                       ; To Node                                                                                                                                                                                                                               ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 39.833 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|idle_state                                                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 1.975      ; 3.796      ;
; 39.950 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_we_reg ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.331     ; 2.571      ;
; 40.418 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 1.974      ; 3.210      ;
; 40.544 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 1.974      ; 3.084      ;
; 40.635 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_init_state_1                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 1.973      ; 2.992      ;
; 40.839 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_data_state                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.141     ; 1.872      ;
; 40.843 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_data_state                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.141     ; 1.868      ;
; 40.941 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_data_state                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.141     ; 1.770      ;
; 40.993 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_data_state                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.141     ; 1.718      ;
; 41.096 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_data_state                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.141     ; 1.615      ;
; 41.198 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate2_state                                                             ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate3_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.017     ; 0.438      ;
; 41.252 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_seq_data_state                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.145     ; 1.455      ;
; 41.272 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[1]                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.142     ; 1.438      ;
; 41.276 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[3]                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.142     ; 1.434      ;
; 41.356 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[2]                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.142     ; 1.354      ;
; 41.429 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[4]                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.142     ; 1.281      ;
; 41.567 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                                             ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.145     ; 1.140      ;
; 41.671 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[0]                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.142     ; 1.039      ;
; 78.949 ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.021     ; 5.549      ;
; 79.821 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                             ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|idle_state                                                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 3.463      ;
; 80.191 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|idle_state                                                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.034     ; 3.095      ;
; 80.503 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                             ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.037     ; 2.780      ;
; 80.641 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                             ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.037     ; 2.642      ;
; 80.732 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                             ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_init_state_1                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.038     ; 2.550      ;
; 80.873 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.035     ; 2.412      ;
; 80.959 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_second_state                                                                ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.142      ; 2.525      ;
; 80.959 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_second_state                                                                ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.142      ; 2.525      ;
; 81.030 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.035     ; 2.255      ;
; 81.119 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_init_state_1                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 2.165      ;
; 81.140 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[2]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.142      ; 2.344      ;
; 81.140 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[2]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.142      ; 2.344      ;
; 81.182 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.034     ; 2.104      ;
; 81.182 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.034     ; 2.104      ;
; 81.182 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.034     ; 2.104      ;
; 81.182 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.034     ; 2.104      ;
; 81.182 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.034     ; 2.104      ;
; 81.182 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[5]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.034     ; 2.104      ;
; 81.182 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[6]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.034     ; 2.104      ;
; 81.182 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[7]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.034     ; 2.104      ;
; 81.203 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.030     ; 2.087      ;
; 81.217 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_first_state                                                                 ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.141      ; 2.266      ;
; 81.217 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_first_state                                                                 ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.141      ; 2.266      ;
; 81.226 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[1]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.142      ; 2.258      ;
; 81.226 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[1]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.142      ; 2.258      ;
; 81.228 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.030     ; 2.062      ;
; 81.232 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.030     ; 2.058      ;
; 81.256 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                   ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 2.028      ;
; 81.257 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_data_state                                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_address_reg0 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.142      ; 2.227      ;
; 81.270 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.034     ; 2.016      ;
; 81.270 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.034     ; 2.016      ;
; 81.270 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.034     ; 2.016      ;
; 81.270 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.034     ; 2.016      ;
; 81.270 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.034     ; 2.016      ;
; 81.270 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[5]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.034     ; 2.016      ;
; 81.270 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[6]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.034     ; 2.016      ;
; 81.270 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[7]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.034     ; 2.016      ;
; 81.281 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                   ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 2.003      ;
; 81.285 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                   ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 1.999      ;
; 81.305 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[3]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.142      ; 2.179      ;
; 81.305 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[3]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.142      ; 2.179      ;
; 81.320 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|idle_state                                                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 1.975      ; 3.975      ;
; 81.325 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[5]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.142      ; 2.159      ;
; 81.325 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[5]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.142      ; 2.159      ;
; 81.329 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[6]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.142      ; 2.155      ;
; 81.329 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[6]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.142      ; 2.155      ;
; 81.360 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_second_last_state                                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_address_reg0 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.143      ; 2.125      ;
; 81.379 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_last_state                                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_address_reg0 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.142      ; 2.105      ;
; 81.380 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[0]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.142      ; 2.104      ;
; 81.380 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[0]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.142      ; 2.104      ;
; 81.409 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[7]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.142      ; 2.075      ;
; 81.409 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[7]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.142      ; 2.075      ;
; 81.422 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                   ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[0]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 1.862      ;
; 81.422 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                   ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 1.862      ;
; 81.422 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                   ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 1.862      ;
; 81.422 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                   ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 1.862      ;
; 81.422 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                   ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 1.862      ;
; 81.422 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                   ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 1.862      ;
; 81.422 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                   ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 1.862      ;
; 81.422 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                   ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 1.862      ;
; 81.429 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[0]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.030     ; 1.861      ;
; 81.429 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.030     ; 1.861      ;
; 81.429 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.030     ; 1.861      ;
; 81.429 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.030     ; 1.861      ;
; 81.429 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.030     ; 1.861      ;
; 81.429 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.030     ; 1.861      ;
; 81.429 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.030     ; 1.861      ;
; 81.429 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                    ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.030     ; 1.861      ;
; 81.449 ; rom_loaded                                                                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.033     ; 1.838      ;
; 81.454 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.034     ; 1.832      ;
; 81.454 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.034     ; 1.832      ;
; 81.454 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.034     ; 1.832      ;
; 81.454 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.034     ; 1.832      ;
; 81.454 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.034     ; 1.832      ;
; 81.454 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[5]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.034     ; 1.832      ;
; 81.454 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[6]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.034     ; 1.832      ;
; 81.454 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_ena_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[7]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.034     ; 1.832      ;
; 81.456 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.033     ; 1.831      ;
; 81.483 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[4]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.142      ; 2.001      ;
; 81.483 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[4]                   ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; 0.142      ; 2.001      ;
; 81.485 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.033     ; 1.802      ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                     ; To Node                                                                                                                                                                                                                                 ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.139 ; user_io:my_user_io|sd_dout[1]                                                                                                                 ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.463      ;
; 0.139 ; user_io:my_user_io|sd_dout[6]                                                                                                                 ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.463      ;
; 0.140 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp3_snap_reg[5]                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.222      ; 0.466      ;
; 0.142 ; user_io:my_user_io|sd_dout[4]                                                                                                                 ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.466      ;
; 0.143 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[0]                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.222      ; 0.469      ;
; 0.144 ; user_io:my_user_io|sd_dout[5]                                                                                                                 ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.468      ;
; 0.145 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_snap_reg[6]                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.470      ;
; 0.146 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[0]                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.471      ;
; 0.147 ; user_io:my_user_io|sd_dout[0]                                                                                                                 ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.471      ;
; 0.148 ; user_io:my_user_io|sd_dout[3]                                                                                                                 ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.472      ;
; 0.149 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[0]                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.222      ; 0.475      ;
; 0.149 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[3]                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.222      ; 0.475      ;
; 0.149 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[3]                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.478      ;
; 0.149 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_snap_reg[4]                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.474      ;
; 0.150 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[6]                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.222      ; 0.476      ;
; 0.151 ; user_io:my_user_io|sd_dout[2]                                                                                                                 ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.475      ;
; 0.152 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_snap_reg[0]                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.477      ;
; 0.153 ; user_io:my_user_io|sd_buff_addr[1]                                                                                                            ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.478      ;
; 0.154 ; user_io:my_user_io|sd_buff_addr[3]                                                                                                            ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.479      ;
; 0.154 ; user_io:my_user_io|sd_buff_addr[6]                                                                                                            ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.479      ;
; 0.154 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[2]                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.222      ; 0.480      ;
; 0.154 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[7]                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.479      ;
; 0.154 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_snap_reg[1]                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.479      ;
; 0.155 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[5]                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.222      ; 0.481      ;
; 0.155 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[2]                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.480      ;
; 0.155 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[5]                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.480      ;
; 0.155 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[31]                                                                                              ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.482      ;
; 0.157 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_snap_reg[5]                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.482      ;
; 0.158 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|cntr_8rf:cntr1|counter_reg_bit[6] ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|altsyncram_14b1:altsyncram2|ram_block5a0~portb_address_reg0                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.485      ;
; 0.159 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|cntr_8rf:cntr1|counter_reg_bit[4] ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|altsyncram_14b1:altsyncram2|ram_block5a0~portb_address_reg0                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.486      ;
; 0.159 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|cntr_8rf:cntr1|counter_reg_bit[6] ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|altsyncram_14b1:altsyncram2|ram_block5a0~porta_address_reg0                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.484      ;
; 0.160 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|cntr_8rf:cntr1|counter_reg_bit[4] ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|altsyncram_14b1:altsyncram2|ram_block5a0~porta_address_reg0                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.485      ;
; 0.160 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_snap_reg[7]                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.485      ;
; 0.161 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|cntr_8rf:cntr1|counter_reg_bit[1] ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|altsyncram_14b1:altsyncram2|ram_block5a0~portb_address_reg0                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.488      ;
; 0.161 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[7]                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.486      ;
; 0.162 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|cntr_8rf:cntr1|counter_reg_bit[1] ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|altsyncram_14b1:altsyncram2|ram_block5a0~porta_address_reg0                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.487      ;
; 0.162 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[7]                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.222      ; 0.488      ;
; 0.163 ; user_io:my_user_io|sd_buff_addr[5]                                                                                                            ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.488      ;
; 0.164 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[1]                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.489      ;
; 0.165 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|cntr_8rf:cntr1|counter_reg_bit[0] ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|altsyncram_14b1:altsyncram2|ram_block5a0~portb_address_reg0                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.492      ;
; 0.166 ; user_io:my_user_io|sd_buff_addr[2]                                                                                                            ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.491      ;
; 0.166 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|cntr_8rf:cntr1|counter_reg_bit[0] ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|altsyncram_14b1:altsyncram2|ram_block5a0~porta_address_reg0                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.491      ;
; 0.166 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[2]                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.491      ;
; 0.167 ; user_io:my_user_io|sd_buff_addr[7]                                                                                                            ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.492      ;
; 0.168 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_snap_reg[2]                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.493      ;
; 0.169 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[3]                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.494      ;
; 0.170 ; user_io:my_user_io|sd_buff_addr[0]                                                                                                            ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.495      ;
; 0.170 ; user_io:my_user_io|sd_buff_addr[8]                                                                                                            ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.495      ;
; 0.175 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|cntr_8rf:cntr1|counter_reg_bit[3] ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|altsyncram_14b1:altsyncram2|ram_block5a0~portb_address_reg0                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.502      ;
; 0.176 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|cntr_8rf:cntr1|counter_reg_bit[3] ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|altsyncram_14b1:altsyncram2|ram_block5a0~porta_address_reg0                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.501      ;
; 0.177 ; zpu_secbuf_d[5]                                                                                                                               ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~portb_datain_reg0                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.502      ;
; 0.179 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|irqb_reg[1]                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|irqb_reg[1]                                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.307      ;
; 0.179 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|irqa_reg[1]                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|irqa_reg[1]                                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.307      ;
; 0.179 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|state[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|state[1]                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.307      ;
; 0.184 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|cntr_8rf:cntr1|counter_reg_bit[5] ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|altsyncram_14b1:altsyncram2|ram_block5a0~portb_address_reg0                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.511      ;
; 0.184 ; user_io:my_user_io|ps2_clk                                                                                                                    ; user_io:my_user_io|ps2_clk                                                                                                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.039      ; 0.307      ;
; 0.185 ; sdram_statemachine:sdram_adaptor|data_out_reg[28]                                                                                             ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[28]                                                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.092      ; 0.382      ;
; 0.185 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|cntr_8rf:cntr1|counter_reg_bit[5] ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|altsyncram_14b1:altsyncram2|ram_block5a0~porta_address_reg0                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.510      ;
; 0.186 ; sdram_statemachine:sdram_adaptor|data_out_reg[26]                                                                                             ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[26]                                                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.092      ; 0.383      ;
; 0.186 ; user_io:my_user_io|ps2_kbd_tx_byte[7]                                                                                                         ; user_io:my_user_io|ps2_kbd_tx_byte[7]                                                                                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; user_io:my_user_io|ps2_kbd_parity                                                                                                             ; user_io:my_user_io|ps2_kbd_parity                                                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[1]                                                                  ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[1]                                                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[2]                                                                  ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[2]                                                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[3]                                                                  ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[3]                                                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|pending_extended_reg                                                         ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|pending_extended_reg                                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|pending_keyup_reg                                                            ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|pending_keyup_reg                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[120]                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[120]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[12]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[12]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[0]                                                                                          ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[0]                                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[91]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[91]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[372]                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[372]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[21]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[21]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[28]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[28]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[88]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[88]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[52]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[52]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[27]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[27]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[30]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[30]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[54]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[54]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[1]                                                         ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[1]                                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[0]                                                         ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[0]                                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[3]                                                         ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[3]                                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[2]                                                         ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[2]                                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[50]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[50]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[84]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[84]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[85]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[85]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[273]                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[273]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[26]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[26]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[34]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[34]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[364]                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[364]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[37]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[37]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[65]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[65]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[69]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[69]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[33]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[33]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[53]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[53]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[60]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[60]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[89]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[89]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[14]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[14]                                                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[119]                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[119]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[369]                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[369]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|ack_error                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|ack_error                                                                                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'SPI_SCK'                                                                                                                                                                                               ;
+-------+--------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                                  ; To Node                                                                                                 ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.140 ; osd:osd_inst|sbuf[1]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.225      ; 0.469      ;
; 0.156 ; osd:osd_inst|sbuf[3]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.222      ; 0.482      ;
; 0.158 ; osd:osd_inst|bcnt[7]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.223      ; 0.485      ;
; 0.159 ; osd:osd_inst|sbuf[5]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.222      ; 0.485      ;
; 0.159 ; osd:osd_inst|sbuf[6]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.222      ; 0.485      ;
; 0.164 ; osd:osd_inst|bcnt[2]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.222      ; 0.490      ;
; 0.164 ; osd:osd_inst|sbuf[4]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.222      ; 0.490      ;
; 0.164 ; osd:osd_inst|sbuf[2]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.223      ; 0.491      ;
; 0.166 ; osd:osd_inst|bcnt[1]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.222      ; 0.492      ;
; 0.167 ; osd:osd_inst|bcnt[4]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.223      ; 0.494      ;
; 0.171 ; osd:osd_inst|bcnt[8]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.222      ; 0.497      ;
; 0.176 ; osd:osd_inst|bcnt[6]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.223      ; 0.503      ;
; 0.177 ; osd:osd_inst|bcnt[4]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.222      ; 0.503      ;
; 0.185 ; user_io:my_user_io|serial_out_rptr[0]      ; user_io:my_user_io|serial_out_rptr[0]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.038      ; 0.307      ;
; 0.186 ; osd:osd_inst|osd_enable                    ; osd:osd_inst|osd_enable                                                                                 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; osd:osd_inst|bcnt[9]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.222      ; 0.512      ;
; 0.187 ; user_io:my_user_io|bit_cnt[1]              ; user_io:my_user_io|bit_cnt[1]                                                                           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; user_io:my_user_io|bit_cnt[2]              ; user_io:my_user_io|bit_cnt[2]                                                                           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; data_io:mist_data_io|bit_cnt[1]            ; data_io:mist_data_io|bit_cnt[1]                                                                         ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; data_io:mist_data_io|bit_cnt[2]            ; data_io:mist_data_io|bit_cnt[2]                                                                         ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; user_io:my_user_io|byte_cnt[0]             ; user_io:my_user_io|byte_cnt[0]                                                                          ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; user_io:my_user_io|cmd[0]                  ; user_io:my_user_io|cmd[0]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; user_io:my_user_io|cmd[2]                  ; user_io:my_user_io|cmd[2]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; user_io:my_user_io|cmd[1]                  ; user_io:my_user_io|cmd[1]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; user_io:my_user_io|cmd[3]                  ; user_io:my_user_io|cmd[3]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.307      ;
; 0.193 ; data_io:mist_data_io|spi_receiver_strobe_r ; data_io:mist_data_io|spi_receiver_strobe_r                                                              ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.314      ;
; 0.193 ; user_io:my_user_io|spi_receiver_strobe_r   ; user_io:my_user_io|spi_receiver_strobe_r                                                                ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.314      ;
; 0.194 ; user_io:my_user_io|bit_cnt[0]              ; user_io:my_user_io|bit_cnt[0]                                                                           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; data_io:mist_data_io|bit_cnt[0]            ; data_io:mist_data_io|bit_cnt[0]                                                                         ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.314      ;
; 0.195 ; data_io:mist_data_io|sbuf[5]               ; data_io:mist_data_io|sbuf[6]                                                                            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.316      ;
; 0.195 ; data_io:mist_data_io|sbuf[6]               ; data_io:mist_data_io|spi_byte_in[7]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.316      ;
; 0.196 ; data_io:mist_data_io|sbuf[3]               ; data_io:mist_data_io|spi_byte_in[4]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.317      ;
; 0.197 ; data_io:mist_data_io|sbuf[0]               ; data_io:mist_data_io|sbuf[1]                                                                            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.318      ;
; 0.197 ; data_io:mist_data_io|sbuf[0]               ; data_io:mist_data_io|spi_byte_in[1]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.318      ;
; 0.197 ; data_io:mist_data_io|sbuf[3]               ; data_io:mist_data_io|sbuf[4]                                                                            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.318      ;
; 0.198 ; data_io:mist_data_io|sbuf[5]               ; data_io:mist_data_io|spi_byte_in[6]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.319      ;
; 0.199 ; user_io:my_user_io|sbuf[6]                 ; user_io:my_user_io|spi_byte_in[7]                                                                       ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.319      ;
; 0.200 ; user_io:my_user_io|sbuf[5]                 ; user_io:my_user_io|sbuf[6]                                                                              ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.320      ;
; 0.201 ; user_io:my_user_io|sbuf[5]                 ; user_io:my_user_io|spi_byte_in[6]                                                                       ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.321      ;
; 0.202 ; user_io:my_user_io|sbuf[3]                 ; user_io:my_user_io|sbuf[4]                                                                              ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.322      ;
; 0.202 ; user_io:my_user_io|sbuf[4]                 ; user_io:my_user_io|spi_byte_in[5]                                                                       ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.322      ;
; 0.203 ; user_io:my_user_io|sbuf[4]                 ; user_io:my_user_io|sbuf[5]                                                                              ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.323      ;
; 0.203 ; user_io:my_user_io|sbuf[3]                 ; user_io:my_user_io|spi_byte_in[4]                                                                       ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.323      ;
; 0.204 ; osd:osd_inst|bcnt[10]                      ; osd:osd_inst|bcnt[10]                                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.324      ;
; 0.206 ; data_io:mist_data_io|bit_cnt[0]            ; data_io:mist_data_io|bit_cnt[2]                                                                         ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.326      ;
; 0.209 ; osd:osd_inst|sbuf[2]                       ; osd:osd_inst|sbuf[3]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.330      ;
; 0.209 ; osd:osd_inst|sbuf[2]                       ; osd:osd_inst|cmd[3]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.330      ;
; 0.209 ; data_io:mist_data_io|bit_cnt[0]            ; data_io:mist_data_io|bit_cnt[1]                                                                         ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.329      ;
; 0.214 ; user_io:my_user_io|sbuf[2]                 ; user_io:my_user_io|spi_byte_in[3]                                                                       ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.334      ;
; 0.259 ; osd:osd_inst|bcnt[3]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.223      ; 0.586      ;
; 0.266 ; osd:osd_inst|bcnt[0]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.222      ; 0.592      ;
; 0.269 ; data_io:mist_data_io|sbuf[2]               ; data_io:mist_data_io|sbuf[3]                                                                            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.390      ;
; 0.270 ; data_io:mist_data_io|sbuf[1]               ; data_io:mist_data_io|spi_byte_in[2]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.391      ;
; 0.271 ; data_io:mist_data_io|sbuf[2]               ; data_io:mist_data_io|spi_byte_in[3]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.392      ;
; 0.271 ; data_io:mist_data_io|sbuf[4]               ; data_io:mist_data_io|spi_byte_in[5]                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.392      ;
; 0.272 ; osd:osd_inst|bcnt[5]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.223      ; 0.599      ;
; 0.273 ; data_io:mist_data_io|sbuf[1]               ; data_io:mist_data_io|sbuf[2]                                                                            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.394      ;
; 0.273 ; data_io:mist_data_io|sbuf[4]               ; data_io:mist_data_io|sbuf[5]                                                                            ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.394      ;
; 0.274 ; user_io:my_user_io|sbuf[1]                 ; user_io:my_user_io|spi_byte_in[2]                                                                       ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.035      ; 0.393      ;
; 0.276 ; user_io:my_user_io|sbuf[1]                 ; user_io:my_user_io|cmd[2]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.396      ;
; 0.278 ; user_io:my_user_io|sbuf[1]                 ; user_io:my_user_io|sbuf[2]                                                                              ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.398      ;
; 0.282 ; osd:osd_inst|sbuf[5]                       ; osd:osd_inst|sbuf[6]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.403      ;
; 0.282 ; osd:osd_inst|sbuf[5]                       ; osd:osd_inst|cmd[6]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.403      ;
; 0.283 ; user_io:my_user_io|sbuf[0]                 ; user_io:my_user_io|cmd[1]                                                                               ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.403      ;
; 0.286 ; osd:osd_inst|sbuf[4]                       ; osd:osd_inst|cmd[5]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.407      ;
; 0.287 ; osd:osd_inst|sbuf[4]                       ; osd:osd_inst|sbuf[5]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.408      ;
; 0.290 ; osd:osd_inst|sbuf[3]                       ; osd:osd_inst|sbuf[4]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.411      ;
; 0.290 ; osd:osd_inst|sbuf[3]                       ; osd:osd_inst|cmd[4]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.411      ;
; 0.292 ; osd:osd_inst|bcnt[5]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.222      ; 0.618      ;
; 0.294 ; user_io:my_user_io|sbuf[0]                 ; user_io:my_user_io|spi_byte_in[1]                                                                       ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.414      ;
; 0.297 ; user_io:my_user_io|sbuf[0]                 ; user_io:my_user_io|sbuf[1]                                                                              ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.417      ;
; 0.297 ; user_io:my_user_io|serial_out_rptr[2]      ; user_io:my_user_io|serial_out_rptr[2]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.038      ; 0.419      ;
; 0.298 ; user_io:my_user_io|serial_out_rptr[3]      ; user_io:my_user_io|serial_out_rptr[3]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.038      ; 0.420      ;
; 0.298 ; user_io:my_user_io|serial_out_rptr[4]      ; user_io:my_user_io|serial_out_rptr[4]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.038      ; 0.420      ;
; 0.298 ; user_io:my_user_io|serial_out_rptr[5]      ; user_io:my_user_io|serial_out_rptr[5]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.038      ; 0.420      ;
; 0.301 ; osd:osd_inst|bcnt[7]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.222      ; 0.627      ;
; 0.303 ; osd:osd_inst|sbuf[0]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_datain_reg0  ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.225      ; 0.632      ;
; 0.304 ; osd:osd_inst|bcnt[9]                       ; osd:osd_inst|bcnt[9]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.424      ;
; 0.304 ; user_io:my_user_io|serial_out_rptr[0]      ; user_io:my_user_io|serial_out_rptr[1]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.038      ; 0.426      ;
; 0.304 ; user_io:my_user_io|serial_out_rptr[1]      ; user_io:my_user_io|serial_out_rptr[1]                                                                   ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.038      ; 0.426      ;
; 0.305 ; osd:osd_inst|bcnt[1]                       ; osd:osd_inst|bcnt[1]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.425      ;
; 0.306 ; osd:osd_inst|bcnt[2]                       ; osd:osd_inst|bcnt[2]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.426      ;
; 0.306 ; osd:osd_inst|bcnt[5]                       ; osd:osd_inst|bcnt[5]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.426      ;
; 0.306 ; osd:osd_inst|bcnt[7]                       ; osd:osd_inst|bcnt[7]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.426      ;
; 0.306 ; osd:osd_inst|bcnt[9]                       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.223      ; 0.633      ;
; 0.306 ; data_io:mist_data_io|bit_cnt[1]            ; data_io:mist_data_io|bit_cnt[2]                                                                         ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.426      ;
; 0.307 ; osd:osd_inst|bcnt[8]                       ; osd:osd_inst|bcnt[8]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.427      ;
; 0.308 ; osd:osd_inst|bcnt[6]                       ; osd:osd_inst|bcnt[6]                                                                                    ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.428      ;
; 0.309 ; osd:osd_inst|cnt[1]                        ; osd:osd_inst|cnt[1]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.430      ;
; 0.309 ; osd:osd_inst|cnt[3]                        ; osd:osd_inst|cnt[3]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.430      ;
; 0.310 ; user_io:my_user_io|byte_cnt[3]             ; user_io:my_user_io|byte_cnt[3]                                                                          ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.430      ;
; 0.310 ; user_io:my_user_io|bit_cnt[1]              ; user_io:my_user_io|bit_cnt[2]                                                                           ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.430      ;
; 0.311 ; osd:osd_inst|cnt[2]                        ; osd:osd_inst|cnt[2]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.432      ;
; 0.311 ; osd:osd_inst|bcnt[10]                      ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.223      ; 0.638      ;
; 0.311 ; user_io:my_user_io|byte_cnt[6]             ; user_io:my_user_io|byte_cnt[6]                                                                          ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.431      ;
; 0.311 ; user_io:my_user_io|byte_cnt[8]             ; user_io:my_user_io|byte_cnt[8]                                                                          ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.431      ;
; 0.311 ; user_io:my_user_io|byte_cnt[9]             ; user_io:my_user_io|byte_cnt[9]                                                                          ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.431      ;
; 0.312 ; osd:osd_inst|cnt[4]                        ; osd:osd_inst|cnt[4]                                                                                     ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.037      ; 0.433      ;
; 0.312 ; user_io:my_user_io|byte_cnt[5]             ; user_io:my_user_io|byte_cnt[5]                                                                          ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.432      ;
; 0.312 ; user_io:my_user_io|byte_cnt[7]             ; user_io:my_user_io|byte_cnt[7]                                                                          ; SPI_SCK      ; SPI_SCK     ; 0.000        ; 0.036      ; 0.432      ;
+-------+--------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                     ; To Node                                                                                                                                                                                                                               ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 0.186 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_seq_data_state                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_seq_data_state                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                              ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; rom_loaded                                                                                                                                                                                                    ; rom_loaded                                                                                                                                                                                                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.187 ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_data_state                                                ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_data_state                                                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                                                                                                                   ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                                                                                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.193 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reset_state                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reset_state                                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.314      ;
; 0.194 ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[1]                                                                                                                                          ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[0]                                                                                                                                                                  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.315      ;
; 0.196 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|tmp_seq_ena_state                                             ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_seq_ena_state                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.316      ;
; 0.196 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate_state                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate2_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.317      ;
; 0.197 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_init_state_1                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.317      ;
; 0.197 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.317      ;
; 0.197 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[4] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.317      ;
; 0.200 ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[0]                                                                                                                                          ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.321      ;
; 0.204 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[16]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[16]                                                                                                                                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.325      ;
; 0.208 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.328      ;
; 0.214 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[3]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[3]                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.334      ;
; 0.215 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[0]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[0]                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.335      ;
; 0.217 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[6]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[6]                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.337      ;
; 0.219 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|idle_state                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_init_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.340      ;
; 0.224 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|idle_state                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_init_state                                                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.345      ;
; 0.233 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.353      ;
; 0.233 ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.353      ;
; 0.259 ; switch_pal_ntsc:pll_switcher|pll_reconfig_write_from_rom                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_init_state                                                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.380      ;
; 0.266 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.386      ;
; 0.267 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[2]                                              ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[2]                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.387      ;
; 0.267 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[1]                                              ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[1]                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.387      ;
; 0.273 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[7]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[7]                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.393      ;
; 0.277 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[5]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[5]                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.397      ;
; 0.278 ; rom_loaded                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|reset_n_reg                                                                                                                                                                                              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.399      ;
; 0.280 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_init_state                                                ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_first_state                                                                       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.401      ;
; 0.284 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[1]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[1]                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.403      ;
; 0.284 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate_state                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.405      ;
; 0.292 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.412      ;
; 0.292 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.412      ;
; 0.292 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[11]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[11]                                                                                                                                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.413      ;
; 0.293 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.413      ;
; 0.293 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[8]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[8]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.414      ;
; 0.293 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[9]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[9]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.414      ;
; 0.293 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[13]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[13]                                                                                                                                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.414      ;
; 0.294 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.414      ;
; 0.294 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[10]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[10]                                                                                                                                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.415      ;
; 0.294 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[14]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[14]                                                                                                                                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.415      ;
; 0.294 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[15]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[15]                                                                                                                                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.415      ;
; 0.295 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.295 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.295 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[12]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[12]                                                                                                                                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.416      ;
; 0.296 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.416      ;
; 0.297 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[7] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[7]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.417      ;
; 0.297 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.418      ;
; 0.298 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.418      ;
; 0.298 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[5] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[5]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.418      ;
; 0.298 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[4] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.419      ;
; 0.298 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[7] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[7]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.419      ;
; 0.299 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.419      ;
; 0.299 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.419      ;
; 0.299 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.419      ;
; 0.299 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[6] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[6]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.419      ;
; 0.299 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.419      ;
; 0.299 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.419      ;
; 0.299 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.420      ;
; 0.300 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.420      ;
; 0.300 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[4] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[4]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.420      ;
; 0.301 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.421      ;
; 0.303 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.424      ;
; 0.305 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[5] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[5]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.426      ;
; 0.305 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[7] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[7]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.425      ;
; 0.306 ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[0]                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[0]                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.426      ;
; 0.306 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[6] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[6]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.427      ;
; 0.306 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[1]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.426      ;
; 0.306 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[3]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.426      ;
; 0.306 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[5] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[5]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.426      ;
; 0.306 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_post_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_wait_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.427      ;
; 0.306 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_ena_state                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_data_state                                                                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.426      ;
; 0.307 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.427      ;
; 0.308 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[2]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.428      ;
; 0.309 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[0]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.430      ;
; 0.309 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr16|cntr_tho:auto_generated|counter_reg_bit[7] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_address_reg0 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.224      ; 0.637      ;
; 0.310 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[0] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[0]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.430      ;
; 0.310 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[0] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[0]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.430      ;
; 0.311 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[1]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[1]                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.431      ;
; 0.312 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[2]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[2]                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.432      ;
; 0.312 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[4]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[4]                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.432      ;
; 0.314 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[7]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[7]                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.434      ;
; 0.315 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[3]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[3]                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.435      ;
; 0.315 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[5]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[5]                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.435      ;
; 0.315 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[6]  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[6]                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.435      ;
; 0.318 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|reconfig_counter_state                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.438      ;
; 0.318 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_second_state                                              ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.222      ; 0.644      ;
; 0.319 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[0] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr15|cntr_heo:auto_generated|counter_reg_bit[0]                         ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.439      ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'clk_27'                                                                                                                                                                 ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                 ; To Node                                                   ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.307      ;
; 0.194 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.314      ;
; 0.300 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.420      ;
; 0.300 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.420      ;
; 0.300 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.420      ;
; 0.377 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.497      ;
; 0.377 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.497      ;
; 0.379 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.499      ;
; 0.379 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.499      ;
; 0.437 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.557      ;
; 0.437 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.557      ;
; 0.439 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.559      ;
; 0.439 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.559      ;
; 0.442 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.562      ;
; 0.442 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.562      ;
; 0.448 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.568      ;
; 0.450 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.570      ;
; 0.457 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.577      ;
; 0.457 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.577      ;
; 0.459 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.579      ;
; 0.460 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.580      ;
; 0.478 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.598      ;
; 0.480 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.600      ;
; 0.498 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.618      ;
; 0.498 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.618      ;
; 0.504 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.624      ;
; 0.505 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.625      ;
; 0.507 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.627      ;
; 0.511 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.631      ;
; 0.511 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.631      ;
; 0.511 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.631      ;
; 0.513 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.633      ;
; 0.513 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.633      ;
; 0.514 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.634      ;
; 0.514 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.634      ;
; 0.514 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.634      ;
; 0.516 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.636      ;
; 0.516 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.636      ;
; 0.525 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.645      ;
; 0.528 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.648      ;
; 0.538 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.658      ;
; 0.560 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.680      ;
; 0.561 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.681      ;
; 0.563 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.683      ;
; 0.571 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.691      ;
; 0.575 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.695      ;
; 0.575 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.695      ;
; 0.576 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.696      ;
; 0.604 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.724      ;
; 0.612 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.732      ;
; 0.614 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.734      ;
; 0.615 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.735      ;
; 0.637 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.757      ;
; 0.638 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.758      ;
; 0.638 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.758      ;
; 0.639 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.759      ;
; 0.640 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.760      ;
; 0.641 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.761      ;
; 0.648 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.768      ;
; 0.649 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; clk_27       ; clk_27      ; 0.000        ; 0.036      ; 0.769      ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                             ;
+-------+---------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                     ; To Node                                                       ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.187 ; sdram_statemachine:sdram_adaptor|reply_reg                    ; sdram_statemachine:sdram_adaptor|reply_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.194 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
; 0.197 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.317      ;
; 0.204 ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.324      ;
; 0.263 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.384      ;
; 0.294 ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.414      ;
; 0.295 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.295 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.295 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.295 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.295 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.296 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.416      ;
; 0.297 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.417      ;
; 0.298 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.418      ;
; 0.298 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.418      ;
; 0.299 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.419      ;
; 0.299 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.419      ;
; 0.299 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.419      ;
; 0.300 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.420      ;
; 0.300 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.420      ;
; 0.301 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.422      ;
; 0.302 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.423      ;
; 0.302 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.423      ;
; 0.302 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.423      ;
; 0.303 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.424      ;
; 0.303 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.424      ;
; 0.304 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.425      ;
; 0.305 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.426      ;
; 0.306 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.427      ;
; 0.307 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.428      ;
; 0.308 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.428      ;
; 0.312 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.432      ;
; 0.312 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.433      ;
; 0.314 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.434      ;
; 0.315 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.435      ;
; 0.317 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.437      ;
; 0.317 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.437      ;
; 0.327 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.447      ;
; 0.338 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.458      ;
; 0.359 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.479      ;
; 0.421 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.541      ;
; 0.444 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.564      ;
; 0.444 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.564      ;
; 0.444 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.564      ;
; 0.446 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.566      ;
; 0.447 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.567      ;
; 0.447 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.567      ;
; 0.448 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.568      ;
; 0.448 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.568      ;
; 0.449 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.570      ;
; 0.450 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.571      ;
; 0.451 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.572      ;
; 0.452 ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.572      ;
; 0.452 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.573      ;
; 0.453 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.573      ;
; 0.453 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.573      ;
; 0.454 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.574      ;
; 0.455 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.576      ;
; 0.456 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.576      ;
; 0.456 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.576      ;
; 0.457 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.577      ;
; 0.457 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.577      ;
; 0.458 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.578      ;
; 0.458 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.578      ;
; 0.459 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.579      ;
; 0.459 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.580      ;
; 0.460 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.580      ;
; 0.461 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.582      ;
; 0.461 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.582      ;
; 0.461 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.581      ;
; 0.461 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.581      ;
; 0.462 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.583      ;
; 0.462 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.582      ;
; 0.462 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.583      ;
; 0.464 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.584      ;
; 0.464 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.585      ;
; 0.464 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.585      ;
; 0.464 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.585      ;
; 0.465 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.586      ;
; 0.465 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.586      ;
; 0.466 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.586      ;
; 0.466 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.586      ;
; 0.467 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.588      ;
; 0.469 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.589      ;
; 0.470 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.590      ;
; 0.472 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.592      ;
; 0.475 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.595      ;
; 0.475 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.595      ;
; 0.476 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.596      ;
; 0.478 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.598      ;
; 0.485 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.605      ;
; 0.488 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.608      ;
; 0.507 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.627      ;
; 0.507 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.627      ;
; 0.507 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.627      ;
; 0.510 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.630      ;
; 0.510 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.630      ;
; 0.510 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.630      ;
; 0.510 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.630      ;
+-------+---------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                   ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 1.850 ; sdram_statemachine:sdram_adaptor|cke_reg                                    ; SDRAM_CKE                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.268      ; 1.581      ;
; 2.082 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8                 ; SDRAM_DQ[8]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.320      ; 1.865      ;
; 2.082 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9                 ; SDRAM_DQ[9]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.320      ; 1.865      ;
; 2.086 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1                 ; SDRAM_DQ[1]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.326      ; 1.875      ;
; 2.090 ; sdram_statemachine:sdram_adaptor|dq_output_reg                              ; SDRAM_DQ[0]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.322      ; 1.875      ;
; 2.096 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12                ; SDRAM_DQ[12]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.316      ; 1.875      ;
; 2.096 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13                ; SDRAM_DQ[13]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.316      ; 1.875      ;
; 2.097 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11                ; SDRAM_DQ[11]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.315      ; 1.875      ;
; 2.097 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10                ; SDRAM_DQ[10]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.315      ; 1.875      ;
; 2.104 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_7                 ; SDRAM_DQ[7]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.291      ; 1.858      ;
; 2.104 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_6                 ; SDRAM_DQ[6]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.291      ; 1.858      ;
; 2.105 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14                ; SDRAM_DQ[14]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.317      ; 1.885      ;
; 2.105 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4                 ; SDRAM_DQ[4]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.290      ; 1.858      ;
; 2.105 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15                ; SDRAM_DQ[15]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.317      ; 1.885      ;
; 2.110 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3                 ; SDRAM_DQ[3]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.312      ; 1.885      ;
; 2.110 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2                 ; SDRAM_DQ[2]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.312      ; 1.885      ;
; 2.115 ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_5                 ; SDRAM_DQ[5]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.290      ; 1.868      ;
; 2.182 ; sdram_statemachine:sdram_adaptor|ba_reg[1]                                  ; SDRAM_BA[1]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.284      ; 1.929      ;
; 2.186 ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]                             ; SDRAM_DQ[12]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.307      ; 1.956      ;
; 2.190 ; sdram_statemachine:sdram_adaptor|ras_n_reg                                  ; SDRAM_nRAS                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.286      ; 1.939      ;
; 2.191 ; sdram_statemachine:sdram_adaptor|ba_reg[0]                                  ; SDRAM_BA[0]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.285      ; 1.939      ;
; 2.191 ; sdram_statemachine:sdram_adaptor|cas_n_reg                                  ; SDRAM_nCAS                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.285      ; 1.939      ;
; 2.192 ; sdram_statemachine:sdram_adaptor|addr_reg[0]                                ; SDRAM_A[0]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.284      ; 1.939      ;
; 2.192 ; sdram_statemachine:sdram_adaptor|addr_reg[10]                               ; SDRAM_A[10]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.284      ; 1.939      ;
; 2.193 ; sdram_statemachine:sdram_adaptor|addr_reg[1]                                ; SDRAM_A[1]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.283      ; 1.939      ;
; 2.193 ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                ; SDRAM_A[2]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.283      ; 1.939      ;
; 2.195 ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                             ; SDRAM_DQ[15]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.308      ; 1.966      ;
; 2.200 ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                              ; SDRAM_DQ[3]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.303      ; 1.966      ;
; 2.200 ; sdram_statemachine:sdram_adaptor|dq_out_reg[2]                              ; SDRAM_DQ[2]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.303      ; 1.966      ;
; 2.201 ; sdram_statemachine:sdram_adaptor|addr_reg[4]                                ; SDRAM_A[4]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.302      ; 1.966      ;
; 2.204 ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                ; SDRAM_A[3]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.282      ; 1.949      ;
; 2.204 ; sdram_statemachine:sdram_adaptor|we_n_reg                                   ; SDRAM_nWE                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.282      ; 1.949      ;
; 2.204 ; sdram_statemachine:sdram_adaptor|ldqm_reg                                   ; SDRAM_DQML                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.282      ; 1.949      ;
; 2.204 ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                              ; SDRAM_DQ[7]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.282      ; 1.949      ;
; 2.204 ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                              ; SDRAM_DQ[6]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.282      ; 1.949      ;
; 2.205 ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]                              ; SDRAM_DQ[4]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.281      ; 1.949      ;
; 2.215 ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]                              ; SDRAM_DQ[5]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.281      ; 1.959      ;
; 2.231 ; sdram_statemachine:sdram_adaptor|udqm_reg                                   ; SDRAM_DQMH                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.311      ; 2.005      ;
; 2.231 ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]                              ; SDRAM_DQ[8]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.311      ; 2.005      ;
; 2.231 ; sdram_statemachine:sdram_adaptor|dq_out_reg[9]                              ; SDRAM_DQ[9]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.311      ; 2.005      ;
; 2.235 ; sdram_statemachine:sdram_adaptor|dq_out_reg[1]                              ; SDRAM_DQ[1]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.317      ; 2.015      ;
; 2.239 ; sdram_statemachine:sdram_adaptor|dq_out_reg[0]                              ; SDRAM_DQ[0]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.313      ; 2.015      ;
; 2.243 ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                ; SDRAM_A[6]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.309      ; 2.015      ;
; 2.245 ; sdram_statemachine:sdram_adaptor|dq_out_reg[13]                             ; SDRAM_DQ[13]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.307      ; 2.015      ;
; 2.246 ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                ; SDRAM_A[9]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.306      ; 2.015      ;
; 2.246 ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]                             ; SDRAM_DQ[11]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.306      ; 2.015      ;
; 2.246 ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                             ; SDRAM_DQ[10]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.306      ; 2.015      ;
; 2.247 ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                ; SDRAM_A[7]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.305      ; 2.015      ;
; 2.247 ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                ; SDRAM_A[8]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.305      ; 2.015      ;
; 2.253 ; sdram_statemachine:sdram_adaptor|addr_reg[11]                               ; SDRAM_A[11]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.309      ; 2.025      ;
; 2.254 ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                             ; SDRAM_DQ[14]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.308      ; 2.025      ;
; 2.258 ; sdram_statemachine:sdram_adaptor|addr_reg[5]                                ; SDRAM_A[5]                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.447       ; 1.304      ; 2.025      ;
; 7.982 ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -6.853       ; -0.826     ; 0.470      ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                 ;
+-------+------------------------------------------------------------------------+--------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                              ; To Node                                                      ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------+--------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 5.945 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.123     ; 2.682      ;
; 5.948 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|udqm_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.128     ; 2.674      ;
; 5.949 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[0]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.130     ; 2.671      ;
; 5.951 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[0]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.184     ; 2.613      ;
; 5.954 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.121     ; 2.675      ;
; 5.954 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.126     ; 2.670      ;
; 5.955 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.128     ; 2.667      ;
; 5.955 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[9]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.128     ; 2.667      ;
; 5.955 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.126     ; 2.669      ;
; 5.957 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[9]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.182     ; 2.609      ;
; 5.957 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[8]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.182     ; 2.609      ;
; 5.961 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.122     ; 2.667      ;
; 5.961 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.122     ; 2.667      ;
; 5.962 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.119     ; 2.669      ;
; 5.965 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[1]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.134     ; 2.651      ;
; 5.967 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[1]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.188     ; 2.593      ;
; 5.968 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[2]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.120     ; 2.662      ;
; 5.968 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.120     ; 2.662      ;
; 5.970 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.174     ; 2.604      ;
; 5.970 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[3]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.174     ; 2.604      ;
; 5.971 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.123     ; 2.656      ;
; 5.971 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.123     ; 2.656      ;
; 5.971 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.124     ; 2.655      ;
; 5.971 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[13]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.124     ; 2.655      ;
; 5.971 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.125     ; 2.654      ;
; 5.971 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.125     ; 2.654      ;
; 5.973 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[11]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.177     ; 2.598      ;
; 5.973 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[14]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.179     ; 2.596      ;
; 5.973 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[13]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.178     ; 2.597      ;
; 5.973 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[12]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.178     ; 2.597      ;
; 5.973 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[15]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.179     ; 2.596      ;
; 5.973 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[10]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.177     ; 2.598      ;
; 5.983 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.099     ; 2.668      ;
; 5.983 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.099     ; 2.668      ;
; 5.983 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ba_reg[1]                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.101     ; 2.666      ;
; 5.983 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cas_n_reg                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.102     ; 2.665      ;
; 5.983 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.100     ; 2.667      ;
; 5.983 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.101     ; 2.666      ;
; 5.984 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.098     ; 2.668      ;
; 5.984 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.098     ; 2.668      ;
; 5.984 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ba_reg[0]                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.102     ; 2.664      ;
; 5.984 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ras_n_reg                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.103     ; 2.663      ;
; 5.984 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|we_n_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.099     ; 2.667      ;
; 5.984 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ldqm_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.099     ; 2.667      ;
; 5.984 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[0]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.101     ; 2.665      ;
; 5.984 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.100     ; 2.666      ;
; 5.984 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.099     ; 2.667      ;
; 5.985 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[7]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.153     ; 2.610      ;
; 5.985 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.153     ; 2.610      ;
; 5.986 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.152     ; 2.610      ;
; 5.986 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.152     ; 2.610      ;
; 6.049 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.139     ; 2.550      ;
; 6.055 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.137     ; 2.546      ;
; 6.055 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.137     ; 2.546      ;
; 6.065 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.143     ; 2.530      ;
; 6.068 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.129     ; 2.541      ;
; 6.068 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.129     ; 2.541      ;
; 6.071 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.132     ; 2.535      ;
; 6.071 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.132     ; 2.535      ;
; 6.071 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.133     ; 2.534      ;
; 6.071 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.133     ; 2.534      ;
; 6.071 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.134     ; 2.533      ;
; 6.071 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.134     ; 2.533      ;
; 6.083 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_6  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.108     ; 2.547      ;
; 6.083 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_7  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.108     ; 2.547      ;
; 6.084 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.107     ; 2.547      ;
; 6.084 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_5  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.107     ; 2.547      ;
; 6.194 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[25]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.090     ; 2.513      ;
; 6.194 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[27]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.090     ; 2.513      ;
; 6.194 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[30]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.090     ; 2.513      ;
; 6.194 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[29]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.090     ; 2.513      ;
; 6.194 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[28]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.090     ; 2.513      ;
; 6.194 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[9]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.090     ; 2.513      ;
; 6.194 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[11]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.090     ; 2.513      ;
; 6.194 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[13]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.090     ; 2.513      ;
; 6.194 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[22]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.090     ; 2.513      ;
; 6.194 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[14]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.090     ; 2.513      ;
; 6.194 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[12]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.090     ; 2.513      ;
; 6.194 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[26]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.090     ; 2.513      ;
; 6.194 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[17]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.090     ; 2.513      ;
; 6.194 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[21]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.090     ; 2.513      ;
; 6.194 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[10]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.090     ; 2.513      ;
; 6.194 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[18]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.090     ; 2.513      ;
; 6.194 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[20]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.090     ; 2.513      ;
; 6.195 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[1]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.094     ; 2.508      ;
; 6.195 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.094     ; 2.508      ;
; 6.195 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[3]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.094     ; 2.508      ;
; 6.195 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.094     ; 2.508      ;
; 6.195 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.094     ; 2.508      ;
; 6.195 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.094     ; 2.508      ;
; 6.195 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[31]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.091     ; 2.511      ;
; 6.195 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[8]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.091     ; 2.511      ;
; 6.195 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[23]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.091     ; 2.511      ;
; 6.195 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[15]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.091     ; 2.511      ;
; 6.195 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[19]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.091     ; 2.511      ;
; 6.195 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[24]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.091     ; 2.511      ;
; 6.195 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[16]            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.091     ; 2.511      ;
; 6.195 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|reply_reg                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.098     ; 2.504      ;
; 6.195 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.094     ; 2.508      ;
; 6.195 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.094     ; 2.508      ;
+-------+------------------------------------------------------------------------+--------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                   ;
+--------+------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                              ; To Node                                                                                                                                                                                                       ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 13.807 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[28]                                                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.091     ; 3.710      ;
; 13.807 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[26]                                                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.091     ; 3.710      ;
; 13.807 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[16]                                                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.091     ; 3.710      ;
; 13.807 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[18]                                                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.091     ; 3.710      ;
; 13.809 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[0]                                                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.085     ; 3.714      ;
; 13.809 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg~_Duplicate_3                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.085     ; 3.714      ;
; 13.819 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[1]                                                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.084     ; 3.705      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.089     ; 3.699      ;
; 13.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.089     ; 3.699      ;
; 13.823 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg~_Duplicate_1                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.090     ; 3.695      ;
; 13.823 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]                                                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.090     ; 3.695      ;
; 13.823 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]~_Duplicate_8                                                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.090     ; 3.695      ;
; 13.823 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[5]~_Duplicate_4                                                                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.090     ; 3.695      ;
; 13.836 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[7]                                                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.093     ; 3.679      ;
; 13.836 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[2]~_Duplicate_1                                                                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.076     ; 3.696      ;
; 13.940 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|compare_latch_reg[5]                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.090     ; 3.578      ;
; 13.940 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|keycode_latch_reg[5]                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.090     ; 3.578      ;
; 13.940 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|keycode_latch_reg[6]                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.090     ; 3.578      ;
; 13.940 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|compare_latch_reg[4]                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.090     ; 3.578      ;
; 13.940 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|keycode_latch_reg[4]                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.090     ; 3.578      ;
; 13.940 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|compare_latch_reg[0]                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.090     ; 3.578      ;
; 13.940 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|compare_latch_reg[2]                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.090     ; 3.578      ;
; 13.940 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|compare_latch_reg[3]                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.090     ; 3.578      ;
; 13.940 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|compare_latch_reg[1]                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.090     ; 3.578      ;
; 13.940 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|keycode_latch_reg[3]                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.090     ; 3.578      ;
; 13.940 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|keycode_latch_reg[0]                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.090     ; 3.578      ;
; 13.941 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[6]                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.089     ; 3.578      ;
; 13.941 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[2]                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.089     ; 3.578      ;
; 13.941 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[2]                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.089     ; 3.578      ;
; 13.941 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[3]                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.089     ; 3.578      ;
; 13.941 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[3]                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.089     ; 3.578      ;
; 13.941 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[5]                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.089     ; 3.578      ;
; 13.941 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[5]                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.089     ; 3.578      ;
; 13.941 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[7]                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.089     ; 3.578      ;
; 13.941 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[7]                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.089     ; 3.578      ;
; 13.941 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|cntr_g7h:cntr5|counter_reg_bit[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.093     ; 3.574      ;
; 13.941 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[4]                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.089     ; 3.578      ;
; 13.941 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|last_bus_reg[0]                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.098     ; 3.569      ;
; 13.945 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf1_reg[2]                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.087     ; 3.576      ;
; 13.945 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|wide_delay_line:audf1_delay|shift_reg[0][2]                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.087     ; 3.576      ;
; 13.945 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf1_reg[0]                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.087     ; 3.576      ;
; 13.945 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|wide_delay_line:audf1_delay|shift_reg[0][0]                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.087     ; 3.576      ;
; 13.945 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer1|count_reg[0]                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.087     ; 3.576      ;
; 13.945 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf1_reg[1]                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.087     ; 3.576      ;
; 13.945 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|wide_delay_line:audf1_delay|shift_reg[0][1]                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.087     ; 3.576      ;
; 13.945 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer1|count_reg[1]                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.087     ; 3.576      ;
; 13.945 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer1|count_reg[2]                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.087     ; 3.576      ;
; 13.945 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf1_reg[3]                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.087     ; 3.576      ;
; 13.945 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|wide_delay_line:audf1_delay|shift_reg[0][3]                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.087     ; 3.576      ;
; 13.945 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer1|count_reg[3]                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.087     ; 3.576      ;
; 13.945 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf1_reg[4]                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.087     ; 3.576      ;
; 13.945 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|wide_delay_line:audf1_delay|shift_reg[0][4]                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.087     ; 3.576      ;
; 13.945 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer1|count_reg[4]                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.087     ; 3.576      ;
; 13.945 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf1_reg[5]                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.087     ; 3.576      ;
; 13.945 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|wide_delay_line:audf1_delay|shift_reg[0][5]                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.087     ; 3.576      ;
; 13.945 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer1|count_reg[5]                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.087     ; 3.576      ;
; 13.945 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf1_reg[6]                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.087     ; 3.576      ;
; 13.945 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|wide_delay_line:audf1_delay|shift_reg[0][6]                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.087     ; 3.576      ;
; 13.945 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer1|count_reg[6]                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.087     ; 3.576      ;
; 13.945 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf1_reg[7]                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.087     ; 3.576      ;
; 13.945 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|wide_delay_line:audf1_delay|shift_reg[0][7]                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.087     ; 3.576      ;
; 13.945 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer1|count_reg[7]                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.087     ; 3.576      ;
; 13.945 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer1|delay_line:underflow0_delay|shift_reg[2]                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.087     ; 3.576      ;
; 13.945 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer1|delay_line:underflow0_delay|shift_reg[1]                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.087     ; 3.576      ;
; 13.945 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[4]                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.084     ; 3.579      ;
; 13.945 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_raw_reg[6]                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.088     ; 3.575      ;
; 13.945 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[0]                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.084     ; 3.579      ;
; 13.945 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[1]                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.084     ; 3.579      ;
; 13.945 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_raw_reg[7]                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.088     ; 3.575      ;
; 13.945 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_raw_reg[4]                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.084     ; 3.579      ;
; 13.945 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_raw_reg[5]                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.084     ; 3.579      ;
; 13.945 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_raw_reg[6]                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.084     ; 3.579      ;
; 13.945 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|sizep3_raw_reg[1]                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.084     ; 3.579      ;
; 13.945 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|sizep3_snap_reg[1]                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.084     ; 3.579      ;
; 13.945 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|sizep3_raw_reg[0]                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.084     ; 3.579      ;
; 13.945 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|sizep3_snap_reg[0]                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.084     ; 3.579      ;
; 13.945 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; scandoubler:scandoubler1|output_address_reg[0]                                                                                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.581      ;
; 13.945 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; scandoubler:scandoubler1|output_address_reg[1]                                                                                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.581      ;
; 13.945 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; scandoubler:scandoubler1|output_address_reg[2]                                                                                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.581      ;
; 13.945 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; scandoubler:scandoubler1|output_address_reg[3]                                                                                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.581      ;
; 13.945 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; scandoubler:scandoubler1|output_address_reg[4]                                                                                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.581      ;
; 13.945 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; scandoubler:scandoubler1|output_address_reg[5]                                                                                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.581      ;
; 13.945 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; scandoubler:scandoubler1|output_address_reg[6]                                                                                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.581      ;
; 13.945 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; scandoubler:scandoubler1|output_address_reg[7]                                                                                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.581      ;
; 13.945 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; scandoubler:scandoubler1|output_address_reg[8]                                                                                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.581      ;
; 13.945 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; scandoubler:scandoubler1|output_address_reg[9]                                                                                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.581      ;
; 13.945 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; scandoubler:scandoubler1|output_address_reg[10]                                                                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 3.581      ;
; 13.945 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|pot_from_signed:pot2|count_reg[0]                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.085     ; 3.578      ;
; 13.945 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|pot_from_signed:pot2|count_reg[1]                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.085     ; 3.578      ;
; 13.945 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|pot_from_signed:pot2|count_reg[2]                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.085     ; 3.578      ;
; 13.945 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|pot_from_signed:pot2|count_reg[3]                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.085     ; 3.578      ;
; 13.945 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|pot_from_signed:pot2|count_reg[4]                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.085     ; 3.578      ;
; 13.945 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|pot_from_signed:pot2|count_reg[5]                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.085     ; 3.578      ;
; 13.945 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|pot_from_signed:pot2|count_reg[6]                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.085     ; 3.578      ;
; 13.945 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|pot_from_signed:pot2|count_reg[7]                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.085     ; 3.578      ;
; 13.945 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|pot_from_signed:pot2|count_reg[8]                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.085     ; 3.578      ;
; 13.945 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|pot_from_signed:pot2|count_reg[9]                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.085     ; 3.578      ;
; 13.946 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|irqen_reg[7]                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.090     ; 3.572      ;
; 13.946 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|latch_delay_line:stimer_delay|data_in_reg                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.086     ; 3.576      ;
; 13.946 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|latch_delay_line:stimer_delay|shift_reg[2]                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.086     ; 3.576      ;
+--------+------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                         ; To Node                                                                                                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.681 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|dffe4                                                                 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|altsyncram_14b1:altsyncram2|ram_block5a0                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.202      ; 0.973      ;
; 0.978 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a59 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.185      ; 1.253      ;
; 0.978 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a58 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.185      ; 1.253      ;
; 0.978 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a57 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.185      ; 1.253      ;
; 0.978 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a56 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.185      ; 1.253      ;
; 0.978 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a55 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.185      ; 1.253      ;
; 0.978 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a54 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.185      ; 1.253      ;
; 0.978 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a53 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.185      ; 1.253      ;
; 0.978 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a52 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.185      ; 1.253      ;
; 0.978 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a51 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.185      ; 1.253      ;
; 0.978 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a50 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.185      ; 1.253      ;
; 0.978 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a49 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.185      ; 1.253      ;
; 0.978 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a48 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.185      ; 1.253      ;
; 0.978 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a31 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.185      ; 1.253      ;
; 0.978 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a30 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.185      ; 1.253      ;
; 0.978 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a29 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.185      ; 1.253      ;
; 0.978 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a28 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.185      ; 1.253      ;
; 0.978 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a27 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.185      ; 1.253      ;
; 0.978 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a26 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.185      ; 1.253      ;
; 0.978 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a25 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.185      ; 1.253      ;
; 0.978 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a24 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.185      ; 1.253      ;
; 0.978 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a23 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.185      ; 1.253      ;
; 0.978 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a22 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.185      ; 1.253      ;
; 0.978 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a21 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.185      ; 1.253      ;
; 0.978 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a20 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.185      ; 1.253      ;
; 0.978 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a19 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.185      ; 1.253      ;
; 0.978 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a18 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.185      ; 1.253      ;
; 0.978 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a17 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.185      ; 1.253      ;
; 0.978 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.185      ; 1.253      ;
; 1.126 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a63 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.397      ;
; 1.126 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a62 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.397      ;
; 1.126 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a61 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.397      ;
; 1.126 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a60 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.397      ;
; 1.126 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a47 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.397      ;
; 1.126 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a46 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.397      ;
; 1.126 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a45 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.397      ;
; 1.126 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a44 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.397      ;
; 1.126 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a43 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.397      ;
; 1.126 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a42 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.397      ;
; 1.126 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a41 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.397      ;
; 1.126 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a40 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.397      ;
; 1.126 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a39 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.397      ;
; 1.126 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a38 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.397      ;
; 1.126 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a37 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.397      ;
; 1.126 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a36 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.397      ;
; 1.126 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a35 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.397      ;
; 1.126 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a34 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.397      ;
; 1.126 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a33 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.397      ;
; 1.126 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a32 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.397      ;
; 1.126 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a15 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.397      ;
; 1.126 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a14 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.397      ;
; 1.126 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a13 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.397      ;
; 1.126 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a12 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.397      ;
; 1.126 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a11 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.397      ;
; 1.126 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a10 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.397      ;
; 1.126 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a9  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.397      ;
; 1.126 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a8  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.397      ;
; 1.126 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a7  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.397      ;
; 1.126 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a6  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.397      ;
; 1.126 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a5  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.397      ;
; 1.126 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a4  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.397      ;
; 1.126 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a3  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.397      ;
; 1.126 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a2  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.397      ;
; 1.126 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a1  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.397      ;
; 1.126 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.397      ;
; 1.860 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ioctl_state.IOCTL_IDLE~_Duplicate_7                                                                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.278      ; 2.222      ;
; 1.860 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|refresh_sreg                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.278      ; 2.222      ;
; 1.861 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ioctl_state.IOCTL_IDLE~_Duplicate_5                                                                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.283      ; 2.228      ;
; 2.025 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ioctl_state.IOCTL_IDLE~_Duplicate_3                                                                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.296      ; 2.405      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_lpf_p2[14]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.221      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_lpf_p2[15]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.221      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_lpf_p2[16]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.221      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p2[15]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.221      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_lpf_p2[17]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.221      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p2[16]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.221      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_lpf_p2[18]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.221      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p2[17]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.221      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_lpf_p2[19]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.221      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p2[18]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.221      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_lpf_p2[20]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.221      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p2[19]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.221      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_lpf_p2[21]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.221      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p2[20]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.221      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_lpf_p2[22]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.221      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p2[21]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.221      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_lpf_p2[23]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.221      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p2[22]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.221      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p2[14]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.221      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_lpf_p2[12]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.221      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_lpf_p2[13]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.221      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p2[13]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.221      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p2[12]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.221      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p2[23]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.221      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|dac_out                                                                                                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.094      ; 2.220      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|ADDRESS_IN_sreg[13]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 2.226      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; sdram_statemachine:sdram_adaptor|ADDRESS_IN_sreg[21]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 2.226      ;
; 2.043 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ZPU_IN1[29]                                                                                                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.085      ; 2.212      ;
; 2.043 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; ZPU_IN1[30]                                                                                                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.085      ; 2.212      ;
; 2.043 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p1[13]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.222      ;
; 2.043 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; hq_dac:dac_left|r_data_fwd_p1[14]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.222      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                   ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                              ; To Node                                                       ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 2.029 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.100      ; 2.232      ;
; 2.029 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.100      ; 2.232      ;
; 2.029 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.100      ; 2.232      ;
; 2.029 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.100      ; 2.232      ;
; 2.029 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.100      ; 2.232      ;
; 2.029 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.100      ; 2.232      ;
; 2.029 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.100      ; 2.232      ;
; 2.029 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.100      ; 2.232      ;
; 2.029 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.100      ; 2.232      ;
; 2.029 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.100      ; 2.232      ;
; 2.029 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.100      ; 2.232      ;
; 2.029 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.100      ; 2.232      ;
; 2.030 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.097      ; 2.230      ;
; 2.030 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.097      ; 2.230      ;
; 2.030 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.097      ; 2.230      ;
; 2.030 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.097      ; 2.230      ;
; 2.030 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.097      ; 2.230      ;
; 2.030 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.097      ; 2.230      ;
; 2.030 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.097      ; 2.230      ;
; 2.030 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.097      ; 2.230      ;
; 2.030 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.097      ; 2.230      ;
; 2.030 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.097      ; 2.230      ;
; 2.030 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.097      ; 2.230      ;
; 2.030 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cke_reg                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.098      ; 2.231      ;
; 2.041 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.088      ; 2.232      ;
; 2.041 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.088      ; 2.232      ;
; 2.041 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.088      ; 2.232      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.088      ; 2.233      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.088      ; 2.233      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.088      ; 2.233      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.088      ; 2.233      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.088      ; 2.233      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[27]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.093      ; 2.238      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[30]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.093      ; 2.238      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[29]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.093      ; 2.238      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[28]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.093      ; 2.238      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[31]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.091      ; 2.236      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[5]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 2.231      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[7]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 2.231      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[4]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 2.231      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[6]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 2.231      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[1]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 2.231      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[2]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 2.231      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[3]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 2.231      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[9]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.093      ; 2.238      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[11]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.093      ; 2.238      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[8]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.091      ; 2.236      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[23]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.091      ; 2.236      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[13]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.093      ; 2.238      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[15]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.091      ; 2.236      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[22]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.093      ; 2.238      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[0]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 2.231      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[14]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.093      ; 2.238      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[12]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.093      ; 2.238      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[26]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.093      ; 2.238      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[19]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.091      ; 2.236      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[17]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.093      ; 2.238      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[21]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.093      ; 2.238      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[24]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.091      ; 2.236      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[16]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.091      ; 2.236      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[10]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.093      ; 2.238      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[18]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.093      ; 2.238      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[20]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.093      ; 2.238      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|reply_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 2.229      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.088      ; 2.233      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.088      ; 2.233      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.088      ; 2.233      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.088      ; 2.233      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.088      ; 2.233      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.088      ; 2.233      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.088      ; 2.233      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.088      ; 2.233      ;
; 2.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.088      ; 2.233      ;
; 2.043 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[25]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.093      ; 2.239      ;
; 2.116 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 2.279      ;
; 2.116 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_5   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 2.279      ;
; 2.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_6   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 2.279      ;
; 2.117 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_7   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 2.279      ;
; 2.133 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.057      ; 2.273      ;
; 2.133 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.057      ; 2.273      ;
; 2.133 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.055      ; 2.271      ;
; 2.133 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.055      ; 2.271      ;
; 2.133 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.054      ; 2.270      ;
; 2.133 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.054      ; 2.270      ;
; 2.133 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.052      ; 2.268      ;
; 2.133 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.052      ; 2.268      ;
; 2.140 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.043      ; 2.266      ;
; 2.146 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.050      ; 2.279      ;
; 2.146 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.050      ; 2.279      ;
; 2.153 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.047      ; 2.283      ;
; 2.237 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.088      ; 2.402      ;
; 2.237 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.088      ; 2.402      ;
; 2.237 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ba_reg[0]                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 2.398      ;
; 2.237 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ba_reg[1]                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 2.400      ;
; 2.237 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ras_n_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 2.397      ;
; 2.237 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cas_n_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.085      ; 2.399      ;
; 2.237 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|we_n_reg                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.087      ; 2.401      ;
; 2.237 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ldqm_reg                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.087      ; 2.401      ;
; 2.237 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[0]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.085      ; 2.399      ;
; 2.237 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[1]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 2.400      ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                             ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                 ; Clock Edge ; Target                                                        ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------+
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[0]              ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[15]             ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[16]             ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[19]             ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[1]              ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[23]             ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[24]             ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[2]              ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[31]             ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[3]              ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[4]              ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[5]              ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[6]              ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[7]              ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[8]              ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|reply_reg                    ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cke_reg                      ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[10]             ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[11]             ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[12]             ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[13]             ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[14]             ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[17]             ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[18]             ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[20]             ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[21]             ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[22]             ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[25]             ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[26]             ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[27]             ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[28]             ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[29]             ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[30]             ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[9]              ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ;
; 4.189 ; 4.344        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_6   ;
; 4.189 ; 4.344        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_7   ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ;
; 4.190 ; 4.345        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2   ;
; 4.190 ; 4.345        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3   ;
; 4.190 ; 4.345        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4   ;
; 4.190 ; 4.345        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_5   ;
; 4.191 ; 4.346        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1   ;
; 4.193 ; 4.348        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg                ;
; 4.193 ; 4.348        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10  ;
; 4.193 ; 4.348        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11  ;
; 4.193 ; 4.348        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12  ;
; 4.193 ; 4.348        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13  ;
; 4.193 ; 4.348        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14  ;
; 4.193 ; 4.348        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15  ;
; 4.193 ; 4.348        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8   ;
; 4.193 ; 4.348        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9   ;
; 4.194 ; 4.349        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[6]                 ;
; 4.194 ; 4.349        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[7]                 ;
; 4.195 ; 4.350        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[2]                 ;
; 4.195 ; 4.350        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[3]                 ;
; 4.195 ; 4.350        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[4]                 ;
; 4.195 ; 4.350        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[5]                 ;
; 4.196 ; 4.351        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[1]                 ;
; 4.198 ; 4.353        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[0]                 ;
; 4.198 ; 4.353        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[10]                ;
; 4.198 ; 4.353        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[11]                ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                     ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                 ; Clock Edge ; Target                                                                                                                                ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+
; 4.331 ; 4.400        ; 0.069          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 4.357 ; 4.410        ; 0.053          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 4.378 ; 4.378        ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK                                                                                                                             ;
; 4.378 ; 4.378        ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK~output|i                                                                                                                    ;
; 4.378 ; 4.378        ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK~output|o                                                                                                                    ;
; 4.400 ; 4.400        ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 4.400 ; 4.400        ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|outclk                                                 ;
; 4.410 ; 4.410        ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 4.410 ; 4.410        ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|outclk                                                 ;
; 4.431 ; 4.431        ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK                                                                                                                             ;
; 4.431 ; 4.431        ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK~output|i                                                                                                                    ;
; 4.431 ; 4.431        ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK~output|o                                                                                                                    ;
; 4.810 ; 8.810        ; 4.000          ; Port Rate        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; SDRAM_CLK                                                                                                                             ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                         ;
+-------+--------------+----------------+-----------------+-----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type            ; Clock                                                                 ; Clock Edge ; Target                                                                                                                                                                                                                                     ;
+-------+--------------+----------------+-----------------+-----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 8.557 ; 8.787        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_p4s3:auto_generated|ram_block1a13~porta_address_reg0                                                                                                                           ;
; 8.559 ; 8.789        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_address_reg0                                                                                              ;
; 8.559 ; 8.789        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg                                                                                                    ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                              ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_we_reg                                                                                                                                    ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|generic_ram_infer:freezer_bram|altsyncram:ram_block_rtl_0|altsyncram_jc41:auto_generated|ram_block1a0~porta_address_reg0 ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|generic_ram_infer:freezer_bram|altsyncram:ram_block_rtl_0|altsyncram_jc41:auto_generated|ram_block1a0~porta_we_reg       ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|generic_ram_infer:reg_file1|altsyncram:ram_block_rtl_0|altsyncram_lc41:auto_generated|ram_block1a0~porta_address_reg0                                 ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|generic_ram_infer:reg_file1|altsyncram:ram_block_rtl_0|altsyncram_lc41:auto_generated|ram_block1a0~porta_we_reg                                       ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16~porta_address_reg0   ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_address_reg0                                                                                              ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg                                                                                                    ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a4~porta_address_reg0                                                                                              ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a4~porta_we_reg                                                                                                    ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a4~porta_address_reg0                                                                                              ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a4~porta_we_reg                                                                                                    ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_p4s3:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                            ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_p4s3:auto_generated|ram_block1a10~porta_address_reg0                                                                                                                           ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_p4s3:auto_generated|ram_block1a11~porta_address_reg0                                                                                                                           ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_p4s3:auto_generated|ram_block1a14~porta_address_reg0                                                                                                                           ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_p4s3:auto_generated|ram_block1a23~porta_address_reg0                                                                                                                           ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_p4s3:auto_generated|ram_block1a2~porta_address_reg0                                                                                                                            ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_p4s3:auto_generated|ram_block1a3~porta_address_reg0                                                                                                                            ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_p4s3:auto_generated|ram_block1a4~porta_address_reg0                                                                                                                            ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_p4s3:auto_generated|ram_block1a5~porta_address_reg0                                                                                                                            ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_p4s3:auto_generated|ram_block1a6~porta_address_reg0                                                                                                                            ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_p4s3:auto_generated|ram_block1a7~porta_address_reg0                                                                                                                            ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_p4s3:auto_generated|ram_block1a9~porta_address_reg0                                                                                                                            ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                           ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                 ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a3~porta_address_reg0                                                                                                           ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a3~porta_we_reg                                                                                                                 ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                           ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                 ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a3~porta_address_reg0                                                                                                           ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a3~porta_we_reg                                                                                                                 ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                            ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                  ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a3~porta_address_reg0                                                                                                            ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a3~porta_we_reg                                                                                                                  ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~portb_address_reg0                                                                                                                              ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~portb_we_reg                                                                                                                                    ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_address_reg0    ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16~portb_address_reg0   ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_datain_reg0                                                                                               ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_p4s3:auto_generated|ram_block1a8~porta_address_reg0                                                                                                                            ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a3~porta_address_reg0                                                                                                          ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a3~porta_we_reg                                                                                                                ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                               ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|generic_ram_infer:freezer_bram|altsyncram:ram_block_rtl_0|altsyncram_jc41:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|generic_ram_infer:reg_file1|altsyncram:ram_block_rtl_0|altsyncram_lc41:auto_generated|ram_block1a0~porta_datain_reg0                                  ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~portb_address_reg0    ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16~porta_datain_reg0    ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|gtia_palette:palette4|altsyncram:Mux18_rtl_0|altsyncram_vq01:auto_generated|ram_block1a0~porta_address_reg0                                                                                                       ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_datain_reg0                                                                                               ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a4~porta_datain_reg0                                                                                               ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a4~porta_datain_reg0                                                                                               ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                            ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a3~porta_datain_reg0                                                                                                            ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                            ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a3~porta_datain_reg0                                                                                                            ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                             ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a3~porta_datain_reg0                                                                                                             ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|altsyncram_cg81:FIFOram|ram_block1a0~porta_address_reg0             ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|altsyncram_cg81:FIFOram|ram_block1a0~porta_we_reg                   ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_tg31:auto_generated|a_dpfifo_4n31:dpfifo|altsyncram_gd81:FIFOram|ram_block1a0~porta_address_reg0           ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_tg31:auto_generated|a_dpfifo_4n31:dpfifo|altsyncram_gd81:FIFOram|ram_block1a0~porta_we_reg                 ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; DualPortRAM:sector_buffer|altsyncram:ram_rtl_0|altsyncram_jim1:auto_generated|ram_block1a0~portb_datain_reg0                                                                                                                               ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a0~porta_datain_reg0     ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_nkm:auto_generated|altsyncram_14b1:altsyncram2|ram_block5a0~porta_address_reg0                                                                    ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_p4s3:auto_generated|ram_block1a12~porta_address_reg0                                                                                                                           ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_p4s3:auto_generated|ram_block1a1~porta_address_reg0                                                                                                                            ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                          ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a3~porta_datain_reg0                                                                                                           ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a16                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a17                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a18                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a19                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a20                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a21                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a22                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a23                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a24                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a25                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a26                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a27                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a28                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a29                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a30                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a31                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a48                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a49                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a50                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a51                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a52                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a53                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a54                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a55                      ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_l4n:auto_generated|altsyncram_u761:altsyncram4|ram_block7a56                      ;
+-------+--------------+----------------+-----------------+-----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                           ;
+--------+--------------+----------------+------------------+----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                ; Clock Edge ; Target                                                                                     ;
+--------+--------------+----------------+------------------+----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------+
; 16.300 ; 16.300       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 16.300 ; 16.300       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 16.300 ; 16.300       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 16.300 ; 16.300       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 16.310 ; 16.310       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 16.310 ; 16.310       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 16.315 ; 16.315       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 16.316 ; 16.316       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 16.321 ; 16.321       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 16.321 ; 16.321       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 16.330 ; 16.330       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 16.330 ; 16.330       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 16.330 ; 16.330       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 16.330 ; 16.330       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
+--------+--------------+----------------+------------------+----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'clk_27'                                                                                                               ;
+--------+--------------+----------------+------------------+--------+------------+--------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target                                                                         ;
+--------+--------------+----------------+------------------+--------+------------+--------------------------------------------------------------------------------+
; 17.784 ; 17.968       ; 0.184          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                      ;
; 17.784 ; 17.968       ; 0.184          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                      ;
; 17.784 ; 17.968       ; 0.184          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                      ;
; 17.784 ; 17.968       ; 0.184          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                      ;
; 17.784 ; 17.968       ; 0.184          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                      ;
; 17.784 ; 17.968       ; 0.184          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                      ;
; 17.784 ; 17.968       ; 0.184          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                      ;
; 17.784 ; 17.968       ; 0.184          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                      ;
; 17.784 ; 17.968       ; 0.184          ; Low Pulse Width  ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                        ;
; 17.928 ; 17.928       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 17.928 ; 17.928       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 17.929 ; 17.929       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                       ;
; 17.929 ; 17.929       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|observablevcoout             ;
; 17.960 ; 17.960       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; CLOCK_27[0]~input|o                                                            ;
; 17.964 ; 17.964       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[0]|clk                                          ;
; 17.964 ; 17.964       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[1]|clk                                          ;
; 17.964 ; 17.964       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[2]|clk                                          ;
; 17.964 ; 17.964       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[3]|clk                                          ;
; 17.964 ; 17.964       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[4]|clk                                          ;
; 17.964 ; 17.964       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[5]|clk                                          ;
; 17.964 ; 17.964       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[6]|clk                                          ;
; 17.964 ; 17.964       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[7]|clk                                          ;
; 17.964 ; 17.964       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; zpu|config_regs|tick_toggle_reg|clk                                            ;
; 17.970 ; 17.970       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 17.971 ; 17.971       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|inclk[0]                     ;
; 17.972 ; 17.972       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; CLOCK_27[0]~inputclkctrl|inclk[0]                                              ;
; 17.972 ; 17.972       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; CLOCK_27[0]~inputclkctrl|outclk                                                ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; CLOCK_27[0]~input|i                                                            ;
; 18.519 ; 18.519       ; 0.000          ; Low Pulse Width  ; clk_27 ; Rise       ; CLOCK_27[0]~input|i                                                            ;
; 18.851 ; 19.067       ; 0.216          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                      ;
; 18.851 ; 19.067       ; 0.216          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                      ;
; 18.851 ; 19.067       ; 0.216          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                      ;
; 18.851 ; 19.067       ; 0.216          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                      ;
; 18.851 ; 19.067       ; 0.216          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                      ;
; 18.851 ; 19.067       ; 0.216          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                      ;
; 18.851 ; 19.067       ; 0.216          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                      ;
; 18.851 ; 19.067       ; 0.216          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                      ;
; 18.851 ; 19.067       ; 0.216          ; High Pulse Width ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                        ;
; 19.064 ; 19.064       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; CLOCK_27[0]~inputclkctrl|inclk[0]                                              ;
; 19.064 ; 19.064       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; CLOCK_27[0]~inputclkctrl|outclk                                                ;
; 19.066 ; 19.066       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|inclk[0]                     ;
; 19.067 ; 19.067       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 19.073 ; 19.073       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[0]|clk                                          ;
; 19.073 ; 19.073       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[1]|clk                                          ;
; 19.073 ; 19.073       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[2]|clk                                          ;
; 19.073 ; 19.073       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[3]|clk                                          ;
; 19.073 ; 19.073       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[4]|clk                                          ;
; 19.073 ; 19.073       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[5]|clk                                          ;
; 19.073 ; 19.073       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[6]|clk                                          ;
; 19.073 ; 19.073       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_count_reg[7]|clk                                          ;
; 19.073 ; 19.073       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; zpu|config_regs|tick_toggle_reg|clk                                            ;
; 19.077 ; 19.077       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; CLOCK_27[0]~input|o                                                            ;
; 19.107 ; 19.107       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                       ;
; 19.107 ; 19.107       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|observablevcoout             ;
; 19.108 ; 19.108       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 19.108 ; 19.108       ; 0.000          ; High Pulse Width ; clk_27 ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 33.037 ; 37.037       ; 4.000          ; Port Rate        ; clk_27 ; Rise       ; CLOCK_27[0]                                                                    ;
; 35.037 ; 37.037       ; 2.000          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                      ;
; 35.037 ; 37.037       ; 2.000          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                      ;
; 35.037 ; 37.037       ; 2.000          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                      ;
; 35.037 ; 37.037       ; 2.000          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                      ;
; 35.037 ; 37.037       ; 2.000          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                      ;
; 35.037 ; 37.037       ; 2.000          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                      ;
; 35.037 ; 37.037       ; 2.000          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                      ;
; 35.037 ; 37.037       ; 2.000          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                      ;
; 35.037 ; 37.037       ; 2.000          ; Min Period       ; clk_27 ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                        ;
+--------+--------------+----------------+------------------+--------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'SPI_SCK'                                                                                                                                        ;
+--------+--------------+----------------+------------------+---------+------------+---------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock   ; Clock Edge ; Target                                                                                                  ;
+--------+--------------+----------------+------------------+---------+------------+---------------------------------------------------------------------------------------------------------+
; 20.000 ; 20.230       ; 0.230          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_address_reg0 ;
; 20.000 ; 20.230       ; 0.230          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_we_reg       ;
; 20.001 ; 20.231       ; 0.230          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_address_reg0 ;
; 20.001 ; 20.231       ; 0.230          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_we_reg       ;
; 20.002 ; 20.232       ; 0.230          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a4~porta_datain_reg0  ;
; 20.003 ; 20.233       ; 0.230          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|altsyncram:osd_buffer_rtl_0|altsyncram_4ke1:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 20.022 ; 20.238       ; 0.216          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|SPI_MISO~reg0                                                                        ;
; 20.023 ; 20.239       ; 0.216          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|SPI_MISO~en                                                                          ;
; 20.023 ; 20.239       ; 0.216          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[0]                                                                   ;
; 20.023 ; 20.239       ; 0.216          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[1]                                                                   ;
; 20.023 ; 20.239       ; 0.216          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[2]                                                                   ;
; 20.023 ; 20.239       ; 0.216          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[3]                                                                   ;
; 20.023 ; 20.239       ; 0.216          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[4]                                                                   ;
; 20.023 ; 20.239       ; 0.216          ; High Pulse Width ; SPI_SCK ; Fall       ; user_io:my_user_io|serial_out_rptr[5]                                                                   ;
; 20.063 ; 20.247       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[0]                                                                               ;
; 20.063 ; 20.247       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[1]                                                                               ;
; 20.063 ; 20.247       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[2]                                                                               ;
; 20.063 ; 20.247       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[3]                                                                               ;
; 20.063 ; 20.247       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|sbuf[0]                                                                              ;
; 20.063 ; 20.247       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|sbuf[1]                                                                              ;
; 20.063 ; 20.247       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|sbuf[2]                                                                              ;
; 20.063 ; 20.247       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_in[0]                                                                       ;
; 20.063 ; 20.247       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_in[1]                                                                       ;
; 20.063 ; 20.247       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_in[2]                                                                       ;
; 20.063 ; 20.247       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_in[3]                                                                       ;
; 20.063 ; 20.247       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_receiver_strobe_r                                                                ;
; 20.063 ; 20.247       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_transmitter.sd_lba_r[29]                                                         ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|bit_cnt[0]                                                                         ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|bit_cnt[1]                                                                         ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|bit_cnt[2]                                                                         ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|sbuf[0]                                                                            ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|sbuf[1]                                                                            ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|sbuf[2]                                                                            ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|sbuf[3]                                                                            ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|sbuf[4]                                                                            ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|sbuf[5]                                                                            ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|sbuf[6]                                                                            ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[0]                                                                     ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[1]                                                                     ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[2]                                                                     ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[3]                                                                     ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[4]                                                                     ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[5]                                                                     ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[6]                                                                     ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_byte_in[7]                                                                     ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_receiver_strobe_r                                                              ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; data_io:mist_data_io|spi_transfer_end_r                                                                 ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[0]                                                                                    ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[10]                                                                                   ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[1]                                                                                    ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[2]                                                                                    ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[3]                                                                                    ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[4]                                                                                    ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[5]                                                                                    ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[6]                                                                                    ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[7]                                                                                    ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[8]                                                                                    ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|bcnt[9]                                                                                    ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cmd[3]                                                                                     ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cmd[4]                                                                                     ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cmd[5]                                                                                     ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cmd[6]                                                                                     ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cmd[7]                                                                                     ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cnt[0]                                                                                     ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cnt[1]                                                                                     ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cnt[2]                                                                                     ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cnt[3]                                                                                     ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|cnt[4]                                                                                     ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|sbuf[0]                                                                                    ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|sbuf[1]                                                                                    ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|sbuf[2]                                                                                    ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|sbuf[3]                                                                                    ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|sbuf[4]                                                                                    ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|sbuf[5]                                                                                    ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; osd:osd_inst|sbuf[6]                                                                                    ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|bit_cnt[0]                                                                           ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|bit_cnt[1]                                                                           ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|bit_cnt[2]                                                                           ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[0]                                                                          ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[1]                                                                          ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[2]                                                                          ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[3]                                                                          ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[4]                                                                          ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[5]                                                                          ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[6]                                                                          ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[7]                                                                          ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[8]                                                                          ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|byte_cnt[9]                                                                          ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[4]                                                                               ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[5]                                                                               ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[6]                                                                               ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|cmd[7]                                                                               ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|sbuf[3]                                                                              ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|sbuf[4]                                                                              ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|sbuf[5]                                                                              ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|sbuf[6]                                                                              ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_in[4]                                                                       ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_in[5]                                                                       ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_in[6]                                                                       ;
; 20.065 ; 20.249       ; 0.184          ; Low Pulse Width  ; SPI_SCK ; Rise       ; user_io:my_user_io|spi_byte_in[7]                                                                       ;
+--------+--------------+----------------+------------------+---------+------------+---------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                      ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                                                                                                                                                                                                                ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 40.631 ; 41.641       ; 1.010          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ;
; 40.680 ; 41.690       ; 1.010          ; Low Pulse Width  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                         ;
; 41.415 ; 41.645       ; 0.230          ; Low Pulse Width  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_address_reg0                                                                                     ;
; 41.415 ; 41.645       ; 0.230          ; Low Pulse Width  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|ram_block1a0~porta_re_reg                                                                                           ;
; 41.415 ; 41.645       ; 0.230          ; Low Pulse Width  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_address_reg0 ;
; 41.415 ; 41.645       ; 0.230          ; Low Pulse Width  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_we_reg       ;
; 41.416 ; 41.646       ; 0.230          ; Low Pulse Width  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|q_a[0]                                                                                                              ;
; 41.416 ; 41.646       ; 0.230          ; Low Pulse Width  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pal_rom:pll_rom_pal|altsyncram:altsyncram_component|altsyncram_gfr3:auto_generated|q_a[0]                                                                                                                ;
; 41.417 ; 41.647       ; 0.230          ; Low Pulse Width  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 41.437 ; 41.653       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate3_state                                                                   ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                                                                  ;
; 41.451 ; 41.667       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[0]                                                                      ;
; 41.451 ; 41.667       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[3]                                                                      ;
; 41.451 ; 41.667       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[5]                                                                      ;
; 41.451 ; 41.667       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[6]                                                                      ;
; 41.451 ; 41.667       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[7]                                                                      ;
; 41.451 ; 41.667       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[0]                         ;
; 41.451 ; 41.667       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[1]                         ;
; 41.451 ; 41.667       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[2]                         ;
; 41.451 ; 41.667       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[3]                         ;
; 41.451 ; 41.667       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[4]                         ;
; 41.451 ; 41.667       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[5]                         ;
; 41.451 ; 41.667       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[6]                         ;
; 41.451 ; 41.667       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[7]                         ;
; 41.451 ; 41.667       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[0]                         ;
; 41.451 ; 41.667       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1]                         ;
; 41.451 ; 41.667       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2]                         ;
; 41.451 ; 41.667       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3]                         ;
; 41.451 ; 41.667       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[4]                         ;
; 41.451 ; 41.667       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5]                         ;
; 41.451 ; 41.667       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[0]                          ;
; 41.451 ; 41.667       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[1]                          ;
; 41.451 ; 41.667       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[2]                          ;
; 41.451 ; 41.667       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[3]                          ;
; 41.451 ; 41.667       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[4]                          ;
; 41.451 ; 41.667       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[5]                          ;
; 41.451 ; 41.667       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[6]                          ;
; 41.451 ; 41.667       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr2|cntr_18o:auto_generated|counter_reg_bit[7]                          ;
; 41.451 ; 41.667       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|rom_data_state                                                                        ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; rom_loaded                                                                                                                                                                                                                            ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|ntsc_rom:pll_rom_ntsc|altsyncram:altsyncram_component|altsyncram_bjr3:auto_generated|rden_a_store                                                                                                        ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                                                                                                                                           ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[0]                                                                                                                                                                                 ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[10]                                                                                                                                                                                ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[11]                                                                                                                                                                                ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[12]                                                                                                                                                                                ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[13]                                                                                                                                                                                ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[14]                                                                                                                                                                                ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[15]                                                                                                                                                                                ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[16]                                                                                                                                                                                ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                                                 ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                                                 ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                                                 ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                                                 ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                                                 ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                                                 ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                                                 ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[8]                                                                                                                                                                                 ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[9]                                                                                                                                                                                 ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_reconfig_write_from_rom                                                                                                                                                                              ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                         ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                                         ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                                         ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                         ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                      ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|reset_n_reg                                                                                                                                                                                              ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[0]                                                                                                                                                                  ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[1]                                                                                                                                                                  ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_data_state                                                                         ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C0_ena_state                                                                          ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_data_state                                                                         ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C1_ena_state                                                                          ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_data_state                                                                         ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C2_ena_state                                                                          ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_data_state                                                                         ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C3_ena_state                                                                          ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_data_state                                                                         ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|C4_ena_state                                                                          ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[0]                                                                     ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[1]                                                                     ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[2]                                                                     ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[3]                                                                     ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[4]                                                                     ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[5]                                                                     ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[6]                                                                     ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom2[7]                                                                     ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[1]                                                                      ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[2]                                                                      ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|addr_from_rom[4]                                                                      ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_init_state_1                                                                   ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|areset_state                                                                          ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate2_state                                                                   ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|configupdate_state                                                                    ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|idle_state                                                                            ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[0]                         ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[1]                         ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[2]                         ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[3]                         ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[4]                         ;
; 41.452 ; 41.668       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_op51:video_pll_reconfig_pllrcfg_op51_component|lpm_counter:cntr14|cntr_keo:auto_generated|counter_reg_bit[5]                         ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                     ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+
; CONF_DATA0    ; SPI_SCK    ; 2.837 ; 3.500 ; Rise       ; SPI_SCK                                                               ;
; SPI_DI        ; SPI_SCK    ; 2.387 ; 2.773 ; Rise       ; SPI_SCK                                                               ;
; SPI_SS2       ; SPI_SCK    ; 0.662 ; 1.065 ; Rise       ; SPI_SCK                                                               ;
; SPI_SS3       ; SPI_SCK    ; 1.032 ; 1.442 ; Rise       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; clk_27     ; 1.470 ; 2.022 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 1.465 ; 2.017 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 1.469 ; 2.021 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 1.465 ; 2.017 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 1.465 ; 2.017 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 1.446 ; 2.004 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 1.456 ; 2.014 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 1.447 ; 2.005 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 1.447 ; 2.005 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 1.453 ; 2.005 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 1.453 ; 2.005 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 1.458 ; 2.010 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 1.458 ; 2.010 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 1.459 ; 2.011 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 1.459 ; 2.011 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 1.470 ; 2.022 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 1.470 ; 2.022 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                        ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; CONF_DATA0    ; SPI_SCK    ; -1.540 ; -2.315 ; Rise       ; SPI_SCK                                                               ;
; SPI_DI        ; SPI_SCK    ; 0.175  ; -0.248 ; Rise       ; SPI_SCK                                                               ;
; SPI_SS2       ; SPI_SCK    ; -0.500 ; -0.922 ; Rise       ; SPI_SCK                                                               ;
; SPI_SS3       ; SPI_SCK    ; -0.090 ; -0.545 ; Rise       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; clk_27     ; -0.968 ; -1.526 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; -0.988 ; -1.540 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; -0.992 ; -1.544 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; -0.988 ; -1.540 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; -0.988 ; -1.540 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; -0.968 ; -1.526 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; -0.978 ; -1.536 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; -0.969 ; -1.527 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; -0.969 ; -1.527 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; -0.975 ; -1.527 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; -0.975 ; -1.527 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; -0.980 ; -1.532 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; -0.980 ; -1.532 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; -0.981 ; -1.533 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; -0.981 ; -1.533 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; -0.993 ; -1.545 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; -0.993 ; -1.545 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                             ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK    ; 5.994  ; 5.934  ; Fall       ; SPI_SCK                                                               ;
; SDRAM_A[*]    ; clk_27     ; 1.615  ; 1.481  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; clk_27     ; 1.534  ; 1.413  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; clk_27     ; 1.535  ; 1.414  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; clk_27     ; 1.536  ; 1.415  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; clk_27     ; 1.546  ; 1.425  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; clk_27     ; 1.539  ; 1.424  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; clk_27     ; 1.615  ; 1.481  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; clk_27     ; 1.599  ; 1.465  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; clk_27     ; 1.603  ; 1.469  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; clk_27     ; 1.603  ; 1.469  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; clk_27     ; 1.603  ; 1.469  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; clk_27     ; 1.535  ; 1.414  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; clk_27     ; 1.610  ; 1.476  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; clk_27     ; 1.533  ; 1.412  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; clk_27     ; 1.533  ; 1.412  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; clk_27     ; 1.525  ; 1.404  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CKE     ; clk_27     ; 1.059  ; 1.053  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; clk_27     ; 1.610  ; 1.476  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 1.595  ; 1.461  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 1.591  ; 1.457  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 1.537  ; 1.422  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 1.537  ; 1.422  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 1.547  ; 1.426  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 1.557  ; 1.436  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 1.546  ; 1.425  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 1.546  ; 1.425  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 1.588  ; 1.454  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 1.588  ; 1.454  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 1.603  ; 1.469  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 1.603  ; 1.469  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 1.524  ; 1.409  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 1.602  ; 1.468  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 1.610  ; 1.476  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 1.532  ; 1.417  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH    ; clk_27     ; 1.587  ; 1.453  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML    ; clk_27     ; 1.546  ; 1.425  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nCAS    ; clk_27     ; 1.534  ; 1.413  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nRAS    ; clk_27     ; 1.532  ; 1.411  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nWE     ; clk_27     ; 1.546  ; 1.425  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; VGA_B[*]      ; clk_27     ; 10.447 ; 10.467 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; clk_27     ; 10.093 ; 10.112 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; clk_27     ; 10.338 ; 10.351 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; clk_27     ; 10.447 ; 10.467 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; clk_27     ; 10.143 ; 10.154 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[4]     ; clk_27     ; 10.035 ; 10.101 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[5]     ; clk_27     ; 9.959  ; 10.054 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; clk_27     ; 9.643  ; 9.667  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; clk_27     ; 9.643  ; 9.667  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; clk_27     ; 9.510  ; 9.554  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; clk_27     ; 9.488  ; 9.647  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; clk_27     ; 9.340  ; 9.364  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[4]     ; clk_27     ; 9.239  ; 9.226  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[5]     ; clk_27     ; 8.111  ; 8.327  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS        ; clk_27     ; 4.314  ; 4.051  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]      ; clk_27     ; 10.977 ; 11.024 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]     ; clk_27     ; 10.877 ; 10.888 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]     ; clk_27     ; 10.932 ; 10.931 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]     ; clk_27     ; 10.977 ; 11.024 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]     ; clk_27     ; 10.773 ; 10.847 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[4]     ; clk_27     ; 10.700 ; 10.831 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[5]     ; clk_27     ; 10.432 ; 10.462 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS        ; clk_27     ; 3.895  ; 3.812  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; clk_27     ; -1.808 ;        ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; clk_27     ;        ; -1.834 ; Fall       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                     ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK    ; 5.892  ; 5.824  ; Fall       ; SPI_SCK                                                               ;
; SDRAM_A[*]    ; clk_27     ; 1.105  ; 0.986  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; clk_27     ; 1.105  ; 0.986  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; clk_27     ; 1.106  ; 0.987  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; clk_27     ; 1.106  ; 0.987  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; clk_27     ; 1.117  ; 0.998  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; clk_27     ; 1.108  ; 0.995  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; clk_27     ; 1.184  ; 1.052  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; clk_27     ; 1.169  ; 1.037  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; clk_27     ; 1.173  ; 1.041  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; clk_27     ; 1.173  ; 1.041  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; clk_27     ; 1.172  ; 1.040  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; clk_27     ; 1.105  ; 0.986  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; clk_27     ; 1.179  ; 1.047  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; clk_27     ; 1.095  ; 0.976  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; clk_27     ; 1.104  ; 0.985  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; clk_27     ; 1.095  ; 0.976  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CKE     ; clk_27     ; 0.651  ; 0.644  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; clk_27     ; 1.093  ; 0.980  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 1.165  ; 1.033  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 1.161  ; 1.029  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 1.107  ; 0.994  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 1.107  ; 0.994  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 1.118  ; 0.999  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 1.128  ; 1.009  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 1.117  ; 0.998  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 1.117  ; 0.998  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 1.157  ; 1.025  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 1.157  ; 1.025  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 1.172  ; 1.040  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 1.172  ; 1.040  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 1.093  ; 0.980  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 1.171  ; 1.039  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 1.180  ; 1.048  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 1.102  ; 0.989  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH    ; clk_27     ; 1.157  ; 1.025  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML    ; clk_27     ; 1.117  ; 0.998  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nCAS    ; clk_27     ; 1.104  ; 0.985  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nRAS    ; clk_27     ; 1.103  ; 0.984  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nWE     ; clk_27     ; 1.117  ; 0.998  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; VGA_B[*]      ; clk_27     ; 2.604  ; 2.614  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; clk_27     ; 2.681  ; 2.666  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; clk_27     ; 2.604  ; 2.614  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; clk_27     ; 2.722  ; 2.709  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; clk_27     ; 2.778  ; 2.781  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[4]     ; clk_27     ; 2.893  ; 2.897  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[5]     ; clk_27     ; 2.997  ; 3.093  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; clk_27     ; 2.785  ; 2.861  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; clk_27     ; 2.928  ; 2.972  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; clk_27     ; 2.790  ; 2.915  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; clk_27     ; 2.829  ; 3.012  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; clk_27     ; 2.837  ; 2.861  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[4]     ; clk_27     ; 2.785  ; 3.056  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[5]     ; clk_27     ; 2.880  ; 3.123  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS        ; clk_27     ; 3.109  ; 2.906  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]      ; clk_27     ; 2.616  ; 2.626  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]     ; clk_27     ; 2.616  ; 2.626  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]     ; clk_27     ; 2.674  ; 2.705  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]     ; clk_27     ; 2.767  ; 2.784  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]     ; clk_27     ; 2.946  ; 2.999  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[4]     ; clk_27     ; 2.762  ; 2.815  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[5]     ; clk_27     ; 2.792  ; 2.850  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS        ; clk_27     ; 3.068  ; 2.851  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; clk_27     ; -2.192 ;        ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; clk_27     ;        ; -2.219 ; Fall       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+


+----------------------------------------------------------+
; Propagation Delay                                        ;
+------------+-------------+-------+-------+-------+-------+
; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
+------------+-------------+-------+-------+-------+-------+
; CONF_DATA0 ; SPI_DO      ; 6.101 ; 6.101 ; 6.724 ; 6.697 ;
+------------+-------------+-------+-------+-------+-------+


+----------------------------------------------------------+
; Minimum Propagation Delay                                ;
+------------+-------------+-------+-------+-------+-------+
; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
+------------+-------------+-------+-------+-------+-------+
; CONF_DATA0 ; SPI_DO      ; 5.171 ; 5.054 ; 5.674 ; 5.674 ;
+------------+-------------+-------+-------+-------+-------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                             ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK    ; 5.631 ; 5.604 ; Fall       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; clk_27     ; 2.249 ; 2.171 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 2.264 ; 2.178 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 2.260 ; 2.174 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 2.284 ; 2.198 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 2.284 ; 2.198 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 2.250 ; 2.175 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 2.260 ; 2.185 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 2.249 ; 2.174 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 2.249 ; 2.174 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 2.257 ; 2.171 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 2.257 ; 2.171 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 2.272 ; 2.186 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 2.272 ; 2.186 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 2.271 ; 2.185 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 2.271 ; 2.185 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 2.279 ; 2.193 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 2.279 ; 2.193 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                     ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK    ; 4.622 ; 4.622 ; Fall       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; clk_27     ; 0.933 ; 0.876 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 0.941 ; 0.884 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 0.937 ; 0.880 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 0.961 ; 0.904 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 0.961 ; 0.904 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 0.953 ; 0.899 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 0.963 ; 0.909 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 0.952 ; 0.898 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 0.952 ; 0.898 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 0.933 ; 0.876 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 0.933 ; 0.876 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 0.948 ; 0.891 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 0.948 ; 0.891 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 0.947 ; 0.890 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 0.947 ; 0.890 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 0.956 ; 0.899 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 0.956 ; 0.899 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                    ;
+---------------+------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK    ; 5.837     ; 5.837     ; Fall       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; clk_27     ; 2.225     ; 2.281     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 2.237     ; 2.296     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 2.233     ; 2.292     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 2.257     ; 2.316     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 2.257     ; 2.316     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 2.226     ; 2.282     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 2.236     ; 2.292     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 2.225     ; 2.281     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 2.225     ; 2.281     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 2.230     ; 2.289     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 2.230     ; 2.289     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 2.245     ; 2.304     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 2.245     ; 2.304     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 2.244     ; 2.303     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 2.244     ; 2.303     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 2.252     ; 2.311     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 2.252     ; 2.311     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+-----------+-----------+------------+-----------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                            ;
+---------------+------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK    ; 4.821     ; 4.938     ; Fall       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; clk_27     ; 0.907     ; 1.081     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 0.915     ; 1.089     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 0.911     ; 1.085     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 0.935     ; 1.109     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 0.935     ; 1.109     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 0.930     ; 1.116     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 0.940     ; 1.126     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 0.929     ; 1.115     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 0.929     ; 1.115     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 0.907     ; 1.081     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 0.907     ; 1.081     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 0.922     ; 1.096     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 0.922     ; 1.096     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 0.921     ; 1.095     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 0.921     ; 1.095     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 0.930     ; 1.104     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 0.930     ; 1.104     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+-----------+-----------+------------+-----------------------------------------------------------------------+


---------------------------------------------
; Fast 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+------------------------------------------------------------------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary                                                                                                ;
+------------------------------------------------------------------------+--------+-------+----------+---------+---------------------+
; Clock                                                                  ; Setup  ; Hold  ; Recovery ; Removal ; Minimum Pulse Width ;
+------------------------------------------------------------------------+--------+-------+----------+---------+---------------------+
; Worst-case Slack                                                       ; -1.593 ; 0.139 ; 2.684    ; 0.681   ; 4.093               ;
;  SPI_SCK                                                               ; 14.954 ; 0.140 ; N/A      ; N/A     ; 20.000              ;
;  clk_27                                                                ; 34.116 ; 0.187 ; N/A      ; N/A     ; 17.784              ;
;  pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.945  ; 0.187 ; 2.684    ; 2.029   ; 4.093               ;
;  pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.593  ; 0.139 ; 9.374    ; 0.681   ; 8.379               ;
;  pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -1.593 ; 1.850 ; N/A      ; N/A     ; 4.167               ;
;  pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; N/A    ; N/A   ; N/A      ; N/A     ; 16.275              ;
;  reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 36.854 ; 0.186 ; N/A      ; N/A     ; 40.596              ;
; Design-wide TNS                                                        ; -1.593 ; 0.0   ; 0.0      ; 0.0     ; 0.0                 ;
;  SPI_SCK                                                               ; 0.000  ; 0.000 ; N/A      ; N/A     ; 0.000               ;
;  clk_27                                                                ; 0.000  ; 0.000 ; N/A      ; N/A     ; 0.000               ;
;  pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000  ; 0.000 ; 0.000    ; 0.000   ; 0.000               ;
;  pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000  ; 0.000 ; 0.000    ; 0.000   ; 0.000               ;
;  pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -1.593 ; 0.000 ; N/A      ; N/A     ; 0.000               ;
;  pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; N/A    ; N/A   ; N/A      ; N/A     ; 0.000               ;
;  reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 0.000  ; 0.000 ; N/A      ; N/A     ; 0.000               ;
+------------------------------------------------------------------------+--------+-------+----------+---------+---------------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                     ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+
; CONF_DATA0    ; SPI_SCK    ; 6.210 ; 6.745 ; Rise       ; SPI_SCK                                                               ;
; SPI_DI        ; SPI_SCK    ; 5.438 ; 5.538 ; Rise       ; SPI_SCK                                                               ;
; SPI_SS2       ; SPI_SCK    ; 1.398 ; 1.746 ; Rise       ; SPI_SCK                                                               ;
; SPI_SS3       ; SPI_SCK    ; 2.185 ; 2.561 ; Rise       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; clk_27     ; 3.025 ; 3.138 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 3.021 ; 3.134 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 3.025 ; 3.138 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 3.015 ; 3.128 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 3.015 ; 3.128 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 2.964 ; 3.081 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 2.974 ; 3.091 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 2.964 ; 3.081 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 2.965 ; 3.082 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 3.008 ; 3.121 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 3.008 ; 3.121 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 3.010 ; 3.123 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 3.010 ; 3.123 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 3.011 ; 3.124 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 3.011 ; 3.124 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 3.023 ; 3.136 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 3.023 ; 3.136 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+-------+-------+------------+-----------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                        ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; CONF_DATA0    ; SPI_SCK    ; -1.540 ; -2.315 ; Rise       ; SPI_SCK                                                               ;
; SPI_DI        ; SPI_SCK    ; 0.521  ; 0.354  ; Rise       ; SPI_SCK                                                               ;
; SPI_SS2       ; SPI_SCK    ; -0.500 ; -0.922 ; Rise       ; SPI_SCK                                                               ;
; SPI_SS3       ; SPI_SCK    ; -0.090 ; -0.323 ; Rise       ; SPI_SCK                                                               ;
; SDRAM_DQ[*]   ; clk_27     ; -0.968 ; -1.526 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; -0.988 ; -1.540 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; -0.992 ; -1.544 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; -0.988 ; -1.540 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; -0.988 ; -1.540 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; -0.968 ; -1.526 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; -0.978 ; -1.536 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; -0.969 ; -1.527 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; -0.969 ; -1.527 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; -0.975 ; -1.527 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; -0.975 ; -1.527 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; -0.980 ; -1.532 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; -0.980 ; -1.532 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; -0.981 ; -1.533 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; -0.981 ; -1.533 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; -0.993 ; -1.545 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; -0.993 ; -1.545 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                             ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK    ; 10.658 ; 10.161 ; Fall       ; SPI_SCK                                                               ;
; SDRAM_A[*]    ; clk_27     ; 3.319  ; 3.129  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; clk_27     ; 3.163  ; 2.970  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; clk_27     ; 3.164  ; 2.971  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; clk_27     ; 3.165  ; 2.972  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; clk_27     ; 3.175  ; 2.982  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; clk_27     ; 3.162  ; 2.985  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; clk_27     ; 3.319  ; 3.129  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; clk_27     ; 3.302  ; 3.112  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; clk_27     ; 3.307  ; 3.117  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; clk_27     ; 3.307  ; 3.117  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; clk_27     ; 3.303  ; 3.113  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; clk_27     ; 3.164  ; 2.971  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; clk_27     ; 3.310  ; 3.120  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; clk_27     ; 3.162  ; 2.969  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; clk_27     ; 3.162  ; 2.969  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; clk_27     ; 3.154  ; 2.961  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CKE     ; clk_27     ; 2.450  ; 2.326  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; clk_27     ; 3.310  ; 3.120  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 3.291  ; 3.101  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 3.287  ; 3.097  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 3.155  ; 2.978  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 3.155  ; 2.978  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 3.176  ; 2.983  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 3.186  ; 2.993  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 3.176  ; 2.983  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 3.176  ; 2.983  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 3.284  ; 3.094  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 3.284  ; 3.094  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 3.302  ; 3.112  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 3.302  ; 3.112  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 3.142  ; 2.965  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 3.301  ; 3.111  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 3.310  ; 3.120  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 3.151  ; 2.974  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH    ; clk_27     ; 3.284  ; 3.094  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML    ; clk_27     ; 3.175  ; 2.982  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nCAS    ; clk_27     ; 3.163  ; 2.970  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nRAS    ; clk_27     ; 3.162  ; 2.969  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nWE     ; clk_27     ; 3.175  ; 2.982  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; VGA_B[*]      ; clk_27     ; 24.807 ; 24.476 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; clk_27     ; 24.007 ; 23.632 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; clk_27     ; 24.509 ; 24.262 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; clk_27     ; 24.807 ; 24.476 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; clk_27     ; 23.904 ; 23.615 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[4]     ; clk_27     ; 23.746 ; 23.460 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[5]     ; clk_27     ; 23.676 ; 23.244 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; clk_27     ; 22.695 ; 22.283 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; clk_27     ; 22.695 ; 22.283 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; clk_27     ; 22.412 ; 21.985 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; clk_27     ; 22.579 ; 22.020 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; clk_27     ; 21.912 ; 21.538 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[4]     ; clk_27     ; 21.600 ; 21.520 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[5]     ; clk_27     ; 19.417 ; 18.723 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS        ; clk_27     ; 8.335  ; 7.714  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]      ; clk_27     ; 26.090 ; 25.835 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]     ; clk_27     ; 25.847 ; 25.576 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]     ; clk_27     ; 25.963 ; 25.682 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]     ; clk_27     ; 26.090 ; 25.835 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]     ; clk_27     ; 25.481 ; 25.266 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[4]     ; clk_27     ; 25.482 ; 25.289 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[5]     ; clk_27     ; 24.662 ; 24.519 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS        ; clk_27     ; 7.680  ; 6.998  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; clk_27     ; -0.884 ;        ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; clk_27     ;        ; -1.122 ; Fall       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                     ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+
; SPI_DO        ; SPI_SCK    ; 5.892  ; 5.824  ; Fall       ; SPI_SCK                                                               ;
; SDRAM_A[*]    ; clk_27     ; 1.105  ; 0.986  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; clk_27     ; 1.105  ; 0.986  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; clk_27     ; 1.106  ; 0.987  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; clk_27     ; 1.106  ; 0.987  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; clk_27     ; 1.117  ; 0.998  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; clk_27     ; 1.108  ; 0.995  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; clk_27     ; 1.184  ; 1.052  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; clk_27     ; 1.169  ; 1.037  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; clk_27     ; 1.173  ; 1.041  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; clk_27     ; 1.173  ; 1.041  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; clk_27     ; 1.172  ; 1.040  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; clk_27     ; 1.105  ; 0.986  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; clk_27     ; 1.179  ; 1.047  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; clk_27     ; 1.095  ; 0.976  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; clk_27     ; 1.104  ; 0.985  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; clk_27     ; 1.095  ; 0.976  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CKE     ; clk_27     ; 0.651  ; 0.644  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; clk_27     ; 1.093  ; 0.980  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; clk_27     ; 1.165  ; 1.033  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; clk_27     ; 1.161  ; 1.029  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; clk_27     ; 1.107  ; 0.994  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; clk_27     ; 1.107  ; 0.994  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; clk_27     ; 1.118  ; 0.999  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; clk_27     ; 1.128  ; 1.009  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; clk_27     ; 1.117  ; 0.998  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; clk_27     ; 1.117  ; 0.998  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; clk_27     ; 1.157  ; 1.025  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; clk_27     ; 1.157  ; 1.025  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; clk_27     ; 1.172  ; 1.040  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; clk_27     ; 1.172  ; 1.040  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; clk_27     ; 1.093  ; 0.980  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; clk_27     ; 1.171  ; 1.039  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; clk_27     ; 1.180  ; 1.048  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; clk_27     ; 1.102  ; 0.989  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH    ; clk_27     ; 1.157  ; 1.025  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML    ; clk_27     ; 1.117  ; 0.998  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nCAS    ; clk_27     ; 1.104  ; 0.985  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nRAS    ; clk_27     ; 1.103  ; 0.984  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nWE     ; clk_27     ; 1.117  ; 0.998  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; VGA_B[*]      ; clk_27     ; 2.604  ; 2.614  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; clk_27     ; 2.681  ; 2.666  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; clk_27     ; 2.604  ; 2.614  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; clk_27     ; 2.722  ; 2.709  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; clk_27     ; 2.778  ; 2.781  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[4]     ; clk_27     ; 2.893  ; 2.897  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[5]     ; clk_27     ; 2.997  ; 3.093  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; clk_27     ; 2.785  ; 2.861  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; clk_27     ; 2.928  ; 2.972  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; clk_27     ; 2.790  ; 2.915  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; clk_27     ; 2.829  ; 3.012  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; clk_27     ; 2.837  ; 2.861  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[4]     ; clk_27     ; 2.785  ; 3.056  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[5]     ; clk_27     ; 2.880  ; 3.123  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS        ; clk_27     ; 3.109  ; 2.906  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]      ; clk_27     ; 2.616  ; 2.626  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]     ; clk_27     ; 2.616  ; 2.626  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]     ; clk_27     ; 2.674  ; 2.705  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]     ; clk_27     ; 2.767  ; 2.784  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]     ; clk_27     ; 2.946  ; 2.999  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[4]     ; clk_27     ; 2.762  ; 2.815  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[5]     ; clk_27     ; 2.792  ; 2.850  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS        ; clk_27     ; 3.068  ; 2.851  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; clk_27     ; -2.192 ;        ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; clk_27     ;        ; -2.219 ; Fall       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+---------------+------------+--------+--------+------------+-----------------------------------------------------------------------+


+--------------------------------------------------------------+
; Progagation Delay                                            ;
+------------+-------------+--------+--------+--------+--------+
; Input Port ; Output Port ; RR     ; RF     ; FR     ; FF     ;
+------------+-------------+--------+--------+--------+--------+
; CONF_DATA0 ; SPI_DO      ; 11.002 ; 10.762 ; 11.387 ; 11.387 ;
+------------+-------------+--------+--------+--------+--------+


+----------------------------------------------------------+
; Minimum Progagation Delay                                ;
+------------+-------------+-------+-------+-------+-------+
; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
+------------+-------------+-------+-------+-------+-------+
; CONF_DATA0 ; SPI_DO      ; 5.171 ; 5.054 ; 5.674 ; 5.674 ;
+------------+-------------+-------+-------+-------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                   ;
+--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; Pin          ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
+--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; VGA_VS       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_HS       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[0]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[1]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[2]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[3]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[4]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[5]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[0]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[1]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[2]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[3]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[4]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[5]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[0]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[1]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[2]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[3]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[4]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[5]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; AUDIO_L      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; AUDIO_R      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_BA[0]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_BA[1]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_nCS    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_nRAS   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_nCAS   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_nWE    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQMH   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQML   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_CLK    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_CKE    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[0]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[1]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[2]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[3]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[4]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[5]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[6]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[7]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[8]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[9]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[10]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[11]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[12]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; LED          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; UART_TX      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[0]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[1]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[2]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[3]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[4]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[5]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[6]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[7]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[8]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[9]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[10] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[11] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[12] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[13] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[14] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[15] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SPI_DO       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+


+------------------------------------------------------------------+
; Input Transition Times                                           ;
+---------------+--------------+-----------------+-----------------+
; Pin           ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+---------------+--------------+-----------------+-----------------+
; CLOCK_27[1]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; UART_RX       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SPI_SS4       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[0]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[1]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[2]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[3]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[4]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[5]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[6]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[7]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[8]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[9]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[10]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[11]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[12]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[13]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[14]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[15]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SPI_DO        ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SPI_SCK       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; CONF_DATA0    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SPI_DI        ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SPI_SS3       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; CLOCK_27[0]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SPI_SS2       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; ~ALTERA_DCLK~ ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+---------------+--------------+-----------------+-----------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin          ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; VGA_VS       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.08 V              ; -0.00526 V          ; 0.185 V                              ; 0.249 V                              ; 5.8e-09 s                   ; 4.45e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.47e-07 V                  ; 3.08 V             ; -0.00526 V         ; 0.185 V                             ; 0.249 V                             ; 5.8e-09 s                  ; 4.45e-09 s                 ; Yes                       ; Yes                       ;
; VGA_HS       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.08 V              ; -0.00526 V          ; 0.185 V                              ; 0.249 V                              ; 5.8e-09 s                   ; 4.45e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.47e-07 V                  ; 3.08 V             ; -0.00526 V         ; 0.185 V                             ; 0.249 V                             ; 5.8e-09 s                  ; 4.45e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; VGA_B[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; VGA_B[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; VGA_B[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; VGA_B[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; VGA_B[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; VGA_G[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; VGA_G[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; VGA_G[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; VGA_G[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; VGA_G[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; VGA_G[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; VGA_R[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; VGA_R[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; VGA_R[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; VGA_R[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; VGA_R[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; VGA_R[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; AUDIO_L      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.08 V              ; -0.00526 V          ; 0.185 V                              ; 0.249 V                              ; 5.8e-09 s                   ; 4.45e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.47e-07 V                  ; 3.08 V             ; -0.00526 V         ; 0.185 V                             ; 0.249 V                             ; 5.8e-09 s                  ; 4.45e-09 s                 ; Yes                       ; Yes                       ;
; AUDIO_R      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.08 V              ; -0.00545 V          ; 0.234 V                              ; 0.291 V                              ; 5.77e-09 s                  ; 4.44e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 5.01e-07 V                  ; 3.08 V             ; -0.00545 V         ; 0.234 V                             ; 0.291 V                             ; 5.77e-09 s                 ; 4.44e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_BA[0]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; SDRAM_BA[1]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; SDRAM_nCS    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; SDRAM_nRAS   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; SDRAM_nCAS   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; SDRAM_nWE    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; SDRAM_DQMH   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; SDRAM_DQML   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; SDRAM_CLK    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; SDRAM_CKE    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0671 V           ; 0.235 V                              ; 0.176 V                              ; 6.85e-10 s                  ; 6.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0671 V          ; 0.235 V                             ; 0.176 V                             ; 6.85e-10 s                 ; 6.31e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[0]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[1]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[2]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[3]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[4]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0671 V           ; 0.235 V                              ; 0.176 V                              ; 6.85e-10 s                  ; 6.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0671 V          ; 0.235 V                             ; 0.176 V                             ; 6.85e-10 s                 ; 6.31e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[5]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; SDRAM_A[6]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; SDRAM_A[7]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; SDRAM_A[8]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; SDRAM_A[9]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; SDRAM_A[10]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[11]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; SDRAM_A[12]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0671 V           ; 0.235 V                              ; 0.176 V                              ; 6.85e-10 s                  ; 6.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0671 V          ; 0.235 V                             ; 0.176 V                             ; 6.85e-10 s                 ; 6.31e-10 s                 ; Yes                       ; No                        ;
; LED          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.08 V              ; -0.00545 V          ; 0.234 V                              ; 0.291 V                              ; 5.77e-09 s                  ; 4.44e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 5.01e-07 V                  ; 3.08 V             ; -0.00545 V         ; 0.234 V                             ; 0.291 V                             ; 5.77e-09 s                 ; 4.44e-09 s                 ; Yes                       ; Yes                       ;
; UART_TX      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.08 V              ; -0.00526 V          ; 0.185 V                              ; 0.249 V                              ; 5.8e-09 s                   ; 4.45e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.47e-07 V                  ; 3.08 V             ; -0.00526 V         ; 0.185 V                             ; 0.249 V                             ; 5.8e-09 s                  ; 4.45e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[0]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[1]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[2]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0671 V           ; 0.235 V                              ; 0.176 V                              ; 6.85e-10 s                  ; 6.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0671 V          ; 0.235 V                             ; 0.176 V                             ; 6.85e-10 s                 ; 6.31e-10 s                 ; Yes                       ; No                        ;
; SDRAM_DQ[3]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0671 V           ; 0.235 V                              ; 0.176 V                              ; 6.85e-10 s                  ; 6.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0671 V          ; 0.235 V                             ; 0.176 V                             ; 6.85e-10 s                 ; 6.31e-10 s                 ; Yes                       ; No                        ;
; SDRAM_DQ[4]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; SDRAM_DQ[5]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; SDRAM_DQ[6]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; SDRAM_DQ[7]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; SDRAM_DQ[8]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[9]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[10] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[11] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[12] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0671 V           ; 0.235 V                              ; 0.176 V                              ; 6.85e-10 s                  ; 6.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0671 V          ; 0.235 V                             ; 0.176 V                             ; 6.85e-10 s                 ; 6.31e-10 s                 ; Yes                       ; No                        ;
; SDRAM_DQ[13] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[14] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[15] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0671 V           ; 0.235 V                              ; 0.176 V                              ; 6.85e-10 s                  ; 6.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0671 V          ; 0.235 V                             ; 0.176 V                             ; 6.85e-10 s                 ; 6.31e-10 s                 ; Yes                       ; No                        ;
; SPI_DO       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.08 V              ; -0.00545 V          ; 0.234 V                              ; 0.291 V                              ; 5.77e-09 s                  ; 4.44e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 5.01e-07 V                  ; 3.08 V             ; -0.00545 V         ; 0.234 V                             ; 0.291 V                             ; 5.77e-09 s                 ; 4.44e-09 s                 ; Yes                       ; Yes                       ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin          ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; VGA_VS       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.48 V              ; -0.0176 V           ; 0.357 V                              ; 0.323 V                              ; 3.9e-09 s                   ; 3.06e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.48 V             ; -0.0176 V          ; 0.357 V                             ; 0.323 V                             ; 3.9e-09 s                  ; 3.06e-09 s                 ; No                        ; No                        ;
; VGA_HS       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.48 V              ; -0.0176 V           ; 0.357 V                              ; 0.323 V                              ; 3.9e-09 s                   ; 3.06e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.48 V             ; -0.0176 V          ; 0.357 V                             ; 0.323 V                             ; 3.9e-09 s                  ; 3.06e-09 s                 ; No                        ; No                        ;
; VGA_B[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; VGA_B[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; VGA_B[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; VGA_B[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; VGA_B[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; VGA_B[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; VGA_G[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; VGA_G[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; VGA_G[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; VGA_G[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; VGA_G[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; VGA_G[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; VGA_R[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; VGA_R[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; VGA_R[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; VGA_R[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; VGA_R[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; VGA_R[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; AUDIO_L      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.48 V              ; -0.0176 V           ; 0.357 V                              ; 0.323 V                              ; 3.9e-09 s                   ; 3.06e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.48 V             ; -0.0176 V          ; 0.357 V                             ; 0.323 V                             ; 3.9e-09 s                  ; 3.06e-09 s                 ; No                        ; No                        ;
; AUDIO_R      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.48 V              ; -0.0164 V           ; 0.353 V                              ; 0.315 V                              ; 3.88e-09 s                  ; 3.06e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.48 V             ; -0.0164 V          ; 0.353 V                             ; 0.315 V                             ; 3.88e-09 s                 ; 3.06e-09 s                 ; No                        ; No                        ;
; SDRAM_BA[0]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; SDRAM_BA[1]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; SDRAM_nCS    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; SDRAM_nRAS   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; SDRAM_nCAS   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; SDRAM_nWE    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; SDRAM_DQMH   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; SDRAM_DQML   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; SDRAM_CLK    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; SDRAM_CKE    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.6 V               ; -0.129 V            ; 0.303 V                              ; 0.209 V                              ; 4.54e-10 s                  ; 4.11e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.6 V              ; -0.129 V           ; 0.303 V                             ; 0.209 V                             ; 4.54e-10 s                 ; 4.11e-10 s                 ; No                        ; No                        ;
; SDRAM_A[0]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; SDRAM_A[1]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; SDRAM_A[2]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; SDRAM_A[3]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; SDRAM_A[4]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.6 V               ; -0.129 V            ; 0.303 V                              ; 0.209 V                              ; 4.54e-10 s                  ; 4.11e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.6 V              ; -0.129 V           ; 0.303 V                             ; 0.209 V                             ; 4.54e-10 s                 ; 4.11e-10 s                 ; No                        ; No                        ;
; SDRAM_A[5]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; SDRAM_A[6]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; SDRAM_A[7]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; SDRAM_A[8]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; SDRAM_A[9]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; SDRAM_A[10]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; SDRAM_A[11]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; SDRAM_A[12]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.6 V               ; -0.129 V            ; 0.303 V                              ; 0.209 V                              ; 4.54e-10 s                  ; 4.11e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.6 V              ; -0.129 V           ; 0.303 V                             ; 0.209 V                             ; 4.54e-10 s                 ; 4.11e-10 s                 ; No                        ; No                        ;
; LED          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.48 V              ; -0.0164 V           ; 0.353 V                              ; 0.315 V                              ; 3.88e-09 s                  ; 3.06e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.48 V             ; -0.0164 V          ; 0.353 V                             ; 0.315 V                             ; 3.88e-09 s                 ; 3.06e-09 s                 ; No                        ; No                        ;
; UART_TX      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.48 V              ; -0.0176 V           ; 0.357 V                              ; 0.323 V                              ; 3.9e-09 s                   ; 3.06e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.48 V             ; -0.0176 V          ; 0.357 V                             ; 0.323 V                             ; 3.9e-09 s                  ; 3.06e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[0]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[1]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[2]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.6 V               ; -0.129 V            ; 0.303 V                              ; 0.209 V                              ; 4.54e-10 s                  ; 4.11e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.6 V              ; -0.129 V           ; 0.303 V                             ; 0.209 V                             ; 4.54e-10 s                 ; 4.11e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[3]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.6 V               ; -0.129 V            ; 0.303 V                              ; 0.209 V                              ; 4.54e-10 s                  ; 4.11e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.6 V              ; -0.129 V           ; 0.303 V                             ; 0.209 V                             ; 4.54e-10 s                 ; 4.11e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[4]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; SDRAM_DQ[5]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; SDRAM_DQ[6]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; SDRAM_DQ[7]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; SDRAM_DQ[8]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[9]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[10] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[11] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[12] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.6 V               ; -0.129 V            ; 0.303 V                              ; 0.209 V                              ; 4.54e-10 s                  ; 4.11e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.6 V              ; -0.129 V           ; 0.303 V                             ; 0.209 V                             ; 4.54e-10 s                 ; 4.11e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[13] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[14] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[15] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.6 V               ; -0.129 V            ; 0.303 V                              ; 0.209 V                              ; 4.54e-10 s                  ; 4.11e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.6 V              ; -0.129 V           ; 0.303 V                             ; 0.209 V                             ; 4.54e-10 s                 ; 4.11e-10 s                 ; No                        ; No                        ;
; SPI_DO       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.48 V              ; -0.0164 V           ; 0.353 V                              ; 0.315 V                              ; 3.88e-09 s                  ; 3.06e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.48 V             ; -0.0164 V          ; 0.353 V                             ; 0.315 V                             ; 3.88e-09 s                 ; 3.06e-09 s                 ; No                        ; No                        ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Transfers                                                                                                                                                                             ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+------------+----------+----------+----------+
; From Clock                                                            ; To Clock                                                              ; RR Paths   ; FR Paths ; RF Paths ; FF Paths ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+------------+----------+----------+----------+
; clk_27                                                                ; clk_27                                                                ; 85         ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 2566       ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 120        ; 0        ; 1        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 16         ; 0        ; 0        ; 0        ;
; clk_27                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; false path ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 39         ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 238636234  ; 20       ; 1        ; 817      ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; false path ; 0        ; 0        ; 0        ;
; SPI_SCK                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; false path ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 52         ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 0          ; 0        ; 1        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; false path ; 0        ; 0        ; 0        ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 1489       ; 4        ; 20       ; 1        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; SPI_SCK                                                               ; false path ; 0        ; 0        ; 0        ;
; SPI_SCK                                                               ; SPI_SCK                                                               ; 7754       ; 6        ; 147      ; 57       ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+------------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Transfers                                                                                                                                                                              ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+------------+----------+----------+----------+
; From Clock                                                            ; To Clock                                                              ; RR Paths   ; FR Paths ; RF Paths ; FF Paths ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+------------+----------+----------+----------+
; clk_27                                                                ; clk_27                                                                ; 85         ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 2566       ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 120        ; 0        ; 1        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 16         ; 0        ; 0        ; 0        ;
; clk_27                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; false path ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 39         ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 238636234  ; 20       ; 1        ; 817      ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; false path ; 0        ; 0        ; 0        ;
; SPI_SCK                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; false path ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 52         ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 0          ; 0        ; 1        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; false path ; 0        ; 0        ; 0        ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 1489       ; 4        ; 20       ; 1        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; SPI_SCK                                                               ; false path ; 0        ; 0        ; 0        ;
; SPI_SCK                                                               ; SPI_SCK                                                               ; 7754       ; 6        ; 147      ; 57       ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+------------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Recovery Transfers                                                                                                                                                                            ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+------------+----------+------------+----------+
; From Clock                                                            ; To Clock                                                              ; RR Paths   ; FR Paths ; RF Paths   ; FF Paths ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+------------+----------+------------+----------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; clk_27                                                                ; false path ; 0        ; 0          ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 141        ; 0        ; 0          ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 14463      ; 0        ; 0          ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; SPI_SCK                                                               ; 0          ; 0        ; false path ; 0        ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+------------+----------+------------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Removal Transfers                                                                                                                                                                             ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+------------+----------+------------+----------+
; From Clock                                                            ; To Clock                                                              ; RR Paths   ; FR Paths ; RF Paths   ; FF Paths ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+------------+----------+------------+----------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; clk_27                                                                ; false path ; 0        ; 0          ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 141        ; 0        ; 0          ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 14463      ; 0        ; 0          ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; SPI_SCK                                                               ; 0          ; 0        ; false path ; 0        ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+------------+----------+------------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design


---------------
; Report RSKM ;
---------------
No dedicated SERDES Receiver circuitry present in device or used in design


+------------------------------------------------+
; Unconstrained Paths                            ;
+---------------------------------+-------+------+
; Property                        ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks                  ; 0     ; 0    ;
; Unconstrained Clocks            ; 0     ; 0    ;
; Unconstrained Input Ports       ; 4     ; 4    ;
; Unconstrained Input Port Paths  ; 186   ; 186  ;
; Unconstrained Output Ports      ; 2     ; 2    ;
; Unconstrained Output Port Paths ; 5     ; 5    ;
+---------------------------------+-------+------+


+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II 32-bit TimeQuest Timing Analyzer
    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
    Info: Processing started: Sun Mar 24 14:03:46 2024
Info: Command: quartus_sta atari800core -c atari800core
Info: qsta_default_script.tcl version: #1
Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (332104): Reading SDC File: 'atari800core.sdc'
Info (332110): Deriving PLL clocks
    Info (332110): create_generated_clock -source {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 27 -multiply_by 100 -duty_cycle 50.00 -name {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]} {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]}
    Info (332110): create_generated_clock -source {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 27 -multiply_by 50 -duty_cycle 50.00 -name {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]} {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]}
    Info (332110): create_generated_clock -source {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 27 -multiply_by 100 -phase -100.00 -duty_cycle 50.00 -name {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]} {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]}
    Info (332110): create_generated_clock -source {pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 200 -multiply_by 227 -duty_cycle 50.00 -name {pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]} {pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]}
    Info (332110): create_generated_clock -source {reconfig_pll|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 9 -multiply_by 4 -duty_cycle 50.00 -name {reconfig_pll|altpll_component|auto_generated|pll1|clk[0]} {reconfig_pll|altpll_component|auto_generated|pll1|clk[0]}
Info (332151): Clock uncertainty is not calculated until you update the timing netlist.
Warning (332125): Found combinational loop of 4 nodes
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqb_next[0]~7|combout"
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqb_next[0]~6|datac"
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqb_next[0]~6|combout"
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqb_next[0]~7|dataa"
Warning (332125): Found combinational loop of 4 nodes
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqa_next[0]~7|combout"
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqa_next[0]~6|datac"
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqa_next[0]~6|combout"
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqa_next[0]~7|dataa"
Warning (332125): Found combinational loop of 4 nodes
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqa_next[1]~10|combout"
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqa_next[1]~8|datab"
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqa_next[1]~8|combout"
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqa_next[1]~10|datab"
Warning (332125): Found combinational loop of 4 nodes
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqb_next[1]~9|combout"
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqb_next[1]~8|datac"
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqb_next[1]~8|combout"
    Warning (332126): Node "atarixl_simple_sdram1|atari800xl|pia1|irqb_next[1]~9|datab"
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Analyzing Slow 1200mV 85C Model
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -1.593
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -1.593        -1.593 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     0.593         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.945         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    14.954         0.000 SPI_SCK 
    Info (332119):    34.116         0.000 clk_27 
    Info (332119):    36.854         0.000 reconfig_pll|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case hold slack is 0.406
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.406         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.419         0.000 SPI_SCK 
    Info (332119):     0.453         0.000 reconfig_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.455         0.000 clk_27 
    Info (332119):     0.455         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     2.208         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
Info (332146): Worst-case recovery slack is 2.684
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     2.684         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     9.374         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
Info (332146): Worst-case removal slack is 1.592
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     1.592         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     4.459         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case minimum pulse width slack is 4.093
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     4.093         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     4.194         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     8.379         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    16.275         0.000 pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    18.275         0.000 clk_27 
    Info (332119):    20.416         0.000 SPI_SCK 
    Info (332119):    40.596         0.000 reconfig_pll|altpll_component|auto_generated|pll1|clk[0] 
Info: Analyzing Slow 1200mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -1.296
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -1.296        -1.296 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     0.981         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     1.488         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    15.363         0.000 SPI_SCK 
    Info (332119):    34.380         0.000 clk_27 
    Info (332119):    37.081         0.000 reconfig_pll|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case hold slack is 0.383
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.383         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.397         0.000 SPI_SCK 
    Info (332119):     0.402         0.000 reconfig_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.403         0.000 clk_27 
    Info (332119):     0.403         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     2.111         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
Info (332146): Worst-case recovery slack is 3.126
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     3.126         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    10.072         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
Info (332146): Worst-case removal slack is 1.443
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     1.443         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     4.025         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case minimum pulse width slack is 4.097
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     4.097         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     4.167         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     8.400         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    16.280         0.000 pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    18.270         0.000 clk_27 
    Info (332119):    20.401         0.000 SPI_SCK 
    Info (332119):    40.596         0.000 reconfig_pll|altpll_component|auto_generated|pll1|clk[0] 
Info: Analyzing Fast 1200mV 0C Model
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info (332146): Worst-case setup slack is 0.323
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.323         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     2.394         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     6.301         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    18.720         0.000 SPI_SCK 
    Info (332119):    35.771         0.000 clk_27 
    Info (332119):    39.833         0.000 reconfig_pll|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case hold slack is 0.139
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.139         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.140         0.000 SPI_SCK 
    Info (332119):     0.186         0.000 reconfig_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.187         0.000 clk_27 
    Info (332119):     0.187         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     1.850         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
Info (332146): Worst-case recovery slack is 5.945
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     5.945         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    13.807         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
Info (332146): Worst-case removal slack is 0.681
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.681         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     2.029         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case minimum pulse width slack is 4.186
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     4.186         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     4.331         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     8.557         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    16.300         0.000 pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    17.784         0.000 clk_27 
    Info (332119):    20.000         0.000 SPI_SCK 
    Info (332119):    40.631         0.000 reconfig_pll|altpll_component|auto_generated|pll1|clk[0] 
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 22 warnings
    Info: Peak virtual memory: 564 megabytes
    Info: Processing ended: Sun Mar 24 14:03:53 2024
    Info: Elapsed time: 00:00:07
    Info: Total CPU time (on all processors): 00:00:09


