Analysis & Synthesis report for sidmax Sun Jun 7 10:18:22 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. Analysis & Synthesis Summary 3. Analysis & Synthesis Settings 4. Analysis & Synthesis Default Parameter Settings 5. Parallel Compilation 6. Analysis & Synthesis Source Files Read 7. Analysis & Synthesis Resource Usage Summary 8. Analysis & Synthesis Resource Utilization by Entity 9. Analysis & Synthesis RAM Summary 10. Analysis & Synthesis DSP Block Usage Summary 11. Analysis & Synthesis IP Cores Summary 12. State Machine - |sidmax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|avmm_read_valid_state 13. State Machine - |sidmax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|read_state 14. State Machine - |sidmax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|erase_state 15. State Machine - |sidmax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|write_state 16. Registers Protected by Synthesis 17. Registers Removed During Synthesis 18. Removed Registers Triggering Further Register Optimizations 19. General Register Statistics 20. Inverted Register Statistics 21. Registers Packed Into Inferred Megafunctions 22. Multiplexer Restructuring Statistics (Restructuring Performed) 23. Source assignments for flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_std_synchronizer:stdsync_busy 24. Source assignments for flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_std_synchronizer:stdsync_busy_clear 25. Source assignments for generic_ram_infer:\sample_on:normal_ram:sample_ram_inst|altsyncram:ram_block_rtl_0|altsyncram_6t31:auto_generated 26. Parameter Settings for User Entity Instance: Top-level Entity: |sidmax 27. Parameter Settings for User Entity Instance: int_osc:oscillator|altera_int_osc:int_osc_0 28. Parameter Settings for User Entity Instance: flash_controller:\flash_on:flash_controller_inst 29. Parameter Settings for User Entity Instance: flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0 30. Parameter Settings for User Entity Instance: flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller 31. Parameter Settings for User Entity Instance: flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller 32. Parameter Settings for User Entity Instance: flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_std_synchronizer:stdsync_busy 33. Parameter Settings for User Entity Instance: flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_std_synchronizer:stdsync_busy_clear 34. Parameter Settings for User Entity Instance: flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|lpm_shiftreg:ufm_data_shiftreg 35. Parameter Settings for User Entity Instance: flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_onchip_flash_address_range_check:address_range_checker 36. Parameter Settings for User Entity Instance: flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_onchip_flash_convert_address:address_convertor 37. Parameter Settings for User Entity Instance: flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_onchip_flash_a_address_write_protection_check:access_address_write_protection_checker 38. Parameter Settings for User Entity Instance: flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_onchip_flash_convert_sector:sector_convertor 39. Parameter Settings for User Entity Instance: pll:pll_inst|altpll:altpll_component 40. Parameter Settings for User Entity Instance: slave_timing_6502:bus_adapt 41. Parameter Settings for User Entity Instance: pokey:\POKEY_ON:0:pokeyx 42. Parameter Settings for User Entity Instance: pokey:\POKEY_ON:0:pokeyx|complete_address_decoder:decode_addr1 43. Parameter Settings for User Entity Instance: pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf0_delay 44. Parameter Settings for User Entity Instance: pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf1_delay 45. Parameter Settings for User Entity Instance: pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf2_delay 46. Parameter Settings for User Entity Instance: pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf3_delay 47. Parameter Settings for User Entity Instance: pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audctl_delay 48. Parameter Settings for User Entity Instance: pokey:\POKEY_ON:0:pokeyx|pokey_countdown_timer:timer0 49. Parameter Settings for User Entity Instance: pokey:\POKEY_ON:0:pokeyx|pokey_countdown_timer:timer0|delay_line:underflow0_delay 50. Parameter Settings for User Entity Instance: pokey:\POKEY_ON:0:pokeyx|pokey_countdown_timer:timer1 51. Parameter Settings for User Entity Instance: pokey:\POKEY_ON:0:pokeyx|pokey_countdown_timer:timer1|delay_line:underflow0_delay 52. Parameter Settings for User Entity Instance: pokey:\POKEY_ON:0:pokeyx|pokey_countdown_timer:timer2 53. Parameter Settings for User Entity Instance: pokey:\POKEY_ON:0:pokeyx|pokey_countdown_timer:timer2|delay_line:underflow0_delay 54. Parameter Settings for User Entity Instance: pokey:\POKEY_ON:0:pokeyx|pokey_countdown_timer:timer3 55. Parameter Settings for User Entity Instance: pokey:\POKEY_ON:0:pokeyx|pokey_countdown_timer:timer3|delay_line:underflow0_delay 56. Parameter Settings for User Entity Instance: pokey:\POKEY_ON:0:pokeyx|latch_delay_line:twotone_del 57. Parameter Settings for User Entity Instance: pokey:\POKEY_ON:0:pokeyx|latch_delay_line:stimer_delay 58. Parameter Settings for User Entity Instance: pokey:\POKEY_ON:0:pokeyx|syncreset_enable_divider:enable_64_div 59. Parameter Settings for User Entity Instance: pokey:\POKEY_ON:0:pokeyx|syncreset_enable_divider:enable_15_div 60. Parameter Settings for User Entity Instance: pokey:\POKEY_ON:0:pokeyx|delay_line:serout_clock_delay 61. Parameter Settings for User Entity Instance: pokey:\POKEY_ON:0:pokeyx|delay_line:serin_clock_delay 62. Parameter Settings for User Entity Instance: pokey:\POKEY_ON:1:pokeyx 63. Parameter Settings for User Entity Instance: pokey:\POKEY_ON:1:pokeyx|complete_address_decoder:decode_addr1 64. Parameter Settings for User Entity Instance: pokey:\POKEY_ON:1:pokeyx|wide_delay_line:audf0_delay 65. Parameter Settings for User Entity Instance: pokey:\POKEY_ON:1:pokeyx|wide_delay_line:audf1_delay 66. Parameter Settings for User Entity Instance: pokey:\POKEY_ON:1:pokeyx|wide_delay_line:audf2_delay 67. Parameter Settings for User Entity Instance: pokey:\POKEY_ON:1:pokeyx|wide_delay_line:audf3_delay 68. Parameter Settings for User Entity Instance: pokey:\POKEY_ON:1:pokeyx|wide_delay_line:audctl_delay 69. Parameter Settings for User Entity Instance: pokey:\POKEY_ON:1:pokeyx|pokey_countdown_timer:timer0 70. Parameter Settings for User Entity Instance: pokey:\POKEY_ON:1:pokeyx|pokey_countdown_timer:timer0|delay_line:underflow0_delay 71. Parameter Settings for User Entity Instance: pokey:\POKEY_ON:1:pokeyx|pokey_countdown_timer:timer1 72. Parameter Settings for User Entity Instance: pokey:\POKEY_ON:1:pokeyx|pokey_countdown_timer:timer1|delay_line:underflow0_delay 73. Parameter Settings for User Entity Instance: pokey:\POKEY_ON:1:pokeyx|pokey_countdown_timer:timer2 74. Parameter Settings for User Entity Instance: pokey:\POKEY_ON:1:pokeyx|pokey_countdown_timer:timer2|delay_line:underflow0_delay 75. Parameter Settings for User Entity Instance: pokey:\POKEY_ON:1:pokeyx|pokey_countdown_timer:timer3 76. Parameter Settings for User Entity Instance: pokey:\POKEY_ON:1:pokeyx|pokey_countdown_timer:timer3|delay_line:underflow0_delay 77. Parameter Settings for User Entity Instance: pokey:\POKEY_ON:1:pokeyx|latch_delay_line:twotone_del 78. Parameter Settings for User Entity Instance: pokey:\POKEY_ON:1:pokeyx|latch_delay_line:stimer_delay 79. Parameter Settings for User Entity Instance: pokey:\POKEY_ON:1:pokeyx|syncreset_enable_divider:enable_64_div 80. Parameter Settings for User Entity Instance: pokey:\POKEY_ON:1:pokeyx|syncreset_enable_divider:enable_15_div 81. Parameter Settings for User Entity Instance: pokey:\POKEY_ON:1:pokeyx|delay_line:serout_clock_delay 82. Parameter Settings for User Entity Instance: pokey:\POKEY_ON:1:pokeyx|delay_line:serin_clock_delay 83. Parameter Settings for User Entity Instance: SID_top:sid1 84. Parameter Settings for User Entity Instance: SID_top:sid1|complete_address_decoder:decode_addr1 85. Parameter Settings for User Entity Instance: SID_top:sid2 86. Parameter Settings for User Entity Instance: SID_top:sid2|complete_address_decoder:decode_addr1 87. Parameter Settings for User Entity Instance: PSG_top:\psg_on:PSG_1|complete_address_decoder:decode_addr1 88. Parameter Settings for User Entity Instance: PSG_top:\psg_on:PSG_1|PSG_freqdiv:core_ticker 89. Parameter Settings for User Entity Instance: PSG_top:\psg_on:PSG_1|PSG_freqdiv:channel_a_ticker 90. Parameter Settings for User Entity Instance: PSG_top:\psg_on:PSG_1|PSG_freqdiv:channel_b_ticker 91. Parameter Settings for User Entity Instance: PSG_top:\psg_on:PSG_1|PSG_freqdiv:channel_c_ticker 92. Parameter Settings for User Entity Instance: PSG_top:\psg_on:PSG_1|PSG_freqdiv:noise_preticker 93. Parameter Settings for User Entity Instance: PSG_top:\psg_on:PSG_1|PSG_freqdiv:noise_ticker 94. Parameter Settings for User Entity Instance: PSG_top:\psg_on:PSG_1|PSG_envelope:envelope|PSG_freqdiv:envelope_ticker 95. Parameter Settings for User Entity Instance: PSG_top:\psg_on:PSG_2|complete_address_decoder:decode_addr1 96. Parameter Settings for User Entity Instance: PSG_top:\psg_on:PSG_2|PSG_freqdiv:core_ticker 97. Parameter Settings for User Entity Instance: PSG_top:\psg_on:PSG_2|PSG_freqdiv:channel_a_ticker 98. Parameter Settings for User Entity Instance: PSG_top:\psg_on:PSG_2|PSG_freqdiv:channel_b_ticker 99. Parameter Settings for User Entity Instance: PSG_top:\psg_on:PSG_2|PSG_freqdiv:channel_c_ticker 100. Parameter Settings for User Entity Instance: PSG_top:\psg_on:PSG_2|PSG_freqdiv:noise_preticker 101. Parameter Settings for User Entity Instance: PSG_top:\psg_on:PSG_2|PSG_freqdiv:noise_ticker 102. Parameter Settings for User Entity Instance: PSG_top:\psg_on:PSG_2|PSG_envelope:envelope|PSG_freqdiv:envelope_ticker 103. Parameter Settings for User Entity Instance: sample_top:\sample_on:sample1|complete_address_decoder:decode_addr2 104. Parameter Settings for User Entity Instance: generic_ram_infer:\sample_on:normal_ram:sample_ram_inst 105. Parameter Settings for User Entity Instance: complete_address_decoder:\gen_config:decode_addr1 106. Parameter Settings for User Entity Instance: sigmadelta_dither:dac_dithergen 107. Parameter Settings for User Entity Instance: filtered_sigmadelta:dac_0 108. Parameter Settings for User Entity Instance: filtered_sigmadelta:dac_0|sigmadelta_2ndorder_dither:\gen_2ndorder_dither_on:dac_2nd_dither 109. Parameter Settings for User Entity Instance: filtered_sigmadelta:dac_2 110. Parameter Settings for User Entity Instance: filtered_sigmadelta:dac_2|sigmadelta_2ndorder_dither:\gen_2ndorder_dither_on:dac_2nd_dither 111. Parameter Settings for User Entity Instance: filtered_sigmadelta:dac_3 112. Parameter Settings for User Entity Instance: filtered_sigmadelta:dac_3|sigmadelta_2ndorder_dither:\gen_2ndorder_dither_on:dac_2nd_dither 113. Parameter Settings for User Entity Instance: sigma_delta_adc:sdelta 114. Parameter Settings for User Entity Instance: sigma_delta_adc:sdelta|cic_integrator:gen_cic[0].cic_inst_u0 115. Parameter Settings for User Entity Instance: sigma_delta_adc:sdelta|cic_comb:gen_cic[0].cic_inst_u1 116. Parameter Settings for User Entity Instance: sigma_delta_adc:sdelta|cic_integrator:gen_cic[1].cic_inst_u0 117. Parameter Settings for User Entity Instance: sigma_delta_adc:sdelta|cic_comb:gen_cic[1].cic_inst_u1 118. Parameter Settings for User Entity Instance: sigma_delta_adc:sdelta|fir_compensator:gen_fir.fir_comp_u0 119. Parameter Settings for Inferred Entity Instance: generic_ram_infer:\sample_on:normal_ram:sample_ram_inst|altsyncram:ram_block_rtl_0 120. Parameter Settings for Inferred Entity Instance: clockgensid:clockgen1|lpm_mult:Mult0 121. Parameter Settings for Inferred Entity Instance: sample_top:\sample_on:sample1|sample_adpcm:adpcm_decoder|lpm_mult:Mult0 122. Parameter Settings for Inferred Entity Instance: sample_top:\sample_on:sample1|lpm_mult:Mult3 123. Parameter Settings for Inferred Entity Instance: sample_top:\sample_on:sample1|lpm_mult:Mult2 124. Parameter Settings for Inferred Entity Instance: SID_top:sid2|SID_postFilterSum:postfilter|lpm_mult:Mult0 125. Parameter Settings for Inferred Entity Instance: sample_top:\sample_on:sample1|lpm_mult:Mult1 126. Parameter Settings for Inferred Entity Instance: sample_top:\sample_on:sample1|lpm_mult:Mult0 127. Parameter Settings for Inferred Entity Instance: SID_top:sid1|SID_postFilterSum:postfilter|lpm_mult:Mult0 128. Parameter Settings for Inferred Entity Instance: SID_top:sid2|SID_amplitudeModulator:vol_abc|lpm_mult:Mult0 129. Parameter Settings for Inferred Entity Instance: SID_top:sid2|SID_filter:variable_state_filter|lpm_mult:Mult4 130. Parameter Settings for Inferred Entity Instance: SID_top:sid1|SID_amplitudeModulator:vol_abc|lpm_mult:Mult0 131. Parameter Settings for Inferred Entity Instance: SID_top:sid1|SID_filter:variable_state_filter|lpm_mult:Mult4 132. Parameter Settings for Inferred Entity Instance: SID_top:sid2|SID_filter:variable_state_filter|lpm_mult:Mult3 133. Parameter Settings for Inferred Entity Instance: SID_top:sid1|SID_filter:variable_state_filter|lpm_mult:Mult3 134. Parameter Settings for Inferred Entity Instance: SID_top:sid2|SID_filter:variable_state_filter|lpm_mult:Mult0 135. Parameter Settings for Inferred Entity Instance: SID_top:sid1|SID_filter:variable_state_filter|lpm_mult:Mult0 136. Parameter Settings for Inferred Entity Instance: SID_f_distortion_mux:f_distortion_mux|SID_f_distortion:f_distortion|lpm_mult:Mult0 137. lpm_shiftreg Parameter Settings by Entity Instance 138. altpll Parameter Settings by Entity Instance 139. altsyncram Parameter Settings by Entity Instance 140. lpm_mult Parameter Settings by Entity Instance 141. Port Connectivity Checks: "sigma_delta_adc:sdelta|cic_integrator:gen_cic[1].cic_inst_u0" 142. Port Connectivity Checks: "sigma_delta_adc:sdelta|cic_integrator:gen_cic[0].cic_inst_u0" 143. Port Connectivity Checks: "sigma_delta_adc:sdelta" 144. Port Connectivity Checks: "filtered_sigmadelta:dac_0|sigmadelta_2ndorder_dither:\gen_2ndorder_dither_on:dac_2nd_dither" 145. Port Connectivity Checks: "sigmadelta_dither:dac_dithergen" 146. Port Connectivity Checks: "mixer:mixer1" 147. Port Connectivity Checks: "complete_address_decoder:\gen_config:decode_addr1" 148. Port Connectivity Checks: "sample_top:\sample_on:sample1|sample_adpcm:adpcm_decoder" 149. Port Connectivity Checks: "sample_top:\sample_on:sample1|complete_address_decoder:decode_addr2" 150. Port Connectivity Checks: "PSG_volume_profile:\psg_on:vol_profile1" 151. Port Connectivity Checks: "PSG_top:\psg_on:PSG_2" 152. Port Connectivity Checks: "PSG_top:\psg_on:PSG_1|PSG_freqdiv:noise_ticker" 153. Port Connectivity Checks: "PSG_top:\psg_on:PSG_1|PSG_freqdiv:noise_preticker" 154. Port Connectivity Checks: "PSG_top:\psg_on:PSG_1|PSG_freqdiv:channel_c_ticker" 155. Port Connectivity Checks: "PSG_top:\psg_on:PSG_1|PSG_freqdiv:channel_b_ticker" 156. Port Connectivity Checks: "PSG_top:\psg_on:PSG_1|PSG_freqdiv:channel_a_ticker" 157. Port Connectivity Checks: "PSG_top:\psg_on:PSG_1|PSG_freqdiv:core_ticker" 158. Port Connectivity Checks: "PSG_top:\psg_on:PSG_1" 159. Port Connectivity Checks: "SID_top:sid2" 160. Port Connectivity Checks: "SID_top:sid1|complete_address_decoder:decode_addr1" 161. Port Connectivity Checks: "SID_top:sid1" 162. Port Connectivity Checks: "pokey:\POKEY_ON:1:pokeyx" 163. Port Connectivity Checks: "pokey:\POKEY_ON:0:pokeyx|latch_delay_line:stimer_delay" 164. Port Connectivity Checks: "pokey:\POKEY_ON:0:pokeyx|latch_delay_line:twotone_del" 165. Port Connectivity Checks: "pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audctl_delay" 166. Port Connectivity Checks: "pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf3_delay" 167. Port Connectivity Checks: "pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf2_delay" 168. Port Connectivity Checks: "pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf1_delay" 169. Port Connectivity Checks: "pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf0_delay" 170. Port Connectivity Checks: "pokey:\POKEY_ON:0:pokeyx|complete_address_decoder:decode_addr1" 171. Port Connectivity Checks: "pokey:\POKEY_ON:0:pokeyx" 172. Port Connectivity Checks: "slave_timing_6502:bus_adapt" 173. Port Connectivity Checks: "synchronizer:synchronizer_fancy_enable" 174. Port Connectivity Checks: "flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_block:altera_onchip_flash_block" 175. Port Connectivity Checks: "flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_onchip_flash_address_range_check:address_range_checker" 176. Port Connectivity Checks: "flash_controller:\flash_on:flash_controller_inst|flash:flash1" 177. Port Connectivity Checks: "flash_controller:\flash_on:flash_controller_inst" 178. Port Connectivity Checks: "int_osc:oscillator" 179. Post-Synthesis Netlist Statistics for Top Partition 180. Elapsed Time Per Partition 181. Analysis & Synthesis Messages ---------------- ; Legal Notice ; ---------------- Copyright (C) 2025 Altera Corporation. All rights reserved. Your use of Altera Corporation's design tools, logic functions and other software and tools, and any partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, the Altera Quartus Prime License Agreement, the Altera IP License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the Altera Software License Subscription Agreements on the Quartus Prime software download page. +--------------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +------------------------------------+-------------------------------------------------+ ; Analysis & Synthesis Status ; Successful - Sun Jun 7 10:18:22 2026 ; ; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; ; Revision Name ; sidmax ; ; Top-level Entity Name ; sidmax ; ; Family ; MAX 10 ; ; Total logic elements ; 9,772 ; ; Total combinational functions ; 7,724 ; ; Dedicated logic registers ; 4,787 ; ; Total registers ; 4787 ; ; Total pins ; 33 ; ; Total virtual pins ; 0 ; ; Total memory bits ; 344,064 ; ; Embedded Multiplier 9-bit elements ; 45 ; ; Total PLLs ; 1 ; ; UFM blocks ; 1 ; ; ADC blocks ; 0 ; +------------------------------------+-------------------------------------------------+ +------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Settings ; +------------------------------------------------------------------+--------------------+--------------------+ ; Option ; Setting ; Default Value ; +------------------------------------------------------------------+--------------------+--------------------+ ; Device ; 10M08SCU169C8G ; ; ; Top-level entity name ; sidmax ; sidmax ; ; Family name ; MAX 10 ; Cyclone V ; ; Use smart compilation ; Off ; Off ; ; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; ; Enable compact report table ; Off ; Off ; ; Restructure Multiplexers ; Auto ; Auto ; ; Create Debugging Nodes for IP Cores ; Off ; Off ; ; Preserve fewer node names ; On ; On ; ; Intel FPGA IP Evaluation Mode ; Enable ; Enable ; ; Verilog Version ; Verilog_2001 ; Verilog_2001 ; ; VHDL Version ; VHDL_1993 ; VHDL_1993 ; ; State Machine Processing ; Auto ; Auto ; ; Safe State Machine ; Off ; Off ; ; Extract Verilog State Machines ; On ; On ; ; Extract VHDL State Machines ; On ; On ; ; Ignore Verilog initial constructs ; Off ; Off ; ; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; ; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; ; Add Pass-Through Logic to Inferred RAMs ; On ; On ; ; Infer RAMs from Raw Logic ; On ; On ; ; Parallel Synthesis ; On ; On ; ; DSP Block Balancing ; Auto ; Auto ; ; NOT Gate Push-Back ; On ; On ; ; Power-Up Don't Care ; On ; On ; ; Remove Redundant Logic Cells ; Off ; Off ; ; Remove Duplicate Registers ; On ; On ; ; Ignore CARRY Buffers ; Off ; Off ; ; Ignore CASCADE Buffers ; Off ; Off ; ; Ignore GLOBAL Buffers ; Off ; Off ; ; Ignore ROW GLOBAL Buffers ; Off ; Off ; ; Ignore LCELL Buffers ; Off ; Off ; ; Ignore SOFT Buffers ; On ; On ; ; Limit AHDL Integers to 32 Bits ; Off ; Off ; ; Optimization Technique ; Balanced ; Balanced ; ; Carry Chain Length ; 70 ; 70 ; ; Auto Carry Chains ; On ; On ; ; Auto Open-Drain Pins ; On ; On ; ; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; ; Auto ROM Replacement ; On ; On ; ; Auto RAM Replacement ; On ; On ; ; Auto DSP Block Replacement ; On ; On ; ; Auto Shift Register Replacement ; Auto ; Auto ; ; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; ; Auto Clock Enable Replacement ; On ; On ; ; Strict RAM Replacement ; Off ; Off ; ; Allow Synchronous Control Signals ; On ; On ; ; Force Use of Synchronous Clear Signals ; Off ; Off ; ; Auto RAM Block Balancing ; On ; On ; ; Auto RAM to Logic Cell Conversion ; Off ; Off ; ; Auto Resource Sharing ; Off ; Off ; ; Allow Any RAM Size For Recognition ; Off ; Off ; ; Allow Any ROM Size For Recognition ; Off ; Off ; ; Allow Any Shift Register Size For Recognition ; Off ; Off ; ; Use LogicLock Constraints during Resource Balancing ; On ; On ; ; Ignore translate_off and synthesis_off directives ; Off ; Off ; ; Timing-Driven Synthesis ; On ; On ; ; Report Parameter Settings ; On ; On ; ; Report Source Assignments ; On ; On ; ; Report Connectivity Checks ; On ; On ; ; Ignore Maximum Fan-Out Assignments ; Off ; Off ; ; Synchronization Register Chain Length ; 2 ; 2 ; ; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ; ; HDL message level ; Level2 ; Level2 ; ; Suppress Register Optimization Related Messages ; Off ; Off ; ; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; ; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; ; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; ; Clock MUX Protection ; On ; On ; ; Auto Gated Clock Conversion ; Off ; Off ; ; Block Design Naming ; Auto ; Auto ; ; SDC constraint protection ; Off ; Off ; ; Synthesis Effort ; Auto ; Auto ; ; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; ; Pre-Mapping Resynthesis Optimization ; Off ; Off ; ; Analysis & Synthesis Message Level ; Medium ; Medium ; ; Disable Register Merging Across Hierarchies ; Auto ; Auto ; ; Resource Aware Inference For Block RAM ; On ; On ; +------------------------------------------------------------------+--------------------+--------------------+ +-------------------------------------------------+ ; Analysis & Synthesis Default Parameter Settings ; +--------------------+----------------------------+ ; Name ; Setting ; +--------------------+----------------------------+ ; a5_bit ; 1 ; ; a6_bit ; 2 ; ; a7_bit ; 3 ; ; board ; 10 ; ; bus ; c64 ; ; enable_auto_stereo ; 1 ; ; enable_covox ; 1 ; ; enable_flash ; 1 ; ; enable_psg ; 1 ; ; enable_sample ; 1 ; ; ext_bits ; 4 ; ; fpga ; 10M08SCU169C8G ; ; irq_bit ; 4 ; ; pokeys ; 2 ; ; sids ; 2 ; ; version ; 131M08SF ; +--------------------+----------------------------+ +------------------------------------------+ ; Parallel Compilation ; +----------------------------+-------------+ ; Processors ; Number ; +----------------------------+-------------+ ; Number detected on machine ; 32 ; ; Maximum allowed ; 16 ; ; ; ; ; Average used ; 1.01 ; ; Maximum used ; 16 ; ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; ; Processor 2 ; 0.1% ; ; Processor 3 ; 0.1% ; ; Processor 4 ; 0.1% ; ; Processor 5 ; 0.1% ; ; Processor 6 ; 0.1% ; ; Processor 7 ; 0.1% ; ; Processor 8 ; 0.1% ; ; Processors 9-16 ; 0.1% ; +----------------------------+-------------+ +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Source Files Read ; +-----------------------------------------------------------------------+-----------------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ ; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; +-----------------------------------------------------------------------+-----------------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ ; audio_signal_detector.vhd ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/audio_signal_detector.vhd ; ; ; flash_controller.vhd ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/flash_controller.vhd ; ; ; stereo_detect.vhd ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/stereo_detect.vhd ; ; ; slave_timing_6502.vhd ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/slave_timing_6502.vhd ; ; ; complete_address_decoder.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/complete_address_decoder.vhdl ; ; ; syncreset_enable_divider.vhd ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/syncreset_enable_divider.vhd ; ; ; enable_divider.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/enable_divider.vhdl ; ; ; delay_line.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/delay_line.vhdl ; ; ; wide_delay_line.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/wide_delay_line.vhdl ; ; ; latch_delay_line.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/latch_delay_line.vhdl ; ; ; sigmadelta_1storder.vhd ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sigmadelta_1storder.vhd ; ; ; sigmadelta_2ndorder.vhd ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sigmadelta_2ndorder.vhd ; ; ; sigmadelta_2ndorder_dither.vhd ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sigmadelta_2ndorder_dither.vhd ; ; ; sigmadelta_dither.vhd ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sigmadelta_dither.vhd ; ; ; filtered_sigmadelta.vhd ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/filtered_sigmadelta.vhd ; ; ; generic_ram_infer.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/generic_ram_infer.vhdl ; ; ; m9k_grouped.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/m9k_grouped.vhdl ; ; ; simple_low_pass_filter.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/simple_low_pass_filter.vhdl ; ; ; pokey/pokey_poly_17_9.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/pokey/pokey_poly_17_9.vhdl ; ; ; pokey/pokey_poly_5.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/pokey/pokey_poly_5.vhdl ; ; ; pokey/pokey_poly_4.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/pokey/pokey_poly_4.vhdl ; ; ; pokey/pokey_noise_filter.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/pokey/pokey_noise_filter.vhdl ; ; ; pokey/pokey_mixer_mux.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/pokey/pokey_mixer_mux.vhdl ; ; ; pokey/pokey_mixer.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/pokey/pokey_mixer.vhdl ; ; ; pokey/pokey_countdown_timer.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/pokey/pokey_countdown_timer.vhdl ; ; ; pokey/pokey.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/pokey/pokey.vhdl ; ; ; synchronizer.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/synchronizer.vhdl ; ; ; audiotypes.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/audiotypes.vhdl ; ; ; mixer.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/mixer.vhdl ; ; ; clockgensid.vhd ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/clockgensid.vhd ; ; ; spdif_transmitter.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/spdif_transmitter.vhdl ; ; ; sidmax.vhd ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sidmax.vhd ; ; ; PSG/envelope.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/PSG/envelope.vhdl ; ; ; PSG/noise.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/PSG/noise.vhdl ; ; ; PSG/top.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/PSG/top.vhdl ; ; ; PSG/freqdiv.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/PSG/freqdiv.vhdl ; ; ; PSG/mixer.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/PSG/mixer.vhdl ; ; ; PSG/volume.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/PSG/volume.vhdl ; ; ; PSG/volume_profile.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/PSG/volume_profile.vhdl ; ; ; SID/top.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/top.vhdl ; ; ; SID/oscillator.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/oscillator.vhdl ; ; ; SID/wavegen.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/wavegen.vhdl ; ; ; SID/envelope.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/envelope.vhdl ; ; ; SID/envelope_tapmatch.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/envelope_tapmatch.vhdl ; ; ; SID/amplitudeModulator.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/amplitudeModulator.vhdl ; ; ; SID/preFilterSum.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/preFilterSum.vhdl ; ; ; SID/filter.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/filter.vhdl ; ; ; SID/f_distortion.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/f_distortion.vhdl ; ; ; SID/f_distortion_mux.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/f_distortion_mux.vhdl ; ; ; SID/postFilterSum.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/postFilterSum.vhdl ; ; ; sample/channel.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sample/channel.vhdl ; ; ; sample/adpcm.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sample/adpcm.vhdl ; ; ; sample/top.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sample/top.vhdl ; ; ; covox/top.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/covox/top.vhdl ; ; ; sigma_delta/sigma_delta_adc.sv ; yes ; User SystemVerilog HDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sigma_delta/sigma_delta_adc.sv ; ; ; sigma_delta/cic_comb.sv ; yes ; User SystemVerilog HDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sigma_delta/cic_comb.sv ; ; ; sigma_delta/cic_integrator.sv ; yes ; User SystemVerilog HDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sigma_delta/cic_integrator.sv ; ; ; sigma_delta/fir_compensator.sv ; yes ; User SystemVerilog HDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sigma_delta/fir_compensator.sv ; ; ; int_osc/synthesis/int_osc.vhd ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/int_osc/synthesis/int_osc.vhd ; int_osc ; ; int_osc/synthesis/submodules/altera_int_osc.v ; yes ; User Verilog HDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/int_osc/synthesis/submodules/altera_int_osc.v ; int_osc ; ; pll.vhd ; yes ; User Wizard-Generated File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/pll.vhd ; ; ; flash/synthesis/flash.vhd ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/flash/synthesis/flash.vhd ; flash ; ; flash/synthesis/submodules/altera_onchip_flash_util.v ; yes ; User Verilog HDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/flash/synthesis/submodules/altera_onchip_flash_util.v ; flash ; ; flash/synthesis/submodules/altera_onchip_flash.v ; yes ; User Verilog HDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/flash/synthesis/submodules/altera_onchip_flash.v ; flash ; ; flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v ; yes ; User Verilog HDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v ; flash ; ; flash/synthesis/submodules/altera_onchip_flash_avmm_csr_controller.v ; yes ; User Verilog HDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/flash/synthesis/submodules/altera_onchip_flash_avmm_csr_controller.v ; flash ; ; flash/synthesis/submodules/rtl/altera_onchip_flash_block.v ; yes ; Encrypted User Verilog HDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/flash/synthesis/submodules/rtl/altera_onchip_flash_block.v ; flash ; ; lvds_tx.vhd ; yes ; User Wizard-Generated File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/lvds_tx.vhd ; lvds_tx ; ; lvds_tx/altera_soft_lvds_tx_uCmMXfGB.v ; yes ; User Verilog HDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/lvds_tx/altera_soft_lvds_tx_uCmMXfGB.v ; lvds_tx ; ; lvds_rx.vhd ; yes ; User Wizard-Generated File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/lvds_rx.vhd ; lvds_rx ; ; lvds_rx/altera_soft_lvds_rx_uCmNW05P.v ; yes ; User Verilog HDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/lvds_rx/altera_soft_lvds_rx_uCmNW05P.v ; lvds_rx ; ; altera_std_synchronizer.v ; yes ; Megafunction ; /home/markw/intelFPGA_lite/25.1std/quartus/libraries/megafunctions/altera_std_synchronizer.v ; ; ; lpm_shiftreg.tdf ; yes ; Megafunction ; /home/markw/intelFPGA_lite/25.1std/quartus/libraries/megafunctions/lpm_shiftreg.tdf ; ; ; lpm_constant.inc ; yes ; Megafunction ; /home/markw/intelFPGA_lite/25.1std/quartus/libraries/megafunctions/lpm_constant.inc ; ; ; dffeea.inc ; yes ; Megafunction ; /home/markw/intelFPGA_lite/25.1std/quartus/libraries/megafunctions/dffeea.inc ; ; ; aglobal251.inc ; yes ; Megafunction ; /home/markw/intelFPGA_lite/25.1std/quartus/libraries/megafunctions/aglobal251.inc ; ; ; altpll.tdf ; yes ; Megafunction ; /home/markw/intelFPGA_lite/25.1std/quartus/libraries/megafunctions/altpll.tdf ; ; ; stratix_pll.inc ; yes ; Megafunction ; /home/markw/intelFPGA_lite/25.1std/quartus/libraries/megafunctions/stratix_pll.inc ; ; ; stratixii_pll.inc ; yes ; Megafunction ; /home/markw/intelFPGA_lite/25.1std/quartus/libraries/megafunctions/stratixii_pll.inc ; ; ; cycloneii_pll.inc ; yes ; Megafunction ; /home/markw/intelFPGA_lite/25.1std/quartus/libraries/megafunctions/cycloneii_pll.inc ; ; ; db/pll_altpll.v ; yes ; Auto-Generated Megafunction ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/db/pll_altpll.v ; ; ; altsyncram.tdf ; yes ; Megafunction ; /home/markw/intelFPGA_lite/25.1std/quartus/libraries/megafunctions/altsyncram.tdf ; ; ; stratix_ram_block.inc ; yes ; Megafunction ; /home/markw/intelFPGA_lite/25.1std/quartus/libraries/megafunctions/stratix_ram_block.inc ; ; ; lpm_mux.inc ; yes ; Megafunction ; /home/markw/intelFPGA_lite/25.1std/quartus/libraries/megafunctions/lpm_mux.inc ; ; ; lpm_decode.inc ; yes ; Megafunction ; /home/markw/intelFPGA_lite/25.1std/quartus/libraries/megafunctions/lpm_decode.inc ; ; ; a_rdenreg.inc ; yes ; Megafunction ; /home/markw/intelFPGA_lite/25.1std/quartus/libraries/megafunctions/a_rdenreg.inc ; ; ; altrom.inc ; yes ; Megafunction ; /home/markw/intelFPGA_lite/25.1std/quartus/libraries/megafunctions/altrom.inc ; ; ; altram.inc ; yes ; Megafunction ; /home/markw/intelFPGA_lite/25.1std/quartus/libraries/megafunctions/altram.inc ; ; ; altdpram.inc ; yes ; Megafunction ; /home/markw/intelFPGA_lite/25.1std/quartus/libraries/megafunctions/altdpram.inc ; ; ; db/altsyncram_6t31.tdf ; yes ; Auto-Generated Megafunction ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/db/altsyncram_6t31.tdf ; ; ; db/decode_f7a.tdf ; yes ; Auto-Generated Megafunction ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/db/decode_f7a.tdf ; ; ; db/decode_8j9.tdf ; yes ; Auto-Generated Megafunction ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/db/decode_8j9.tdf ; ; ; db/mux_v1b.tdf ; yes ; Auto-Generated Megafunction ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/db/mux_v1b.tdf ; ; ; lpm_mult.tdf ; yes ; Megafunction ; /home/markw/intelFPGA_lite/25.1std/quartus/libraries/megafunctions/lpm_mult.tdf ; ; ; lpm_add_sub.inc ; yes ; Megafunction ; /home/markw/intelFPGA_lite/25.1std/quartus/libraries/megafunctions/lpm_add_sub.inc ; ; ; multcore.inc ; yes ; Megafunction ; /home/markw/intelFPGA_lite/25.1std/quartus/libraries/megafunctions/multcore.inc ; ; ; bypassff.inc ; yes ; Megafunction ; /home/markw/intelFPGA_lite/25.1std/quartus/libraries/megafunctions/bypassff.inc ; ; ; altshift.inc ; yes ; Megafunction ; /home/markw/intelFPGA_lite/25.1std/quartus/libraries/megafunctions/altshift.inc ; ; ; db/mult_uks.tdf ; yes ; Auto-Generated Megafunction ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/db/mult_uks.tdf ; ; ; db/mult_5fs.tdf ; yes ; Auto-Generated Megafunction ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/db/mult_5fs.tdf ; ; ; db/mult_4fs.tdf ; yes ; Auto-Generated Megafunction ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/db/mult_4fs.tdf ; ; ; db/mult_gfs.tdf ; yes ; Auto-Generated Megafunction ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/db/mult_gfs.tdf ; ; ; db/mult_6fs.tdf ; yes ; Auto-Generated Megafunction ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/db/mult_6fs.tdf ; ; ; db/mult_pgs.tdf ; yes ; Auto-Generated Megafunction ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/db/mult_pgs.tdf ; ; ; db/mult_1hs.tdf ; yes ; Auto-Generated Megafunction ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/db/mult_1hs.tdf ; ; ; db/mult_ons.tdf ; yes ; Auto-Generated Megafunction ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/db/mult_ons.tdf ; ; +-----------------------------------------------------------------------+-----------------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ +-------------------------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Resource Usage Summary ; +---------------------------------------------+---------------------------------------------------------------------------------+ ; Resource ; Usage ; +---------------------------------------------+---------------------------------------------------------------------------------+ ; Estimated Total logic elements ; 9,772 ; ; ; ; ; Total combinational functions ; 7724 ; ; Logic element usage by number of LUT inputs ; ; ; -- 4 input functions ; 2942 ; ; -- 3 input functions ; 2951 ; ; -- <=2 input functions ; 1831 ; ; ; ; ; Logic elements by mode ; ; ; -- normal mode ; 5317 ; ; -- arithmetic mode ; 2407 ; ; ; ; ; Total registers ; 4787 ; ; -- Dedicated logic registers ; 4787 ; ; -- I/O registers ; 0 ; ; ; ; ; I/O pins ; 33 ; ; Total memory bits ; 344064 ; ; UFM blocks ; 1 ; ; ; ; ; Embedded Multiplier 9-bit elements ; 45 ; ; ; ; ; Total PLLs ; 1 ; ; -- PLLs ; 1 ; ; ; ; ; Maximum fan-out node ; pll:pll_inst|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] ; ; Maximum fan-out ; 4832 ; ; Total fan-out ; 43582 ; ; Average fan-out ; 3.43 ; +---------------------------------------------+---------------------------------------------------------------------------------+ +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Resource Utilization by Entity ; +---------------------------------------------------------------------------------------------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------+--------------+ ; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; UFM Blocks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; ADC blocks ; Full Hierarchy Name ; Entity Name ; Library Name ; +---------------------------------------------------------------------------------------------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------+--------------+ ; |sidmax ; 7724 (306) ; 4787 (123) ; 344064 ; 1 ; 45 ; 1 ; 22 ; 33 ; 0 ; 0 ; |sidmax ; sidmax ; work ; ; |PSG_top:\psg_on:PSG_1| ; 304 (58) ; 198 (84) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|PSG_top:\psg_on:PSG_1 ; PSG_top ; work ; ; |PSG_envelope:envelope| ; 74 (25) ; 27 (11) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|PSG_top:\psg_on:PSG_1|PSG_envelope:envelope ; PSG_envelope ; work ; ; |PSG_freqdiv:envelope_ticker| ; 49 (49) ; 16 (16) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|PSG_top:\psg_on:PSG_1|PSG_envelope:envelope|PSG_freqdiv:envelope_ticker ; PSG_freqdiv ; work ; ; |PSG_freqdiv:channel_a_ticker| ; 36 (36) ; 12 (12) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|PSG_top:\psg_on:PSG_1|PSG_freqdiv:channel_a_ticker ; PSG_freqdiv ; work ; ; |PSG_freqdiv:channel_b_ticker| ; 36 (36) ; 12 (12) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|PSG_top:\psg_on:PSG_1|PSG_freqdiv:channel_b_ticker ; PSG_freqdiv ; work ; ; |PSG_freqdiv:channel_c_ticker| ; 36 (36) ; 12 (12) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|PSG_top:\psg_on:PSG_1|PSG_freqdiv:channel_c_ticker ; PSG_freqdiv ; work ; ; |PSG_freqdiv:core_ticker| ; 3 (3) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|PSG_top:\psg_on:PSG_1|PSG_freqdiv:core_ticker ; PSG_freqdiv ; work ; ; |PSG_freqdiv:noise_preticker| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|PSG_top:\psg_on:PSG_1|PSG_freqdiv:noise_preticker ; PSG_freqdiv ; work ; ; |PSG_freqdiv:noise_ticker| ; 13 (13) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|PSG_top:\psg_on:PSG_1|PSG_freqdiv:noise_ticker ; PSG_freqdiv ; work ; ; |PSG_mixer:mix_a| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|PSG_top:\psg_on:PSG_1|PSG_mixer:mix_a ; PSG_mixer ; work ; ; |PSG_mixer:mix_b| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|PSG_top:\psg_on:PSG_1|PSG_mixer:mix_b ; PSG_mixer ; work ; ; |PSG_mixer:mix_c| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|PSG_top:\psg_on:PSG_1|PSG_mixer:mix_c ; PSG_mixer ; work ; ; |PSG_noise:noise| ; 1 (1) ; 18 (18) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|PSG_top:\psg_on:PSG_1|PSG_noise:noise ; PSG_noise ; work ; ; |PSG_volume:vol_a| ; 13 (13) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|PSG_top:\psg_on:PSG_1|PSG_volume:vol_a ; PSG_volume ; work ; ; |PSG_volume:vol_b| ; 13 (13) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|PSG_top:\psg_on:PSG_1|PSG_volume:vol_b ; PSG_volume ; work ; ; |PSG_volume:vol_c| ; 13 (13) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|PSG_top:\psg_on:PSG_1|PSG_volume:vol_c ; PSG_volume ; work ; ; |PSG_top:\psg_on:PSG_2| ; 301 (59) ; 194 (84) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|PSG_top:\psg_on:PSG_2 ; PSG_top ; work ; ; |PSG_envelope:envelope| ; 74 (25) ; 27 (11) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|PSG_top:\psg_on:PSG_2|PSG_envelope:envelope ; PSG_envelope ; work ; ; |PSG_freqdiv:envelope_ticker| ; 49 (49) ; 16 (16) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|PSG_top:\psg_on:PSG_2|PSG_envelope:envelope|PSG_freqdiv:envelope_ticker ; PSG_freqdiv ; work ; ; |PSG_freqdiv:channel_a_ticker| ; 36 (36) ; 12 (12) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|PSG_top:\psg_on:PSG_2|PSG_freqdiv:channel_a_ticker ; PSG_freqdiv ; work ; ; |PSG_freqdiv:channel_b_ticker| ; 36 (36) ; 12 (12) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|PSG_top:\psg_on:PSG_2|PSG_freqdiv:channel_b_ticker ; PSG_freqdiv ; work ; ; |PSG_freqdiv:channel_c_ticker| ; 36 (36) ; 12 (12) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|PSG_top:\psg_on:PSG_2|PSG_freqdiv:channel_c_ticker ; PSG_freqdiv ; work ; ; |PSG_freqdiv:noise_ticker| ; 13 (13) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|PSG_top:\psg_on:PSG_2|PSG_freqdiv:noise_ticker ; PSG_freqdiv ; work ; ; |PSG_mixer:mix_a| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|PSG_top:\psg_on:PSG_2|PSG_mixer:mix_a ; PSG_mixer ; work ; ; |PSG_mixer:mix_b| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|PSG_top:\psg_on:PSG_2|PSG_mixer:mix_b ; PSG_mixer ; work ; ; |PSG_mixer:mix_c| ; 3 (3) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|PSG_top:\psg_on:PSG_2|PSG_mixer:mix_c ; PSG_mixer ; work ; ; |PSG_noise:noise| ; 1 (1) ; 18 (18) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|PSG_top:\psg_on:PSG_2|PSG_noise:noise ; PSG_noise ; work ; ; |PSG_volume:vol_a| ; 13 (13) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|PSG_top:\psg_on:PSG_2|PSG_volume:vol_a ; PSG_volume ; work ; ; |PSG_volume:vol_b| ; 13 (13) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|PSG_top:\psg_on:PSG_2|PSG_volume:vol_b ; PSG_volume ; work ; ; |PSG_volume:vol_c| ; 13 (13) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|PSG_top:\psg_on:PSG_2|PSG_volume:vol_c ; PSG_volume ; work ; ; |PSG_volume_profile:\psg_on:vol_profile1| ; 63 (63) ; 59 (59) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|PSG_volume_profile:\psg_on:vol_profile1 ; PSG_volume_profile ; work ; ; |SID_f_distortion_mux:f_distortion_mux| ; 228 (62) ; 101 (52) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 0 ; |sidmax|SID_f_distortion_mux:f_distortion_mux ; SID_f_distortion_mux ; work ; ; |SID_f_distortion:f_distortion| ; 166 (166) ; 49 (49) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 0 ; |sidmax|SID_f_distortion_mux:f_distortion_mux|SID_f_distortion:f_distortion ; SID_f_distortion ; work ; ; |lpm_mult:Mult0| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 0 ; |sidmax|SID_f_distortion_mux:f_distortion_mux|SID_f_distortion:f_distortion|lpm_mult:Mult0 ; lpm_mult ; work ; ; |mult_ons:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 0 ; |sidmax|SID_f_distortion_mux:f_distortion_mux|SID_f_distortion:f_distortion|lpm_mult:Mult0|mult_ons:auto_generated ; mult_ons ; work ; ; |SID_top:sid1| ; 1665 (163) ; 1095 (270) ; 0 ; 0 ; 16 ; 0 ; 8 ; 0 ; 0 ; 0 ; |sidmax|SID_top:sid1 ; SID_top ; work ; ; |SID_amplitudeModulator:vol_abc| ; 63 (63) ; 0 (0) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 0 ; |sidmax|SID_top:sid1|SID_amplitudeModulator:vol_abc ; SID_amplitudeModulator ; work ; ; |lpm_mult:Mult0| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 0 ; |sidmax|SID_top:sid1|SID_amplitudeModulator:vol_abc|lpm_mult:Mult0 ; lpm_mult ; work ; ; |mult_6fs:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 0 ; |sidmax|SID_top:sid1|SID_amplitudeModulator:vol_abc|lpm_mult:Mult0|mult_6fs:auto_generated ; mult_6fs ; work ; ; |SID_envelope:envelope_a| ; 80 (80) ; 88 (88) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|SID_top:sid1|SID_envelope:envelope_a ; SID_envelope ; work ; ; |SID_envelope:envelope_b| ; 80 (80) ; 88 (88) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|SID_top:sid1|SID_envelope:envelope_b ; SID_envelope ; work ; ; |SID_envelope:envelope_c| ; 80 (80) ; 88 (88) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|SID_top:sid1|SID_envelope:envelope_c ; SID_envelope ; work ; ; |SID_envelope_tapmatch:envelope_tapmatcher| ; 60 (60) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|SID_top:sid1|SID_envelope_tapmatch:envelope_tapmatcher ; SID_envelope_tapmatch ; work ; ; |SID_filter:variable_state_filter| ; 390 (336) ; 232 (232) ; 0 ; 0 ; 12 ; 0 ; 6 ; 0 ; 0 ; 0 ; |sidmax|SID_top:sid1|SID_filter:variable_state_filter ; SID_filter ; work ; ; |lpm_mult:Mult0| ; 16 (0) ; 0 (0) ; 0 ; 0 ; 4 ; 0 ; 2 ; 0 ; 0 ; 0 ; |sidmax|SID_top:sid1|SID_filter:variable_state_filter|lpm_mult:Mult0 ; lpm_mult ; work ; ; |mult_1hs:auto_generated| ; 16 (16) ; 0 (0) ; 0 ; 0 ; 4 ; 0 ; 2 ; 0 ; 0 ; 0 ; |sidmax|SID_top:sid1|SID_filter:variable_state_filter|lpm_mult:Mult0|mult_1hs:auto_generated ; mult_1hs ; work ; ; |lpm_mult:Mult3| ; 19 (0) ; 0 (0) ; 0 ; 0 ; 4 ; 0 ; 2 ; 0 ; 0 ; 0 ; |sidmax|SID_top:sid1|SID_filter:variable_state_filter|lpm_mult:Mult3 ; lpm_mult ; work ; ; |mult_pgs:auto_generated| ; 19 (19) ; 0 (0) ; 0 ; 0 ; 4 ; 0 ; 2 ; 0 ; 0 ; 0 ; |sidmax|SID_top:sid1|SID_filter:variable_state_filter|lpm_mult:Mult3|mult_pgs:auto_generated ; mult_pgs ; work ; ; |lpm_mult:Mult4| ; 19 (0) ; 0 (0) ; 0 ; 0 ; 4 ; 0 ; 2 ; 0 ; 0 ; 0 ; |sidmax|SID_top:sid1|SID_filter:variable_state_filter|lpm_mult:Mult4 ; lpm_mult ; work ; ; |mult_pgs:auto_generated| ; 19 (19) ; 0 (0) ; 0 ; 0 ; 4 ; 0 ; 2 ; 0 ; 0 ; 0 ; |sidmax|SID_top:sid1|SID_filter:variable_state_filter|lpm_mult:Mult4|mult_pgs:auto_generated ; mult_pgs ; work ; ; |SID_oscillator:osc_a| ; 57 (57) ; 26 (26) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|SID_top:sid1|SID_oscillator:osc_a ; SID_oscillator ; work ; ; |SID_oscillator:osc_b| ; 57 (57) ; 26 (26) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|SID_top:sid1|SID_oscillator:osc_b ; SID_oscillator ; work ; ; |SID_oscillator:osc_c| ; 58 (58) ; 26 (26) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|SID_top:sid1|SID_oscillator:osc_c ; SID_oscillator ; work ; ; |SID_postFilterSum:postfilter| ; 128 (128) ; 16 (16) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 0 ; |sidmax|SID_top:sid1|SID_postFilterSum:postfilter ; SID_postFilterSum ; work ; ; |lpm_mult:Mult0| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 0 ; |sidmax|SID_top:sid1|SID_postFilterSum:postfilter|lpm_mult:Mult0 ; lpm_mult ; work ; ; |mult_gfs:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 0 ; |sidmax|SID_top:sid1|SID_postFilterSum:postfilter|lpm_mult:Mult0|mult_gfs:auto_generated ; mult_gfs ; work ; ; |SID_preFilterSum:prefilter| ; 51 (51) ; 53 (53) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|SID_top:sid1|SID_preFilterSum:prefilter ; SID_preFilterSum ; work ; ; |SID_wavegen:wavegen_a| ; 132 (132) ; 59 (59) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|SID_top:sid1|SID_wavegen:wavegen_a ; SID_wavegen ; work ; ; |SID_wavegen:wavegen_b| ; 132 (132) ; 59 (59) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|SID_top:sid1|SID_wavegen:wavegen_b ; SID_wavegen ; work ; ; |SID_wavegen:wavegen_c| ; 133 (133) ; 59 (59) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|SID_top:sid1|SID_wavegen:wavegen_c ; SID_wavegen ; work ; ; |complete_address_decoder:decode_addr1| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|SID_top:sid1|complete_address_decoder:decode_addr1 ; complete_address_decoder ; work ; ; |SID_top:sid2| ; 1686 (191) ; 1063 (243) ; 0 ; 0 ; 16 ; 0 ; 8 ; 0 ; 0 ; 0 ; |sidmax|SID_top:sid2 ; SID_top ; work ; ; |SID_amplitudeModulator:vol_abc| ; 63 (63) ; 0 (0) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 0 ; |sidmax|SID_top:sid2|SID_amplitudeModulator:vol_abc ; SID_amplitudeModulator ; work ; ; |lpm_mult:Mult0| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 0 ; |sidmax|SID_top:sid2|SID_amplitudeModulator:vol_abc|lpm_mult:Mult0 ; lpm_mult ; work ; ; |mult_6fs:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 0 ; |sidmax|SID_top:sid2|SID_amplitudeModulator:vol_abc|lpm_mult:Mult0|mult_6fs:auto_generated ; mult_6fs ; work ; ; |SID_envelope:envelope_a| ; 80 (80) ; 88 (88) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|SID_top:sid2|SID_envelope:envelope_a ; SID_envelope ; work ; ; |SID_envelope:envelope_b| ; 80 (80) ; 88 (88) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|SID_top:sid2|SID_envelope:envelope_b ; SID_envelope ; work ; ; |SID_envelope:envelope_c| ; 80 (80) ; 88 (88) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|SID_top:sid2|SID_envelope:envelope_c ; SID_envelope ; work ; ; |SID_envelope_tapmatch:envelope_tapmatcher| ; 58 (58) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|SID_top:sid2|SID_envelope_tapmatch:envelope_tapmatcher ; SID_envelope_tapmatch ; work ; ; |SID_filter:variable_state_filter| ; 390 (336) ; 232 (232) ; 0 ; 0 ; 12 ; 0 ; 6 ; 0 ; 0 ; 0 ; |sidmax|SID_top:sid2|SID_filter:variable_state_filter ; SID_filter ; work ; ; |lpm_mult:Mult0| ; 16 (0) ; 0 (0) ; 0 ; 0 ; 4 ; 0 ; 2 ; 0 ; 0 ; 0 ; |sidmax|SID_top:sid2|SID_filter:variable_state_filter|lpm_mult:Mult0 ; lpm_mult ; work ; ; |mult_1hs:auto_generated| ; 16 (16) ; 0 (0) ; 0 ; 0 ; 4 ; 0 ; 2 ; 0 ; 0 ; 0 ; |sidmax|SID_top:sid2|SID_filter:variable_state_filter|lpm_mult:Mult0|mult_1hs:auto_generated ; mult_1hs ; work ; ; |lpm_mult:Mult3| ; 19 (0) ; 0 (0) ; 0 ; 0 ; 4 ; 0 ; 2 ; 0 ; 0 ; 0 ; |sidmax|SID_top:sid2|SID_filter:variable_state_filter|lpm_mult:Mult3 ; lpm_mult ; work ; ; |mult_pgs:auto_generated| ; 19 (19) ; 0 (0) ; 0 ; 0 ; 4 ; 0 ; 2 ; 0 ; 0 ; 0 ; |sidmax|SID_top:sid2|SID_filter:variable_state_filter|lpm_mult:Mult3|mult_pgs:auto_generated ; mult_pgs ; work ; ; |lpm_mult:Mult4| ; 19 (0) ; 0 (0) ; 0 ; 0 ; 4 ; 0 ; 2 ; 0 ; 0 ; 0 ; |sidmax|SID_top:sid2|SID_filter:variable_state_filter|lpm_mult:Mult4 ; lpm_mult ; work ; ; |mult_pgs:auto_generated| ; 19 (19) ; 0 (0) ; 0 ; 0 ; 4 ; 0 ; 2 ; 0 ; 0 ; 0 ; |sidmax|SID_top:sid2|SID_filter:variable_state_filter|lpm_mult:Mult4|mult_pgs:auto_generated ; mult_pgs ; work ; ; |SID_oscillator:osc_a| ; 57 (57) ; 26 (26) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|SID_top:sid2|SID_oscillator:osc_a ; SID_oscillator ; work ; ; |SID_oscillator:osc_b| ; 57 (57) ; 26 (26) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|SID_top:sid2|SID_oscillator:osc_b ; SID_oscillator ; work ; ; |SID_oscillator:osc_c| ; 58 (58) ; 26 (26) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|SID_top:sid2|SID_oscillator:osc_c ; SID_oscillator ; work ; ; |SID_postFilterSum:postfilter| ; 128 (128) ; 16 (16) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 0 ; |sidmax|SID_top:sid2|SID_postFilterSum:postfilter ; SID_postFilterSum ; work ; ; |lpm_mult:Mult0| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 0 ; |sidmax|SID_top:sid2|SID_postFilterSum:postfilter|lpm_mult:Mult0 ; lpm_mult ; work ; ; |mult_gfs:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 0 ; |sidmax|SID_top:sid2|SID_postFilterSum:postfilter|lpm_mult:Mult0|mult_gfs:auto_generated ; mult_gfs ; work ; ; |SID_preFilterSum:prefilter| ; 45 (45) ; 50 (50) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|SID_top:sid2|SID_preFilterSum:prefilter ; SID_preFilterSum ; work ; ; |SID_wavegen:wavegen_a| ; 132 (132) ; 59 (59) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|SID_top:sid2|SID_wavegen:wavegen_a ; SID_wavegen ; work ; ; |SID_wavegen:wavegen_b| ; 132 (132) ; 59 (59) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|SID_top:sid2|SID_wavegen:wavegen_b ; SID_wavegen ; work ; ; |SID_wavegen:wavegen_c| ; 134 (134) ; 59 (59) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|SID_top:sid2|SID_wavegen:wavegen_c ; SID_wavegen ; work ; ; |complete_address_decoder:decode_addr1| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|SID_top:sid2|complete_address_decoder:decode_addr1 ; complete_address_decoder ; work ; ; |clockgensid:clockgen1| ; 84 (84) ; 30 (30) ; 0 ; 0 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; |sidmax|clockgensid:clockgen1 ; clockgensid ; work ; ; |lpm_mult:Mult0| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; |sidmax|clockgensid:clockgen1|lpm_mult:Mult0 ; lpm_mult ; work ; ; |mult_uks:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; |sidmax|clockgensid:clockgen1|lpm_mult:Mult0|mult_uks:auto_generated ; mult_uks ; work ; ; |complete_address_decoder:\gen_config:decode_addr1| ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|complete_address_decoder:\gen_config:decode_addr1 ; complete_address_decoder ; work ; ; |filtered_sigmadelta:dac_0| ; 144 (0) ; 45 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|filtered_sigmadelta:dac_0 ; filtered_sigmadelta ; work ; ; |sigmadelta_2ndorder_dither:\gen_2ndorder_dither_on:dac_2nd_dither| ; 144 (144) ; 45 (45) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|filtered_sigmadelta:dac_0|sigmadelta_2ndorder_dither:\gen_2ndorder_dither_on:dac_2nd_dither ; sigmadelta_2ndorder_dither ; work ; ; |filtered_sigmadelta:dac_2| ; 144 (0) ; 45 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|filtered_sigmadelta:dac_2 ; filtered_sigmadelta ; work ; ; |sigmadelta_2ndorder_dither:\gen_2ndorder_dither_on:dac_2nd_dither| ; 144 (144) ; 45 (45) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|filtered_sigmadelta:dac_2|sigmadelta_2ndorder_dither:\gen_2ndorder_dither_on:dac_2nd_dither ; sigmadelta_2ndorder_dither ; work ; ; |filtered_sigmadelta:dac_3| ; 144 (0) ; 45 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|filtered_sigmadelta:dac_3 ; filtered_sigmadelta ; work ; ; |sigmadelta_2ndorder_dither:\gen_2ndorder_dither_on:dac_2nd_dither| ; 144 (144) ; 45 (45) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|filtered_sigmadelta:dac_3|sigmadelta_2ndorder_dither:\gen_2ndorder_dither_on:dac_2nd_dither ; sigmadelta_2ndorder_dither ; work ; ; |flash_controller:\flash_on:flash_controller_inst| ; 770 (298) ; 401 (148) ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|flash_controller:\flash_on:flash_controller_inst ; flash_controller ; work ; ; |flash:flash1| ; 472 (0) ; 253 (0) ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|flash_controller:\flash_on:flash_controller_inst|flash:flash1 ; flash ; flash ; ; |altera_onchip_flash:onchip_flash_0| ; 472 (0) ; 253 (0) ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0 ; altera_onchip_flash ; flash ; ; |altera_onchip_flash_avmm_csr_controller:avmm_csr_controller| ; 44 (44) ; 33 (33) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller ; altera_onchip_flash_avmm_csr_controller ; flash ; ; |altera_onchip_flash_avmm_data_controller:avmm_data_controller| ; 428 (355) ; 220 (184) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller ; altera_onchip_flash_avmm_data_controller ; flash ; ; |altera_onchip_flash_a_address_write_protection_check:access_address_write_protection_checker| ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_onchip_flash_a_address_write_protection_check:access_address_write_protection_checker ; altera_onchip_flash_a_address_write_protection_check ; flash ; ; |altera_onchip_flash_convert_address:address_convertor| ; 25 (25) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_onchip_flash_convert_address:address_convertor ; altera_onchip_flash_convert_address ; flash ; ; |altera_std_synchronizer:stdsync_busy_clear| ; 0 (0) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_std_synchronizer:stdsync_busy_clear ; altera_std_synchronizer ; work ; ; |altera_std_synchronizer:stdsync_busy| ; 0 (0) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_std_synchronizer:stdsync_busy ; altera_std_synchronizer ; work ; ; |lpm_shiftreg:ufm_data_shiftreg| ; 32 (32) ; 32 (32) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|lpm_shiftreg:ufm_data_shiftreg ; lpm_shiftreg ; work ; ; |altera_onchip_flash_block:altera_onchip_flash_block| ; 0 (0) ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_block:altera_onchip_flash_block ; altera_onchip_flash_block ; flash ; ; |generic_ram_infer:\sample_on:normal_ram:sample_ram_inst| ; 92 (47) ; 3 (0) ; 344064 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|generic_ram_infer:\sample_on:normal_ram:sample_ram_inst ; generic_ram_infer ; work ; ; |altsyncram:ram_block_rtl_0| ; 45 (0) ; 3 (0) ; 344064 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|generic_ram_infer:\sample_on:normal_ram:sample_ram_inst|altsyncram:ram_block_rtl_0 ; altsyncram ; work ; ; |altsyncram_6t31:auto_generated| ; 45 (0) ; 3 (3) ; 344064 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|generic_ram_infer:\sample_on:normal_ram:sample_ram_inst|altsyncram:ram_block_rtl_0|altsyncram_6t31:auto_generated ; altsyncram_6t31 ; work ; ; |decode_8j9:rden_decode| ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|generic_ram_infer:\sample_on:normal_ram:sample_ram_inst|altsyncram:ram_block_rtl_0|altsyncram_6t31:auto_generated|decode_8j9:rden_decode ; decode_8j9 ; work ; ; |decode_f7a:decode3| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|generic_ram_infer:\sample_on:normal_ram:sample_ram_inst|altsyncram:ram_block_rtl_0|altsyncram_6t31:auto_generated|decode_f7a:decode3 ; decode_f7a ; work ; ; |mux_v1b:mux2| ; 33 (33) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|generic_ram_infer:\sample_on:normal_ram:sample_ram_inst|altsyncram:ram_block_rtl_0|altsyncram_6t31:auto_generated|mux_v1b:mux2 ; mux_v1b ; work ; ; |int_osc:oscillator| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|int_osc:oscillator ; int_osc ; int_osc ; ; |altera_int_osc:int_osc_0| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|int_osc:oscillator|altera_int_osc:int_osc_0 ; altera_int_osc ; int_osc ; ; |mixer:mixer1| ; 351 (351) ; 211 (211) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|mixer:mixer1 ; mixer ; work ; ; |pll:pll_inst| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|pll:pll_inst ; pll ; work ; ; |altpll:altpll_component| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|pll:pll_inst|altpll:altpll_component ; altpll ; work ; ; |pll_altpll:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|pll:pll_inst|altpll:altpll_component|pll_altpll:auto_generated ; pll_altpll ; work ; ; |pokey:\POKEY_ON:1:pokeyx| ; 284 (146) ; 342 (199) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|pokey:\POKEY_ON:1:pokeyx ; pokey ; work ; ; |complete_address_decoder:decode_addr1| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|pokey:\POKEY_ON:1:pokeyx|complete_address_decoder:decode_addr1 ; complete_address_decoder ; work ; ; |delay_line:serin_clock_delay| ; 7 (7) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|pokey:\POKEY_ON:1:pokeyx|delay_line:serin_clock_delay ; delay_line ; work ; ; |delay_line:serout_clock_delay| ; 4 (4) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|pokey:\POKEY_ON:1:pokeyx|delay_line:serout_clock_delay ; delay_line ; work ; ; |latch_delay_line:stimer_delay| ; 2 (2) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|pokey:\POKEY_ON:1:pokeyx|latch_delay_line:stimer_delay ; latch_delay_line ; work ; ; |latch_delay_line:twotone_del| ; 3 (3) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|pokey:\POKEY_ON:1:pokeyx|latch_delay_line:twotone_del ; latch_delay_line ; work ; ; |pokey_countdown_timer:timer0| ; 14 (9) ; 11 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|pokey:\POKEY_ON:1:pokeyx|pokey_countdown_timer:timer0 ; pokey_countdown_timer ; work ; ; |delay_line:underflow0_delay| ; 5 (5) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|pokey:\POKEY_ON:1:pokeyx|pokey_countdown_timer:timer0|delay_line:underflow0_delay ; delay_line ; work ; ; |pokey_countdown_timer:timer1| ; 14 (9) ; 11 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|pokey:\POKEY_ON:1:pokeyx|pokey_countdown_timer:timer1 ; pokey_countdown_timer ; work ; ; |delay_line:underflow0_delay| ; 5 (5) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|pokey:\POKEY_ON:1:pokeyx|pokey_countdown_timer:timer1|delay_line:underflow0_delay ; delay_line ; work ; ; |pokey_countdown_timer:timer2| ; 14 (9) ; 11 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|pokey:\POKEY_ON:1:pokeyx|pokey_countdown_timer:timer2 ; pokey_countdown_timer ; work ; ; |delay_line:underflow0_delay| ; 5 (5) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|pokey:\POKEY_ON:1:pokeyx|pokey_countdown_timer:timer2|delay_line:underflow0_delay ; delay_line ; work ; ; |pokey_countdown_timer:timer3| ; 16 (9) ; 11 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|pokey:\POKEY_ON:1:pokeyx|pokey_countdown_timer:timer3 ; pokey_countdown_timer ; work ; ; |delay_line:underflow0_delay| ; 7 (7) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|pokey:\POKEY_ON:1:pokeyx|pokey_countdown_timer:timer3|delay_line:underflow0_delay ; delay_line ; work ; ; |pokey_noise_filter:pokey_noise_filter0| ; 4 (4) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|pokey:\POKEY_ON:1:pokeyx|pokey_noise_filter:pokey_noise_filter0 ; pokey_noise_filter ; work ; ; |pokey_noise_filter:pokey_noise_filter1| ; 4 (4) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|pokey:\POKEY_ON:1:pokeyx|pokey_noise_filter:pokey_noise_filter1 ; pokey_noise_filter ; work ; ; |pokey_noise_filter:pokey_noise_filter2| ; 4 (4) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|pokey:\POKEY_ON:1:pokeyx|pokey_noise_filter:pokey_noise_filter2 ; pokey_noise_filter ; work ; ; |pokey_noise_filter:pokey_noise_filter3| ; 4 (4) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|pokey:\POKEY_ON:1:pokeyx|pokey_noise_filter:pokey_noise_filter3 ; pokey_noise_filter ; work ; ; |pokey_poly_17_9:poly_17_19_lfsr| ; 18 (18) ; 18 (18) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|pokey:\POKEY_ON:1:pokeyx|pokey_poly_17_9:poly_17_19_lfsr ; pokey_poly_17_9 ; work ; ; |pokey_poly_4:poly_4_lfsr| ; 4 (4) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|pokey:\POKEY_ON:1:pokeyx|pokey_poly_4:poly_4_lfsr ; pokey_poly_4 ; work ; ; |pokey_poly_5:poly_5_lfsr| ; 5 (5) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|pokey:\POKEY_ON:1:pokeyx|pokey_poly_5:poly_5_lfsr ; pokey_poly_5 ; work ; ; |syncreset_enable_divider:enable_15_div| ; 11 (11) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|pokey:\POKEY_ON:1:pokeyx|syncreset_enable_divider:enable_15_div ; syncreset_enable_divider ; work ; ; |syncreset_enable_divider:enable_64_div| ; 8 (8) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|pokey:\POKEY_ON:1:pokeyx|syncreset_enable_divider:enable_64_div ; syncreset_enable_divider ; work ; ; |wide_delay_line:audctl_delay| ; 0 (0) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|pokey:\POKEY_ON:1:pokeyx|wide_delay_line:audctl_delay ; wide_delay_line ; work ; ; |wide_delay_line:audf0_delay| ; 0 (0) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|pokey:\POKEY_ON:1:pokeyx|wide_delay_line:audf0_delay ; wide_delay_line ; work ; ; |wide_delay_line:audf1_delay| ; 0 (0) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|pokey:\POKEY_ON:1:pokeyx|wide_delay_line:audf1_delay ; wide_delay_line ; work ; ; |wide_delay_line:audf2_delay| ; 0 (0) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|pokey:\POKEY_ON:1:pokeyx|wide_delay_line:audf2_delay ; wide_delay_line ; work ; ; |wide_delay_line:audf3_delay| ; 0 (0) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|pokey:\POKEY_ON:1:pokeyx|wide_delay_line:audf3_delay ; wide_delay_line ; work ; ; |pokey_mixer_mux:pokey_mixer_both| ; 36 (36) ; 89 (89) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|pokey_mixer_mux:pokey_mixer_both ; pokey_mixer_mux ; work ; ; |sample_top:\sample_on:sample1| ; 804 (252) ; 591 (292) ; 0 ; 0 ; 10 ; 0 ; 5 ; 0 ; 0 ; 0 ; |sidmax|sample_top:\sample_on:sample1 ; sample_top ; work ; ; |complete_address_decoder:decode_addr2| ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|sample_top:\sample_on:sample1|complete_address_decoder:decode_addr2 ; complete_address_decoder ; work ; ; |lpm_mult:Mult0| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 0 ; |sidmax|sample_top:\sample_on:sample1|lpm_mult:Mult0 ; lpm_mult ; work ; ; |mult_4fs:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 0 ; |sidmax|sample_top:\sample_on:sample1|lpm_mult:Mult0|mult_4fs:auto_generated ; mult_4fs ; work ; ; |lpm_mult:Mult1| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 0 ; |sidmax|sample_top:\sample_on:sample1|lpm_mult:Mult1 ; lpm_mult ; work ; ; |mult_4fs:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 0 ; |sidmax|sample_top:\sample_on:sample1|lpm_mult:Mult1|mult_4fs:auto_generated ; mult_4fs ; work ; ; |lpm_mult:Mult2| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 0 ; |sidmax|sample_top:\sample_on:sample1|lpm_mult:Mult2 ; lpm_mult ; work ; ; |mult_4fs:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 0 ; |sidmax|sample_top:\sample_on:sample1|lpm_mult:Mult2|mult_4fs:auto_generated ; mult_4fs ; work ; ; |lpm_mult:Mult3| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 0 ; |sidmax|sample_top:\sample_on:sample1|lpm_mult:Mult3 ; lpm_mult ; work ; ; |mult_4fs:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 0 ; |sidmax|sample_top:\sample_on:sample1|lpm_mult:Mult3|mult_4fs:auto_generated ; mult_4fs ; work ; ; |sample_adpcm:adpcm_decoder| ; 171 (171) ; 107 (107) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 0 ; |sidmax|sample_top:\sample_on:sample1|sample_adpcm:adpcm_decoder ; sample_adpcm ; work ; ; |lpm_mult:Mult0| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 0 ; |sidmax|sample_top:\sample_on:sample1|sample_adpcm:adpcm_decoder|lpm_mult:Mult0 ; lpm_mult ; work ; ; |mult_5fs:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 0 ; |sidmax|sample_top:\sample_on:sample1|sample_adpcm:adpcm_decoder|lpm_mult:Mult0|mult_5fs:auto_generated ; mult_5fs ; work ; ; |sample_channel:ch0_inst| ; 93 (93) ; 48 (48) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|sample_top:\sample_on:sample1|sample_channel:ch0_inst ; sample_channel ; work ; ; |sample_channel:ch1_inst| ; 93 (93) ; 48 (48) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|sample_top:\sample_on:sample1|sample_channel:ch1_inst ; sample_channel ; work ; ; |sample_channel:ch2_inst| ; 93 (93) ; 48 (48) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|sample_top:\sample_on:sample1|sample_channel:ch2_inst ; sample_channel ; work ; ; |sample_channel:ch3_inst| ; 94 (94) ; 48 (48) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|sample_top:\sample_on:sample1|sample_channel:ch3_inst ; sample_channel ; work ; ; |sigmadelta_dither:dac_dithergen| ; 9 (9) ; 16 (16) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|sigmadelta_dither:dac_dithergen ; sigmadelta_dither ; work ; ; |simple_low_pass_filter:adcfilter2| ; 83 (83) ; 42 (42) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|simple_low_pass_filter:adcfilter2 ; simple_low_pass_filter ; work ; ; |simple_low_pass_filter:adcfilter| ; 83 (83) ; 42 (42) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|simple_low_pass_filter:adcfilter ; simple_low_pass_filter ; work ; ; |slave_timing_6502:bus_adapt| ; 136 (135) ; 46 (40) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|slave_timing_6502:bus_adapt ; slave_timing_6502 ; work ; ; |synchronizer:synchronizer_cs| ; 1 (1) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|slave_timing_6502:bus_adapt|synchronizer:synchronizer_cs ; synchronizer ; work ; ; |synchronizer:synchronizer_phi| ; 0 (0) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|slave_timing_6502:bus_adapt|synchronizer:synchronizer_phi ; synchronizer ; work ; ; |stereo_detect:\auto_stereo:a4| ; 4 (4) ; 6 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|stereo_detect:\auto_stereo:a4 ; stereo_detect ; work ; ; |synchronizer:synchronizer_4| ; 0 (0) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sidmax|stereo_detect:\auto_stereo:a4|synchronizer:synchronizer_4 ; synchronizer ; work ; +---------------------------------------------------------------------------------------------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------+--------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis RAM Summary ; +------------------------------------------------------------------------------------------------------------------------------+------+-------------+--------------+--------------+--------------+--------------+--------+------+ ; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ; +------------------------------------------------------------------------------------------------------------------------------+------+-------------+--------------+--------------+--------------+--------------+--------+------+ ; generic_ram_infer:\sample_on:normal_ram:sample_ram_inst|altsyncram:ram_block_rtl_0|altsyncram_6t31:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; 43008 ; 8 ; -- ; -- ; 344064 ; None ; +------------------------------------------------------------------------------------------------------------------------------+------+-------------+--------------+--------------+--------------+--------------+--------+------+ +-----------------------------------------------------+ ; Analysis & Synthesis DSP Block Usage Summary ; +---------------------------------------+-------------+ ; Statistic ; Number Used ; +---------------------------------------+-------------+ ; Simple Multipliers (9-bit) ; 1 ; ; Simple Multipliers (18-bit) ; 22 ; ; Embedded Multiplier Blocks ; -- ; ; Embedded Multiplier 9-bit elements ; 45 ; ; Signed Embedded Multipliers ; 15 ; ; Unsigned Embedded Multipliers ; 2 ; ; Mixed Sign Embedded Multipliers ; 6 ; ; Variable Sign Embedded Multipliers ; 0 ; ; Dedicated Input Shift Register Chains ; 0 ; +---------------------------------------+-------------+ Note: number of Embedded Multiplier Blocks used is only available after a successful fit. +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis IP Cores Summary ; +--------+---------------------+---------+--------------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+ ; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ; +--------+---------------------+---------+--------------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+ ; N/A ; altera_onchip_flash ; 23.1 ; N/A ; N/A ; |sidmax|flash_controller:\flash_on:flash_controller_inst|flash:flash1 ; flash.qsys ; ; Altera ; 6AF7_FFFF ; N/A ; N/A ; Licensed ; |sidmax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_block:altera_onchip_flash_block ; ; ; Altera ; altera_soft_lvds ; 23.1 ; N/A ; N/A ; |sidmax|lvds_rx:lvds_rx0 ; lvds_rx.vhd ; ; Altera ; altera_soft_lvds ; 23.1 ; N/A ; N/A ; |sidmax|lvds_tx:lvds_tx0 ; lvds_tx.vhd ; ; N/A ; altera_int_osc ; 23.1 ; N/A ; N/A ; |sidmax|int_osc:oscillator ; int_osc.qsys ; ; Altera ; ALTPLL ; 23.1 ; N/A ; N/A ; |sidmax|pll:pll_inst ; pll.vhd ; +--------+---------------------+---------+--------------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+ Encoding Type: One-Hot +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; State Machine - |sidmax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|avmm_read_valid_state ; +----------------------------------------------+---------------------------------------+----------------------------------------------+------------------------------------------------------------------------+ ; Name ; avmm_read_valid_state.READ_VALID_IDLE ; avmm_read_valid_state.READ_VALID_PRE_READING ; avmm_read_valid_state.READ_VALID_READING ; +----------------------------------------------+---------------------------------------+----------------------------------------------+------------------------------------------------------------------------+ ; avmm_read_valid_state.READ_VALID_IDLE ; 0 ; 0 ; 0 ; ; avmm_read_valid_state.READ_VALID_READING ; 1 ; 0 ; 1 ; ; avmm_read_valid_state.READ_VALID_PRE_READING ; 1 ; 1 ; 0 ; +----------------------------------------------+---------------------------------------+----------------------------------------------+------------------------------------------------------------------------+ Encoding Type: One-Hot +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; State Machine - |sidmax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|read_state ; +--------------------------------+----------------------------+----------------------------+----------------------------+---------------------------------------------------------------------------+ ; Name ; read_state.READ_STATE_READ ; read_state.READ_STATE_ADDR ; read_state.READ_STATE_IDLE ; read_state.READ_STATE_PULSE_SE ; +--------------------------------+----------------------------+----------------------------+----------------------------+---------------------------------------------------------------------------+ ; read_state.READ_STATE_IDLE ; 0 ; 0 ; 0 ; 0 ; ; read_state.READ_STATE_ADDR ; 0 ; 1 ; 1 ; 0 ; ; read_state.READ_STATE_READ ; 1 ; 0 ; 1 ; 0 ; ; read_state.READ_STATE_PULSE_SE ; 0 ; 0 ; 1 ; 1 ; +--------------------------------+----------------------------+----------------------------+----------------------------+---------------------------------------------------------------------------+ Encoding Type: One-Hot +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; State Machine - |sidmax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|erase_state ; +-----------------------------------+-------------------------------+-------------------------------+-----------------------------------+-----------------------------------+------------------------------+------------------------------+ ; Name ; erase_state.ERASE_STATE_ERROR ; erase_state.ERASE_STATE_RESET ; erase_state.ERASE_STATE_WAIT_DONE ; erase_state.ERASE_STATE_WAIT_BUSY ; erase_state.ERASE_STATE_ADDR ; erase_state.ERASE_STATE_IDLE ; +-----------------------------------+-------------------------------+-------------------------------+-----------------------------------+-----------------------------------+------------------------------+------------------------------+ ; erase_state.ERASE_STATE_IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; ; erase_state.ERASE_STATE_ADDR ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ; ; erase_state.ERASE_STATE_WAIT_BUSY ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ; ; erase_state.ERASE_STATE_WAIT_DONE ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ; ; erase_state.ERASE_STATE_RESET ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ; ; erase_state.ERASE_STATE_ERROR ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ; +-----------------------------------+-------------------------------+-------------------------------+-----------------------------------+-----------------------------------+------------------------------+------------------------------+ Encoding Type: One-Hot +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; State Machine - |sidmax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|write_state ; +-----------------------------------+-------------------------------+-------------------------------+-----------------------------------+-----------------------------------+-------------------------------+------------------------------+------------------------------+ ; Name ; write_state.WRITE_STATE_ERROR ; write_state.WRITE_STATE_RESET ; write_state.WRITE_STATE_WAIT_DONE ; write_state.WRITE_STATE_WAIT_BUSY ; write_state.WRITE_STATE_WRITE ; write_state.WRITE_STATE_ADDR ; write_state.WRITE_STATE_IDLE ; +-----------------------------------+-------------------------------+-------------------------------+-----------------------------------+-----------------------------------+-------------------------------+------------------------------+------------------------------+ ; write_state.WRITE_STATE_IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; ; write_state.WRITE_STATE_ADDR ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ; ; write_state.WRITE_STATE_WRITE ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ; ; write_state.WRITE_STATE_WAIT_BUSY ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ; ; write_state.WRITE_STATE_WAIT_DONE ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ; ; write_state.WRITE_STATE_RESET ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ; ; write_state.WRITE_STATE_ERROR ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +-----------------------------------+-------------------------------+-------------------------------+-----------------------------------+-----------------------------------+-------------------------------+------------------------------+------------------------------+ +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Registers Protected by Synthesis ; +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+ ; Register Name ; Protected by Synthesis Attribute or Preserve Register Assignment ; Not to be Touched by Netlist Optimizations ; +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+ ; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_std_synchronizer:stdsync_busy_clear|dreg[0] ; yes ; yes ; ; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_std_synchronizer:stdsync_busy|dreg[0] ; yes ; yes ; ; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_std_synchronizer:stdsync_busy_clear|din_s1 ; yes ; yes ; ; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_std_synchronizer:stdsync_busy|din_s1 ; yes ; yes ; ; Total number of protected registers is 4 ; ; ; +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+ +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Registers Removed During Synthesis ; +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Register name ; Reason for Removal ; +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; pokey:\POKEY_ON:1:pokeyx|irqst_reg[6,7] ; Stuck at VCC due to stuck port data_in ; ; pokey:\POKEY_ON:1:pokeyx|keyboard_overrun_reg ; Stuck at GND due to stuck port data_in ; ; pokey:\POKEY_ON:1:pokeyx|synchronizer:sio_clk1_synchronizer|ff_reg[2] ; Stuck at VCC due to stuck port data_in ; ; pokey:\POKEY_ON:1:pokeyx|synchronizer:sio_in1_synchronizer|ff_reg[2] ; Stuck at VCC due to stuck port data_in ; ; pokey:\POKEY_ON:0:pokeyx|audf0_reg[0..7] ; Stuck at GND due to stuck port clock_enable ; ; pokey:\POKEY_ON:0:pokeyx|audc0_reg[0..7] ; Stuck at GND due to stuck port clock_enable ; ; pokey:\POKEY_ON:0:pokeyx|audf1_reg[0..7] ; Stuck at GND due to stuck port clock_enable ; ; pokey:\POKEY_ON:0:pokeyx|audc1_reg[0..7] ; Stuck at GND due to stuck port clock_enable ; ; pokey:\POKEY_ON:0:pokeyx|audf2_reg[0..7] ; Stuck at GND due to stuck port clock_enable ; ; pokey:\POKEY_ON:0:pokeyx|audc2_reg[0..7] ; Stuck at GND due to stuck port clock_enable ; ; pokey:\POKEY_ON:0:pokeyx|audf3_reg[0..7] ; Stuck at GND due to stuck port clock_enable ; ; pokey:\POKEY_ON:0:pokeyx|audc3_reg[0..7] ; Stuck at GND due to stuck port clock_enable ; ; pokey:\POKEY_ON:0:pokeyx|audctl_reg[0..7] ; Stuck at GND due to stuck port clock_enable ; ; pokey:\POKEY_ON:0:pokeyx|irqen_reg[0..7] ; Stuck at GND due to stuck port clock_enable ; ; pokey:\POKEY_ON:0:pokeyx|irqst_reg[6,7] ; Stuck at VCC due to stuck port data_in ; ; pokey:\POKEY_ON:0:pokeyx|skctl_reg[3..7] ; Stuck at GND due to stuck port clock_enable ; ; pokey:\POKEY_ON:0:pokeyx|serout_holding_reg[0..7] ; Stuck at GND due to stuck port clock_enable ; ; pokey:\POKEY_ON:0:pokeyx|irqst_reg[3] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|synchronizer:sio_clk1_synchronizer|ff_reg[2] ; Stuck at VCC due to stuck port data_in ; ; pokey:\POKEY_ON:0:pokeyx|synchronizer:sio_in1_synchronizer|ff_reg[2] ; Stuck at VCC due to stuck port data_in ; ; pokey:\POKEY_ON:0:pokeyx|noise_4_reg[0..2] ; Lost fanout ; ; synchronizer:synchronizer_fancy_enable|ff_reg[2] ; Stuck at VCC due to stuck port data_in ; ; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|is_sector5_writable_reg ; Stuck at GND due to stuck port data_in ; ; pokey:\POKEY_ON:1:pokeyx|synchronizer:sio_clk1_synchronizer|ff_reg[1] ; Stuck at VCC due to stuck port data_in ; ; pokey:\POKEY_ON:1:pokeyx|synchronizer:sio_in1_synchronizer|ff_reg[1] ; Stuck at VCC due to stuck port data_in ; ; pokey:\POKEY_ON:0:pokeyx|irqst_reg[0..2,4,5] ; Stuck at VCC due to stuck port data_in ; ; pokey:\POKEY_ON:0:pokeyx|chan2_output_reg ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|chan3_output_reg ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|volume_channel_0_reg[0..3] ; Stuck at GND due to stuck port data_in ; ; pokey:\POKEY_ON:0:pokeyx|volume_channel_1_reg[0..3] ; Stuck at GND due to stuck port data_in ; ; pokey:\POKEY_ON:0:pokeyx|volume_channel_2_reg[0..3] ; Stuck at GND due to stuck port data_in ; ; pokey:\POKEY_ON:0:pokeyx|volume_channel_3_reg[0..3] ; Stuck at GND due to stuck port data_in ; ; pokey:\POKEY_ON:0:pokeyx|serial_op_needed_interrupt_delayed_reg[1] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|chan0_output_del_reg ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|chan1_output_del_reg ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|serial_out_reg ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|synchronizer:sio_clk1_synchronizer|ff_reg[1] ; Stuck at VCC due to stuck port data_in ; ; pokey:\POKEY_ON:0:pokeyx|synchronizer:sio_in1_synchronizer|ff_reg[1] ; Stuck at VCC due to stuck port data_in ; ; synchronizer:synchronizer_fancy_enable|ff_reg[1] ; Stuck at VCC due to stuck port data_in ; ; pokey:\POKEY_ON:1:pokeyx|synchronizer:sio_clk1_synchronizer|ff_reg[0] ; Stuck at VCC due to stuck port data_in ; ; pokey:\POKEY_ON:1:pokeyx|synchronizer:sio_in1_synchronizer|ff_reg[0] ; Stuck at VCC due to stuck port data_in ; ; pokey:\POKEY_ON:0:pokeyx|synchronizer:sio_clk1_synchronizer|ff_reg[0] ; Stuck at VCC due to stuck port data_in ; ; pokey:\POKEY_ON:0:pokeyx|synchronizer:sio_in1_synchronizer|ff_reg[0] ; Stuck at VCC due to stuck port data_in ; ; synchronizer:synchronizer_fancy_enable|ff_reg[0] ; Stuck at VCC due to stuck port data_in ; ; pokey:\POKEY_ON:1:pokeyx|synchronizer:sio_in2_synchronizer|ff_reg[2] ; Stuck at VCC due to stuck port data_in ; ; pokey:\POKEY_ON:0:pokeyx|synchronizer:sio_in2_synchronizer|ff_reg[2] ; Stuck at VCC due to stuck port data_in ; ; pokey:\POKEY_ON:1:pokeyx|synchronizer:sio_in2_synchronizer|ff_reg[1] ; Stuck at VCC due to stuck port data_in ; ; pokey:\POKEY_ON:0:pokeyx|synchronizer:sio_in2_synchronizer|ff_reg[1] ; Stuck at VCC due to stuck port data_in ; ; pokey:\POKEY_ON:1:pokeyx|synchronizer:sio_in2_synchronizer|ff_reg[0] ; Stuck at VCC due to stuck port data_in ; ; pokey:\POKEY_ON:0:pokeyx|synchronizer:sio_in2_synchronizer|ff_reg[0] ; Stuck at VCC due to stuck port data_in ; ; pokey:\POKEY_ON:1:pokeyx|irqen_reg[6,7] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|skctl_reg[0,1] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|highpass0_reg ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|highpass1_reg ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|chan0_output_reg ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|chan1_output_reg ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|serin_bitcount_reg[0..3] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|serout_shift_reg[1..9] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|serout_holding_full_reg ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|serout_active_reg ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|clock_reg ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|clock_sync_reg ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|serin_clock_reg ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|serin_clock_last_reg ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|serout_clock_reg ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|serout_clock_last_reg ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|sio_in_reg ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|noise_5_reg[0..2] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|noise_large_reg[0..2] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|serial_op_needed_interrupt_delayed_reg[0] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|serout_bitcount_reg[0..3] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|delay_line:serin_clock_delay|shift_reg[0..4] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|delay_line:serout_clock_delay|shift_reg[0,1] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|pokey_poly_4:poly_4_lfsr|shift_reg[0..3] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|pokey_poly_5:poly_5_lfsr|shift_reg[0..4] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[0..16] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|pokey_poly_17_9:poly_17_19_lfsr|cycle_delay_reg ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|pokey_poly_17_9:poly_17_19_lfsr|select_9_17_del_reg ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|syncreset_enable_divider:enable_15_div|count_reg[0..6] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|syncreset_enable_divider:enable_15_div|enabled_out_reg ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|syncreset_enable_divider:enable_64_div|count_reg[0..4] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|syncreset_enable_divider:enable_64_div|enabled_out_reg ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|pokey_noise_filter:pokey_noise_filter3|out_reg ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|pokey_noise_filter:pokey_noise_filter2|out_reg ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|pokey_noise_filter:pokey_noise_filter1|out_reg ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|pokey_noise_filter:pokey_noise_filter0|out_reg ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|latch_delay_line:stimer_delay|shift_reg[0..2] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|latch_delay_line:stimer_delay|data_in_reg ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|latch_delay_line:twotone_del|shift_reg[0,1] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|latch_delay_line:twotone_del|data_in_reg ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|pokey_countdown_timer:timer3|count_reg[0..7] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|pokey_countdown_timer:timer3|delay_line:underflow0_delay|shift_reg[0..2] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|pokey_countdown_timer:timer2|count_reg[0..7] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|pokey_countdown_timer:timer2|delay_line:underflow0_delay|shift_reg[0..2] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|pokey_countdown_timer:timer1|count_reg[0..7] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|pokey_countdown_timer:timer1|delay_line:underflow0_delay|shift_reg[0..2] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|pokey_countdown_timer:timer0|count_reg[0..7] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[0..2] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audctl_delay|shift_reg[0][7] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audctl_delay|shift_reg[0][6] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audctl_delay|shift_reg[0][5] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audctl_delay|shift_reg[0][4] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audctl_delay|shift_reg[0][3] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audctl_delay|shift_reg[0][2] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audctl_delay|shift_reg[0][1] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audctl_delay|shift_reg[0][0] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf3_delay|shift_reg[0][7] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf3_delay|shift_reg[0][6] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf3_delay|shift_reg[0][5] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf3_delay|shift_reg[0][4] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf3_delay|shift_reg[0][3] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf3_delay|shift_reg[0][2] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf3_delay|shift_reg[0][1] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf3_delay|shift_reg[0][0] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf2_delay|shift_reg[0][7] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf2_delay|shift_reg[0][6] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf2_delay|shift_reg[0][5] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf2_delay|shift_reg[0][4] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf2_delay|shift_reg[0][3] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf2_delay|shift_reg[0][2] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf2_delay|shift_reg[0][1] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf2_delay|shift_reg[0][0] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf1_delay|shift_reg[0][7] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf1_delay|shift_reg[0][6] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf1_delay|shift_reg[0][5] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf1_delay|shift_reg[0][4] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf1_delay|shift_reg[0][3] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf1_delay|shift_reg[0][2] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf1_delay|shift_reg[0][1] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf1_delay|shift_reg[0][0] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf0_delay|shift_reg[0][7] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf0_delay|shift_reg[0][6] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf0_delay|shift_reg[0][5] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf0_delay|shift_reg[0][4] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf0_delay|shift_reg[0][3] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf0_delay|shift_reg[0][2] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf0_delay|shift_reg[0][1] ; Lost fanout ; ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf0_delay|shift_reg[0][0] ; Lost fanout ; ; CHANNEL0SUM_REG[4,5] ; Stuck at GND due to stuck port data_in ; ; CHANNEL2SUM_REG[4,5] ; Stuck at GND due to stuck port data_in ; ; CHANNEL3SUM_REG[4,5] ; Stuck at GND due to stuck port data_in ; ; pokey_mixer_mux:pokey_mixer_both|CHANNEL_IN_0_REG[4,5] ; Stuck at GND due to stuck port data_in ; ; pokey_mixer_mux:pokey_mixer_both|CHANNEL_IN_2_REG[4,5] ; Stuck at GND due to stuck port data_in ; ; pokey_mixer_mux:pokey_mixer_both|CHANNEL_IN_3_REG[4,5] ; Stuck at GND due to stuck port data_in ; ; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|flash_page_addr[21,22] ; Stuck at GND due to stuck port data_in ; ; SID_top:sid2|SID_filter:variable_state_filter|mult1_reg[49,50] ; Merged with SID_top:sid2|SID_filter:variable_state_filter|mult1_reg[51] ; ; SID_top:sid2|SID_filter:variable_state_filter|mult2_reg[49,50] ; Merged with SID_top:sid2|SID_filter:variable_state_filter|mult2_reg[51] ; ; SID_top:sid1|SID_filter:variable_state_filter|mult1_reg[49,50] ; Merged with SID_top:sid1|SID_filter:variable_state_filter|mult1_reg[51] ; ; SID_top:sid1|SID_filter:variable_state_filter|mult2_reg[49,50] ; Merged with SID_top:sid1|SID_filter:variable_state_filter|mult2_reg[51] ; ; pokey:\POKEY_ON:1:pokeyx|allpot_reg[0..6] ; Merged with pokey:\POKEY_ON:1:pokeyx|allpot_reg[7] ; ; pokey:\POKEY_ON:1:pokeyx|pokey_poly_17_9:poly_17_19_lfsr|cycle_delay_reg ; Merged with pokey:\POKEY_ON:1:pokeyx|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[8] ; ; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|reset_n_reg2 ; Merged with flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|reset_n_reg2 ; ; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|reset_n_reg1 ; Merged with flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|reset_n_reg1 ; ; SID_top:sid2|potcount_reg[8] ; Merged with SID_top:sid1|potcount_reg[8] ; ; SID_top:sid2|potcount_reg[7] ; Merged with SID_top:sid1|potcount_reg[7] ; ; SID_top:sid2|potcount_reg[6] ; Merged with SID_top:sid1|potcount_reg[6] ; ; SID_top:sid2|potcount_reg[5] ; Merged with SID_top:sid1|potcount_reg[5] ; ; SID_top:sid2|potcount_reg[4] ; Merged with SID_top:sid1|potcount_reg[4] ; ; SID_top:sid2|potcount_reg[3] ; Merged with SID_top:sid1|potcount_reg[3] ; ; SID_top:sid2|potcount_reg[2] ; Merged with SID_top:sid1|potcount_reg[2] ; ; SID_top:sid2|potcount_reg[1] ; Merged with SID_top:sid1|potcount_reg[1] ; ; SID_top:sid2|potcount_reg[0] ; Merged with SID_top:sid1|potcount_reg[0] ; ; PSG_top:\psg_on:PSG_2|PSG_freqdiv:core_ticker|count_reg[3] ; Merged with PSG_top:\psg_on:PSG_1|PSG_freqdiv:core_ticker|count_reg[3] ; ; PSG_top:\psg_on:PSG_2|PSG_freqdiv:core_ticker|count_reg[2] ; Merged with PSG_top:\psg_on:PSG_1|PSG_freqdiv:core_ticker|count_reg[2] ; ; PSG_top:\psg_on:PSG_2|PSG_freqdiv:core_ticker|count_reg[1] ; Merged with PSG_top:\psg_on:PSG_1|PSG_freqdiv:core_ticker|count_reg[1] ; ; PSG_top:\psg_on:PSG_2|PSG_freqdiv:core_ticker|count_reg[0] ; Merged with PSG_top:\psg_on:PSG_1|PSG_freqdiv:core_ticker|count_reg[0] ; ; pokey:\POKEY_ON:1:pokeyx|pot1_reg[0] ; Merged with pokey:\POKEY_ON:1:pokeyx|pot0_reg[0] ; ; pokey:\POKEY_ON:1:pokeyx|pot2_reg[0] ; Merged with pokey:\POKEY_ON:1:pokeyx|pot0_reg[0] ; ; pokey:\POKEY_ON:1:pokeyx|pot3_reg[0] ; Merged with pokey:\POKEY_ON:1:pokeyx|pot0_reg[0] ; ; pokey:\POKEY_ON:1:pokeyx|pot4_reg[0] ; Merged with pokey:\POKEY_ON:1:pokeyx|pot0_reg[0] ; ; pokey:\POKEY_ON:1:pokeyx|pot5_reg[0] ; Merged with pokey:\POKEY_ON:1:pokeyx|pot0_reg[0] ; ; pokey:\POKEY_ON:1:pokeyx|pot6_reg[0] ; Merged with pokey:\POKEY_ON:1:pokeyx|pot0_reg[0] ; ; pokey:\POKEY_ON:1:pokeyx|pot7_reg[0] ; Merged with pokey:\POKEY_ON:1:pokeyx|pot0_reg[0] ; ; SID_top:sid2|potx_reg[0] ; Merged with SID_top:sid1|potx_reg[0] ; ; SID_top:sid2|poty_reg[0] ; Merged with SID_top:sid1|poty_reg[0] ; ; pokey:\POKEY_ON:1:pokeyx|pot1_reg[1] ; Merged with pokey:\POKEY_ON:1:pokeyx|pot0_reg[1] ; ; pokey:\POKEY_ON:1:pokeyx|pot2_reg[1] ; Merged with pokey:\POKEY_ON:1:pokeyx|pot0_reg[1] ; ; pokey:\POKEY_ON:1:pokeyx|pot3_reg[1] ; Merged with pokey:\POKEY_ON:1:pokeyx|pot0_reg[1] ; ; pokey:\POKEY_ON:1:pokeyx|pot4_reg[1] ; Merged with pokey:\POKEY_ON:1:pokeyx|pot0_reg[1] ; ; pokey:\POKEY_ON:1:pokeyx|pot5_reg[1] ; Merged with pokey:\POKEY_ON:1:pokeyx|pot0_reg[1] ; ; pokey:\POKEY_ON:1:pokeyx|pot6_reg[1] ; Merged with pokey:\POKEY_ON:1:pokeyx|pot0_reg[1] ; ; pokey:\POKEY_ON:1:pokeyx|pot7_reg[1] ; Merged with pokey:\POKEY_ON:1:pokeyx|pot0_reg[1] ; ; SID_top:sid2|potx_reg[1] ; Merged with SID_top:sid1|potx_reg[1] ; ; SID_top:sid2|poty_reg[1] ; Merged with SID_top:sid1|poty_reg[1] ; ; pokey:\POKEY_ON:1:pokeyx|pot1_reg[2] ; Merged with pokey:\POKEY_ON:1:pokeyx|pot0_reg[2] ; ; pokey:\POKEY_ON:1:pokeyx|pot2_reg[2] ; Merged with pokey:\POKEY_ON:1:pokeyx|pot0_reg[2] ; ; pokey:\POKEY_ON:1:pokeyx|pot3_reg[2] ; Merged with pokey:\POKEY_ON:1:pokeyx|pot0_reg[2] ; ; pokey:\POKEY_ON:1:pokeyx|pot4_reg[2] ; Merged with pokey:\POKEY_ON:1:pokeyx|pot0_reg[2] ; ; pokey:\POKEY_ON:1:pokeyx|pot5_reg[2] ; Merged with pokey:\POKEY_ON:1:pokeyx|pot0_reg[2] ; ; pokey:\POKEY_ON:1:pokeyx|pot6_reg[2] ; Merged with pokey:\POKEY_ON:1:pokeyx|pot0_reg[2] ; ; pokey:\POKEY_ON:1:pokeyx|pot7_reg[2] ; Merged with pokey:\POKEY_ON:1:pokeyx|pot0_reg[2] ; ; SID_top:sid2|potx_reg[2] ; Merged with SID_top:sid1|potx_reg[2] ; ; SID_top:sid2|poty_reg[2] ; Merged with SID_top:sid1|poty_reg[2] ; ; pokey:\POKEY_ON:1:pokeyx|pot1_reg[3] ; Merged with pokey:\POKEY_ON:1:pokeyx|pot0_reg[3] ; ; pokey:\POKEY_ON:1:pokeyx|pot2_reg[3] ; Merged with pokey:\POKEY_ON:1:pokeyx|pot0_reg[3] ; ; pokey:\POKEY_ON:1:pokeyx|pot3_reg[3] ; Merged with pokey:\POKEY_ON:1:pokeyx|pot0_reg[3] ; ; pokey:\POKEY_ON:1:pokeyx|pot4_reg[3] ; Merged with pokey:\POKEY_ON:1:pokeyx|pot0_reg[3] ; ; pokey:\POKEY_ON:1:pokeyx|pot5_reg[3] ; Merged with pokey:\POKEY_ON:1:pokeyx|pot0_reg[3] ; ; pokey:\POKEY_ON:1:pokeyx|pot6_reg[3] ; Merged with pokey:\POKEY_ON:1:pokeyx|pot0_reg[3] ; ; pokey:\POKEY_ON:1:pokeyx|pot7_reg[3] ; Merged with pokey:\POKEY_ON:1:pokeyx|pot0_reg[3] ; ; SID_top:sid2|potx_reg[3] ; Merged with SID_top:sid1|potx_reg[3] ; ; SID_top:sid2|poty_reg[3] ; Merged with SID_top:sid1|poty_reg[3] ; ; pokey:\POKEY_ON:1:pokeyx|pot1_reg[4] ; Merged with pokey:\POKEY_ON:1:pokeyx|pot0_reg[4] ; ; pokey:\POKEY_ON:1:pokeyx|pot2_reg[4] ; Merged with pokey:\POKEY_ON:1:pokeyx|pot0_reg[4] ; ; pokey:\POKEY_ON:1:pokeyx|pot3_reg[4] ; Merged with pokey:\POKEY_ON:1:pokeyx|pot0_reg[4] ; ; pokey:\POKEY_ON:1:pokeyx|pot4_reg[4] ; Merged with pokey:\POKEY_ON:1:pokeyx|pot0_reg[4] ; ; pokey:\POKEY_ON:1:pokeyx|pot5_reg[4] ; Merged with pokey:\POKEY_ON:1:pokeyx|pot0_reg[4] ; ; pokey:\POKEY_ON:1:pokeyx|pot6_reg[4] ; Merged with pokey:\POKEY_ON:1:pokeyx|pot0_reg[4] ; ; pokey:\POKEY_ON:1:pokeyx|pot7_reg[4] ; Merged with pokey:\POKEY_ON:1:pokeyx|pot0_reg[4] ; ; SID_top:sid2|potx_reg[4] ; Merged with SID_top:sid1|potx_reg[4] ; ; SID_top:sid2|poty_reg[4] ; Merged with SID_top:sid1|poty_reg[4] ; ; pokey:\POKEY_ON:1:pokeyx|pot1_reg[5] ; Merged with pokey:\POKEY_ON:1:pokeyx|pot0_reg[5] ; ; pokey:\POKEY_ON:1:pokeyx|pot2_reg[5] ; Merged with pokey:\POKEY_ON:1:pokeyx|pot0_reg[5] ; ; pokey:\POKEY_ON:1:pokeyx|pot3_reg[5] ; Merged with pokey:\POKEY_ON:1:pokeyx|pot0_reg[5] ; ; pokey:\POKEY_ON:1:pokeyx|pot4_reg[5] ; Merged with pokey:\POKEY_ON:1:pokeyx|pot0_reg[5] ; ; pokey:\POKEY_ON:1:pokeyx|pot5_reg[5] ; Merged with pokey:\POKEY_ON:1:pokeyx|pot0_reg[5] ; ; pokey:\POKEY_ON:1:pokeyx|pot6_reg[5] ; Merged with pokey:\POKEY_ON:1:pokeyx|pot0_reg[5] ; ; pokey:\POKEY_ON:1:pokeyx|pot7_reg[5] ; Merged with pokey:\POKEY_ON:1:pokeyx|pot0_reg[5] ; ; SID_top:sid2|potx_reg[5] ; Merged with SID_top:sid1|potx_reg[5] ; ; SID_top:sid2|poty_reg[5] ; Merged with SID_top:sid1|poty_reg[5] ; ; pokey:\POKEY_ON:1:pokeyx|pot1_reg[6] ; Merged with pokey:\POKEY_ON:1:pokeyx|pot0_reg[6] ; ; pokey:\POKEY_ON:1:pokeyx|pot2_reg[6] ; Merged with pokey:\POKEY_ON:1:pokeyx|pot0_reg[6] ; ; pokey:\POKEY_ON:1:pokeyx|pot3_reg[6] ; Merged with pokey:\POKEY_ON:1:pokeyx|pot0_reg[6] ; ; pokey:\POKEY_ON:1:pokeyx|pot4_reg[6] ; Merged with pokey:\POKEY_ON:1:pokeyx|pot0_reg[6] ; ; pokey:\POKEY_ON:1:pokeyx|pot5_reg[6] ; Merged with pokey:\POKEY_ON:1:pokeyx|pot0_reg[6] ; ; pokey:\POKEY_ON:1:pokeyx|pot6_reg[6] ; Merged with pokey:\POKEY_ON:1:pokeyx|pot0_reg[6] ; ; pokey:\POKEY_ON:1:pokeyx|pot7_reg[6] ; Merged with pokey:\POKEY_ON:1:pokeyx|pot0_reg[6] ; ; SID_top:sid2|potx_reg[6] ; Merged with SID_top:sid1|potx_reg[6] ; ; SID_top:sid2|poty_reg[6] ; Merged with SID_top:sid1|poty_reg[6] ; ; pokey:\POKEY_ON:1:pokeyx|pot1_reg[7] ; Merged with pokey:\POKEY_ON:1:pokeyx|pot0_reg[7] ; ; pokey:\POKEY_ON:1:pokeyx|pot2_reg[7] ; Merged with pokey:\POKEY_ON:1:pokeyx|pot0_reg[7] ; ; pokey:\POKEY_ON:1:pokeyx|pot3_reg[7] ; Merged with pokey:\POKEY_ON:1:pokeyx|pot0_reg[7] ; ; pokey:\POKEY_ON:1:pokeyx|pot4_reg[7] ; Merged with pokey:\POKEY_ON:1:pokeyx|pot0_reg[7] ; ; pokey:\POKEY_ON:1:pokeyx|pot5_reg[7] ; Merged with pokey:\POKEY_ON:1:pokeyx|pot0_reg[7] ; ; pokey:\POKEY_ON:1:pokeyx|pot6_reg[7] ; Merged with pokey:\POKEY_ON:1:pokeyx|pot0_reg[7] ; ; pokey:\POKEY_ON:1:pokeyx|pot7_reg[7] ; Merged with pokey:\POKEY_ON:1:pokeyx|pot0_reg[7] ; ; SID_top:sid2|potx_reg[7] ; Merged with SID_top:sid1|potx_reg[7] ; ; SID_top:sid2|poty_reg[7] ; Merged with SID_top:sid1|poty_reg[7] ; ; PSG_top:\psg_on:PSG_2|PSG_freqdiv:noise_preticker|count_reg[1] ; Merged with PSG_top:\psg_on:PSG_1|PSG_freqdiv:noise_preticker|count_reg[1] ; ; PSG_top:\psg_on:PSG_2|PSG_freqdiv:noise_preticker|count_reg[0] ; Merged with PSG_top:\psg_on:PSG_1|PSG_freqdiv:noise_preticker|count_reg[0] ; ; SID_top:sid2|potread_x_reg ; Merged with SID_top:sid1|potread_x_reg ; ; SID_top:sid2|potread_y_reg ; Merged with SID_top:sid1|potread_y_reg ; ; SID_top:sid2|SID_envelope_tapmatch:envelope_tapmatcher|state_reg[1] ; Merged with SID_top:sid1|SID_envelope_tapmatch:envelope_tapmatcher|state_reg[1] ; ; SID_top:sid2|SID_preFilterSum:prefilter|phase_reg[2] ; Merged with SID_top:sid1|SID_preFilterSum:prefilter|phase_reg[2] ; ; SID_top:sid2|SID_preFilterSum:prefilter|phase_reg[1] ; Merged with SID_top:sid1|SID_preFilterSum:prefilter|phase_reg[1] ; ; SID_top:sid2|SID_preFilterSum:prefilter|phase_reg[0] ; Merged with SID_top:sid1|SID_preFilterSum:prefilter|phase_reg[0] ; ; SID_top:sid2|SID_envelope_tapmatch:envelope_tapmatcher|state_reg[0] ; Merged with SID_top:sid1|SID_envelope_tapmatch:envelope_tapmatcher|state_reg[0] ; ; pokey:\POKEY_ON:0:pokeyx|irq_n_reg ; Stuck at VCC due to stuck port data_in ; ; lvds_rx:lvds_rx0|altera_soft_lvds_rx_uCmNW05P:lvds_rx_inst|ff_dffe[0] ; Stuck at GND due to stuck port clock ; ; sigma_delta_adc:sdelta|adc_fb_pin ; Stuck at GND due to stuck port clock ; ; PSG_top:\psg_on:PSG_1|PSG_freqdiv:noise_preticker|count_reg[1] ; Stuck at GND due to stuck port data_in ; ; PSG_top:\psg_on:PSG_1|PSG_freqdiv:core_ticker|count_reg[3] ; Stuck at GND due to stuck port data_in ; ; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|avmm_burstcount_input_reg[1] ; Stuck at GND due to stuck port data_in ; ; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|read_count[2] ; Stuck at GND due to stuck port data_in ; ; SID_f_distortion_mux:f_distortion_mux|state_reg[0] ; Merged with SID_top:sid1|SID_preFilterSum:prefilter|phase_reg[0] ; ; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|read_state~5 ; Lost fanout ; ; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|read_state~6 ; Lost fanout ; ; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|erase_state~6 ; Lost fanout ; ; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|erase_state~7 ; Lost fanout ; ; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|erase_state~8 ; Lost fanout ; ; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|write_state~5 ; Lost fanout ; ; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|write_state~6 ; Lost fanout ; ; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|write_state~7 ; Lost fanout ; ; SID_f_distortion_mux:f_distortion_mux|state_reg[1] ; Merged with SID_top:sid1|SID_preFilterSum:prefilter|phase_reg[1] ; ; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|read_count[1] ; Stuck at GND due to stuck port data_in ; ; Total Number of Removed Registers = 480 ; ; +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Removed Registers Triggering Further Register Optimizations ; +------------------------------------------------------------------------+--------------------------------+------------------------------------------------------------------------------------------------+ ; Register name ; Reason for Removal ; Registers Removed due to This Register ; +------------------------------------------------------------------------+--------------------------------+------------------------------------------------------------------------------------------------+ ; pokey:\POKEY_ON:0:pokeyx|skctl_reg[4] ; Stuck at GND ; pokey:\POKEY_ON:0:pokeyx|skctl_reg[0], pokey:\POKEY_ON:0:pokeyx|chan0_output_reg, ; ; ; due to stuck port clock_enable ; pokey:\POKEY_ON:0:pokeyx|chan1_output_reg, ; ; ; ; pokey:\POKEY_ON:0:pokeyx|delay_line:serin_clock_delay|shift_reg[0], ; ; ; ; pokey:\POKEY_ON:0:pokeyx|pokey_noise_filter:pokey_noise_filter1|out_reg, ; ; ; ; pokey:\POKEY_ON:0:pokeyx|pokey_noise_filter:pokey_noise_filter0|out_reg, ; ; ; ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audctl_delay|shift_reg[0][3], ; ; ; ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audctl_delay|shift_reg[0][2], ; ; ; ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audctl_delay|shift_reg[0][1], ; ; ; ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf3_delay|shift_reg[0][7], ; ; ; ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf3_delay|shift_reg[0][6], ; ; ; ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf3_delay|shift_reg[0][5], ; ; ; ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf3_delay|shift_reg[0][4], ; ; ; ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf3_delay|shift_reg[0][3], ; ; ; ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf3_delay|shift_reg[0][2], ; ; ; ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf3_delay|shift_reg[0][1], ; ; ; ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf3_delay|shift_reg[0][0], ; ; ; ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf2_delay|shift_reg[0][7], ; ; ; ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf2_delay|shift_reg[0][6], ; ; ; ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf2_delay|shift_reg[0][5], ; ; ; ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf2_delay|shift_reg[0][4], ; ; ; ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf2_delay|shift_reg[0][3], ; ; ; ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf2_delay|shift_reg[0][2], ; ; ; ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf2_delay|shift_reg[0][1], ; ; ; ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf2_delay|shift_reg[0][0] ; ; pokey:\POKEY_ON:0:pokeyx|serout_holding_reg[7] ; Stuck at GND ; pokey:\POKEY_ON:0:pokeyx|serout_shift_reg[9], ; ; ; due to stuck port clock_enable ; pokey:\POKEY_ON:0:pokeyx|serout_holding_full_reg, ; ; ; ; pokey:\POKEY_ON:0:pokeyx|serout_clock_reg, ; ; ; ; pokey:\POKEY_ON:0:pokeyx|serout_clock_last_reg, ; ; ; ; pokey:\POKEY_ON:0:pokeyx|serout_bitcount_reg[3], ; ; ; ; pokey:\POKEY_ON:0:pokeyx|serout_bitcount_reg[2], ; ; ; ; pokey:\POKEY_ON:0:pokeyx|serout_bitcount_reg[1], ; ; ; ; pokey:\POKEY_ON:0:pokeyx|serout_bitcount_reg[0], ; ; ; ; pokey:\POKEY_ON:0:pokeyx|delay_line:serout_clock_delay|shift_reg[0] ; ; pokey:\POKEY_ON:0:pokeyx|audc2_reg[7] ; Stuck at GND ; pokey:\POKEY_ON:0:pokeyx|noise_4_reg[1], ; ; ; due to stuck port clock_enable ; pokey:\POKEY_ON:0:pokeyx|serin_bitcount_reg[3], ; ; ; ; pokey:\POKEY_ON:0:pokeyx|serin_bitcount_reg[2], ; ; ; ; pokey:\POKEY_ON:0:pokeyx|serin_bitcount_reg[1], ; ; ; ; pokey:\POKEY_ON:0:pokeyx|serin_bitcount_reg[0], ; ; ; ; pokey:\POKEY_ON:0:pokeyx|sio_in_reg, pokey:\POKEY_ON:0:pokeyx|noise_5_reg[1], ; ; ; ; pokey:\POKEY_ON:0:pokeyx|noise_large_reg[1], ; ; ; ; pokey:\POKEY_ON:0:pokeyx|pokey_countdown_timer:timer2|delay_line:underflow0_delay|shift_reg[0] ; ; pokey:\POKEY_ON:0:pokeyx|audc3_reg[4] ; Stuck at GND ; pokey:\POKEY_ON:0:pokeyx|chan3_output_reg, ; ; ; due to stuck port clock_enable ; pokey:\POKEY_ON:0:pokeyx|volume_channel_3_reg[3], ; ; ; ; pokey:\POKEY_ON:0:pokeyx|volume_channel_3_reg[2], ; ; ; ; pokey:\POKEY_ON:0:pokeyx|volume_channel_3_reg[1], ; ; ; ; pokey:\POKEY_ON:0:pokeyx|volume_channel_3_reg[0], ; ; ; ; pokey:\POKEY_ON:0:pokeyx|pokey_noise_filter:pokey_noise_filter3|out_reg, ; ; ; ; CHANNEL3SUM_REG[5], CHANNEL3SUM_REG[4] ; ; pokey:\POKEY_ON:0:pokeyx|audc2_reg[4] ; Stuck at GND ; pokey:\POKEY_ON:0:pokeyx|chan2_output_reg, ; ; ; due to stuck port clock_enable ; pokey:\POKEY_ON:0:pokeyx|volume_channel_2_reg[3], ; ; ; ; pokey:\POKEY_ON:0:pokeyx|volume_channel_2_reg[2], ; ; ; ; pokey:\POKEY_ON:0:pokeyx|volume_channel_2_reg[1], ; ; ; ; pokey:\POKEY_ON:0:pokeyx|volume_channel_2_reg[0], ; ; ; ; pokey:\POKEY_ON:0:pokeyx|pokey_noise_filter:pokey_noise_filter2|out_reg, ; ; ; ; CHANNEL2SUM_REG[5], CHANNEL2SUM_REG[4] ; ; pokey:\POKEY_ON:0:pokeyx|audc0_reg[4] ; Stuck at GND ; pokey:\POKEY_ON:0:pokeyx|volume_channel_0_reg[3], ; ; ; due to stuck port clock_enable ; pokey:\POKEY_ON:0:pokeyx|volume_channel_0_reg[2], ; ; ; ; pokey:\POKEY_ON:0:pokeyx|volume_channel_0_reg[1], ; ; ; ; pokey:\POKEY_ON:0:pokeyx|volume_channel_0_reg[0], ; ; ; ; pokey:\POKEY_ON:0:pokeyx|chan0_output_del_reg, ; ; ; ; pokey:\POKEY_ON:0:pokeyx|highpass0_reg, CHANNEL0SUM_REG[5], CHANNEL0SUM_REG[4] ; ; pokey:\POKEY_ON:0:pokeyx|audc1_reg[4] ; Stuck at GND ; pokey:\POKEY_ON:0:pokeyx|volume_channel_1_reg[3], ; ; ; due to stuck port clock_enable ; pokey:\POKEY_ON:0:pokeyx|volume_channel_1_reg[2], ; ; ; ; pokey:\POKEY_ON:0:pokeyx|volume_channel_1_reg[1], ; ; ; ; pokey:\POKEY_ON:0:pokeyx|volume_channel_1_reg[0], ; ; ; ; pokey:\POKEY_ON:0:pokeyx|chan1_output_del_reg, ; ; ; ; pokey:\POKEY_ON:0:pokeyx|highpass1_reg ; ; pokey:\POKEY_ON:0:pokeyx|audc0_reg[7] ; Stuck at GND ; pokey:\POKEY_ON:0:pokeyx|pokey_poly_4:poly_4_lfsr|shift_reg[0], ; ; ; due to stuck port clock_enable ; pokey:\POKEY_ON:0:pokeyx|pokey_poly_5:poly_5_lfsr|shift_reg[0], ; ; ; ; pokey:\POKEY_ON:0:pokeyx|pokey_poly_17_9:poly_17_19_lfsr|cycle_delay_reg, ; ; ; ; pokey:\POKEY_ON:0:pokeyx|latch_delay_line:stimer_delay|shift_reg[0], ; ; ; ; pokey:\POKEY_ON:0:pokeyx|latch_delay_line:twotone_del|shift_reg[0], ; ; ; ; pokey:\POKEY_ON:0:pokeyx|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[0] ; ; pokey:\POKEY_ON:1:pokeyx|synchronizer:sio_in1_synchronizer|ff_reg[2] ; Stuck at VCC ; pokey:\POKEY_ON:1:pokeyx|synchronizer:sio_in1_synchronizer|ff_reg[1], ; ; ; due to stuck port data_in ; pokey:\POKEY_ON:1:pokeyx|synchronizer:sio_in1_synchronizer|ff_reg[0], ; ; ; ; pokey:\POKEY_ON:1:pokeyx|synchronizer:sio_in2_synchronizer|ff_reg[2], ; ; ; ; pokey:\POKEY_ON:1:pokeyx|synchronizer:sio_in2_synchronizer|ff_reg[1], ; ; ; ; pokey:\POKEY_ON:1:pokeyx|synchronizer:sio_in2_synchronizer|ff_reg[0] ; ; pokey:\POKEY_ON:0:pokeyx|synchronizer:sio_in1_synchronizer|ff_reg[2] ; Stuck at VCC ; pokey:\POKEY_ON:0:pokeyx|synchronizer:sio_in1_synchronizer|ff_reg[1], ; ; ; due to stuck port data_in ; pokey:\POKEY_ON:0:pokeyx|synchronizer:sio_in1_synchronizer|ff_reg[0], ; ; ; ; pokey:\POKEY_ON:0:pokeyx|synchronizer:sio_in2_synchronizer|ff_reg[2], ; ; ; ; pokey:\POKEY_ON:0:pokeyx|synchronizer:sio_in2_synchronizer|ff_reg[1], ; ; ; ; pokey:\POKEY_ON:0:pokeyx|synchronizer:sio_in2_synchronizer|ff_reg[0] ; ; pokey:\POKEY_ON:0:pokeyx|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[16] ; Lost Fanouts ; pokey:\POKEY_ON:0:pokeyx|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[13], ; ; ; ; pokey:\POKEY_ON:0:pokeyx|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[8], ; ; ; ; pokey:\POKEY_ON:0:pokeyx|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[0], ; ; ; ; pokey:\POKEY_ON:0:pokeyx|pokey_poly_17_9:poly_17_19_lfsr|select_9_17_del_reg, ; ; ; ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audctl_delay|shift_reg[0][7] ; ; pokey:\POKEY_ON:0:pokeyx|audc1_reg[7] ; Stuck at GND ; pokey:\POKEY_ON:0:pokeyx|noise_4_reg[0], pokey:\POKEY_ON:0:pokeyx|noise_5_reg[0], ; ; ; due to stuck port clock_enable ; pokey:\POKEY_ON:0:pokeyx|noise_large_reg[0], ; ; ; ; pokey:\POKEY_ON:0:pokeyx|pokey_countdown_timer:timer1|delay_line:underflow0_delay|shift_reg[0] ; ; pokey:\POKEY_ON:0:pokeyx|audc3_reg[7] ; Stuck at GND ; pokey:\POKEY_ON:0:pokeyx|noise_4_reg[2], pokey:\POKEY_ON:0:pokeyx|noise_5_reg[2], ; ; ; due to stuck port clock_enable ; pokey:\POKEY_ON:0:pokeyx|noise_large_reg[2], ; ; ; ; pokey:\POKEY_ON:0:pokeyx|pokey_countdown_timer:timer3|delay_line:underflow0_delay|shift_reg[0] ; ; pokey:\POKEY_ON:0:pokeyx|irqen_reg[5] ; Stuck at GND ; pokey:\POKEY_ON:0:pokeyx|irqst_reg[5], pokey:\POKEY_ON:0:pokeyx|serin_clock_reg, ; ; ; due to stuck port clock_enable ; pokey:\POKEY_ON:0:pokeyx|serin_clock_last_reg ; ; pokey:\POKEY_ON:0:pokeyx|irqen_reg[4] ; Stuck at GND ; pokey:\POKEY_ON:0:pokeyx|irqst_reg[4], ; ; ; due to stuck port clock_enable ; pokey:\POKEY_ON:0:pokeyx|serial_op_needed_interrupt_delayed_reg[1], ; ; ; ; pokey:\POKEY_ON:0:pokeyx|serial_op_needed_interrupt_delayed_reg[0] ; ; pokey:\POKEY_ON:0:pokeyx|irqen_reg[3] ; Stuck at GND ; pokey:\POKEY_ON:0:pokeyx|irqst_reg[3], pokey:\POKEY_ON:0:pokeyx|serout_active_reg, ; ; ; due to stuck port clock_enable ; pokey:\POKEY_ON:0:pokeyx|irq_n_reg ; ; pokey:\POKEY_ON:0:pokeyx|skctl_reg[6] ; Stuck at GND ; pokey:\POKEY_ON:0:pokeyx|skctl_reg[1], pokey:\POKEY_ON:0:pokeyx|clock_reg, ; ; ; due to stuck port clock_enable ; pokey:\POKEY_ON:0:pokeyx|clock_sync_reg ; ; pokey:\POKEY_ON:1:pokeyx|synchronizer:sio_clk1_synchronizer|ff_reg[2] ; Stuck at VCC ; pokey:\POKEY_ON:1:pokeyx|synchronizer:sio_clk1_synchronizer|ff_reg[1], ; ; ; due to stuck port data_in ; pokey:\POKEY_ON:1:pokeyx|synchronizer:sio_clk1_synchronizer|ff_reg[0] ; ; pokey:\POKEY_ON:0:pokeyx|synchronizer:sio_clk1_synchronizer|ff_reg[2] ; Stuck at VCC ; pokey:\POKEY_ON:0:pokeyx|synchronizer:sio_clk1_synchronizer|ff_reg[1], ; ; ; due to stuck port data_in ; pokey:\POKEY_ON:0:pokeyx|synchronizer:sio_clk1_synchronizer|ff_reg[0] ; ; synchronizer:synchronizer_fancy_enable|ff_reg[2] ; Stuck at VCC ; synchronizer:synchronizer_fancy_enable|ff_reg[1], ; ; ; due to stuck port data_in ; synchronizer:synchronizer_fancy_enable|ff_reg[0] ; ; pokey:\POKEY_ON:0:pokeyx|skctl_reg[7] ; Stuck at GND ; pokey:\POKEY_ON:0:pokeyx|serial_out_reg, ; ; ; due to stuck port clock_enable ; pokey:\POKEY_ON:0:pokeyx|serout_shift_reg[1] ; ; pokey:\POKEY_ON:0:pokeyx|pokey_countdown_timer:timer1|count_reg[4] ; Lost Fanouts ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf1_delay|shift_reg[0][4] ; ; pokey:\POKEY_ON:0:pokeyx|pokey_countdown_timer:timer1|count_reg[3] ; Lost Fanouts ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf1_delay|shift_reg[0][3] ; ; pokey:\POKEY_ON:0:pokeyx|pokey_countdown_timer:timer0|count_reg[5] ; Lost Fanouts ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf0_delay|shift_reg[0][5] ; ; pokey:\POKEY_ON:0:pokeyx|pokey_countdown_timer:timer1|count_reg[5] ; Lost Fanouts ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf1_delay|shift_reg[0][5] ; ; pokey:\POKEY_ON:0:pokeyx|pokey_countdown_timer:timer1|count_reg[6] ; Lost Fanouts ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf1_delay|shift_reg[0][6] ; ; pokey:\POKEY_ON:0:pokeyx|pokey_countdown_timer:timer1|count_reg[7] ; Lost Fanouts ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf1_delay|shift_reg[0][7] ; ; pokey:\POKEY_ON:0:pokeyx|pokey_countdown_timer:timer1|count_reg[0] ; Lost Fanouts ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf1_delay|shift_reg[0][0] ; ; pokey:\POKEY_ON:0:pokeyx|pokey_countdown_timer:timer1|count_reg[2] ; Lost Fanouts ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf1_delay|shift_reg[0][2] ; ; pokey:\POKEY_ON:0:pokeyx|pokey_countdown_timer:timer1|count_reg[1] ; Lost Fanouts ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf1_delay|shift_reg[0][1] ; ; pokey:\POKEY_ON:0:pokeyx|pokey_countdown_timer:timer0|count_reg[0] ; Lost Fanouts ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf0_delay|shift_reg[0][0] ; ; pokey:\POKEY_ON:0:pokeyx|pokey_countdown_timer:timer0|count_reg[7] ; Lost Fanouts ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf0_delay|shift_reg[0][7] ; ; pokey:\POKEY_ON:0:pokeyx|pokey_countdown_timer:timer0|count_reg[6] ; Lost Fanouts ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf0_delay|shift_reg[0][6] ; ; pokey:\POKEY_ON:0:pokeyx|serout_holding_reg[2] ; Stuck at GND ; pokey:\POKEY_ON:0:pokeyx|serout_shift_reg[4] ; ; ; due to stuck port clock_enable ; ; ; pokey:\POKEY_ON:0:pokeyx|pokey_countdown_timer:timer0|count_reg[4] ; Lost Fanouts ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf0_delay|shift_reg[0][4] ; ; pokey:\POKEY_ON:0:pokeyx|pokey_countdown_timer:timer0|count_reg[3] ; Lost Fanouts ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf0_delay|shift_reg[0][3] ; ; pokey:\POKEY_ON:0:pokeyx|pokey_countdown_timer:timer0|count_reg[2] ; Lost Fanouts ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf0_delay|shift_reg[0][2] ; ; pokey:\POKEY_ON:0:pokeyx|pokey_countdown_timer:timer0|count_reg[1] ; Lost Fanouts ; pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf0_delay|shift_reg[0][1] ; ; lvds_rx:lvds_rx0|altera_soft_lvds_rx_uCmNW05P:lvds_rx_inst|ff_dffe[0] ; Stuck at GND ; sigma_delta_adc:sdelta|adc_fb_pin ; ; ; due to stuck port clock ; ; ; pokey:\POKEY_ON:0:pokeyx|serout_holding_reg[4] ; Stuck at GND ; pokey:\POKEY_ON:0:pokeyx|serout_shift_reg[6] ; ; ; due to stuck port clock_enable ; ; ; pokey:\POKEY_ON:1:pokeyx|irqst_reg[6] ; Stuck at VCC ; pokey:\POKEY_ON:1:pokeyx|irqen_reg[6] ; ; ; due to stuck port data_in ; ; ; pokey:\POKEY_ON:0:pokeyx|irqen_reg[7] ; Stuck at GND ; pokey:\POKEY_ON:0:pokeyx|irqst_reg[7] ; ; ; due to stuck port clock_enable ; ; ; pokey:\POKEY_ON:0:pokeyx|irqen_reg[6] ; Stuck at GND ; pokey:\POKEY_ON:0:pokeyx|irqst_reg[6] ; ; ; due to stuck port clock_enable ; ; ; pokey:\POKEY_ON:0:pokeyx|irqen_reg[2] ; Stuck at GND ; pokey:\POKEY_ON:0:pokeyx|irqst_reg[2] ; ; ; due to stuck port clock_enable ; ; ; pokey:\POKEY_ON:0:pokeyx|irqen_reg[1] ; Stuck at GND ; pokey:\POKEY_ON:0:pokeyx|irqst_reg[1] ; ; ; due to stuck port clock_enable ; ; ; pokey:\POKEY_ON:0:pokeyx|irqen_reg[0] ; Stuck at GND ; pokey:\POKEY_ON:0:pokeyx|irqst_reg[0] ; ; ; due to stuck port clock_enable ; ; ; pokey:\POKEY_ON:0:pokeyx|serout_holding_reg[6] ; Stuck at GND ; pokey:\POKEY_ON:0:pokeyx|serout_shift_reg[8] ; ; ; due to stuck port clock_enable ; ; ; pokey:\POKEY_ON:0:pokeyx|serout_holding_reg[5] ; Stuck at GND ; pokey:\POKEY_ON:0:pokeyx|serout_shift_reg[7] ; ; ; due to stuck port clock_enable ; ; ; pokey:\POKEY_ON:0:pokeyx|latch_delay_line:twotone_del|shift_reg[1] ; Lost Fanouts ; pokey:\POKEY_ON:0:pokeyx|latch_delay_line:twotone_del|data_in_reg ; ; pokey:\POKEY_ON:0:pokeyx|serout_holding_reg[3] ; Stuck at GND ; pokey:\POKEY_ON:0:pokeyx|serout_shift_reg[5] ; ; ; due to stuck port clock_enable ; ; ; pokey:\POKEY_ON:1:pokeyx|irqst_reg[7] ; Stuck at VCC ; pokey:\POKEY_ON:1:pokeyx|irqen_reg[7] ; ; ; due to stuck port data_in ; ; ; pokey:\POKEY_ON:0:pokeyx|serout_holding_reg[1] ; Stuck at GND ; pokey:\POKEY_ON:0:pokeyx|serout_shift_reg[3] ; ; ; due to stuck port clock_enable ; ; ; pokey:\POKEY_ON:0:pokeyx|serout_holding_reg[0] ; Stuck at GND ; pokey:\POKEY_ON:0:pokeyx|serout_shift_reg[2] ; ; ; due to stuck port clock_enable ; ; ; pokey:\POKEY_ON:0:pokeyx|pokey_poly_4:poly_4_lfsr|shift_reg[3] ; Lost Fanouts ; pokey:\POKEY_ON:0:pokeyx|pokey_poly_4:poly_4_lfsr|shift_reg[1] ; ; pokey:\POKEY_ON:0:pokeyx|pokey_poly_5:poly_5_lfsr|shift_reg[4] ; Lost Fanouts ; pokey:\POKEY_ON:0:pokeyx|pokey_poly_5:poly_5_lfsr|shift_reg[2] ; ; pokey:\POKEY_ON:0:pokeyx|latch_delay_line:stimer_delay|shift_reg[2] ; Lost Fanouts ; pokey:\POKEY_ON:0:pokeyx|latch_delay_line:stimer_delay|data_in_reg ; +------------------------------------------------------------------------+--------------------------------+------------------------------------------------------------------------------------------------+ +------------------------------------------------------+ ; General Register Statistics ; +----------------------------------------------+-------+ ; Statistic ; Value ; +----------------------------------------------+-------+ ; Total registers ; 4787 ; ; Number of registers using Synchronous Clear ; 109 ; ; Number of registers using Synchronous Load ; 265 ; ; Number of registers using Asynchronous Clear ; 4456 ; ; Number of registers using Asynchronous Load ; 0 ; ; Number of registers using Clock Enable ; 3429 ; ; Number of registers using Preset ; 0 ; +----------------------------------------------+-------+ +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Inverted Register Statistics ; +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ ; Inverted Register ; Fan out ; +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ ; CHANNEL_EN_REG[0] ; 2 ; ; CHANNEL_EN_REG[2] ; 2 ; ; CHANNEL_EN_REG[3] ; 2 ; ; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|flash_drshft_neg_reg ; 1 ; ; sigmadelta_dither:dac_dithergen|lfsr_reg[5] ; 3 ; ; sigmadelta_dither:dac_dithergen|lfsr_reg[0] ; 3 ; ; RESTRICT_CAPABILITY_REG[1] ; 2 ; ; RESTRICT_CAPABILITY_REG[0] ; 3 ; ; RESTRICT_CAPABILITY_REG[4] ; 4 ; ; RESTRICT_CAPABILITY_REG[2] ; 2 ; ; RESTRICT_CAPABILITY_REG[3] ; 2 ; ; slave_timing_6502:bus_adapt|phi_rw_n_reg ; 12 ; ; slave_timing_6502:bus_adapt|phi_edge_prev_reg ; 4 ; ; sigmadelta_dither:dac_dithergen|lfsr_reg[11] ; 3 ; ; sigmadelta_dither:dac_dithergen|lfsr_reg[7] ; 2 ; ; sigmadelta_dither:dac_dithergen|lfsr_reg[10] ; 3 ; ; sigmadelta_dither:dac_dithergen|lfsr_reg[6] ; 2 ; ; sigmadelta_dither:dac_dithergen|lfsr_reg[15] ; 3 ; ; sigmadelta_dither:dac_dithergen|lfsr_reg[13] ; 3 ; ; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|flash_drshft_reg ; 2 ; ; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_sector_page_erase_addr_reg[20] ; 7 ; ; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_sector_page_erase_addr_reg[21] ; 6 ; ; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_sector_page_erase_addr_reg[22] ; 7 ; ; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_sector_page_erase_addr_reg[15] ; 2 ; ; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_sector_page_erase_addr_reg[12] ; 2 ; ; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_sector_page_erase_addr_reg[11] ; 2 ; ; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_sector_page_erase_addr_reg[10] ; 2 ; ; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_sector_page_erase_addr_reg[9] ; 2 ; ; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_sector_page_erase_addr_reg[13] ; 2 ; ; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_sector_page_erase_addr_reg[14] ; 2 ; ; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_sector_page_erase_addr_reg[16] ; 6 ; ; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_sector_page_erase_addr_reg[17] ; 6 ; ; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_sector_page_erase_addr_reg[19] ; 8 ; ; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_sector_page_erase_addr_reg[18] ; 8 ; ; flash_controller:\flash_on:flash_controller_inst|robin_reg[7] ; 4 ; ; PSG_volume_profile:\psg_on:vol_profile1|channelsel_reg[5] ; 9 ; ; PSG_STEREOMODE_REG[0] ; 4 ; ; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_wp_mode[1] ; 2 ; ; stereo_detect:\auto_stereo:a4|addr_bit_sync_reg ; 2 ; ; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_wp_mode[3] ; 2 ; ; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_wp_mode[4] ; 1 ; ; pokey:\POKEY_ON:1:pokeyx|irq_n_reg ; 1 ; ; SID_AUTO_REG ; 5 ; ; SID_FILTER2_REG[0] ; 3 ; ; SID_FILTER1_REG[0] ; 3 ; ; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_wp_mode[2] ; 2 ; ; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_wp_mode[0] ; 2 ; ; CPU_FLASH_WRITE_N_REG ; 3 ; ; PSG_top:\psg_on:PSG_1|PSG_volume:vol_a|changed_reg ; 1 ; ; PSG_top:\psg_on:PSG_1|PSG_volume:vol_b|changed_reg ; 1 ; ; PSG_top:\psg_on:PSG_1|PSG_volume:vol_c|changed_reg ; 1 ; ; PSG_top:\psg_on:PSG_2|PSG_volume:vol_a|changed_reg ; 1 ; ; PSG_top:\psg_on:PSG_2|PSG_volume:vol_b|changed_reg ; 1 ; ; PSG_top:\psg_on:PSG_2|PSG_volume:vol_c|changed_reg ; 1 ; ; pokey_mixer_mux:pokey_mixer_both|CHANNEL_DIRTY_REG[2] ; 3 ; ; pokey_mixer_mux:pokey_mixer_both|CHANNEL_DIRTY_REG[1] ; 4 ; ; pokey_mixer_mux:pokey_mixer_both|CHANNEL_DIRTY_REG[0] ; 3 ; ; pokey_mixer_mux:pokey_mixer_both|CHANNEL_DIRTY_REG[3] ; 4 ; ; SID_top:sid2|statevariable_f_dirty_reg ; 2 ; ; SID_top:sid2|statevariable_q_dirty_reg ; 3 ; ; SID_top:sid1|statevariable_f_dirty_reg ; 2 ; ; SID_top:sid1|statevariable_q_dirty_reg ; 3 ; ; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_sector_page_erase_addr_reg[0] ; 2 ; ; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_sector_page_erase_addr_reg[1] ; 2 ; ; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_sector_page_erase_addr_reg[2] ; 2 ; ; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_sector_page_erase_addr_reg[3] ; 2 ; ; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_sector_page_erase_addr_reg[4] ; 2 ; ; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_sector_page_erase_addr_reg[5] ; 2 ; ; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_sector_page_erase_addr_reg[6] ; 2 ; ; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_sector_page_erase_addr_reg[7] ; 2 ; ; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_sector_page_erase_addr_reg[8] ; 2 ; ; DETECT_RIGHT_REG ; 2 ; ; pokey:\POKEY_ON:1:pokeyx|irqst_reg[3] ; 2 ; ; pokey:\POKEY_ON:1:pokeyx|irqst_reg[5] ; 4 ; ; pokey:\POKEY_ON:1:pokeyx|irqst_reg[4] ; 3 ; ; pokey:\POKEY_ON:1:pokeyx|irqst_reg[2] ; 3 ; ; pokey:\POKEY_ON:1:pokeyx|irqst_reg[1] ; 3 ; ; pokey:\POKEY_ON:1:pokeyx|irqst_reg[0] ; 3 ; ; SATURATE_REG ; 2 ; ; POST_DIVIDE_REG[5] ; 3 ; ; POST_DIVIDE_REG[7] ; 2 ; ; pokey:\POKEY_ON:1:pokeyx|allpot_reg[7] ; 7 ; ; sample_top:\sample_on:sample1|bits8_reg[1] ; 3 ; ; sample_top:\sample_on:sample1|bits8_reg[2] ; 3 ; ; sample_top:\sample_on:sample1|bits8_reg[0] ; 3 ; ; sample_top:\sample_on:sample1|bits8_reg[3] ; 3 ; ; pokey:\POKEY_ON:1:pokeyx|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[9] ; 2 ; ; SID_EXT1_REG[1] ; 3 ; ; CHANNEL_EN_REG[1] ; 1 ; ; GTIA_ENABLE_REG[2] ; 1 ; ; GTIA_ENABLE_REG[3] ; 1 ; ; SID_EXT2_REG[1] ; 3 ; ; pokey:\POKEY_ON:1:pokeyx|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[11] ; 2 ; ; CHANNEL_EN_REG[4] ; 1 ; ; ADC_VOLUME_REG[0] ; 1 ; ; pokey:\POKEY_ON:1:pokeyx|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[13] ; 4 ; ; ADC_VOLUME_REG[1] ; 2 ; ; PAL_REG ; 7 ; ; pokey:\POKEY_ON:1:pokeyx|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[15] ; 2 ; ; SIO_DATA_VOLUME_REG[1] ; 1 ; ; Total number of inverted registers = 416* ; ; +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ * Table truncated at 100 items. To change the number of inverted registers reported, set the "Number of Inverted Registers Reported" option under Assignments->Settings->Analysis and Synthesis Settings->More Settings +------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Registers Packed Into Inferred Megafunctions ; +---------------------------------------------------------------------+-------------------------------------------------------------------------+------+ ; Register Name ; Megafunction ; Type ; +---------------------------------------------------------------------+-------------------------------------------------------------------------+------+ ; generic_ram_infer:\sample_on:normal_ram:sample_ram_inst|q_ram[0..7] ; generic_ram_infer:\sample_on:normal_ram:sample_ram_inst|ram_block_rtl_0 ; RAM ; +---------------------------------------------------------------------+-------------------------------------------------------------------------+------+ +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Multiplexer Restructuring Statistics (Restructuring Performed) ; +--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; +--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 3:1 ; 9 bits ; 18 LEs ; 18 LEs ; 0 LEs ; Yes ; |sidmax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|flash_page_addr[2] ; ; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |sidmax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|flash_addr_wire_neg_reg[21] ; ; 3:1 ; 20 bits ; 40 LEs ; 40 LEs ; 0 LEs ; Yes ; |sidmax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|flash_addr_wire_neg_reg[4] ; ; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |sidmax|PSG_PROFILESEL_REG[1] ; ; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |sidmax|IRQ_EN_REG ; ; 3:1 ; 39 bits ; 78 LEs ; 0 LEs ; 78 LEs ; Yes ; |sidmax|flash_controller:\flash_on:flash_controller_inst|request_di_reg[29] ; ; 3:1 ; 6 bits ; 12 LEs ; 6 LEs ; 6 LEs ; Yes ; |sidmax|SID_top:sid2|readcount_reg[6] ; ; 3:1 ; 10 bits ; 20 LEs ; 10 LEs ; 10 LEs ; Yes ; |sidmax|SID_top:sid2|readcount_reg[5] ; ; 3:1 ; 6 bits ; 12 LEs ; 6 LEs ; 6 LEs ; Yes ; |sidmax|SID_top:sid1|readcount_reg[8] ; ; 3:1 ; 10 bits ; 20 LEs ; 10 LEs ; 10 LEs ; Yes ; |sidmax|SID_top:sid1|readcount_reg[4] ; ; 3:1 ; 8 bits ; 16 LEs ; 0 LEs ; 16 LEs ; Yes ; |sidmax|slave_timing_6502:bus_adapt|phi_addr_reg[6] ; ; 3:1 ; 12 bits ; 24 LEs ; 0 LEs ; 24 LEs ; Yes ; |sidmax|SID_top:sid1|statevariable_F_reg[11] ; ; 3:1 ; 12 bits ; 24 LEs ; 0 LEs ; 24 LEs ; Yes ; |sidmax|SID_top:sid2|statevariable_F_reg[11] ; ; 3:1 ; 18 bits ; 36 LEs ; 18 LEs ; 18 LEs ; Yes ; |sidmax|PSG_volume_profile:\psg_on:vol_profile1|acc_reg[8] ; ; 3:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; Yes ; |sidmax|PSG_volume_profile:\psg_on:vol_profile1|channelsel_reg[2] ; ; 3:1 ; 8 bits ; 16 LEs ; 0 LEs ; 16 LEs ; Yes ; |sidmax|sample_top:\sample_on:sample1|ch0_len_reg[4] ; ; 3:1 ; 8 bits ; 16 LEs ; 0 LEs ; 16 LEs ; Yes ; |sidmax|sample_top:\sample_on:sample1|ch1_len_reg[3] ; ; 3:1 ; 8 bits ; 16 LEs ; 0 LEs ; 16 LEs ; Yes ; |sidmax|sample_top:\sample_on:sample1|ch2_len_reg[1] ; ; 3:1 ; 8 bits ; 16 LEs ; 0 LEs ; 16 LEs ; Yes ; |sidmax|sample_top:\sample_on:sample1|ch3_len_reg[2] ; ; 3:1 ; 12 bits ; 24 LEs ; 0 LEs ; 24 LEs ; Yes ; |sidmax|mixer:mixer1|RIGHT_SNAP_REG[13] ; ; 3:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; Yes ; |sidmax|PSG_top:\psg_on:PSG_1|PSG_envelope:envelope|envelope_reg[4] ; ; 3:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; Yes ; |sidmax|PSG_top:\psg_on:PSG_1|PSG_envelope:envelope|count_reg[4] ; ; 3:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; Yes ; |sidmax|PSG_top:\psg_on:PSG_2|PSG_envelope:envelope|envelope_reg[4] ; ; 3:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; Yes ; |sidmax|PSG_top:\psg_on:PSG_2|PSG_envelope:envelope|count_reg[4] ; ; 3:1 ; 24 bits ; 48 LEs ; 24 LEs ; 24 LEs ; Yes ; |sidmax|mixer:mixer1|RIGHT_PLAYING_COUNT_REG[23] ; ; 3:1 ; 8 bits ; 16 LEs ; 0 LEs ; 16 LEs ; Yes ; |sidmax|sample_top:\sample_on:sample1|ch0_start_addr_reg[15] ; ; 3:1 ; 8 bits ; 16 LEs ; 0 LEs ; 16 LEs ; Yes ; |sidmax|sample_top:\sample_on:sample1|ch1_start_addr_reg[14] ; ; 3:1 ; 8 bits ; 16 LEs ; 0 LEs ; 16 LEs ; Yes ; |sidmax|sample_top:\sample_on:sample1|ch2_start_addr_reg[8] ; ; 3:1 ; 8 bits ; 16 LEs ; 0 LEs ; 16 LEs ; Yes ; |sidmax|sample_top:\sample_on:sample1|ch3_start_addr_reg[11] ; ; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |sidmax|sample_top:\sample_on:sample1|ram_cpu_addr_reg[12] ; ; 3:1 ; 8 bits ; 16 LEs ; 0 LEs ; 16 LEs ; Yes ; |sidmax|sample_top:\sample_on:sample1|ch0_start_addr_reg[0] ; ; 3:1 ; 8 bits ; 16 LEs ; 0 LEs ; 16 LEs ; Yes ; |sidmax|sample_top:\sample_on:sample1|ch1_start_addr_reg[2] ; ; 3:1 ; 8 bits ; 16 LEs ; 0 LEs ; 16 LEs ; Yes ; |sidmax|sample_top:\sample_on:sample1|ch2_start_addr_reg[7] ; ; 3:1 ; 8 bits ; 16 LEs ; 0 LEs ; 16 LEs ; Yes ; |sidmax|sample_top:\sample_on:sample1|ch3_start_addr_reg[2] ; ; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |sidmax|sample_top:\sample_on:sample1|ram_cpu_addr_reg[5] ; ; 3:1 ; 8 bits ; 16 LEs ; 0 LEs ; 16 LEs ; Yes ; |sidmax|sample_top:\sample_on:sample1|ch0_len_reg[8] ; ; 3:1 ; 8 bits ; 16 LEs ; 0 LEs ; 16 LEs ; Yes ; |sidmax|sample_top:\sample_on:sample1|ch1_len_reg[10] ; ; 3:1 ; 8 bits ; 16 LEs ; 0 LEs ; 16 LEs ; Yes ; |sidmax|sample_top:\sample_on:sample1|ch2_len_reg[13] ; ; 3:1 ; 8 bits ; 16 LEs ; 0 LEs ; 16 LEs ; Yes ; |sidmax|sample_top:\sample_on:sample1|ch3_len_reg[9] ; ; 3:1 ; 4 bits ; 8 LEs ; 0 LEs ; 8 LEs ; Yes ; |sidmax|sample_top:\sample_on:sample1|ch0_period_reg[9] ; ; 3:1 ; 4 bits ; 8 LEs ; 0 LEs ; 8 LEs ; Yes ; |sidmax|sample_top:\sample_on:sample1|ch1_period_reg[10] ; ; 3:1 ; 4 bits ; 8 LEs ; 0 LEs ; 8 LEs ; Yes ; |sidmax|sample_top:\sample_on:sample1|ch2_period_reg[8] ; ; 3:1 ; 4 bits ; 8 LEs ; 0 LEs ; 8 LEs ; Yes ; |sidmax|sample_top:\sample_on:sample1|ch3_period_reg[8] ; ; 3:1 ; 8 bits ; 16 LEs ; 0 LEs ; 16 LEs ; Yes ; |sidmax|sample_top:\sample_on:sample1|ch0_period_reg[0] ; ; 3:1 ; 8 bits ; 16 LEs ; 0 LEs ; 16 LEs ; Yes ; |sidmax|sample_top:\sample_on:sample1|ch1_period_reg[7] ; ; 3:1 ; 8 bits ; 16 LEs ; 0 LEs ; 16 LEs ; Yes ; |sidmax|sample_top:\sample_on:sample1|ch2_period_reg[1] ; ; 3:1 ; 8 bits ; 16 LEs ; 0 LEs ; 16 LEs ; Yes ; |sidmax|sample_top:\sample_on:sample1|ch3_period_reg[2] ; ; 3:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |sidmax|pokey:\POKEY_ON:1:pokeyx|pokey_countdown_timer:timer3|delay_line:underflow0_delay|shift_reg[2] ; ; 3:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |sidmax|pokey:\POKEY_ON:1:pokeyx|pokey_countdown_timer:timer2|delay_line:underflow0_delay|shift_reg[1] ; ; 3:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |sidmax|pokey:\POKEY_ON:1:pokeyx|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[1] ; ; 3:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |sidmax|pokey:\POKEY_ON:1:pokeyx|pokey_countdown_timer:timer1|delay_line:underflow0_delay|shift_reg[0] ; ; 3:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; Yes ; |sidmax|pokey:\POKEY_ON:1:pokeyx|delay_line:serin_clock_delay|shift_reg[3] ; ; 3:1 ; 20 bits ; 40 LEs ; 0 LEs ; 40 LEs ; Yes ; |sidmax|mixer:mixer1|dc_reg[0][14] ; ; 3:1 ; 20 bits ; 40 LEs ; 0 LEs ; 40 LEs ; Yes ; |sidmax|mixer:mixer1|dc_reg[1][2] ; ; 3:1 ; 20 bits ; 40 LEs ; 0 LEs ; 40 LEs ; Yes ; |sidmax|mixer:mixer1|dc_reg[2][13] ; ; 3:1 ; 20 bits ; 40 LEs ; 0 LEs ; 40 LEs ; Yes ; |sidmax|mixer:mixer1|dc_reg[3][15] ; ; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |sidmax|pokey:\POKEY_ON:1:pokeyx|pot_counter_reg[2] ; ; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |sidmax|pokey:\POKEY_ON:1:pokeyx|serin_shift_reg[8] ; ; 4:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |sidmax|SID_top:sid2|SID_envelope:envelope_c|adrmux_reg[1] ; ; 4:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |sidmax|SID_top:sid1|SID_envelope:envelope_c|adrmux_reg[1] ; ; 4:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |sidmax|pokey:\POKEY_ON:1:pokeyx|pokey_countdown_timer:timer3|count_reg[3] ; ; 4:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |sidmax|pokey:\POKEY_ON:1:pokeyx|pokey_countdown_timer:timer2|count_reg[1] ; ; 4:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |sidmax|pokey:\POKEY_ON:1:pokeyx|pokey_countdown_timer:timer0|count_reg[7] ; ; 4:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |sidmax|pokey:\POKEY_ON:1:pokeyx|pokey_countdown_timer:timer1|count_reg[7] ; ; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |sidmax|SID_top:sid2|SID_envelope:envelope_a|tapkey_reg[3] ; ; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |sidmax|SID_top:sid2|SID_envelope:envelope_b|tapkey_reg[2] ; ; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |sidmax|SID_top:sid2|SID_envelope:envelope_c|tapkey_reg[1] ; ; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |sidmax|SID_top:sid1|SID_envelope:envelope_a|tapkey_reg[0] ; ; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |sidmax|SID_top:sid1|SID_envelope:envelope_b|tapkey_reg[0] ; ; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |sidmax|SID_top:sid1|SID_envelope:envelope_c|tapkey_reg[1] ; ; 4:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |sidmax|SID_top:sid1|SID_envelope:envelope_a|adrmux_reg[0] ; ; 4:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |sidmax|SID_top:sid1|SID_envelope:envelope_b|adrmux_reg[0] ; ; 4:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |sidmax|SID_top:sid2|SID_envelope:envelope_a|adrmux_reg[0] ; ; 4:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |sidmax|SID_top:sid2|SID_envelope:envelope_b|adrmux_reg[0] ; ; 4:1 ; 10 bits ; 20 LEs ; 20 LEs ; 0 LEs ; Yes ; |sidmax|SID_f_distortion_mux:f_distortion_mux|SID_f_distortion:f_distortion|STATE_reg[14] ; ; 3:1 ; 20 bits ; 40 LEs ; 20 LEs ; 20 LEs ; Yes ; |sidmax|mixer:mixer1|acc_reg[3] ; ; 3:1 ; 16 bits ; 32 LEs ; 16 LEs ; 16 LEs ; Yes ; |sidmax|sample_top:\sample_on:sample1|sample_channel:ch0_inst|remaining_reg[4] ; ; 3:1 ; 16 bits ; 32 LEs ; 16 LEs ; 16 LEs ; Yes ; |sidmax|sample_top:\sample_on:sample1|sample_channel:ch1_inst|remaining_reg[0] ; ; 3:1 ; 16 bits ; 32 LEs ; 16 LEs ; 16 LEs ; Yes ; |sidmax|sample_top:\sample_on:sample1|sample_channel:ch2_inst|remaining_reg[7] ; ; 3:1 ; 16 bits ; 32 LEs ; 16 LEs ; 16 LEs ; Yes ; |sidmax|sample_top:\sample_on:sample1|sample_channel:ch3_inst|remaining_reg[6] ; ; 4:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |sidmax|clockgensid:clockgen1|cycle_count_reg[2] ; ; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |sidmax|CPU_FLASH_DATA_REG[22] ; ; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |sidmax|CPU_FLASH_DATA_REG[12] ; ; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |sidmax|CPU_FLASH_DATA_REG[31] ; ; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |sidmax|CPU_FLASH_DATA_REG[6] ; ; 4:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |sidmax|pokey:\POKEY_ON:1:pokeyx|serin_bitcount_reg[0] ; ; 4:1 ; 7 bits ; 14 LEs ; 14 LEs ; 0 LEs ; Yes ; |sidmax|pokey:\POKEY_ON:1:pokeyx|syncreset_enable_divider:enable_15_div|count_reg[6] ; ; 4:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; Yes ; |sidmax|pokey:\POKEY_ON:1:pokeyx|syncreset_enable_divider:enable_64_div|count_reg[1] ; ; 4:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |sidmax|pokey:\POKEY_ON:1:pokeyx|serout_shift_reg[5] ; ; 4:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |sidmax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|csr_status_busy[0] ; ; 4:1 ; 16 bits ; 32 LEs ; 16 LEs ; 16 LEs ; Yes ; |sidmax|PSG_top:\psg_on:PSG_1|PSG_envelope:envelope|PSG_freqdiv:envelope_ticker|count_reg[2] ; ; 4:1 ; 16 bits ; 32 LEs ; 16 LEs ; 16 LEs ; Yes ; |sidmax|PSG_top:\psg_on:PSG_2|PSG_envelope:envelope|PSG_freqdiv:envelope_ticker|count_reg[5] ; ; 4:1 ; 10 bits ; 20 LEs ; 20 LEs ; 0 LEs ; Yes ; |sidmax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|flash_page_addr[10] ; ; 5:1 ; 3 bits ; 9 LEs ; 6 LEs ; 3 LEs ; Yes ; |sidmax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|read_count[2] ; ; 6:1 ; 2 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |sidmax|CONFIG_FLASH_STATE_REG[0] ; ; 6:1 ; 6 bits ; 24 LEs ; 6 LEs ; 18 LEs ; Yes ; |sidmax|clockgensid:clockgen1|err_reg[0] ; ; 6:1 ; 8 bits ; 32 LEs ; 16 LEs ; 16 LEs ; Yes ; |sidmax|clockgensid:clockgen1|err_reg[8] ; ; 5:1 ; 8 bits ; 24 LEs ; 0 LEs ; 24 LEs ; Yes ; |sidmax|SID_top:sid2|SID_envelope:envelope_c|envelope_reg[6] ; ; 5:1 ; 8 bits ; 24 LEs ; 0 LEs ; 24 LEs ; Yes ; |sidmax|SID_top:sid1|SID_envelope:envelope_c|envelope_reg[7] ; ; 5:1 ; 4 bits ; 12 LEs ; 8 LEs ; 4 LEs ; Yes ; |sidmax|pokey:\POKEY_ON:1:pokeyx|serout_bitcount_reg[0] ; ; 5:1 ; 8 bits ; 24 LEs ; 0 LEs ; 24 LEs ; Yes ; |sidmax|SID_top:sid1|SID_envelope:envelope_a|envelope_reg[7] ; ; 5:1 ; 8 bits ; 24 LEs ; 0 LEs ; 24 LEs ; Yes ; |sidmax|SID_top:sid1|SID_envelope:envelope_b|envelope_reg[0] ; ; 5:1 ; 8 bits ; 24 LEs ; 0 LEs ; 24 LEs ; Yes ; |sidmax|SID_top:sid2|SID_envelope:envelope_a|envelope_reg[3] ; ; 5:1 ; 8 bits ; 24 LEs ; 0 LEs ; 24 LEs ; Yes ; |sidmax|SID_top:sid2|SID_envelope:envelope_b|envelope_reg[0] ; ; 5:1 ; 2 bits ; 6 LEs ; 2 LEs ; 4 LEs ; Yes ; |sidmax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|data_count[1] ; ; 5:1 ; 2 bits ; 6 LEs ; 6 LEs ; 0 LEs ; Yes ; |sidmax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|flash_sector_addr[0] ; ; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; Yes ; |sidmax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|read_ctrl_count[2] ; ; 8:1 ; 2 bits ; 10 LEs ; 4 LEs ; 6 LEs ; Yes ; |sidmax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_erase_state[1] ; ; 7:1 ; 12 bits ; 48 LEs ; 36 LEs ; 12 LEs ; Yes ; |sidmax|SID_top:sid1|SID_wavegen:wavegen_a|wave_reg[5] ; ; 7:1 ; 12 bits ; 48 LEs ; 36 LEs ; 12 LEs ; Yes ; |sidmax|SID_top:sid1|SID_wavegen:wavegen_b|wave_reg[6] ; ; 7:1 ; 12 bits ; 48 LEs ; 36 LEs ; 12 LEs ; Yes ; |sidmax|SID_top:sid1|SID_wavegen:wavegen_c|wave_reg[4] ; ; 7:1 ; 12 bits ; 48 LEs ; 36 LEs ; 12 LEs ; Yes ; |sidmax|SID_top:sid2|SID_wavegen:wavegen_a|wave_reg[8] ; ; 7:1 ; 12 bits ; 48 LEs ; 36 LEs ; 12 LEs ; Yes ; |sidmax|SID_top:sid2|SID_wavegen:wavegen_b|wave_reg[10] ; ; 7:1 ; 12 bits ; 48 LEs ; 36 LEs ; 12 LEs ; Yes ; |sidmax|SID_top:sid2|SID_wavegen:wavegen_c|wave_reg[11] ; ; 18:1 ; 2 bits ; 24 LEs ; 10 LEs ; 14 LEs ; Yes ; |sidmax|flash_controller:\flash_on:flash_controller_inst|state_reg[1] ; ; 256:1 ; 3 bits ; 510 LEs ; 12 LEs ; 498 LEs ; Yes ; |sidmax|SID_top:sid2|SID_envelope:envelope_c|exptapmatch_reg[0] ; ; 256:1 ; 3 bits ; 510 LEs ; 12 LEs ; 498 LEs ; Yes ; |sidmax|SID_top:sid1|SID_envelope:envelope_c|exptapmatch_reg[2] ; ; 256:1 ; 3 bits ; 510 LEs ; 12 LEs ; 498 LEs ; Yes ; |sidmax|SID_top:sid1|SID_envelope:envelope_a|exptapmatch_reg[2] ; ; 256:1 ; 3 bits ; 510 LEs ; 12 LEs ; 498 LEs ; Yes ; |sidmax|SID_top:sid1|SID_envelope:envelope_b|exptapmatch_reg[2] ; ; 256:1 ; 3 bits ; 510 LEs ; 12 LEs ; 498 LEs ; Yes ; |sidmax|SID_top:sid2|SID_envelope:envelope_a|exptapmatch_reg[1] ; ; 256:1 ; 3 bits ; 510 LEs ; 12 LEs ; 498 LEs ; Yes ; |sidmax|SID_top:sid2|SID_envelope:envelope_b|exptapmatch_reg[2] ; ; 10:1 ; 3 bits ; 18 LEs ; 12 LEs ; 6 LEs ; Yes ; |sidmax|SID_top:sid1|rom_state_reg[1] ; ; 10:1 ; 3 bits ; 18 LEs ; 12 LEs ; 6 LEs ; Yes ; |sidmax|SID_top:sid2|rom_state_reg[0] ; ; 7:1 ; 22 bits ; 88 LEs ; 66 LEs ; 22 LEs ; Yes ; |sidmax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|erase_count[13] ; ; 15:1 ; 2 bits ; 20 LEs ; 8 LEs ; 12 LEs ; Yes ; |sidmax|PSG_volume_profile:\psg_on:vol_profile1|state_reg[0] ; ; 8:1 ; 3 bits ; 15 LEs ; 12 LEs ; 3 LEs ; Yes ; |sidmax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|erase_count[7] ; ; 7:1 ; 11 bits ; 44 LEs ; 33 LEs ; 11 LEs ; Yes ; |sidmax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|write_count[0] ; ; 9:1 ; 3 bits ; 18 LEs ; 6 LEs ; 12 LEs ; Yes ; |sidmax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|write_count[7] ; ; 272:1 ; 3 bits ; 543 LEs ; 9 LEs ; 534 LEs ; Yes ; |sidmax|flash_controller:\flash_on:flash_controller_inst|request_addr_reg[14] ; ; 272:1 ; 2 bits ; 362 LEs ; 18 LEs ; 344 LEs ; Yes ; |sidmax|flash_controller:\flash_on:flash_controller_inst|request_addr_reg[9] ; ; 282:1 ; 2 bits ; 376 LEs ; 36 LEs ; 340 LEs ; Yes ; |sidmax|flash_controller:\flash_on:flash_controller_inst|request_addr_reg[7] ; ; 348:1 ; 3 bits ; 696 LEs ; 60 LEs ; 636 LEs ; Yes ; |sidmax|flash_controller:\flash_on:flash_controller_inst|request_addr_reg[2] ; ; 96:1 ; 2 bits ; 128 LEs ; 92 LEs ; 36 LEs ; Yes ; |sidmax|slave_timing_6502:bus_adapt|registered_read_data_reg[3] ; ; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |sidmax|POST_DIVIDE_REG[7] ; ; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |sidmax|SIO_DATA_VOLUME_REG[1] ; ; 3:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; Yes ; |sidmax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_wp_mode[0] ; ; 3:1 ; 23 bits ; 46 LEs ; 23 LEs ; 23 LEs ; Yes ; |sidmax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_sector_page_erase_addr_reg[15] ; ; 3:1 ; 18 bits ; 36 LEs ; 0 LEs ; 36 LEs ; Yes ; |sidmax|SID_top:sid1|statevariable_1q_reg[9] ; ; 3:1 ; 18 bits ; 36 LEs ; 0 LEs ; 36 LEs ; Yes ; |sidmax|SID_top:sid2|statevariable_1q_reg[10] ; ; 3:1 ; 6 bits ; 12 LEs ; 0 LEs ; 12 LEs ; Yes ; |sidmax|sample_top:\sample_on:sample1|ch0_volume_reg[1] ; ; 3:1 ; 6 bits ; 12 LEs ; 0 LEs ; 12 LEs ; Yes ; |sidmax|sample_top:\sample_on:sample1|ch1_volume_reg[5] ; ; 3:1 ; 6 bits ; 12 LEs ; 0 LEs ; 12 LEs ; Yes ; |sidmax|sample_top:\sample_on:sample1|ch2_volume_reg[1] ; ; 3:1 ; 6 bits ; 12 LEs ; 0 LEs ; 12 LEs ; Yes ; |sidmax|sample_top:\sample_on:sample1|ch3_volume_reg[3] ; ; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |sidmax|pokey:\POKEY_ON:1:pokeyx|allpot_reg[7] ; ; 3:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; Yes ; |sidmax|SID_top:sid2|SID_envelope:envelope_c|expdelay_lfsr_reg[4] ; ; 3:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; Yes ; |sidmax|SID_top:sid1|SID_envelope:envelope_c|expdelay_lfsr_reg[0] ; ; 3:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; Yes ; |sidmax|SID_top:sid2|SID_envelope:envelope_a|expdelay_lfsr_reg[0] ; ; 3:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; Yes ; |sidmax|SID_top:sid2|SID_envelope:envelope_b|expdelay_lfsr_reg[0] ; ; 3:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; Yes ; |sidmax|SID_top:sid1|SID_envelope:envelope_a|expdelay_lfsr_reg[1] ; ; 3:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; Yes ; |sidmax|SID_top:sid1|SID_envelope:envelope_b|expdelay_lfsr_reg[3] ; ; 8:1 ; 2 bits ; 10 LEs ; 6 LEs ; 4 LEs ; Yes ; |sidmax|SID_top:sid2|SID_envelope:envelope_c|state_reg[1] ; ; 8:1 ; 2 bits ; 10 LEs ; 6 LEs ; 4 LEs ; Yes ; |sidmax|SID_top:sid1|SID_envelope:envelope_c|state_reg[1] ; ; 8:1 ; 2 bits ; 10 LEs ; 6 LEs ; 4 LEs ; Yes ; |sidmax|SID_top:sid1|SID_envelope:envelope_a|state_reg[1] ; ; 8:1 ; 2 bits ; 10 LEs ; 6 LEs ; 4 LEs ; Yes ; |sidmax|SID_top:sid1|SID_envelope:envelope_b|state_reg[0] ; ; 8:1 ; 2 bits ; 10 LEs ; 6 LEs ; 4 LEs ; Yes ; |sidmax|SID_top:sid2|SID_envelope:envelope_a|state_reg[0] ; ; 8:1 ; 2 bits ; 10 LEs ; 6 LEs ; 4 LEs ; Yes ; |sidmax|SID_top:sid2|SID_envelope:envelope_b|state_reg[0] ; ; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |sidmax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|read_state ; ; 4:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; No ; |sidmax|sample_top:\sample_on:sample1|Mux282 ; ; 3:1 ; 25 bits ; 50 LEs ; 50 LEs ; 0 LEs ; No ; |sidmax|flash_controller:\flash_on:flash_controller_inst|flash_do[25] ; ; 3:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; No ; |sidmax|flash_controller:\flash_on:flash_controller_inst|flash_do[4] ; ; 3:1 ; 12 bits ; 24 LEs ; 24 LEs ; 0 LEs ; No ; |sidmax|SID_top:sid1|SID_oscillator:osc_a|count_next[23] ; ; 3:1 ; 12 bits ; 24 LEs ; 24 LEs ; 0 LEs ; No ; |sidmax|SID_top:sid1|SID_oscillator:osc_b|count_next[13] ; ; 3:1 ; 12 bits ; 24 LEs ; 24 LEs ; 0 LEs ; No ; |sidmax|SID_top:sid1|SID_oscillator:osc_c|count_next[15] ; ; 3:1 ; 12 bits ; 24 LEs ; 24 LEs ; 0 LEs ; No ; |sidmax|SID_top:sid2|SID_oscillator:osc_a|count_next[19] ; ; 3:1 ; 12 bits ; 24 LEs ; 24 LEs ; 0 LEs ; No ; |sidmax|SID_top:sid2|SID_oscillator:osc_b|count_next[17] ; ; 3:1 ; 12 bits ; 24 LEs ; 24 LEs ; 0 LEs ; No ; |sidmax|SID_top:sid2|SID_oscillator:osc_c|count_next[21] ; ; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; No ; |sidmax|sample_top:\sample_on:sample1|irq_clear_n[0] ; ; 3:1 ; 7 bits ; 14 LEs ; 14 LEs ; 0 LEs ; No ; |sidmax|sample_top:\sample_on:sample1|sample_adpcm:adpcm_decoder|decstep_next[0] ; ; 4:1 ; 22 bits ; 44 LEs ; 44 LEs ; 0 LEs ; No ; |sidmax|mixer:mixer1|Mux1 ; ; 1:1 ; 8 bits ; 0 LEs ; 0 LEs ; 0 LEs ; No ; |sidmax|SID_top:sid2|SID_envelope:envelope_c|Add0 ; ; 1:1 ; 8 bits ; 0 LEs ; 0 LEs ; 0 LEs ; No ; |sidmax|SID_top:sid1|SID_envelope:envelope_c|Add0 ; ; 4:1 ; 38 bits ; 76 LEs ; 76 LEs ; 0 LEs ; No ; |sidmax|SID_top:sid2|SID_envelope_tapmatch:envelope_tapmatcher|Mux5 ; ; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |sidmax|SID_top:sid1|SID_preFilterSum:prefilter|Mux1 ; ; 1:1 ; 8 bits ; 0 LEs ; 0 LEs ; 0 LEs ; No ; |sidmax|SID_top:sid1|SID_envelope:envelope_a|Add0 ; ; 1:1 ; 8 bits ; 0 LEs ; 0 LEs ; 0 LEs ; No ; |sidmax|SID_top:sid1|SID_envelope:envelope_b|Add0 ; ; 1:1 ; 8 bits ; 0 LEs ; 0 LEs ; 0 LEs ; No ; |sidmax|SID_top:sid2|SID_envelope:envelope_a|Add0 ; ; 1:1 ; 8 bits ; 0 LEs ; 0 LEs ; 0 LEs ; No ; |sidmax|SID_top:sid2|SID_envelope:envelope_b|Add0 ; ; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; No ; |sidmax|SID_f_distortion_mux:f_distortion_mux|SID_f_distortion:f_distortion|pos[10] ; ; 5:1 ; 5 bits ; 15 LEs ; 15 LEs ; 0 LEs ; No ; |sidmax|sample_top:\sample_on:sample1|RAM_ADDR[13] ; ; 5:1 ; 23 bits ; 69 LEs ; 69 LEs ; 0 LEs ; No ; |sidmax|sample_top:\sample_on:sample1|sample_adpcm:adpcm_decoder|STEP_ADDR[1] ; ; 8:1 ; 2 bits ; 10 LEs ; 4 LEs ; 6 LEs ; No ; |sidmax|PSG_volume_profile:\psg_on:vol_profile1|Mux5 ; ; 8:1 ; 3 bits ; 15 LEs ; 9 LEs ; 6 LEs ; No ; |sidmax|SID_top:sid1|Mux74 ; ; 8:1 ; 3 bits ; 15 LEs ; 9 LEs ; 6 LEs ; No ; |sidmax|SID_top:sid2|Mux74 ; ; 3:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; No ; |sidmax|sample_top:\sample_on:sample1|store ; ; 4:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |sidmax|SID_top:sid1|SID_preFilterSum:prefilter|Mux2 ; ; 4:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |sidmax|SID_top:sid2|SID_preFilterSum:prefilter|Mux1 ; ; 8:1 ; 2 bits ; 10 LEs ; 4 LEs ; 6 LEs ; No ; |sidmax|SID_top:sid1|SID_preFilterSum:prefilter|Mux0 ; ; 8:1 ; 20 bits ; 100 LEs ; 60 LEs ; 40 LEs ; No ; |sidmax|SID_top:sid1|SID_amplitudeModulator:vol_abc|Mux16 ; ; 8:1 ; 20 bits ; 100 LEs ; 60 LEs ; 40 LEs ; No ; |sidmax|SID_top:sid2|SID_amplitudeModulator:vol_abc|Mux8 ; ; 4:1 ; 16 bits ; 32 LEs ; 32 LEs ; 0 LEs ; No ; |sidmax|sample_top:\sample_on:sample1|sample_channel:ch0_inst|addr[9] ; ; 4:1 ; 16 bits ; 32 LEs ; 32 LEs ; 0 LEs ; No ; |sidmax|sample_top:\sample_on:sample1|sample_channel:ch1_inst|addr[7] ; ; 4:1 ; 16 bits ; 32 LEs ; 32 LEs ; 0 LEs ; No ; |sidmax|sample_top:\sample_on:sample1|sample_channel:ch2_inst|addr[9] ; ; 4:1 ; 16 bits ; 32 LEs ; 32 LEs ; 0 LEs ; No ; |sidmax|sample_top:\sample_on:sample1|sample_channel:ch3_inst|addr[14] ; ; 6:1 ; 11 bits ; 44 LEs ; 44 LEs ; 0 LEs ; No ; |sidmax|generic_ram_infer:\sample_on:normal_ram:sample_ram_inst|ram_block.raddr_a[9] ; ; 16:1 ; 16 bits ; 160 LEs ; 112 LEs ; 48 LEs ; No ; |sidmax|mixer:mixer1|Mux167 ; ; 16:1 ; 4 bits ; 40 LEs ; 12 LEs ; 28 LEs ; No ; |sidmax|sample_top:\sample_on:sample1|Mux4 ; ; 16:1 ; 4 bits ; 40 LEs ; 8 LEs ; 32 LEs ; No ; |sidmax|sample_top:\sample_on:sample1|Mux0 ; ; 9:1 ; 15 bits ; 90 LEs ; 30 LEs ; 60 LEs ; No ; |sidmax|SID_top:sid1|SID_amplitudeModulator:vol_abc|Mux33 ; ; 9:1 ; 15 bits ; 90 LEs ; 30 LEs ; 60 LEs ; No ; |sidmax|SID_top:sid2|SID_amplitudeModulator:vol_abc|Mux32 ; ; 7:1 ; 8 bits ; 32 LEs ; 32 LEs ; 0 LEs ; No ; |sidmax|SID_top:sid2|DO[1] ; ; 7:1 ; 8 bits ; 32 LEs ; 32 LEs ; 0 LEs ; No ; |sidmax|SID_top:sid1|DO[1] ; ; 8:1 ; 2 bits ; 10 LEs ; 8 LEs ; 2 LEs ; No ; |sidmax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|read_state ; ; 8:1 ; 2 bits ; 10 LEs ; 8 LEs ; 2 LEs ; No ; |sidmax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|erase_state ; ; 8:1 ; 2 bits ; 10 LEs ; 4 LEs ; 6 LEs ; No ; |sidmax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|erase_state ; ; 10:1 ; 2 bits ; 12 LEs ; 10 LEs ; 2 LEs ; No ; |sidmax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|erase_state ; ; 8:1 ; 2 bits ; 10 LEs ; 8 LEs ; 2 LEs ; No ; |sidmax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|write_state ; ; 8:1 ; 2 bits ; 10 LEs ; 4 LEs ; 6 LEs ; No ; |sidmax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|write_state ; ; 6:1 ; 2 bits ; 8 LEs ; 2 LEs ; 6 LEs ; No ; |sidmax|SID_top:sid2|Add1 ; ; 16:1 ; 2 bits ; 20 LEs ; 8 LEs ; 12 LEs ; No ; |sidmax|SID_top:sid2|Add1 ; +--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Source assignments for flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_std_synchronizer:stdsync_busy ; +-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Assignment ; Value ; From ; To ; +-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[0] ; ; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[0] ; ; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; ; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; ; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; din_s1 ; ; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; din_s1 ; ; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; ; PRESERVE_REGISTER ; ON ; - ; din_s1 ; +-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Source assignments for flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_std_synchronizer:stdsync_busy_clear ; +-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Assignment ; Value ; From ; To ; +-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; dreg[0] ; ; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[0] ; ; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; ; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; ; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; din_s1 ; ; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; din_s1 ; ; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; ; PRESERVE_REGISTER ; ON ; - ; din_s1 ; +-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +------------------------------------------------------------------------------------------------------------------------------------------+ ; Source assignments for generic_ram_infer:\sample_on:normal_ram:sample_ram_inst|altsyncram:ram_block_rtl_0|altsyncram_6t31:auto_generated ; +---------------------------------+--------------------+------+----------------------------------------------------------------------------+ ; Assignment ; Value ; From ; To ; +---------------------------------+--------------------+------+----------------------------------------------------------------------------+ ; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; +---------------------------------+--------------------+------+----------------------------------------------------------------------------+ +------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: Top-level Entity: |sidmax ; +----------------------------+----------+--------------------------------+ ; Parameter Name ; Value ; Type ; +----------------------------+----------+--------------------------------+ ; pokeys ; 2 ; Untyped ; ; lowpass ; 0 ; Signed Integer ; ; enable_auto_stereo ; 1 ; Untyped ; ; fancy_switch_bit ; 20 ; Signed Integer ; ; detect_right_on_by_default ; 1 ; Signed Integer ; ; saturate_on_by_default ; 1 ; Signed Integer ; ; a5_bit ; 1 ; Untyped ; ; a6_bit ; 2 ; Untyped ; ; a7_bit ; 3 ; Untyped ; ; spdif_bit ; 0 ; Signed Integer ; ; irq_bit ; 4 ; Untyped ; ; adc_audio_detect ; 0 ; Signed Integer ; ; sigmadelta_implementation ; 4 ; Signed Integer ; ; ext_bits ; 4 ; Untyped ; ; enable_config ; 1 ; Signed Integer ; ; enable_psg ; 1 ; Untyped ; ; enable_covox ; 1 ; Untyped ; ; enable_sample ; 1 ; Untyped ; ; enable_flash ; 1 ; Untyped ; ; enable_spdif ; 0 ; Signed Integer ; ; enable_adc ; 1 ; Signed Integer ; ; sid_wave_base ; 42496 ; Signed Integer ; ; sample_ram_size ; 43008 ; Signed Integer ; ; flash_addr_bits ; 16 ; Signed Integer ; ; version ; 131M08SF ; Untyped ; ; board ; 10 ; Untyped ; +----------------------------+----------+--------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: int_osc:oscillator|altera_int_osc:int_osc_0 ; +-----------------+--------+---------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +-----------------+--------+---------------------------------------------------------------+ ; DEVICE_FAMILY ; MAX 10 ; String ; ; DEVICE_ID ; 08 ; String ; ; CLOCK_FREQUENCY ; 116 ; String ; +-----------------+--------+---------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-----------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: flash_controller:\flash_on:flash_controller_inst ; +----------------+-------+----------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+----------------------------------------------------------------------+ ; addr_bits ; 16 ; Signed Integer ; +----------------+-------+----------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-----------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0 ; +-------------------------------------+----------------+----------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +-------------------------------------+----------------+----------------------------------------------------------------------------------------+ ; DEVICE_FAMILY ; MAX 10 ; String ; ; PART_NAME ; 10M08SCU169C8G ; String ; ; IS_DUAL_BOOT ; False ; String ; ; IS_ERAM_SKIP ; True ; String ; ; IS_COMPRESSED_IMAGE ; False ; String ; ; INIT_FILENAME ; ; String ; ; DEVICE_ID ; 08 ; String ; ; INIT_FILENAME_SIM ; ; String ; ; PARALLEL_MODE ; true ; Enumerated ; ; READ_AND_WRITE_MODE ; true ; Enumerated ; ; WRAPPING_BURST_MODE ; true ; Enumerated ; ; AVMM_CSR_DATA_WIDTH ; 32 ; Signed Integer ; ; AVMM_DATA_DATA_WIDTH ; 32 ; Signed Integer ; ; AVMM_DATA_ADDR_WIDTH ; 16 ; Signed Integer ; ; AVMM_DATA_BURSTCOUNT_WIDTH ; 2 ; Signed Integer ; ; FLASH_DATA_WIDTH ; 32 ; Signed Integer ; ; FLASH_ADDR_WIDTH ; 23 ; Signed Integer ; ; FLASH_SEQ_READ_DATA_COUNT ; 2 ; Signed Integer ; ; FLASH_READ_CYCLE_MAX_INDEX ; 4 ; Signed Integer ; ; FLASH_ADDR_ALIGNMENT_BITS ; 1 ; Signed Integer ; ; FLASH_RESET_CYCLE_MAX_INDEX ; 29 ; Signed Integer ; ; FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX ; 139 ; Signed Integer ; ; FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX ; 40600000 ; Signed Integer ; ; FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX ; 35380 ; Signed Integer ; ; MIN_VALID_ADDR ; 0 ; Signed Integer ; ; MAX_VALID_ADDR ; 58879 ; Signed Integer ; ; MIN_UFM_VALID_ADDR ; 0 ; Signed Integer ; ; MAX_UFM_VALID_ADDR ; 8191 ; Signed Integer ; ; SECTOR1_START_ADDR ; 0 ; Signed Integer ; ; SECTOR1_END_ADDR ; 4095 ; Signed Integer ; ; SECTOR2_START_ADDR ; 4096 ; Signed Integer ; ; SECTOR2_END_ADDR ; 8191 ; Signed Integer ; ; SECTOR3_START_ADDR ; 8192 ; Signed Integer ; ; SECTOR3_END_ADDR ; 23039 ; Signed Integer ; ; SECTOR4_START_ADDR ; 23040 ; Signed Integer ; ; SECTOR4_END_ADDR ; 58879 ; Signed Integer ; ; SECTOR5_START_ADDR ; 0 ; Signed Integer ; ; SECTOR5_END_ADDR ; 0 ; Signed Integer ; ; SECTOR_READ_PROTECTION_MODE ; 16 ; Signed Integer ; ; SECTOR1_MAP ; 1 ; Signed Integer ; ; SECTOR2_MAP ; 2 ; Signed Integer ; ; SECTOR3_MAP ; 4 ; Signed Integer ; ; SECTOR4_MAP ; 5 ; Signed Integer ; ; SECTOR5_MAP ; 0 ; Signed Integer ; ; ADDR_RANGE1_END_ADDR ; 8191 ; Signed Integer ; ; ADDR_RANGE2_END_ADDR ; 58879 ; Signed Integer ; ; ADDR_RANGE1_OFFSET ; 512 ; Signed Integer ; ; ADDR_RANGE2_OFFSET ; 21504 ; Signed Integer ; ; ADDR_RANGE3_OFFSET ; 0 ; Signed Integer ; +-------------------------------------+----------------+----------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller ; +---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; AVMM_CSR_DATA_WIDTH ; 32 ; Signed Integer ; +---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller ; +-------------------------------------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +-------------------------------------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; READ_AND_WRITE_MODE ; 1 ; Signed Integer ; ; WRAPPING_BURST_MODE ; 1 ; Signed Integer ; ; DATA_WIDTH ; 32 ; Signed Integer ; ; AVMM_DATA_ADDR_WIDTH ; 16 ; Signed Integer ; ; AVMM_DATA_BURSTCOUNT_WIDTH ; 2 ; Signed Integer ; ; FLASH_ADDR_WIDTH ; 23 ; Signed Integer ; ; FLASH_SEQ_READ_DATA_COUNT ; 2 ; Signed Integer ; ; FLASH_READ_CYCLE_MAX_INDEX ; 4 ; Signed Integer ; ; FLASH_ADDR_ALIGNMENT_BITS ; 1 ; Signed Integer ; ; FLASH_RESET_CYCLE_MAX_INDEX ; 29 ; Signed Integer ; ; FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX ; 139 ; Signed Integer ; ; FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX ; 40600000 ; Signed Integer ; ; FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX ; 35380 ; Signed Integer ; ; MIN_VALID_ADDR ; 0 ; Signed Integer ; ; MAX_VALID_ADDR ; 58879 ; Signed Integer ; ; SECTOR1_START_ADDR ; 0 ; Signed Integer ; ; SECTOR1_END_ADDR ; 4095 ; Signed Integer ; ; SECTOR2_START_ADDR ; 4096 ; Signed Integer ; ; SECTOR2_END_ADDR ; 8191 ; Signed Integer ; ; SECTOR3_START_ADDR ; 8192 ; Signed Integer ; ; SECTOR3_END_ADDR ; 23039 ; Signed Integer ; ; SECTOR4_START_ADDR ; 23040 ; Signed Integer ; ; SECTOR4_END_ADDR ; 58879 ; Signed Integer ; ; SECTOR5_START_ADDR ; 0 ; Signed Integer ; ; SECTOR5_END_ADDR ; 0 ; Signed Integer ; ; SECTOR_READ_PROTECTION_MODE ; 16 ; Signed Integer ; ; SECTOR1_MAP ; 1 ; Signed Integer ; ; SECTOR2_MAP ; 2 ; Signed Integer ; ; SECTOR3_MAP ; 4 ; Signed Integer ; ; SECTOR4_MAP ; 5 ; Signed Integer ; ; SECTOR5_MAP ; 0 ; Signed Integer ; ; ADDR_RANGE1_END_ADDR ; 8191 ; Signed Integer ; ; ADDR_RANGE2_END_ADDR ; 58879 ; Signed Integer ; ; ADDR_RANGE1_OFFSET ; 512 ; Signed Integer ; ; ADDR_RANGE2_OFFSET ; 21504 ; Signed Integer ; ; ADDR_RANGE3_OFFSET ; 0 ; Signed Integer ; +-------------------------------------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_std_synchronizer:stdsync_busy ; +----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; depth ; 2 ; Signed Integer ; +----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_std_synchronizer:stdsync_busy_clear ; +----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; depth ; 2 ; Signed Integer ; +----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|lpm_shiftreg:ufm_data_shiftreg ; +------------------------+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +------------------------+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; LPM_WIDTH ; 32 ; Signed Integer ; ; LPM_DIRECTION ; LEFT ; Untyped ; ; LPM_AVALUE ; UNUSED ; Untyped ; ; LPM_SVALUE ; UNUSED ; Untyped ; ; DEVICE_FAMILY ; MAX 10 ; Untyped ; ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +------------------------+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_onchip_flash_address_range_check:address_range_checker ; +------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; FLASH_ADDR_WIDTH ; 23 ; Signed Integer ; ; MIN_VALID_ADDR ; 0 ; Signed Integer ; ; MAX_VALID_ADDR ; 58879 ; Signed Integer ; +------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_onchip_flash_convert_address:address_convertor ; +----------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; FLASH_ADDR_WIDTH ; 23 ; Signed Integer ; ; ADDR_RANGE1_END_ADDR ; 8191 ; Signed Integer ; ; ADDR_RANGE2_END_ADDR ; 58879 ; Signed Integer ; ; ADDR_RANGE1_OFFSET ; 512 ; Signed Integer ; ; ADDR_RANGE2_OFFSET ; 21504 ; Signed Integer ; ; ADDR_RANGE3_OFFSET ; 0 ; Signed Integer ; +----------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_onchip_flash_a_address_write_protection_check:access_address_write_protection_checker ; +--------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +--------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; FLASH_ADDR_WIDTH ; 23 ; Signed Integer ; ; SECTOR1_START_ADDR ; 0 ; Signed Integer ; ; SECTOR1_END_ADDR ; 4095 ; Signed Integer ; ; SECTOR2_START_ADDR ; 4096 ; Signed Integer ; ; SECTOR2_END_ADDR ; 8191 ; Signed Integer ; ; SECTOR3_START_ADDR ; 8192 ; Signed Integer ; ; SECTOR3_END_ADDR ; 23039 ; Signed Integer ; ; SECTOR4_START_ADDR ; 23040 ; Signed Integer ; ; SECTOR4_END_ADDR ; 58879 ; Signed Integer ; ; SECTOR5_START_ADDR ; 0 ; Signed Integer ; ; SECTOR5_END_ADDR ; 0 ; Signed Integer ; +--------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_onchip_flash_convert_sector:sector_convertor ; +----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; SECTOR1_MAP ; 1 ; Signed Integer ; ; SECTOR2_MAP ; 2 ; Signed Integer ; ; SECTOR3_MAP ; 4 ; Signed Integer ; ; SECTOR4_MAP ; 5 ; Signed Integer ; ; SECTOR5_MAP ; 0 ; Signed Integer ; +----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-----------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pll:pll_inst|altpll:altpll_component ; +-------------------------------+-----------------------+---------------------------+ ; Parameter Name ; Value ; Type ; +-------------------------------+-----------------------+---------------------------+ ; OPERATION_MODE ; NO_COMPENSATION ; Untyped ; ; PLL_TYPE ; AUTO ; Untyped ; ; LPM_HINT ; CBX_MODULE_PREFIX=pll ; Untyped ; ; QUALIFY_CONF_DONE ; OFF ; Untyped ; ; COMPENSATE_CLOCK ; CLK0 ; Untyped ; ; SCAN_CHAIN ; LONG ; Untyped ; ; PRIMARY_CLOCK ; INCLK0 ; Untyped ; ; INCLK0_INPUT_FREQUENCY ; 11446 ; Signed Integer ; ; INCLK1_INPUT_FREQUENCY ; 0 ; Untyped ; ; GATE_LOCK_SIGNAL ; NO ; Untyped ; ; GATE_LOCK_COUNTER ; 0 ; Untyped ; ; LOCK_HIGH ; 1 ; Untyped ; ; LOCK_LOW ; 1 ; Untyped ; ; VALID_LOCK_MULTIPLIER ; 1 ; Untyped ; ; INVALID_LOCK_MULTIPLIER ; 5 ; Untyped ; ; SWITCH_OVER_ON_LOSSCLK ; OFF ; Untyped ; ; SWITCH_OVER_ON_GATED_LOCK ; OFF ; Untyped ; ; ENABLE_SWITCH_OVER_COUNTER ; OFF ; Untyped ; ; SKIP_VCO ; OFF ; Untyped ; ; SWITCH_OVER_COUNTER ; 0 ; Untyped ; ; SWITCH_OVER_TYPE ; AUTO ; Untyped ; ; FEEDBACK_SOURCE ; EXTCLK0 ; Untyped ; ; BANDWIDTH ; 0 ; Untyped ; ; BANDWIDTH_TYPE ; AUTO ; Untyped ; ; SPREAD_FREQUENCY ; 0 ; Untyped ; ; DOWN_SPREAD ; 0 ; Untyped ; ; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF ; Untyped ; ; SELF_RESET_ON_LOSS_LOCK ; OFF ; Untyped ; ; CLK9_MULTIPLY_BY ; 0 ; Untyped ; ; CLK8_MULTIPLY_BY ; 0 ; Untyped ; ; CLK7_MULTIPLY_BY ; 0 ; Untyped ; ; CLK6_MULTIPLY_BY ; 0 ; Untyped ; ; CLK5_MULTIPLY_BY ; 1 ; Untyped ; ; CLK4_MULTIPLY_BY ; 1 ; Untyped ; ; CLK3_MULTIPLY_BY ; 1 ; Untyped ; ; CLK2_MULTIPLY_BY ; 11 ; Signed Integer ; ; CLK1_MULTIPLY_BY ; 4 ; Signed Integer ; ; CLK0_MULTIPLY_BY ; 2 ; Signed Integer ; ; CLK9_DIVIDE_BY ; 0 ; Untyped ; ; CLK8_DIVIDE_BY ; 0 ; Untyped ; ; CLK7_DIVIDE_BY ; 0 ; Untyped ; ; CLK6_DIVIDE_BY ; 0 ; Untyped ; ; CLK5_DIVIDE_BY ; 1 ; Untyped ; ; CLK4_DIVIDE_BY ; 1 ; Untyped ; ; CLK3_DIVIDE_BY ; 1 ; Untyped ; ; CLK2_DIVIDE_BY ; 9 ; Signed Integer ; ; CLK1_DIVIDE_BY ; 3 ; Signed Integer ; ; CLK0_DIVIDE_BY ; 3 ; Signed Integer ; ; CLK9_PHASE_SHIFT ; 0 ; Untyped ; ; CLK8_PHASE_SHIFT ; 0 ; Untyped ; ; CLK7_PHASE_SHIFT ; 0 ; Untyped ; ; CLK6_PHASE_SHIFT ; 0 ; Untyped ; ; CLK5_PHASE_SHIFT ; 0 ; Untyped ; ; CLK4_PHASE_SHIFT ; 0 ; Untyped ; ; CLK3_PHASE_SHIFT ; 0 ; Untyped ; ; CLK2_PHASE_SHIFT ; 0 ; Untyped ; ; CLK1_PHASE_SHIFT ; 0 ; Untyped ; ; CLK0_PHASE_SHIFT ; 0 ; Untyped ; ; CLK5_TIME_DELAY ; 0 ; Untyped ; ; CLK4_TIME_DELAY ; 0 ; Untyped ; ; CLK3_TIME_DELAY ; 0 ; Untyped ; ; CLK2_TIME_DELAY ; 0 ; Untyped ; ; CLK1_TIME_DELAY ; 0 ; Untyped ; ; CLK0_TIME_DELAY ; 0 ; Untyped ; ; CLK9_DUTY_CYCLE ; 50 ; Untyped ; ; CLK8_DUTY_CYCLE ; 50 ; Untyped ; ; CLK7_DUTY_CYCLE ; 50 ; Untyped ; ; CLK6_DUTY_CYCLE ; 50 ; Untyped ; ; CLK5_DUTY_CYCLE ; 50 ; Untyped ; ; CLK4_DUTY_CYCLE ; 50 ; Untyped ; ; CLK3_DUTY_CYCLE ; 50 ; Untyped ; ; CLK2_DUTY_CYCLE ; 50 ; Signed Integer ; ; CLK1_DUTY_CYCLE ; 50 ; Signed Integer ; ; CLK0_DUTY_CYCLE ; 50 ; Signed Integer ; ; CLK9_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK8_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK7_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK6_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK5_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK4_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK3_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK2_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK1_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK0_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK9_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK8_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK7_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK6_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK5_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK4_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK3_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK2_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK1_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK0_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; LOCK_WINDOW_UI ; 0.05 ; Untyped ; ; LOCK_WINDOW_UI_BITS ; UNUSED ; Untyped ; ; VCO_RANGE_DETECTOR_LOW_BITS ; UNUSED ; Untyped ; ; VCO_RANGE_DETECTOR_HIGH_BITS ; UNUSED ; Untyped ; ; DPA_MULTIPLY_BY ; 0 ; Untyped ; ; DPA_DIVIDE_BY ; 1 ; Untyped ; ; DPA_DIVIDER ; 0 ; Untyped ; ; EXTCLK3_MULTIPLY_BY ; 1 ; Untyped ; ; EXTCLK2_MULTIPLY_BY ; 1 ; Untyped ; ; EXTCLK1_MULTIPLY_BY ; 1 ; Untyped ; ; EXTCLK0_MULTIPLY_BY ; 1 ; Untyped ; ; EXTCLK3_DIVIDE_BY ; 1 ; Untyped ; ; EXTCLK2_DIVIDE_BY ; 1 ; Untyped ; ; EXTCLK1_DIVIDE_BY ; 1 ; Untyped ; ; EXTCLK0_DIVIDE_BY ; 1 ; Untyped ; ; EXTCLK3_PHASE_SHIFT ; 0 ; Untyped ; ; EXTCLK2_PHASE_SHIFT ; 0 ; Untyped ; ; EXTCLK1_PHASE_SHIFT ; 0 ; Untyped ; ; EXTCLK0_PHASE_SHIFT ; 0 ; Untyped ; ; EXTCLK3_TIME_DELAY ; 0 ; Untyped ; ; EXTCLK2_TIME_DELAY ; 0 ; Untyped ; ; EXTCLK1_TIME_DELAY ; 0 ; Untyped ; ; EXTCLK0_TIME_DELAY ; 0 ; Untyped ; ; EXTCLK3_DUTY_CYCLE ; 50 ; Untyped ; ; EXTCLK2_DUTY_CYCLE ; 50 ; Untyped ; ; EXTCLK1_DUTY_CYCLE ; 50 ; Untyped ; ; EXTCLK0_DUTY_CYCLE ; 50 ; Untyped ; ; VCO_MULTIPLY_BY ; 0 ; Untyped ; ; VCO_DIVIDE_BY ; 0 ; Untyped ; ; SCLKOUT0_PHASE_SHIFT ; 0 ; Untyped ; ; SCLKOUT1_PHASE_SHIFT ; 0 ; Untyped ; ; VCO_MIN ; 0 ; Untyped ; ; VCO_MAX ; 0 ; Untyped ; ; VCO_CENTER ; 0 ; Untyped ; ; PFD_MIN ; 0 ; Untyped ; ; PFD_MAX ; 0 ; Untyped ; ; M_INITIAL ; 0 ; Untyped ; ; M ; 0 ; Untyped ; ; N ; 1 ; Untyped ; ; M2 ; 1 ; Untyped ; ; N2 ; 1 ; Untyped ; ; SS ; 1 ; Untyped ; ; C0_HIGH ; 0 ; Untyped ; ; C1_HIGH ; 0 ; Untyped ; ; C2_HIGH ; 0 ; Untyped ; ; C3_HIGH ; 0 ; Untyped ; ; C4_HIGH ; 0 ; Untyped ; ; C5_HIGH ; 0 ; Untyped ; ; C6_HIGH ; 0 ; Untyped ; ; C7_HIGH ; 0 ; Untyped ; ; C8_HIGH ; 0 ; Untyped ; ; C9_HIGH ; 0 ; Untyped ; ; C0_LOW ; 0 ; Untyped ; ; C1_LOW ; 0 ; Untyped ; ; C2_LOW ; 0 ; Untyped ; ; C3_LOW ; 0 ; Untyped ; ; C4_LOW ; 0 ; Untyped ; ; C5_LOW ; 0 ; Untyped ; ; C6_LOW ; 0 ; Untyped ; ; C7_LOW ; 0 ; Untyped ; ; C8_LOW ; 0 ; Untyped ; ; C9_LOW ; 0 ; Untyped ; ; C0_INITIAL ; 0 ; Untyped ; ; C1_INITIAL ; 0 ; Untyped ; ; C2_INITIAL ; 0 ; Untyped ; ; C3_INITIAL ; 0 ; Untyped ; ; C4_INITIAL ; 0 ; Untyped ; ; C5_INITIAL ; 0 ; Untyped ; ; C6_INITIAL ; 0 ; Untyped ; ; C7_INITIAL ; 0 ; Untyped ; ; C8_INITIAL ; 0 ; Untyped ; ; C9_INITIAL ; 0 ; Untyped ; ; C0_MODE ; BYPASS ; Untyped ; ; C1_MODE ; BYPASS ; Untyped ; ; C2_MODE ; BYPASS ; Untyped ; ; C3_MODE ; BYPASS ; Untyped ; ; C4_MODE ; BYPASS ; Untyped ; ; C5_MODE ; BYPASS ; Untyped ; ; C6_MODE ; BYPASS ; Untyped ; ; C7_MODE ; BYPASS ; Untyped ; ; C8_MODE ; BYPASS ; Untyped ; ; C9_MODE ; BYPASS ; Untyped ; ; C0_PH ; 0 ; Untyped ; ; C1_PH ; 0 ; Untyped ; ; C2_PH ; 0 ; Untyped ; ; C3_PH ; 0 ; Untyped ; ; C4_PH ; 0 ; Untyped ; ; C5_PH ; 0 ; Untyped ; ; C6_PH ; 0 ; Untyped ; ; C7_PH ; 0 ; Untyped ; ; C8_PH ; 0 ; Untyped ; ; C9_PH ; 0 ; Untyped ; ; L0_HIGH ; 1 ; Untyped ; ; L1_HIGH ; 1 ; Untyped ; ; G0_HIGH ; 1 ; Untyped ; ; G1_HIGH ; 1 ; Untyped ; ; G2_HIGH ; 1 ; Untyped ; ; G3_HIGH ; 1 ; Untyped ; ; E0_HIGH ; 1 ; Untyped ; ; E1_HIGH ; 1 ; Untyped ; ; E2_HIGH ; 1 ; Untyped ; ; E3_HIGH ; 1 ; Untyped ; ; L0_LOW ; 1 ; Untyped ; ; L1_LOW ; 1 ; Untyped ; ; G0_LOW ; 1 ; Untyped ; ; G1_LOW ; 1 ; Untyped ; ; G2_LOW ; 1 ; Untyped ; ; G3_LOW ; 1 ; Untyped ; ; E0_LOW ; 1 ; Untyped ; ; E1_LOW ; 1 ; Untyped ; ; E2_LOW ; 1 ; Untyped ; ; E3_LOW ; 1 ; Untyped ; ; L0_INITIAL ; 1 ; Untyped ; ; L1_INITIAL ; 1 ; Untyped ; ; G0_INITIAL ; 1 ; Untyped ; ; G1_INITIAL ; 1 ; Untyped ; ; G2_INITIAL ; 1 ; Untyped ; ; G3_INITIAL ; 1 ; Untyped ; ; E0_INITIAL ; 1 ; Untyped ; ; E1_INITIAL ; 1 ; Untyped ; ; E2_INITIAL ; 1 ; Untyped ; ; E3_INITIAL ; 1 ; Untyped ; ; L0_MODE ; BYPASS ; Untyped ; ; L1_MODE ; BYPASS ; Untyped ; ; G0_MODE ; BYPASS ; Untyped ; ; G1_MODE ; BYPASS ; Untyped ; ; G2_MODE ; BYPASS ; Untyped ; ; G3_MODE ; BYPASS ; Untyped ; ; E0_MODE ; BYPASS ; Untyped ; ; E1_MODE ; BYPASS ; Untyped ; ; E2_MODE ; BYPASS ; Untyped ; ; E3_MODE ; BYPASS ; Untyped ; ; L0_PH ; 0 ; Untyped ; ; L1_PH ; 0 ; Untyped ; ; G0_PH ; 0 ; Untyped ; ; G1_PH ; 0 ; Untyped ; ; G2_PH ; 0 ; Untyped ; ; G3_PH ; 0 ; Untyped ; ; E0_PH ; 0 ; Untyped ; ; E1_PH ; 0 ; Untyped ; ; E2_PH ; 0 ; Untyped ; ; E3_PH ; 0 ; Untyped ; ; M_PH ; 0 ; Untyped ; ; C1_USE_CASC_IN ; OFF ; Untyped ; ; C2_USE_CASC_IN ; OFF ; Untyped ; ; C3_USE_CASC_IN ; OFF ; Untyped ; ; C4_USE_CASC_IN ; OFF ; Untyped ; ; C5_USE_CASC_IN ; OFF ; Untyped ; ; C6_USE_CASC_IN ; OFF ; Untyped ; ; C7_USE_CASC_IN ; OFF ; Untyped ; ; C8_USE_CASC_IN ; OFF ; Untyped ; ; C9_USE_CASC_IN ; OFF ; Untyped ; ; CLK0_COUNTER ; G0 ; Untyped ; ; CLK1_COUNTER ; G0 ; Untyped ; ; CLK2_COUNTER ; G0 ; Untyped ; ; CLK3_COUNTER ; G0 ; Untyped ; ; CLK4_COUNTER ; G0 ; Untyped ; ; CLK5_COUNTER ; G0 ; Untyped ; ; CLK6_COUNTER ; E0 ; Untyped ; ; CLK7_COUNTER ; E1 ; Untyped ; ; CLK8_COUNTER ; E2 ; Untyped ; ; CLK9_COUNTER ; E3 ; Untyped ; ; L0_TIME_DELAY ; 0 ; Untyped ; ; L1_TIME_DELAY ; 0 ; Untyped ; ; G0_TIME_DELAY ; 0 ; Untyped ; ; G1_TIME_DELAY ; 0 ; Untyped ; ; G2_TIME_DELAY ; 0 ; Untyped ; ; G3_TIME_DELAY ; 0 ; Untyped ; ; E0_TIME_DELAY ; 0 ; Untyped ; ; E1_TIME_DELAY ; 0 ; Untyped ; ; E2_TIME_DELAY ; 0 ; Untyped ; ; E3_TIME_DELAY ; 0 ; Untyped ; ; M_TIME_DELAY ; 0 ; Untyped ; ; N_TIME_DELAY ; 0 ; Untyped ; ; EXTCLK3_COUNTER ; E3 ; Untyped ; ; EXTCLK2_COUNTER ; E2 ; Untyped ; ; EXTCLK1_COUNTER ; E1 ; Untyped ; ; EXTCLK0_COUNTER ; E0 ; Untyped ; ; ENABLE0_COUNTER ; L0 ; Untyped ; ; ENABLE1_COUNTER ; L0 ; Untyped ; ; CHARGE_PUMP_CURRENT ; 2 ; Untyped ; ; LOOP_FILTER_R ; 1.000000 ; Untyped ; ; LOOP_FILTER_C ; 5 ; Untyped ; ; CHARGE_PUMP_CURRENT_BITS ; 9999 ; Untyped ; ; LOOP_FILTER_R_BITS ; 9999 ; Untyped ; ; LOOP_FILTER_C_BITS ; 9999 ; Untyped ; ; VCO_POST_SCALE ; 0 ; Untyped ; ; CLK2_OUTPUT_FREQUENCY ; 0 ; Untyped ; ; CLK1_OUTPUT_FREQUENCY ; 0 ; Untyped ; ; CLK0_OUTPUT_FREQUENCY ; 0 ; Untyped ; ; INTENDED_DEVICE_FAMILY ; MAX 10 ; Untyped ; ; PORT_CLKENA0 ; PORT_UNUSED ; Untyped ; ; PORT_CLKENA1 ; PORT_UNUSED ; Untyped ; ; PORT_CLKENA2 ; PORT_UNUSED ; Untyped ; ; PORT_CLKENA3 ; PORT_UNUSED ; Untyped ; ; PORT_CLKENA4 ; PORT_UNUSED ; Untyped ; ; PORT_CLKENA5 ; PORT_UNUSED ; Untyped ; ; PORT_EXTCLKENA0 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_EXTCLKENA1 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_EXTCLKENA2 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_EXTCLKENA3 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_EXTCLK0 ; PORT_UNUSED ; Untyped ; ; PORT_EXTCLK1 ; PORT_UNUSED ; Untyped ; ; PORT_EXTCLK2 ; PORT_UNUSED ; Untyped ; ; PORT_EXTCLK3 ; PORT_UNUSED ; Untyped ; ; PORT_CLKBAD0 ; PORT_UNUSED ; Untyped ; ; PORT_CLKBAD1 ; PORT_UNUSED ; Untyped ; ; PORT_CLK0 ; PORT_USED ; Untyped ; ; PORT_CLK1 ; PORT_USED ; Untyped ; ; PORT_CLK2 ; PORT_USED ; Untyped ; ; PORT_CLK3 ; PORT_UNUSED ; Untyped ; ; PORT_CLK4 ; PORT_UNUSED ; Untyped ; ; PORT_CLK5 ; PORT_UNUSED ; Untyped ; ; PORT_CLK6 ; PORT_UNUSED ; Untyped ; ; PORT_CLK7 ; PORT_UNUSED ; Untyped ; ; PORT_CLK8 ; PORT_UNUSED ; Untyped ; ; PORT_CLK9 ; PORT_UNUSED ; Untyped ; ; PORT_SCANDATA ; PORT_UNUSED ; Untyped ; ; PORT_SCANDATAOUT ; PORT_UNUSED ; Untyped ; ; PORT_SCANDONE ; PORT_UNUSED ; Untyped ; ; PORT_SCLKOUT1 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_SCLKOUT0 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_ACTIVECLOCK ; PORT_UNUSED ; Untyped ; ; PORT_CLKLOSS ; PORT_UNUSED ; Untyped ; ; PORT_INCLK1 ; PORT_UNUSED ; Untyped ; ; PORT_INCLK0 ; PORT_USED ; Untyped ; ; PORT_FBIN ; PORT_UNUSED ; Untyped ; ; PORT_PLLENA ; PORT_UNUSED ; Untyped ; ; PORT_CLKSWITCH ; PORT_UNUSED ; Untyped ; ; PORT_ARESET ; PORT_UNUSED ; Untyped ; ; PORT_PFDENA ; PORT_UNUSED ; Untyped ; ; PORT_SCANCLK ; PORT_UNUSED ; Untyped ; ; PORT_SCANACLR ; PORT_UNUSED ; Untyped ; ; PORT_SCANREAD ; PORT_UNUSED ; Untyped ; ; PORT_SCANWRITE ; PORT_UNUSED ; Untyped ; ; PORT_ENABLE0 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_ENABLE1 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_LOCKED ; PORT_USED ; Untyped ; ; PORT_CONFIGUPDATE ; PORT_UNUSED ; Untyped ; ; PORT_FBOUT ; PORT_CONNECTIVITY ; Untyped ; ; PORT_PHASEDONE ; PORT_UNUSED ; Untyped ; ; PORT_PHASESTEP ; PORT_UNUSED ; Untyped ; ; PORT_PHASEUPDOWN ; PORT_UNUSED ; Untyped ; ; PORT_SCANCLKENA ; PORT_UNUSED ; Untyped ; ; PORT_PHASECOUNTERSELECT ; PORT_UNUSED ; Untyped ; ; PORT_VCOOVERRANGE ; PORT_CONNECTIVITY ; Untyped ; ; PORT_VCOUNDERRANGE ; PORT_CONNECTIVITY ; Untyped ; ; M_TEST_SOURCE ; 5 ; Untyped ; ; C0_TEST_SOURCE ; 5 ; Untyped ; ; C1_TEST_SOURCE ; 5 ; Untyped ; ; C2_TEST_SOURCE ; 5 ; Untyped ; ; C3_TEST_SOURCE ; 5 ; Untyped ; ; C4_TEST_SOURCE ; 5 ; Untyped ; ; C5_TEST_SOURCE ; 5 ; Untyped ; ; C6_TEST_SOURCE ; 5 ; Untyped ; ; C7_TEST_SOURCE ; 5 ; Untyped ; ; C8_TEST_SOURCE ; 5 ; Untyped ; ; C9_TEST_SOURCE ; 5 ; Untyped ; ; CBXI_PARAMETER ; pll_altpll ; Untyped ; ; VCO_FREQUENCY_CONTROL ; AUTO ; Untyped ; ; VCO_PHASE_SHIFT_STEP ; 0 ; Untyped ; ; WIDTH_CLOCK ; 5 ; Signed Integer ; ; WIDTH_PHASECOUNTERSELECT ; 4 ; Untyped ; ; USING_FBMIMICBIDIR_PORT ; OFF ; Untyped ; ; DEVICE_FAMILY ; MAX 10 ; Untyped ; ; SCAN_CHAIN_MIF_FILE ; UNUSED ; Untyped ; ; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF ; Untyped ; ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +-------------------------------+-----------------------+---------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +--------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: slave_timing_6502:bus_adapt ; +----------------+-------+-------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-------------------------------------------------+ ; address_bits ; 8 ; Signed Integer ; +----------------+-------+-------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-----------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:\POKEY_ON:0:pokeyx ; +----------------------+-------+----------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------------+-------+----------------------------------------+ ; custom_keyboard_scan ; 2 ; Signed Integer ; +----------------------+-------+----------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:\POKEY_ON:0:pokeyx|complete_address_decoder:decode_addr1 ; +----------------+-------+------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+------------------------------------------------------------------------------------+ ; width ; 4 ; Signed Integer ; +----------------+-------+------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +---------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf0_delay ; +----------------+-------+--------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+--------------------------------------------------------------------------+ ; count ; 1 ; Signed Integer ; ; width ; 8 ; Signed Integer ; +----------------+-------+--------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +---------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf1_delay ; +----------------+-------+--------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+--------------------------------------------------------------------------+ ; count ; 1 ; Signed Integer ; ; width ; 8 ; Signed Integer ; +----------------+-------+--------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +---------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf2_delay ; +----------------+-------+--------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+--------------------------------------------------------------------------+ ; count ; 1 ; Signed Integer ; ; width ; 8 ; Signed Integer ; +----------------+-------+--------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +---------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf3_delay ; +----------------+-------+--------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+--------------------------------------------------------------------------+ ; count ; 1 ; Signed Integer ; ; width ; 8 ; Signed Integer ; +----------------+-------+--------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +----------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audctl_delay ; +----------------+-------+---------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+---------------------------------------------------------------------------+ ; count ; 1 ; Signed Integer ; ; width ; 8 ; Signed Integer ; +----------------+-------+---------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +----------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:\POKEY_ON:0:pokeyx|pokey_countdown_timer:timer0 ; +-----------------+-------+--------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +-----------------+-------+--------------------------------------------------------------------------+ ; underflow_delay ; 3 ; Signed Integer ; +-----------------+-------+--------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +--------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:\POKEY_ON:0:pokeyx|pokey_countdown_timer:timer0|delay_line:underflow0_delay ; +----------------+-------+-------------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-------------------------------------------------------------------------------------------------------+ ; count ; 3 ; Signed Integer ; +----------------+-------+-------------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +----------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:\POKEY_ON:0:pokeyx|pokey_countdown_timer:timer1 ; +-----------------+-------+--------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +-----------------+-------+--------------------------------------------------------------------------+ ; underflow_delay ; 3 ; Signed Integer ; +-----------------+-------+--------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +--------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:\POKEY_ON:0:pokeyx|pokey_countdown_timer:timer1|delay_line:underflow0_delay ; +----------------+-------+-------------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-------------------------------------------------------------------------------------------------------+ ; count ; 3 ; Signed Integer ; +----------------+-------+-------------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +----------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:\POKEY_ON:0:pokeyx|pokey_countdown_timer:timer2 ; +-----------------+-------+--------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +-----------------+-------+--------------------------------------------------------------------------+ ; underflow_delay ; 3 ; Signed Integer ; +-----------------+-------+--------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +--------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:\POKEY_ON:0:pokeyx|pokey_countdown_timer:timer2|delay_line:underflow0_delay ; +----------------+-------+-------------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-------------------------------------------------------------------------------------------------------+ ; count ; 3 ; Signed Integer ; +----------------+-------+-------------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +----------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:\POKEY_ON:0:pokeyx|pokey_countdown_timer:timer3 ; +-----------------+-------+--------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +-----------------+-------+--------------------------------------------------------------------------+ ; underflow_delay ; 3 ; Signed Integer ; +-----------------+-------+--------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +--------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:\POKEY_ON:0:pokeyx|pokey_countdown_timer:timer3|delay_line:underflow0_delay ; +----------------+-------+-------------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-------------------------------------------------------------------------------------------------------+ ; count ; 3 ; Signed Integer ; +----------------+-------+-------------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +----------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:\POKEY_ON:0:pokeyx|latch_delay_line:twotone_del ; +----------------+-------+---------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+---------------------------------------------------------------------------+ ; count ; 2 ; Signed Integer ; +----------------+-------+---------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-----------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:\POKEY_ON:0:pokeyx|latch_delay_line:stimer_delay ; +----------------+-------+----------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+----------------------------------------------------------------------------+ ; count ; 3 ; Signed Integer ; +----------------+-------+----------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +--------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:\POKEY_ON:0:pokeyx|syncreset_enable_divider:enable_64_div ; +----------------+-------+-------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-------------------------------------------------------------------------------------+ ; count ; 28 ; Signed Integer ; ; resetcount ; 7 ; Signed Integer ; +----------------+-------+-------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +--------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:\POKEY_ON:0:pokeyx|syncreset_enable_divider:enable_15_div ; +----------------+-------+-------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-------------------------------------------------------------------------------------+ ; count ; 114 ; Signed Integer ; ; resetcount ; 34 ; Signed Integer ; +----------------+-------+-------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-----------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:\POKEY_ON:0:pokeyx|delay_line:serout_clock_delay ; +----------------+-------+----------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+----------------------------------------------------------------------------+ ; count ; 2 ; Signed Integer ; +----------------+-------+----------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +----------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:\POKEY_ON:0:pokeyx|delay_line:serin_clock_delay ; +----------------+-------+---------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+---------------------------------------------------------------------------+ ; count ; 5 ; Signed Integer ; +----------------+-------+---------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-----------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:\POKEY_ON:1:pokeyx ; +----------------------+-------+----------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------------+-------+----------------------------------------+ ; custom_keyboard_scan ; 2 ; Signed Integer ; +----------------------+-------+----------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:\POKEY_ON:1:pokeyx|complete_address_decoder:decode_addr1 ; +----------------+-------+------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+------------------------------------------------------------------------------------+ ; width ; 4 ; Signed Integer ; +----------------+-------+------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +---------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:\POKEY_ON:1:pokeyx|wide_delay_line:audf0_delay ; +----------------+-------+--------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+--------------------------------------------------------------------------+ ; count ; 1 ; Signed Integer ; ; width ; 8 ; Signed Integer ; +----------------+-------+--------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +---------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:\POKEY_ON:1:pokeyx|wide_delay_line:audf1_delay ; +----------------+-------+--------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+--------------------------------------------------------------------------+ ; count ; 1 ; Signed Integer ; ; width ; 8 ; Signed Integer ; +----------------+-------+--------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +---------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:\POKEY_ON:1:pokeyx|wide_delay_line:audf2_delay ; +----------------+-------+--------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+--------------------------------------------------------------------------+ ; count ; 1 ; Signed Integer ; ; width ; 8 ; Signed Integer ; +----------------+-------+--------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +---------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:\POKEY_ON:1:pokeyx|wide_delay_line:audf3_delay ; +----------------+-------+--------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+--------------------------------------------------------------------------+ ; count ; 1 ; Signed Integer ; ; width ; 8 ; Signed Integer ; +----------------+-------+--------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +----------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:\POKEY_ON:1:pokeyx|wide_delay_line:audctl_delay ; +----------------+-------+---------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+---------------------------------------------------------------------------+ ; count ; 1 ; Signed Integer ; ; width ; 8 ; Signed Integer ; +----------------+-------+---------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +----------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:\POKEY_ON:1:pokeyx|pokey_countdown_timer:timer0 ; +-----------------+-------+--------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +-----------------+-------+--------------------------------------------------------------------------+ ; underflow_delay ; 3 ; Signed Integer ; +-----------------+-------+--------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +--------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:\POKEY_ON:1:pokeyx|pokey_countdown_timer:timer0|delay_line:underflow0_delay ; +----------------+-------+-------------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-------------------------------------------------------------------------------------------------------+ ; count ; 3 ; Signed Integer ; +----------------+-------+-------------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +----------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:\POKEY_ON:1:pokeyx|pokey_countdown_timer:timer1 ; +-----------------+-------+--------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +-----------------+-------+--------------------------------------------------------------------------+ ; underflow_delay ; 3 ; Signed Integer ; +-----------------+-------+--------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +--------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:\POKEY_ON:1:pokeyx|pokey_countdown_timer:timer1|delay_line:underflow0_delay ; +----------------+-------+-------------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-------------------------------------------------------------------------------------------------------+ ; count ; 3 ; Signed Integer ; +----------------+-------+-------------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +----------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:\POKEY_ON:1:pokeyx|pokey_countdown_timer:timer2 ; +-----------------+-------+--------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +-----------------+-------+--------------------------------------------------------------------------+ ; underflow_delay ; 3 ; Signed Integer ; +-----------------+-------+--------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +--------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:\POKEY_ON:1:pokeyx|pokey_countdown_timer:timer2|delay_line:underflow0_delay ; +----------------+-------+-------------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-------------------------------------------------------------------------------------------------------+ ; count ; 3 ; Signed Integer ; +----------------+-------+-------------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +----------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:\POKEY_ON:1:pokeyx|pokey_countdown_timer:timer3 ; +-----------------+-------+--------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +-----------------+-------+--------------------------------------------------------------------------+ ; underflow_delay ; 3 ; Signed Integer ; +-----------------+-------+--------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +--------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:\POKEY_ON:1:pokeyx|pokey_countdown_timer:timer3|delay_line:underflow0_delay ; +----------------+-------+-------------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-------------------------------------------------------------------------------------------------------+ ; count ; 3 ; Signed Integer ; +----------------+-------+-------------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +----------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:\POKEY_ON:1:pokeyx|latch_delay_line:twotone_del ; +----------------+-------+---------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+---------------------------------------------------------------------------+ ; count ; 2 ; Signed Integer ; +----------------+-------+---------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-----------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:\POKEY_ON:1:pokeyx|latch_delay_line:stimer_delay ; +----------------+-------+----------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+----------------------------------------------------------------------------+ ; count ; 3 ; Signed Integer ; +----------------+-------+----------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +--------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:\POKEY_ON:1:pokeyx|syncreset_enable_divider:enable_64_div ; +----------------+-------+-------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-------------------------------------------------------------------------------------+ ; count ; 28 ; Signed Integer ; ; resetcount ; 7 ; Signed Integer ; +----------------+-------+-------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +--------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:\POKEY_ON:1:pokeyx|syncreset_enable_divider:enable_15_div ; +----------------+-------+-------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-------------------------------------------------------------------------------------+ ; count ; 114 ; Signed Integer ; ; resetcount ; 34 ; Signed Integer ; +----------------+-------+-------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-----------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:\POKEY_ON:1:pokeyx|delay_line:serout_clock_delay ; +----------------+-------+----------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+----------------------------------------------------------------------------+ ; count ; 2 ; Signed Integer ; +----------------+-------+----------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +----------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:\POKEY_ON:1:pokeyx|delay_line:serin_clock_delay ; +----------------+-------+---------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+---------------------------------------------------------------------------+ ; count ; 5 ; Signed Integer ; +----------------+-------+---------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-----------------------------------------------------------+ ; Parameter Settings for User Entity Instance: SID_top:sid1 ; +----------------+-------------------+----------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------------------+----------------------+ ; wave_base ; 01010011000000000 ; Unsigned Binary ; +----------------+-------------------+----------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: SID_top:sid1|complete_address_decoder:decode_addr1 ; +----------------+-------+------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+------------------------------------------------------------------------+ ; width ; 5 ; Signed Integer ; +----------------+-------+------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-----------------------------------------------------------+ ; Parameter Settings for User Entity Instance: SID_top:sid2 ; +----------------+-------------------+----------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------------------+----------------------+ ; wave_base ; 01010011000000000 ; Unsigned Binary ; +----------------+-------------------+----------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: SID_top:sid2|complete_address_decoder:decode_addr1 ; +----------------+-------+------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+------------------------------------------------------------------------+ ; width ; 5 ; Signed Integer ; +----------------+-------+------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +----------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: PSG_top:\psg_on:PSG_1|complete_address_decoder:decode_addr1 ; +----------------+-------+---------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+---------------------------------------------------------------------------------+ ; width ; 4 ; Signed Integer ; +----------------+-------+---------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +--------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: PSG_top:\psg_on:PSG_1|PSG_freqdiv:core_ticker ; +----------------+-------+-------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-------------------------------------------------------------------+ ; bits ; 4 ; Signed Integer ; +----------------+-------+-------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: PSG_top:\psg_on:PSG_1|PSG_freqdiv:channel_a_ticker ; +----------------+-------+------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+------------------------------------------------------------------------+ ; bits ; 12 ; Signed Integer ; +----------------+-------+------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: PSG_top:\psg_on:PSG_1|PSG_freqdiv:channel_b_ticker ; +----------------+-------+------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+------------------------------------------------------------------------+ ; bits ; 12 ; Signed Integer ; +----------------+-------+------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: PSG_top:\psg_on:PSG_1|PSG_freqdiv:channel_c_ticker ; +----------------+-------+------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+------------------------------------------------------------------------+ ; bits ; 12 ; Signed Integer ; +----------------+-------+------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: PSG_top:\psg_on:PSG_1|PSG_freqdiv:noise_preticker ; +----------------+-------+-----------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------------------------------+ ; bits ; 2 ; Signed Integer ; +----------------+-------+-----------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +---------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: PSG_top:\psg_on:PSG_1|PSG_freqdiv:noise_ticker ; +----------------+-------+--------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+--------------------------------------------------------------------+ ; bits ; 5 ; Signed Integer ; +----------------+-------+--------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +----------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: PSG_top:\psg_on:PSG_1|PSG_envelope:envelope|PSG_freqdiv:envelope_ticker ; +----------------+-------+---------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+---------------------------------------------------------------------------------------------+ ; bits ; 16 ; Signed Integer ; +----------------+-------+---------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +----------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: PSG_top:\psg_on:PSG_2|complete_address_decoder:decode_addr1 ; +----------------+-------+---------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+---------------------------------------------------------------------------------+ ; width ; 4 ; Signed Integer ; +----------------+-------+---------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +--------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: PSG_top:\psg_on:PSG_2|PSG_freqdiv:core_ticker ; +----------------+-------+-------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-------------------------------------------------------------------+ ; bits ; 4 ; Signed Integer ; +----------------+-------+-------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: PSG_top:\psg_on:PSG_2|PSG_freqdiv:channel_a_ticker ; +----------------+-------+------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+------------------------------------------------------------------------+ ; bits ; 12 ; Signed Integer ; +----------------+-------+------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: PSG_top:\psg_on:PSG_2|PSG_freqdiv:channel_b_ticker ; +----------------+-------+------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+------------------------------------------------------------------------+ ; bits ; 12 ; Signed Integer ; +----------------+-------+------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: PSG_top:\psg_on:PSG_2|PSG_freqdiv:channel_c_ticker ; +----------------+-------+------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+------------------------------------------------------------------------+ ; bits ; 12 ; Signed Integer ; +----------------+-------+------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: PSG_top:\psg_on:PSG_2|PSG_freqdiv:noise_preticker ; +----------------+-------+-----------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------------------------------+ ; bits ; 2 ; Signed Integer ; +----------------+-------+-----------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +---------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: PSG_top:\psg_on:PSG_2|PSG_freqdiv:noise_ticker ; +----------------+-------+--------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+--------------------------------------------------------------------+ ; bits ; 5 ; Signed Integer ; +----------------+-------+--------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +----------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: PSG_top:\psg_on:PSG_2|PSG_envelope:envelope|PSG_freqdiv:envelope_ticker ; +----------------+-------+---------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+---------------------------------------------------------------------------------------------+ ; bits ; 16 ; Signed Integer ; +----------------+-------+---------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: sample_top:\sample_on:sample1|complete_address_decoder:decode_addr2 ; +----------------+-------+-----------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------------------------------------------------+ ; width ; 5 ; Signed Integer ; +----------------+-------+-----------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: generic_ram_infer:\sample_on:normal_ram:sample_ram_inst ; +----------------+-------+-----------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------------------------------------+ ; address_width ; 16 ; Signed Integer ; ; space ; 43008 ; Signed Integer ; ; data_width ; 8 ; Signed Integer ; +----------------+-------+-----------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: complete_address_decoder:\gen_config:decode_addr1 ; +----------------+-------+-----------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------------------------------+ ; width ; 4 ; Signed Integer ; +----------------+-------+-----------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: sigmadelta_dither:dac_dithergen ; +----------------+------------------+------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+------------------+------------------------------------------+ ; lfsr_seed ; 1010110011100001 ; Unsigned Binary ; +----------------+------------------+------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: filtered_sigmadelta:dac_0 ; +----------------+-------+-----------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------+ ; implementation ; 4 ; Signed Integer ; ; lowpass ; 0 ; Signed Integer ; +----------------+-------+-----------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: filtered_sigmadelta:dac_0|sigmadelta_2ndorder_dither:\gen_2ndorder_dither_on:dac_2nd_dither ; +----------------+-------+-----------------------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------------------------------------------------------------------------+ ; dither_enable ; 1 ; Signed Integer ; ; dither_bits ; 3 ; Signed Integer ; +----------------+-------+-----------------------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: filtered_sigmadelta:dac_2 ; +----------------+-------+-----------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------+ ; implementation ; 4 ; Signed Integer ; ; lowpass ; 0 ; Signed Integer ; +----------------+-------+-----------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: filtered_sigmadelta:dac_2|sigmadelta_2ndorder_dither:\gen_2ndorder_dither_on:dac_2nd_dither ; +----------------+-------+-----------------------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------------------------------------------------------------------------+ ; dither_enable ; 1 ; Signed Integer ; ; dither_bits ; 3 ; Signed Integer ; +----------------+-------+-----------------------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: filtered_sigmadelta:dac_3 ; +----------------+-------+-----------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------+ ; implementation ; 4 ; Signed Integer ; ; lowpass ; 0 ; Signed Integer ; +----------------+-------+-----------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: filtered_sigmadelta:dac_3|sigmadelta_2ndorder_dither:\gen_2ndorder_dither_on:dac_2nd_dither ; +----------------+-------+-----------------------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------------------------------------------------------------------------+ ; dither_enable ; 1 ; Signed Integer ; ; dither_bits ; 3 ; Signed Integer ; +----------------+-------+-----------------------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +---------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: sigma_delta_adc:sdelta ; +------------------+-------+------------------------------------------+ ; Parameter Name ; Value ; Type ; +------------------+-------+------------------------------------------+ ; OVERSAMPLE_RATE ; 1024 ; Signed Integer ; ; CIC_STAGES ; 2 ; Signed Integer ; ; ADC_BITLEN ; 20 ; Signed Integer ; ; USE_FIR_COMP ; 1 ; Unsigned Binary ; ; FIR_COMP_ALPHA_8 ; 2 ; Signed Integer ; +------------------+-------+------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-----------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: sigma_delta_adc:sdelta|cic_integrator:gen_cic[0].cic_inst_u0 ; +----------------+-------+----------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+----------------------------------------------------------------------------------+ ; WIDTH ; 22 ; Signed Integer ; +----------------+-------+----------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-----------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: sigma_delta_adc:sdelta|cic_comb:gen_cic[0].cic_inst_u1 ; +----------------+-------+----------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+----------------------------------------------------------------------------+ ; WIDTH ; 22 ; Signed Integer ; +----------------+-------+----------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-----------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: sigma_delta_adc:sdelta|cic_integrator:gen_cic[1].cic_inst_u0 ; +----------------+-------+----------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+----------------------------------------------------------------------------------+ ; WIDTH ; 22 ; Signed Integer ; +----------------+-------+----------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-----------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: sigma_delta_adc:sdelta|cic_comb:gen_cic[1].cic_inst_u1 ; +----------------+-------+----------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+----------------------------------------------------------------------------+ ; WIDTH ; 22 ; Signed Integer ; +----------------+-------+----------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +---------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: sigma_delta_adc:sdelta|fir_compensator:gen_fir.fir_comp_u0 ; +----------------+-------+--------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+--------------------------------------------------------------------------------+ ; WIDTH ; 22 ; Signed Integer ; ; ALPHA_8 ; 2 ; Signed Integer ; +----------------+-------+--------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for Inferred Entity Instance: generic_ram_infer:\sample_on:normal_ram:sample_ram_inst|altsyncram:ram_block_rtl_0 ; +------------------------------------+----------------------+-------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +------------------------------------+----------------------+-------------------------------------------------------------------------+ ; BYTE_SIZE_BLOCK ; 8 ; Untyped ; ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ; WIDTH_BYTEENA ; 1 ; Untyped ; ; OPERATION_MODE ; SINGLE_PORT ; Untyped ; ; WIDTH_A ; 8 ; Untyped ; ; WIDTHAD_A ; 16 ; Untyped ; ; NUMWORDS_A ; 43008 ; Untyped ; ; OUTDATA_REG_A ; UNREGISTERED ; Untyped ; ; ADDRESS_ACLR_A ; NONE ; Untyped ; ; OUTDATA_ACLR_A ; NONE ; Untyped ; ; WRCONTROL_ACLR_A ; NONE ; Untyped ; ; INDATA_ACLR_A ; NONE ; Untyped ; ; BYTEENA_ACLR_A ; NONE ; Untyped ; ; WIDTH_B ; 1 ; Untyped ; ; WIDTHAD_B ; 1 ; Untyped ; ; NUMWORDS_B ; 1 ; Untyped ; ; INDATA_REG_B ; CLOCK1 ; Untyped ; ; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; ; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; ; ADDRESS_REG_B ; CLOCK1 ; Untyped ; ; OUTDATA_REG_B ; UNREGISTERED ; Untyped ; ; BYTEENA_REG_B ; CLOCK1 ; Untyped ; ; INDATA_ACLR_B ; NONE ; Untyped ; ; WRCONTROL_ACLR_B ; NONE ; Untyped ; ; ADDRESS_ACLR_B ; NONE ; Untyped ; ; OUTDATA_ACLR_B ; NONE ; Untyped ; ; RDCONTROL_ACLR_B ; NONE ; Untyped ; ; BYTEENA_ACLR_B ; NONE ; Untyped ; ; WIDTH_BYTEENA_A ; 1 ; Untyped ; ; WIDTH_BYTEENA_B ; 1 ; Untyped ; ; RAM_BLOCK_TYPE ; AUTO ; Untyped ; ; BYTE_SIZE ; 8 ; Untyped ; ; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ; ; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ; ; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ; ; INIT_FILE ; UNUSED ; Untyped ; ; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; ; MAXIMUM_DEPTH ; 0 ; Untyped ; ; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ; ; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ; ; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ; ; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ; ; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; ; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; ; ENABLE_ECC ; FALSE ; Untyped ; ; ECC_PIPELINE_STAGE_ENABLED ; FALSE ; Untyped ; ; WIDTH_ECCSTATUS ; 3 ; Untyped ; ; DEVICE_FAMILY ; MAX 10 ; Untyped ; ; CBXI_PARAMETER ; altsyncram_6t31 ; Untyped ; +------------------------------------+----------------------+-------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +---------------------------------------------------------------------------------------+ ; Parameter Settings for Inferred Entity Instance: clockgensid:clockgen1|lpm_mult:Mult0 ; +------------------------------------------------+----------+---------------------------+ ; Parameter Name ; Value ; Type ; +------------------------------------------------+----------+---------------------------+ ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ; LPM_WIDTHA ; 6 ; Untyped ; ; LPM_WIDTHB ; 9 ; Untyped ; ; LPM_WIDTHP ; 15 ; Untyped ; ; LPM_WIDTHR ; 15 ; Untyped ; ; LPM_WIDTHS ; 1 ; Untyped ; ; LPM_REPRESENTATION ; UNSIGNED ; Untyped ; ; LPM_PIPELINE ; 0 ; Untyped ; ; LATENCY ; 0 ; Untyped ; ; INPUT_A_IS_CONSTANT ; NO ; Untyped ; ; INPUT_B_IS_CONSTANT ; NO ; Untyped ; ; USE_EAB ; OFF ; Untyped ; ; MAXIMIZE_SPEED ; 5 ; Untyped ; ; DEVICE_FAMILY ; MAX 10 ; Untyped ; ; CARRY_CHAIN ; MANUAL ; Untyped ; ; APEX20K_TECHNOLOGY_MAPPER ; LUT ; TECH_MAPPER_APEX20K ; ; DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; Untyped ; ; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; ; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; ; CBXI_PARAMETER ; mult_uks ; Untyped ; ; INPUT_A_FIXED_VALUE ; Bx ; Untyped ; ; INPUT_B_FIXED_VALUE ; Bx ; Untyped ; ; USE_AHDL_IMPLEMENTATION ; OFF ; Untyped ; +------------------------------------------------+----------+---------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +--------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for Inferred Entity Instance: sample_top:\sample_on:sample1|sample_adpcm:adpcm_decoder|lpm_mult:Mult0 ; +------------------------------------------------+----------+--------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +------------------------------------------------+----------+--------------------------------------------------------------+ ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ; LPM_WIDTHA ; 5 ; Untyped ; ; LPM_WIDTHB ; 16 ; Untyped ; ; LPM_WIDTHP ; 21 ; Untyped ; ; LPM_WIDTHR ; 21 ; Untyped ; ; LPM_WIDTHS ; 1 ; Untyped ; ; LPM_REPRESENTATION ; SIGNED ; Untyped ; ; LPM_PIPELINE ; 0 ; Untyped ; ; LATENCY ; 0 ; Untyped ; ; INPUT_A_IS_CONSTANT ; NO ; Untyped ; ; INPUT_B_IS_CONSTANT ; NO ; Untyped ; ; USE_EAB ; OFF ; Untyped ; ; MAXIMIZE_SPEED ; 5 ; Untyped ; ; DEVICE_FAMILY ; MAX 10 ; Untyped ; ; CARRY_CHAIN ; MANUAL ; Untyped ; ; APEX20K_TECHNOLOGY_MAPPER ; LUT ; TECH_MAPPER_APEX20K ; ; DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; Untyped ; ; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; ; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; ; CBXI_PARAMETER ; mult_5fs ; Untyped ; ; INPUT_A_FIXED_VALUE ; Bx ; Untyped ; ; INPUT_B_FIXED_VALUE ; Bx ; Untyped ; ; USE_AHDL_IMPLEMENTATION ; OFF ; Untyped ; +------------------------------------------------+----------+--------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-----------------------------------------------------------------------------------------------+ ; Parameter Settings for Inferred Entity Instance: sample_top:\sample_on:sample1|lpm_mult:Mult3 ; +------------------------------------------------+----------+-----------------------------------+ ; Parameter Name ; Value ; Type ; +------------------------------------------------+----------+-----------------------------------+ ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ; LPM_WIDTHA ; 13 ; Untyped ; ; LPM_WIDTHB ; 7 ; Untyped ; ; LPM_WIDTHP ; 20 ; Untyped ; ; LPM_WIDTHR ; 20 ; Untyped ; ; LPM_WIDTHS ; 1 ; Untyped ; ; LPM_REPRESENTATION ; SIGNED ; Untyped ; ; LPM_PIPELINE ; 0 ; Untyped ; ; LATENCY ; 0 ; Untyped ; ; INPUT_A_IS_CONSTANT ; NO ; Untyped ; ; INPUT_B_IS_CONSTANT ; NO ; Untyped ; ; USE_EAB ; OFF ; Untyped ; ; MAXIMIZE_SPEED ; 6 ; Untyped ; ; DEVICE_FAMILY ; MAX 10 ; Untyped ; ; CARRY_CHAIN ; MANUAL ; Untyped ; ; APEX20K_TECHNOLOGY_MAPPER ; LUT ; TECH_MAPPER_APEX20K ; ; DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; Untyped ; ; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; ; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; ; CBXI_PARAMETER ; mult_4fs ; Untyped ; ; INPUT_A_FIXED_VALUE ; Bx ; Untyped ; ; INPUT_B_FIXED_VALUE ; Bx ; Untyped ; ; USE_AHDL_IMPLEMENTATION ; OFF ; Untyped ; +------------------------------------------------+----------+-----------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-----------------------------------------------------------------------------------------------+ ; Parameter Settings for Inferred Entity Instance: sample_top:\sample_on:sample1|lpm_mult:Mult2 ; +------------------------------------------------+----------+-----------------------------------+ ; Parameter Name ; Value ; Type ; +------------------------------------------------+----------+-----------------------------------+ ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ; LPM_WIDTHA ; 13 ; Untyped ; ; LPM_WIDTHB ; 7 ; Untyped ; ; LPM_WIDTHP ; 20 ; Untyped ; ; LPM_WIDTHR ; 20 ; Untyped ; ; LPM_WIDTHS ; 1 ; Untyped ; ; LPM_REPRESENTATION ; SIGNED ; Untyped ; ; LPM_PIPELINE ; 0 ; Untyped ; ; LATENCY ; 0 ; Untyped ; ; INPUT_A_IS_CONSTANT ; NO ; Untyped ; ; INPUT_B_IS_CONSTANT ; NO ; Untyped ; ; USE_EAB ; OFF ; Untyped ; ; MAXIMIZE_SPEED ; 6 ; Untyped ; ; DEVICE_FAMILY ; MAX 10 ; Untyped ; ; CARRY_CHAIN ; MANUAL ; Untyped ; ; APEX20K_TECHNOLOGY_MAPPER ; LUT ; TECH_MAPPER_APEX20K ; ; DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; Untyped ; ; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; ; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; ; CBXI_PARAMETER ; mult_4fs ; Untyped ; ; INPUT_A_FIXED_VALUE ; Bx ; Untyped ; ; INPUT_B_FIXED_VALUE ; Bx ; Untyped ; ; USE_AHDL_IMPLEMENTATION ; OFF ; Untyped ; +------------------------------------------------+----------+-----------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-----------------------------------------------------------------------------------------------------------+ ; Parameter Settings for Inferred Entity Instance: SID_top:sid2|SID_postFilterSum:postfilter|lpm_mult:Mult0 ; +------------------------------------------------+----------+-----------------------------------------------+ ; Parameter Name ; Value ; Type ; +------------------------------------------------+----------+-----------------------------------------------+ ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ; LPM_WIDTHA ; 18 ; Untyped ; ; LPM_WIDTHB ; 8 ; Untyped ; ; LPM_WIDTHP ; 26 ; Untyped ; ; LPM_WIDTHR ; 26 ; Untyped ; ; LPM_WIDTHS ; 1 ; Untyped ; ; LPM_REPRESENTATION ; SIGNED ; Untyped ; ; LPM_PIPELINE ; 0 ; Untyped ; ; LATENCY ; 0 ; Untyped ; ; INPUT_A_IS_CONSTANT ; NO ; Untyped ; ; INPUT_B_IS_CONSTANT ; NO ; Untyped ; ; USE_EAB ; OFF ; Untyped ; ; MAXIMIZE_SPEED ; 6 ; Untyped ; ; DEVICE_FAMILY ; MAX 10 ; Untyped ; ; CARRY_CHAIN ; MANUAL ; Untyped ; ; APEX20K_TECHNOLOGY_MAPPER ; LUT ; TECH_MAPPER_APEX20K ; ; DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; Untyped ; ; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; ; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; ; CBXI_PARAMETER ; mult_gfs ; Untyped ; ; INPUT_A_FIXED_VALUE ; Bx ; Untyped ; ; INPUT_B_FIXED_VALUE ; Bx ; Untyped ; ; USE_AHDL_IMPLEMENTATION ; OFF ; Untyped ; +------------------------------------------------+----------+-----------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-----------------------------------------------------------------------------------------------+ ; Parameter Settings for Inferred Entity Instance: sample_top:\sample_on:sample1|lpm_mult:Mult1 ; +------------------------------------------------+----------+-----------------------------------+ ; Parameter Name ; Value ; Type ; +------------------------------------------------+----------+-----------------------------------+ ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ; LPM_WIDTHA ; 13 ; Untyped ; ; LPM_WIDTHB ; 7 ; Untyped ; ; LPM_WIDTHP ; 20 ; Untyped ; ; LPM_WIDTHR ; 20 ; Untyped ; ; LPM_WIDTHS ; 1 ; Untyped ; ; LPM_REPRESENTATION ; SIGNED ; Untyped ; ; LPM_PIPELINE ; 0 ; Untyped ; ; LATENCY ; 0 ; Untyped ; ; INPUT_A_IS_CONSTANT ; NO ; Untyped ; ; INPUT_B_IS_CONSTANT ; NO ; Untyped ; ; USE_EAB ; OFF ; Untyped ; ; MAXIMIZE_SPEED ; 6 ; Untyped ; ; DEVICE_FAMILY ; MAX 10 ; Untyped ; ; CARRY_CHAIN ; MANUAL ; Untyped ; ; APEX20K_TECHNOLOGY_MAPPER ; LUT ; TECH_MAPPER_APEX20K ; ; DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; Untyped ; ; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; ; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; ; CBXI_PARAMETER ; mult_4fs ; Untyped ; ; INPUT_A_FIXED_VALUE ; Bx ; Untyped ; ; INPUT_B_FIXED_VALUE ; Bx ; Untyped ; ; USE_AHDL_IMPLEMENTATION ; OFF ; Untyped ; +------------------------------------------------+----------+-----------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-----------------------------------------------------------------------------------------------+ ; Parameter Settings for Inferred Entity Instance: sample_top:\sample_on:sample1|lpm_mult:Mult0 ; +------------------------------------------------+----------+-----------------------------------+ ; Parameter Name ; Value ; Type ; +------------------------------------------------+----------+-----------------------------------+ ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ; LPM_WIDTHA ; 13 ; Untyped ; ; LPM_WIDTHB ; 7 ; Untyped ; ; LPM_WIDTHP ; 20 ; Untyped ; ; LPM_WIDTHR ; 20 ; Untyped ; ; LPM_WIDTHS ; 1 ; Untyped ; ; LPM_REPRESENTATION ; SIGNED ; Untyped ; ; LPM_PIPELINE ; 0 ; Untyped ; ; LATENCY ; 0 ; Untyped ; ; INPUT_A_IS_CONSTANT ; NO ; Untyped ; ; INPUT_B_IS_CONSTANT ; NO ; Untyped ; ; USE_EAB ; OFF ; Untyped ; ; MAXIMIZE_SPEED ; 6 ; Untyped ; ; DEVICE_FAMILY ; MAX 10 ; Untyped ; ; CARRY_CHAIN ; MANUAL ; Untyped ; ; APEX20K_TECHNOLOGY_MAPPER ; LUT ; TECH_MAPPER_APEX20K ; ; DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; Untyped ; ; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; ; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; ; CBXI_PARAMETER ; mult_4fs ; Untyped ; ; INPUT_A_FIXED_VALUE ; Bx ; Untyped ; ; INPUT_B_FIXED_VALUE ; Bx ; Untyped ; ; USE_AHDL_IMPLEMENTATION ; OFF ; Untyped ; +------------------------------------------------+----------+-----------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-----------------------------------------------------------------------------------------------------------+ ; Parameter Settings for Inferred Entity Instance: SID_top:sid1|SID_postFilterSum:postfilter|lpm_mult:Mult0 ; +------------------------------------------------+----------+-----------------------------------------------+ ; Parameter Name ; Value ; Type ; +------------------------------------------------+----------+-----------------------------------------------+ ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ; LPM_WIDTHA ; 18 ; Untyped ; ; LPM_WIDTHB ; 8 ; Untyped ; ; LPM_WIDTHP ; 26 ; Untyped ; ; LPM_WIDTHR ; 26 ; Untyped ; ; LPM_WIDTHS ; 1 ; Untyped ; ; LPM_REPRESENTATION ; SIGNED ; Untyped ; ; LPM_PIPELINE ; 0 ; Untyped ; ; LATENCY ; 0 ; Untyped ; ; INPUT_A_IS_CONSTANT ; NO ; Untyped ; ; INPUT_B_IS_CONSTANT ; NO ; Untyped ; ; USE_EAB ; OFF ; Untyped ; ; MAXIMIZE_SPEED ; 6 ; Untyped ; ; DEVICE_FAMILY ; MAX 10 ; Untyped ; ; CARRY_CHAIN ; MANUAL ; Untyped ; ; APEX20K_TECHNOLOGY_MAPPER ; LUT ; TECH_MAPPER_APEX20K ; ; DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; Untyped ; ; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; ; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; ; CBXI_PARAMETER ; mult_gfs ; Untyped ; ; INPUT_A_FIXED_VALUE ; Bx ; Untyped ; ; INPUT_B_FIXED_VALUE ; Bx ; Untyped ; ; USE_AHDL_IMPLEMENTATION ; OFF ; Untyped ; +------------------------------------------------+----------+-----------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for Inferred Entity Instance: SID_top:sid2|SID_amplitudeModulator:vol_abc|lpm_mult:Mult0 ; +------------------------------------------------+----------+-------------------------------------------------+ ; Parameter Name ; Value ; Type ; +------------------------------------------------+----------+-------------------------------------------------+ ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ; LPM_WIDTHA ; 9 ; Untyped ; ; LPM_WIDTHB ; 12 ; Untyped ; ; LPM_WIDTHP ; 21 ; Untyped ; ; LPM_WIDTHR ; 21 ; Untyped ; ; LPM_WIDTHS ; 1 ; Untyped ; ; LPM_REPRESENTATION ; SIGNED ; Untyped ; ; LPM_PIPELINE ; 0 ; Untyped ; ; LATENCY ; 0 ; Untyped ; ; INPUT_A_IS_CONSTANT ; NO ; Untyped ; ; INPUT_B_IS_CONSTANT ; NO ; Untyped ; ; USE_EAB ; OFF ; Untyped ; ; MAXIMIZE_SPEED ; 6 ; Untyped ; ; DEVICE_FAMILY ; MAX 10 ; Untyped ; ; CARRY_CHAIN ; MANUAL ; Untyped ; ; APEX20K_TECHNOLOGY_MAPPER ; LUT ; TECH_MAPPER_APEX20K ; ; DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; Untyped ; ; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; ; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; ; CBXI_PARAMETER ; mult_6fs ; Untyped ; ; INPUT_A_FIXED_VALUE ; Bx ; Untyped ; ; INPUT_B_FIXED_VALUE ; Bx ; Untyped ; ; USE_AHDL_IMPLEMENTATION ; OFF ; Untyped ; +------------------------------------------------+----------+-------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +---------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for Inferred Entity Instance: SID_top:sid2|SID_filter:variable_state_filter|lpm_mult:Mult4 ; +------------------------------------------------+----------+---------------------------------------------------+ ; Parameter Name ; Value ; Type ; +------------------------------------------------+----------+---------------------------------------------------+ ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ; LPM_WIDTHA ; 14 ; Untyped ; ; LPM_WIDTHB ; 36 ; Untyped ; ; LPM_WIDTHP ; 50 ; Untyped ; ; LPM_WIDTHR ; 50 ; Untyped ; ; LPM_WIDTHS ; 1 ; Untyped ; ; LPM_REPRESENTATION ; SIGNED ; Untyped ; ; LPM_PIPELINE ; 0 ; Untyped ; ; LATENCY ; 0 ; Untyped ; ; INPUT_A_IS_CONSTANT ; NO ; Untyped ; ; INPUT_B_IS_CONSTANT ; NO ; Untyped ; ; USE_EAB ; OFF ; Untyped ; ; MAXIMIZE_SPEED ; 5 ; Untyped ; ; DEVICE_FAMILY ; MAX 10 ; Untyped ; ; CARRY_CHAIN ; MANUAL ; Untyped ; ; APEX20K_TECHNOLOGY_MAPPER ; LUT ; TECH_MAPPER_APEX20K ; ; DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; Untyped ; ; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; ; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; ; CBXI_PARAMETER ; mult_pgs ; Untyped ; ; INPUT_A_FIXED_VALUE ; Bx ; Untyped ; ; INPUT_B_FIXED_VALUE ; Bx ; Untyped ; ; USE_AHDL_IMPLEMENTATION ; OFF ; Untyped ; +------------------------------------------------+----------+---------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for Inferred Entity Instance: SID_top:sid1|SID_amplitudeModulator:vol_abc|lpm_mult:Mult0 ; +------------------------------------------------+----------+-------------------------------------------------+ ; Parameter Name ; Value ; Type ; +------------------------------------------------+----------+-------------------------------------------------+ ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ; LPM_WIDTHA ; 9 ; Untyped ; ; LPM_WIDTHB ; 12 ; Untyped ; ; LPM_WIDTHP ; 21 ; Untyped ; ; LPM_WIDTHR ; 21 ; Untyped ; ; LPM_WIDTHS ; 1 ; Untyped ; ; LPM_REPRESENTATION ; SIGNED ; Untyped ; ; LPM_PIPELINE ; 0 ; Untyped ; ; LATENCY ; 0 ; Untyped ; ; INPUT_A_IS_CONSTANT ; NO ; Untyped ; ; INPUT_B_IS_CONSTANT ; NO ; Untyped ; ; USE_EAB ; OFF ; Untyped ; ; MAXIMIZE_SPEED ; 6 ; Untyped ; ; DEVICE_FAMILY ; MAX 10 ; Untyped ; ; CARRY_CHAIN ; MANUAL ; Untyped ; ; APEX20K_TECHNOLOGY_MAPPER ; LUT ; TECH_MAPPER_APEX20K ; ; DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; Untyped ; ; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; ; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; ; CBXI_PARAMETER ; mult_6fs ; Untyped ; ; INPUT_A_FIXED_VALUE ; Bx ; Untyped ; ; INPUT_B_FIXED_VALUE ; Bx ; Untyped ; ; USE_AHDL_IMPLEMENTATION ; OFF ; Untyped ; +------------------------------------------------+----------+-------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +---------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for Inferred Entity Instance: SID_top:sid1|SID_filter:variable_state_filter|lpm_mult:Mult4 ; +------------------------------------------------+----------+---------------------------------------------------+ ; Parameter Name ; Value ; Type ; +------------------------------------------------+----------+---------------------------------------------------+ ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ; LPM_WIDTHA ; 14 ; Untyped ; ; LPM_WIDTHB ; 36 ; Untyped ; ; LPM_WIDTHP ; 50 ; Untyped ; ; LPM_WIDTHR ; 50 ; Untyped ; ; LPM_WIDTHS ; 1 ; Untyped ; ; LPM_REPRESENTATION ; SIGNED ; Untyped ; ; LPM_PIPELINE ; 0 ; Untyped ; ; LATENCY ; 0 ; Untyped ; ; INPUT_A_IS_CONSTANT ; NO ; Untyped ; ; INPUT_B_IS_CONSTANT ; NO ; Untyped ; ; USE_EAB ; OFF ; Untyped ; ; MAXIMIZE_SPEED ; 5 ; Untyped ; ; DEVICE_FAMILY ; MAX 10 ; Untyped ; ; CARRY_CHAIN ; MANUAL ; Untyped ; ; APEX20K_TECHNOLOGY_MAPPER ; LUT ; TECH_MAPPER_APEX20K ; ; DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; Untyped ; ; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; ; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; ; CBXI_PARAMETER ; mult_pgs ; Untyped ; ; INPUT_A_FIXED_VALUE ; Bx ; Untyped ; ; INPUT_B_FIXED_VALUE ; Bx ; Untyped ; ; USE_AHDL_IMPLEMENTATION ; OFF ; Untyped ; +------------------------------------------------+----------+---------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +---------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for Inferred Entity Instance: SID_top:sid2|SID_filter:variable_state_filter|lpm_mult:Mult3 ; +------------------------------------------------+----------+---------------------------------------------------+ ; Parameter Name ; Value ; Type ; +------------------------------------------------+----------+---------------------------------------------------+ ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ; LPM_WIDTHA ; 14 ; Untyped ; ; LPM_WIDTHB ; 36 ; Untyped ; ; LPM_WIDTHP ; 50 ; Untyped ; ; LPM_WIDTHR ; 50 ; Untyped ; ; LPM_WIDTHS ; 1 ; Untyped ; ; LPM_REPRESENTATION ; SIGNED ; Untyped ; ; LPM_PIPELINE ; 0 ; Untyped ; ; LATENCY ; 0 ; Untyped ; ; INPUT_A_IS_CONSTANT ; NO ; Untyped ; ; INPUT_B_IS_CONSTANT ; NO ; Untyped ; ; USE_EAB ; OFF ; Untyped ; ; MAXIMIZE_SPEED ; 5 ; Untyped ; ; DEVICE_FAMILY ; MAX 10 ; Untyped ; ; CARRY_CHAIN ; MANUAL ; Untyped ; ; APEX20K_TECHNOLOGY_MAPPER ; LUT ; TECH_MAPPER_APEX20K ; ; DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; Untyped ; ; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; ; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; ; CBXI_PARAMETER ; mult_pgs ; Untyped ; ; INPUT_A_FIXED_VALUE ; Bx ; Untyped ; ; INPUT_B_FIXED_VALUE ; Bx ; Untyped ; ; USE_AHDL_IMPLEMENTATION ; OFF ; Untyped ; +------------------------------------------------+----------+---------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +---------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for Inferred Entity Instance: SID_top:sid1|SID_filter:variable_state_filter|lpm_mult:Mult3 ; +------------------------------------------------+----------+---------------------------------------------------+ ; Parameter Name ; Value ; Type ; +------------------------------------------------+----------+---------------------------------------------------+ ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ; LPM_WIDTHA ; 14 ; Untyped ; ; LPM_WIDTHB ; 36 ; Untyped ; ; LPM_WIDTHP ; 50 ; Untyped ; ; LPM_WIDTHR ; 50 ; Untyped ; ; LPM_WIDTHS ; 1 ; Untyped ; ; LPM_REPRESENTATION ; SIGNED ; Untyped ; ; LPM_PIPELINE ; 0 ; Untyped ; ; LATENCY ; 0 ; Untyped ; ; INPUT_A_IS_CONSTANT ; NO ; Untyped ; ; INPUT_B_IS_CONSTANT ; NO ; Untyped ; ; USE_EAB ; OFF ; Untyped ; ; MAXIMIZE_SPEED ; 5 ; Untyped ; ; DEVICE_FAMILY ; MAX 10 ; Untyped ; ; CARRY_CHAIN ; MANUAL ; Untyped ; ; APEX20K_TECHNOLOGY_MAPPER ; LUT ; TECH_MAPPER_APEX20K ; ; DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; Untyped ; ; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; ; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; ; CBXI_PARAMETER ; mult_pgs ; Untyped ; ; INPUT_A_FIXED_VALUE ; Bx ; Untyped ; ; INPUT_B_FIXED_VALUE ; Bx ; Untyped ; ; USE_AHDL_IMPLEMENTATION ; OFF ; Untyped ; +------------------------------------------------+----------+---------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +---------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for Inferred Entity Instance: SID_top:sid2|SID_filter:variable_state_filter|lpm_mult:Mult0 ; +------------------------------------------------+----------+---------------------------------------------------+ ; Parameter Name ; Value ; Type ; +------------------------------------------------+----------+---------------------------------------------------+ ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ; LPM_WIDTHA ; 36 ; Untyped ; ; LPM_WIDTHB ; 18 ; Untyped ; ; LPM_WIDTHP ; 54 ; Untyped ; ; LPM_WIDTHR ; 54 ; Untyped ; ; LPM_WIDTHS ; 1 ; Untyped ; ; LPM_REPRESENTATION ; SIGNED ; Untyped ; ; LPM_PIPELINE ; 0 ; Untyped ; ; LATENCY ; 0 ; Untyped ; ; INPUT_A_IS_CONSTANT ; NO ; Untyped ; ; INPUT_B_IS_CONSTANT ; NO ; Untyped ; ; USE_EAB ; OFF ; Untyped ; ; MAXIMIZE_SPEED ; 5 ; Untyped ; ; DEVICE_FAMILY ; MAX 10 ; Untyped ; ; CARRY_CHAIN ; MANUAL ; Untyped ; ; APEX20K_TECHNOLOGY_MAPPER ; LUT ; TECH_MAPPER_APEX20K ; ; DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; Untyped ; ; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; ; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; ; CBXI_PARAMETER ; mult_1hs ; Untyped ; ; INPUT_A_FIXED_VALUE ; Bx ; Untyped ; ; INPUT_B_FIXED_VALUE ; Bx ; Untyped ; ; USE_AHDL_IMPLEMENTATION ; OFF ; Untyped ; +------------------------------------------------+----------+---------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +---------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for Inferred Entity Instance: SID_top:sid1|SID_filter:variable_state_filter|lpm_mult:Mult0 ; +------------------------------------------------+----------+---------------------------------------------------+ ; Parameter Name ; Value ; Type ; +------------------------------------------------+----------+---------------------------------------------------+ ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ; LPM_WIDTHA ; 36 ; Untyped ; ; LPM_WIDTHB ; 18 ; Untyped ; ; LPM_WIDTHP ; 54 ; Untyped ; ; LPM_WIDTHR ; 54 ; Untyped ; ; LPM_WIDTHS ; 1 ; Untyped ; ; LPM_REPRESENTATION ; SIGNED ; Untyped ; ; LPM_PIPELINE ; 0 ; Untyped ; ; LATENCY ; 0 ; Untyped ; ; INPUT_A_IS_CONSTANT ; NO ; Untyped ; ; INPUT_B_IS_CONSTANT ; NO ; Untyped ; ; USE_EAB ; OFF ; Untyped ; ; MAXIMIZE_SPEED ; 5 ; Untyped ; ; DEVICE_FAMILY ; MAX 10 ; Untyped ; ; CARRY_CHAIN ; MANUAL ; Untyped ; ; APEX20K_TECHNOLOGY_MAPPER ; LUT ; TECH_MAPPER_APEX20K ; ; DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; Untyped ; ; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; ; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; ; CBXI_PARAMETER ; mult_1hs ; Untyped ; ; INPUT_A_FIXED_VALUE ; Bx ; Untyped ; ; INPUT_B_FIXED_VALUE ; Bx ; Untyped ; ; USE_AHDL_IMPLEMENTATION ; OFF ; Untyped ; +------------------------------------------------+----------+---------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for Inferred Entity Instance: SID_f_distortion_mux:f_distortion_mux|SID_f_distortion:f_distortion|lpm_mult:Mult0 ; +------------------------------------------------+----------+-------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +------------------------------------------------+----------+-------------------------------------------------------------------------+ ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ; LPM_WIDTHA ; 13 ; Untyped ; ; LPM_WIDTHB ; 12 ; Untyped ; ; LPM_WIDTHP ; 25 ; Untyped ; ; LPM_WIDTHR ; 25 ; Untyped ; ; LPM_WIDTHS ; 1 ; Untyped ; ; LPM_REPRESENTATION ; UNSIGNED ; Untyped ; ; LPM_PIPELINE ; 0 ; Untyped ; ; LATENCY ; 0 ; Untyped ; ; INPUT_A_IS_CONSTANT ; NO ; Untyped ; ; INPUT_B_IS_CONSTANT ; NO ; Untyped ; ; USE_EAB ; OFF ; Untyped ; ; MAXIMIZE_SPEED ; 6 ; Untyped ; ; DEVICE_FAMILY ; MAX 10 ; Untyped ; ; CARRY_CHAIN ; MANUAL ; Untyped ; ; APEX20K_TECHNOLOGY_MAPPER ; LUT ; TECH_MAPPER_APEX20K ; ; DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; Untyped ; ; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; ; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; ; CBXI_PARAMETER ; mult_ons ; Untyped ; ; INPUT_A_FIXED_VALUE ; Bx ; Untyped ; ; INPUT_B_FIXED_VALUE ; Bx ; Untyped ; ; USE_AHDL_IMPLEMENTATION ; OFF ; Untyped ; +------------------------------------------------+----------+-------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; lpm_shiftreg Parameter Settings by Entity Instance ; +----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Name ; Value ; +----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Number of entity instances ; 1 ; ; Entity Instance ; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|lpm_shiftreg:ufm_data_shiftreg ; ; -- LPM_WIDTH ; 32 ; ; -- LPM_DIRECTION ; LEFT ; +----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +----------------------------------------------------------------------+ ; altpll Parameter Settings by Entity Instance ; +-------------------------------+--------------------------------------+ ; Name ; Value ; +-------------------------------+--------------------------------------+ ; Number of entity instances ; 1 ; ; Entity Instance ; pll:pll_inst|altpll:altpll_component ; ; -- OPERATION_MODE ; NO_COMPENSATION ; ; -- PLL_TYPE ; AUTO ; ; -- PRIMARY_CLOCK ; INCLK0 ; ; -- INCLK0_INPUT_FREQUENCY ; 11446 ; ; -- INCLK1_INPUT_FREQUENCY ; 0 ; ; -- VCO_MULTIPLY_BY ; 0 ; ; -- VCO_DIVIDE_BY ; 0 ; +-------------------------------+--------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------------+ ; altsyncram Parameter Settings by Entity Instance ; +-------------------------------------------+------------------------------------------------------------------------------------+ ; Name ; Value ; +-------------------------------------------+------------------------------------------------------------------------------------+ ; Number of entity instances ; 1 ; ; Entity Instance ; generic_ram_infer:\sample_on:normal_ram:sample_ram_inst|altsyncram:ram_block_rtl_0 ; ; -- OPERATION_MODE ; SINGLE_PORT ; ; -- WIDTH_A ; 8 ; ; -- NUMWORDS_A ; 43008 ; ; -- OUTDATA_REG_A ; UNREGISTERED ; ; -- WIDTH_B ; 1 ; ; -- NUMWORDS_B ; 1 ; ; -- ADDRESS_REG_B ; CLOCK1 ; ; -- OUTDATA_REG_B ; UNREGISTERED ; ; -- RAM_BLOCK_TYPE ; AUTO ; ; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; +-------------------------------------------+------------------------------------------------------------------------------------+ +----------------------------------------------------------------------------------------------------------------------------+ ; lpm_mult Parameter Settings by Entity Instance ; +---------------------------------------+------------------------------------------------------------------------------------+ ; Name ; Value ; +---------------------------------------+------------------------------------------------------------------------------------+ ; Number of entity instances ; 17 ; ; Entity Instance ; clockgensid:clockgen1|lpm_mult:Mult0 ; ; -- LPM_WIDTHA ; 6 ; ; -- LPM_WIDTHB ; 9 ; ; -- LPM_WIDTHP ; 15 ; ; -- LPM_REPRESENTATION ; UNSIGNED ; ; -- INPUT_A_IS_CONSTANT ; NO ; ; -- INPUT_B_IS_CONSTANT ; NO ; ; -- USE_EAB ; OFF ; ; -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; ; -- INPUT_A_FIXED_VALUE ; Bx ; ; -- INPUT_B_FIXED_VALUE ; Bx ; ; Entity Instance ; sample_top:\sample_on:sample1|sample_adpcm:adpcm_decoder|lpm_mult:Mult0 ; ; -- LPM_WIDTHA ; 5 ; ; -- LPM_WIDTHB ; 16 ; ; -- LPM_WIDTHP ; 21 ; ; -- LPM_REPRESENTATION ; SIGNED ; ; -- INPUT_A_IS_CONSTANT ; NO ; ; -- INPUT_B_IS_CONSTANT ; NO ; ; -- USE_EAB ; OFF ; ; -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; ; -- INPUT_A_FIXED_VALUE ; Bx ; ; -- INPUT_B_FIXED_VALUE ; Bx ; ; Entity Instance ; sample_top:\sample_on:sample1|lpm_mult:Mult3 ; ; -- LPM_WIDTHA ; 13 ; ; -- LPM_WIDTHB ; 7 ; ; -- LPM_WIDTHP ; 20 ; ; -- LPM_REPRESENTATION ; SIGNED ; ; -- INPUT_A_IS_CONSTANT ; NO ; ; -- INPUT_B_IS_CONSTANT ; NO ; ; -- USE_EAB ; OFF ; ; -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; ; -- INPUT_A_FIXED_VALUE ; Bx ; ; -- INPUT_B_FIXED_VALUE ; Bx ; ; Entity Instance ; sample_top:\sample_on:sample1|lpm_mult:Mult2 ; ; -- LPM_WIDTHA ; 13 ; ; -- LPM_WIDTHB ; 7 ; ; -- LPM_WIDTHP ; 20 ; ; -- LPM_REPRESENTATION ; SIGNED ; ; -- INPUT_A_IS_CONSTANT ; NO ; ; -- INPUT_B_IS_CONSTANT ; NO ; ; -- USE_EAB ; OFF ; ; -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; ; -- INPUT_A_FIXED_VALUE ; Bx ; ; -- INPUT_B_FIXED_VALUE ; Bx ; ; Entity Instance ; SID_top:sid2|SID_postFilterSum:postfilter|lpm_mult:Mult0 ; ; -- LPM_WIDTHA ; 18 ; ; -- LPM_WIDTHB ; 8 ; ; -- LPM_WIDTHP ; 26 ; ; -- LPM_REPRESENTATION ; SIGNED ; ; -- INPUT_A_IS_CONSTANT ; NO ; ; -- INPUT_B_IS_CONSTANT ; NO ; ; -- USE_EAB ; OFF ; ; -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; ; -- INPUT_A_FIXED_VALUE ; Bx ; ; -- INPUT_B_FIXED_VALUE ; Bx ; ; Entity Instance ; sample_top:\sample_on:sample1|lpm_mult:Mult1 ; ; -- LPM_WIDTHA ; 13 ; ; -- LPM_WIDTHB ; 7 ; ; -- LPM_WIDTHP ; 20 ; ; -- LPM_REPRESENTATION ; SIGNED ; ; -- INPUT_A_IS_CONSTANT ; NO ; ; -- INPUT_B_IS_CONSTANT ; NO ; ; -- USE_EAB ; OFF ; ; -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; ; -- INPUT_A_FIXED_VALUE ; Bx ; ; -- INPUT_B_FIXED_VALUE ; Bx ; ; Entity Instance ; sample_top:\sample_on:sample1|lpm_mult:Mult0 ; ; -- LPM_WIDTHA ; 13 ; ; -- LPM_WIDTHB ; 7 ; ; -- LPM_WIDTHP ; 20 ; ; -- LPM_REPRESENTATION ; SIGNED ; ; -- INPUT_A_IS_CONSTANT ; NO ; ; -- INPUT_B_IS_CONSTANT ; NO ; ; -- USE_EAB ; OFF ; ; -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; ; -- INPUT_A_FIXED_VALUE ; Bx ; ; -- INPUT_B_FIXED_VALUE ; Bx ; ; Entity Instance ; SID_top:sid1|SID_postFilterSum:postfilter|lpm_mult:Mult0 ; ; -- LPM_WIDTHA ; 18 ; ; -- LPM_WIDTHB ; 8 ; ; -- LPM_WIDTHP ; 26 ; ; -- LPM_REPRESENTATION ; SIGNED ; ; -- INPUT_A_IS_CONSTANT ; NO ; ; -- INPUT_B_IS_CONSTANT ; NO ; ; -- USE_EAB ; OFF ; ; -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; ; -- INPUT_A_FIXED_VALUE ; Bx ; ; -- INPUT_B_FIXED_VALUE ; Bx ; ; Entity Instance ; SID_top:sid2|SID_amplitudeModulator:vol_abc|lpm_mult:Mult0 ; ; -- LPM_WIDTHA ; 9 ; ; -- LPM_WIDTHB ; 12 ; ; -- LPM_WIDTHP ; 21 ; ; -- LPM_REPRESENTATION ; SIGNED ; ; -- INPUT_A_IS_CONSTANT ; NO ; ; -- INPUT_B_IS_CONSTANT ; NO ; ; -- USE_EAB ; OFF ; ; -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; ; -- INPUT_A_FIXED_VALUE ; Bx ; ; -- INPUT_B_FIXED_VALUE ; Bx ; ; Entity Instance ; SID_top:sid2|SID_filter:variable_state_filter|lpm_mult:Mult4 ; ; -- LPM_WIDTHA ; 14 ; ; -- LPM_WIDTHB ; 36 ; ; -- LPM_WIDTHP ; 50 ; ; -- LPM_REPRESENTATION ; SIGNED ; ; -- INPUT_A_IS_CONSTANT ; NO ; ; -- INPUT_B_IS_CONSTANT ; NO ; ; -- USE_EAB ; OFF ; ; -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; ; -- INPUT_A_FIXED_VALUE ; Bx ; ; -- INPUT_B_FIXED_VALUE ; Bx ; ; Entity Instance ; SID_top:sid1|SID_amplitudeModulator:vol_abc|lpm_mult:Mult0 ; ; -- LPM_WIDTHA ; 9 ; ; -- LPM_WIDTHB ; 12 ; ; -- LPM_WIDTHP ; 21 ; ; -- LPM_REPRESENTATION ; SIGNED ; ; -- INPUT_A_IS_CONSTANT ; NO ; ; -- INPUT_B_IS_CONSTANT ; NO ; ; -- USE_EAB ; OFF ; ; -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; ; -- INPUT_A_FIXED_VALUE ; Bx ; ; -- INPUT_B_FIXED_VALUE ; Bx ; ; Entity Instance ; SID_top:sid1|SID_filter:variable_state_filter|lpm_mult:Mult4 ; ; -- LPM_WIDTHA ; 14 ; ; -- LPM_WIDTHB ; 36 ; ; -- LPM_WIDTHP ; 50 ; ; -- LPM_REPRESENTATION ; SIGNED ; ; -- INPUT_A_IS_CONSTANT ; NO ; ; -- INPUT_B_IS_CONSTANT ; NO ; ; -- USE_EAB ; OFF ; ; -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; ; -- INPUT_A_FIXED_VALUE ; Bx ; ; -- INPUT_B_FIXED_VALUE ; Bx ; ; Entity Instance ; SID_top:sid2|SID_filter:variable_state_filter|lpm_mult:Mult3 ; ; -- LPM_WIDTHA ; 14 ; ; -- LPM_WIDTHB ; 36 ; ; -- LPM_WIDTHP ; 50 ; ; -- LPM_REPRESENTATION ; SIGNED ; ; -- INPUT_A_IS_CONSTANT ; NO ; ; -- INPUT_B_IS_CONSTANT ; NO ; ; -- USE_EAB ; OFF ; ; -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; ; -- INPUT_A_FIXED_VALUE ; Bx ; ; -- INPUT_B_FIXED_VALUE ; Bx ; ; Entity Instance ; SID_top:sid1|SID_filter:variable_state_filter|lpm_mult:Mult3 ; ; -- LPM_WIDTHA ; 14 ; ; -- LPM_WIDTHB ; 36 ; ; -- LPM_WIDTHP ; 50 ; ; -- LPM_REPRESENTATION ; SIGNED ; ; -- INPUT_A_IS_CONSTANT ; NO ; ; -- INPUT_B_IS_CONSTANT ; NO ; ; -- USE_EAB ; OFF ; ; -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; ; -- INPUT_A_FIXED_VALUE ; Bx ; ; -- INPUT_B_FIXED_VALUE ; Bx ; ; Entity Instance ; SID_top:sid2|SID_filter:variable_state_filter|lpm_mult:Mult0 ; ; -- LPM_WIDTHA ; 36 ; ; -- LPM_WIDTHB ; 18 ; ; -- LPM_WIDTHP ; 54 ; ; -- LPM_REPRESENTATION ; SIGNED ; ; -- INPUT_A_IS_CONSTANT ; NO ; ; -- INPUT_B_IS_CONSTANT ; NO ; ; -- USE_EAB ; OFF ; ; -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; ; -- INPUT_A_FIXED_VALUE ; Bx ; ; -- INPUT_B_FIXED_VALUE ; Bx ; ; Entity Instance ; SID_top:sid1|SID_filter:variable_state_filter|lpm_mult:Mult0 ; ; -- LPM_WIDTHA ; 36 ; ; -- LPM_WIDTHB ; 18 ; ; -- LPM_WIDTHP ; 54 ; ; -- LPM_REPRESENTATION ; SIGNED ; ; -- INPUT_A_IS_CONSTANT ; NO ; ; -- INPUT_B_IS_CONSTANT ; NO ; ; -- USE_EAB ; OFF ; ; -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; ; -- INPUT_A_FIXED_VALUE ; Bx ; ; -- INPUT_B_FIXED_VALUE ; Bx ; ; Entity Instance ; SID_f_distortion_mux:f_distortion_mux|SID_f_distortion:f_distortion|lpm_mult:Mult0 ; ; -- LPM_WIDTHA ; 13 ; ; -- LPM_WIDTHB ; 12 ; ; -- LPM_WIDTHP ; 25 ; ; -- LPM_REPRESENTATION ; UNSIGNED ; ; -- INPUT_A_IS_CONSTANT ; NO ; ; -- INPUT_B_IS_CONSTANT ; NO ; ; -- USE_EAB ; OFF ; ; -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; ; -- INPUT_A_FIXED_VALUE ; Bx ; ; -- INPUT_B_FIXED_VALUE ; Bx ; +---------------------------------------+------------------------------------------------------------------------------------+ +------------------------------------------------------------------------------------------+ ; Port Connectivity Checks: "sigma_delta_adc:sdelta|cic_integrator:gen_cic[1].cic_inst_u0" ; +------+-------+----------+----------------------------------------------------------------+ ; Port ; Type ; Severity ; Details ; +------+-------+----------+----------------------------------------------------------------+ ; ena ; Input ; Info ; Stuck at VCC ; +------+-------+----------+----------------------------------------------------------------+ +------------------------------------------------------------------------------------------+ ; Port Connectivity Checks: "sigma_delta_adc:sdelta|cic_integrator:gen_cic[0].cic_inst_u0" ; +----------------+-------+----------+------------------------------------------------------+ ; Port ; Type ; Severity ; Details ; +----------------+-------+----------+------------------------------------------------------+ ; ena ; Input ; Info ; Stuck at VCC ; ; data_in[21..1] ; Input ; Info ; Stuck at GND ; +----------------+-------+----------+------------------------------------------------------+ +----------------------------------------------------------------------------------------------------------------------+ ; Port Connectivity Checks: "sigma_delta_adc:sdelta" ; +------------+--------+----------+-------------------------------------------------------------------------------------+ ; Port ; Type ; Severity ; Details ; +------------+--------+----------+-------------------------------------------------------------------------------------+ ; adc_output ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ; adc_valid ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +------------+--------+----------+-------------------------------------------------------------------------------------+ +-------------------------------------------------------------------------------------------------------------------------+ ; Port Connectivity Checks: "filtered_sigmadelta:dac_0|sigmadelta_2ndorder_dither:\gen_2ndorder_dither_on:dac_2nd_dither" ; +--------+-------+----------+---------------------------------------------------------------------------------------------+ ; Port ; Type ; Severity ; Details ; +--------+-------+----------+---------------------------------------------------------------------------------------------+ ; enable ; Input ; Info ; Stuck at VCC ; +--------+-------+----------+---------------------------------------------------------------------------------------------+ +-----------------------------------------------------------------------------------------------------------------------+ ; Port Connectivity Checks: "sigmadelta_dither:dac_dithergen" ; +-------------+--------+----------+-------------------------------------------------------------------------------------+ ; Port ; Type ; Severity ; Details ; +-------------+--------+----------+-------------------------------------------------------------------------------------+ ; dither_out2 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +-------------+--------+----------+-------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------+ ; Port Connectivity Checks: "mixer:mixer1" ; +----------------+--------+----------+-------------------------------------------------------------------------------------+ ; Port ; Type ; Severity ; Details ; +----------------+--------+----------+-------------------------------------------------------------------------------------+ ; b_ch0_en ; Input ; Info ; Stuck at GND ; ; b_ch1_en ; Input ; Info ; Stuck at GND ; ; b_ch0 ; Input ; Info ; Stuck at GND ; ; b_ch1 ; Input ; Info ; Stuck at GND ; ; audio_1_signed ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +----------------+--------+----------+-------------------------------------------------------------------------------------+ +----------------------------------------------------------------------------------------------------------------------------+ ; Port Connectivity Checks: "complete_address_decoder:\gen_config:decode_addr1" ; +------------------+--------+----------+-------------------------------------------------------------------------------------+ ; Port ; Type ; Severity ; Details ; +------------------+--------+----------+-------------------------------------------------------------------------------------+ ; addr_decoded[10] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +------------------+--------+----------+-------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------+ ; Port Connectivity Checks: "sample_top:\sample_on:sample1|sample_adpcm:adpcm_decoder" ; +----------------+--------+----------+-------------------------------------------------------------------------------------+ ; Port ; Type ; Severity ; Details ; +----------------+--------+----------+-------------------------------------------------------------------------------------+ ; data_out[2..0] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +----------------+--------+----------+-------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------------+ ; Port Connectivity Checks: "sample_top:\sample_on:sample1|complete_address_decoder:decode_addr2" ; +----------------------+--------+----------+-------------------------------------------------------------------------------------+ ; Port ; Type ; Severity ; Details ; +----------------------+--------+----------+-------------------------------------------------------------------------------------+ ; addr_decoded[31..20] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +----------------------+--------+----------+-------------------------------------------------------------------------------------+ +---------------------------------------------------------------------+ ; Port Connectivity Checks: "PSG_volume_profile:\psg_on:vol_profile1" ; +----------------------+-------+----------+---------------------------+ ; Port ; Type ; Severity ; Details ; +----------------------+-------+----------+---------------------------+ ; channel_mask_1[5] ; Input ; Info ; Stuck at VCC ; ; channel_mask_2[1..0] ; Input ; Info ; Stuck at VCC ; +----------------------+-------+----------+---------------------------+ +-------------------------------------------------------------------------------------------------------------------+ ; Port Connectivity Checks: "PSG_top:\psg_on:PSG_2" ; +---------+--------+----------+-------------------------------------------------------------------------------------+ ; Port ; Type ; Severity ; Details ; +---------+--------+----------+-------------------------------------------------------------------------------------+ ; ioa_in ; Input ; Info ; Stuck at GND ; ; iob_in ; Input ; Info ; Stuck at GND ; ; ioa_out ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ; iob_out ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ; ioa_oe ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ; iob_oe ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +---------+--------+----------+-------------------------------------------------------------------------------------+ +----------------------------------------------------------------------------+ ; Port Connectivity Checks: "PSG_top:\psg_on:PSG_1|PSG_freqdiv:noise_ticker" ; +------------+-------+----------+--------------------------------------------+ ; Port ; Type ; Severity ; Details ; +------------+-------+----------+--------------------------------------------+ ; sync_reset ; Input ; Info ; Stuck at GND ; +------------+-------+----------+--------------------------------------------+ +-------------------------------------------------------------------------------+ ; Port Connectivity Checks: "PSG_top:\psg_on:PSG_1|PSG_freqdiv:noise_preticker" ; +--------------+-------+----------+---------------------------------------------+ ; Port ; Type ; Severity ; Details ; +--------------+-------+----------+---------------------------------------------+ ; sync_reset ; Input ; Info ; Stuck at GND ; ; threshold[1] ; Input ; Info ; Stuck at VCC ; ; threshold[0] ; Input ; Info ; Stuck at GND ; +--------------+-------+----------+---------------------------------------------+ +--------------------------------------------------------------------------------+ ; Port Connectivity Checks: "PSG_top:\psg_on:PSG_1|PSG_freqdiv:channel_c_ticker" ; +------------+-------+----------+------------------------------------------------+ ; Port ; Type ; Severity ; Details ; +------------+-------+----------+------------------------------------------------+ ; sync_reset ; Input ; Info ; Stuck at GND ; +------------+-------+----------+------------------------------------------------+ +--------------------------------------------------------------------------------+ ; Port Connectivity Checks: "PSG_top:\psg_on:PSG_1|PSG_freqdiv:channel_b_ticker" ; +------------+-------+----------+------------------------------------------------+ ; Port ; Type ; Severity ; Details ; +------------+-------+----------+------------------------------------------------+ ; sync_reset ; Input ; Info ; Stuck at GND ; +------------+-------+----------+------------------------------------------------+ +--------------------------------------------------------------------------------+ ; Port Connectivity Checks: "PSG_top:\psg_on:PSG_1|PSG_freqdiv:channel_a_ticker" ; +------------+-------+----------+------------------------------------------------+ ; Port ; Type ; Severity ; Details ; +------------+-------+----------+------------------------------------------------+ ; sync_reset ; Input ; Info ; Stuck at GND ; +------------+-------+----------+------------------------------------------------+ +---------------------------------------------------------------------------+ ; Port Connectivity Checks: "PSG_top:\psg_on:PSG_1|PSG_freqdiv:core_ticker" ; +-----------------+-------+----------+--------------------------------------+ ; Port ; Type ; Severity ; Details ; +-----------------+-------+----------+--------------------------------------+ ; sync_reset ; Input ; Info ; Stuck at GND ; ; threshold[2..0] ; Input ; Info ; Stuck at GND ; ; threshold[3] ; Input ; Info ; Stuck at VCC ; +-----------------+-------+----------+--------------------------------------+ +-------------------------------------------------------------------------------------------------------------------+ ; Port Connectivity Checks: "PSG_top:\psg_on:PSG_1" ; +---------+--------+----------+-------------------------------------------------------------------------------------+ ; Port ; Type ; Severity ; Details ; +---------+--------+----------+-------------------------------------------------------------------------------------+ ; ioa_in ; Input ; Info ; Stuck at GND ; ; iob_in ; Input ; Info ; Stuck at GND ; ; ioa_out ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ; iob_out ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ; ioa_oe ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ; iob_oe ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +---------+--------+----------+-------------------------------------------------------------------------------------+ +------------------------------------------------------------------------------------------------------------------------+ ; Port Connectivity Checks: "SID_top:sid2" ; +--------------+--------+----------+-------------------------------------------------------------------------------------+ ; Port ; Type ; Severity ; Details ; +--------------+--------+----------+-------------------------------------------------------------------------------------+ ; pot_reset ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ; debug_wv1 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ; debug_ev1 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ; debug_am1 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ; rom_addr[16] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +--------------+--------+----------+-------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------------+ ; Port Connectivity Checks: "SID_top:sid1|complete_address_decoder:decode_addr1" ; +----------------------+--------+----------+-------------------------------------------------------------------------------------+ ; Port ; Type ; Severity ; Details ; +----------------------+--------+----------+-------------------------------------------------------------------------------------+ ; addr_decoded[31..29] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +----------------------+--------+----------+-------------------------------------------------------------------------------------+ +------------------------------------------------------------------------------------------------------------------------+ ; Port Connectivity Checks: "SID_top:sid1" ; +--------------+--------+----------+-------------------------------------------------------------------------------------+ ; Port ; Type ; Severity ; Details ; +--------------+--------+----------+-------------------------------------------------------------------------------------+ ; debug_wv1 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ; debug_ev1 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ; debug_am1 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ; rom_addr[16] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +--------------+--------+----------+-------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------------+ ; Port Connectivity Checks: "pokey:\POKEY_ON:1:pokeyx" ; +----------------------+--------+----------+-------------------------------------------------------------------------------------+ ; Port ; Type ; Severity ; Details ; +----------------------+--------+----------+-------------------------------------------------------------------------------------+ ; keyboard_scan_enable ; Input ; Info ; Stuck at GND ; ; keyboard_scan ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ; keyboard_scan_update ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ; keyboard_response ; Input ; Info ; Stuck at GND ; ; pot_in ; Input ; Info ; Stuck at GND ; ; sio_in1 ; Input ; Info ; Stuck at VCC ; ; sio_out1 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ; sio_out2 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ; sio_out3 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ; sio_clockin_in ; Input ; Info ; Stuck at VCC ; ; sio_clockin_out ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ; sio_clockin_oe ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ; sio_clockout ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ; pot_reset ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +----------------------+--------+----------+-------------------------------------------------------------------------------------+ +------------------------------------------------------------------------------------+ ; Port Connectivity Checks: "pokey:\POKEY_ON:0:pokeyx|latch_delay_line:stimer_delay" ; +------------+-------+----------+----------------------------------------------------+ ; Port ; Type ; Severity ; Details ; +------------+-------+----------+----------------------------------------------------+ ; sync_reset ; Input ; Info ; Stuck at GND ; +------------+-------+----------+----------------------------------------------------+ +-----------------------------------------------------------------------------------+ ; Port Connectivity Checks: "pokey:\POKEY_ON:0:pokeyx|latch_delay_line:twotone_del" ; +------------+-------+----------+---------------------------------------------------+ ; Port ; Type ; Severity ; Details ; +------------+-------+----------+---------------------------------------------------+ ; sync_reset ; Input ; Info ; Stuck at GND ; +------------+-------+----------+---------------------------------------------------+ +-----------------------------------------------------------------------------------+ ; Port Connectivity Checks: "pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audctl_delay" ; +------------+-------+----------+---------------------------------------------------+ ; Port ; Type ; Severity ; Details ; +------------+-------+----------+---------------------------------------------------+ ; sync_reset ; Input ; Info ; Stuck at GND ; +------------+-------+----------+---------------------------------------------------+ +----------------------------------------------------------------------------------+ ; Port Connectivity Checks: "pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf3_delay" ; +------------+-------+----------+--------------------------------------------------+ ; Port ; Type ; Severity ; Details ; +------------+-------+----------+--------------------------------------------------+ ; sync_reset ; Input ; Info ; Stuck at GND ; +------------+-------+----------+--------------------------------------------------+ +----------------------------------------------------------------------------------+ ; Port Connectivity Checks: "pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf2_delay" ; +------------+-------+----------+--------------------------------------------------+ ; Port ; Type ; Severity ; Details ; +------------+-------+----------+--------------------------------------------------+ ; sync_reset ; Input ; Info ; Stuck at GND ; +------------+-------+----------+--------------------------------------------------+ +----------------------------------------------------------------------------------+ ; Port Connectivity Checks: "pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf1_delay" ; +------------+-------+----------+--------------------------------------------------+ ; Port ; Type ; Severity ; Details ; +------------+-------+----------+--------------------------------------------------+ ; sync_reset ; Input ; Info ; Stuck at GND ; +------------+-------+----------+--------------------------------------------------+ +----------------------------------------------------------------------------------+ ; Port Connectivity Checks: "pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf0_delay" ; +------------+-------+----------+--------------------------------------------------+ ; Port ; Type ; Severity ; Details ; +------------+-------+----------+--------------------------------------------------+ ; sync_reset ; Input ; Info ; Stuck at GND ; +------------+-------+----------+--------------------------------------------------+ +----------------------------------------------------------------------------------------------------------------------------+ ; Port Connectivity Checks: "pokey:\POKEY_ON:0:pokeyx|complete_address_decoder:decode_addr1" ; +------------------+--------+----------+-------------------------------------------------------------------------------------+ ; Port ; Type ; Severity ; Details ; +------------------+--------+----------+-------------------------------------------------------------------------------------+ ; addr_decoded[12] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +------------------+--------+----------+-------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------------+ ; Port Connectivity Checks: "pokey:\POKEY_ON:0:pokeyx" ; +----------------------+--------+----------+-------------------------------------------------------------------------------------+ ; Port ; Type ; Severity ; Details ; +----------------------+--------+----------+-------------------------------------------------------------------------------------+ ; wr_en ; Input ; Info ; Stuck at GND ; ; keyboard_scan_enable ; Input ; Info ; Stuck at GND ; ; keyboard_scan ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ; keyboard_scan_update ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ; keyboard_response ; Input ; Info ; Stuck at GND ; ; pot_in ; Input ; Info ; Stuck at GND ; ; sio_in1 ; Input ; Info ; Stuck at VCC ; ; data_out ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ; sio_out1 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ; sio_out2 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ; sio_out3 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ; sio_clockin_in ; Input ; Info ; Stuck at VCC ; ; sio_clockin_out ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ; sio_clockin_oe ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ; sio_clockout ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ; pot_reset ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +----------------------+--------+----------+-------------------------------------------------------------------------------------+ +----------------------------------------------------------------------------------------------------------------+ ; Port Connectivity Checks: "slave_timing_6502:bus_adapt" ; +------+--------+----------+-------------------------------------------------------------------------------------+ ; Port ; Type ; Severity ; Details ; +------+--------+----------+-------------------------------------------------------------------------------------+ ; cs ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +------+--------+----------+-------------------------------------------------------------------------------------+ +--------------------------------------------------------------------+ ; Port Connectivity Checks: "synchronizer:synchronizer_fancy_enable" ; +------+-------+----------+------------------------------------------+ ; Port ; Type ; Severity ; Details ; +------+-------+----------+------------------------------------------+ ; raw ; Input ; Info ; Stuck at VCC ; +------+-------+----------+------------------------------------------+ +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Port Connectivity Checks: "flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_block:altera_onchip_flash_block" ; +----------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------+ ; Port ; Type ; Severity ; Details ; +----------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------+ ; nosc_ena ; Input ; Info ; Stuck at GND ; ; par_en ; Input ; Info ; Stuck at VCC ; +----------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------+ +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Port Connectivity Checks: "flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_onchip_flash_address_range_check:address_range_checker" ; +-----------------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Port ; Type ; Severity ; Details ; +-----------------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; address[22..16] ; Input ; Info ; Stuck at GND ; +-----------------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +-------------------------------------------------------------------------------------------+ ; Port Connectivity Checks: "flash_controller:\flash_on:flash_controller_inst|flash:flash1" ; +-------------------------+-------+----------+----------------------------------------------+ ; Port ; Type ; Severity ; Details ; +-------------------------+-------+----------+----------------------------------------------+ ; avmm_data_burstcount[1] ; Input ; Info ; Stuck at GND ; ; avmm_data_burstcount[0] ; Input ; Info ; Stuck at VCC ; +-------------------------+-------+----------+----------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------+ ; Port Connectivity Checks: "flash_controller:\flash_on:flash_controller_inst" ; +----------------------------+--------+----------+-------------------------------------------------------------------------------------+ ; Port ; Type ; Severity ; Details ; +----------------------------+--------+----------+-------------------------------------------------------------------------------------+ ; flash_req_complete ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ; flash_req_complete_slow[7] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ; flash_req2_addr[12..1] ; Input ; Info ; Stuck at GND ; ; flash_req3_addr[12..8] ; Input ; Info ; Stuck at GND ; ; flash_req3_addr[7] ; Input ; Info ; Stuck at VCC ; ; flash_req6_addr[12..9] ; Input ; Info ; Stuck at GND ; ; flash_req6_addr[8] ; Input ; Info ; Stuck at VCC ; ; flash_req6_addr[7] ; Input ; Info ; Stuck at GND ; ; flash_req7_addr[8..7] ; Input ; Info ; Stuck at VCC ; ; flash_req7_addr[12..9] ; Input ; Info ; Stuck at GND ; ; flash_req8_addr ; Input ; Info ; Stuck at GND ; ; flash_data_out ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +----------------------------+--------+----------+-------------------------------------------------------------------------------------+ +------------------------------------------------+ ; Port Connectivity Checks: "int_osc:oscillator" ; +--------+-------+----------+--------------------+ ; Port ; Type ; Severity ; Details ; +--------+-------+----------+--------------------+ ; oscena ; Input ; Info ; Stuck at VCC ; +--------+-------+----------+--------------------+ +-----------------------------------------------------+ ; Post-Synthesis Netlist Statistics for Top Partition ; +------------------------+----------------------------+ ; Type ; Count ; +------------------------+----------------------------+ ; boundary_port ; 33 ; ; cycloneiii_ff ; 4787 ; ; CLR ; 1151 ; ; CLR SCLR ; 8 ; ; CLR SLD ; 39 ; ; ENA ; 167 ; ; ENA CLR ; 3000 ; ; ENA CLR SCLR ; 38 ; ; ENA CLR SCLR SLD ; 24 ; ; ENA CLR SLD ; 196 ; ; ENA SCLR ; 4 ; ; SCLR ; 35 ; ; SLD ; 6 ; ; plain ; 119 ; ; cycloneiii_io_obuf ; 14 ; ; cycloneiii_lcell_comb ; 7724 ; ; arith ; 2407 ; ; 2 data inputs ; 923 ; ; 3 data inputs ; 1484 ; ; normal ; 5317 ; ; 0 data inputs ; 24 ; ; 1 data inputs ; 151 ; ; 2 data inputs ; 733 ; ; 3 data inputs ; 1467 ; ; 4 data inputs ; 2942 ; ; cycloneiii_mac_mult ; 23 ; ; cycloneiii_mac_out ; 23 ; ; cycloneiii_pll ; 1 ; ; cycloneiii_ram_block ; 48 ; ; fiftyfivenm_oscillator ; 1 ; ; fiftyfivenm_unvm ; 1 ; ; ; ; ; Max LUT depth ; 17.00 ; ; Average LUT depth ; 5.23 ; +------------------------+----------------------------+ +-------------------------------+ ; Elapsed Time Per Partition ; +----------------+--------------+ ; Partition Name ; Elapsed Time ; +----------------+--------------+ ; Top ; 00:00:09 ; +----------------+--------------+ +-------------------------------+ ; Analysis & Synthesis Messages ; +-------------------------------+ Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition Info: Processing started: Sun Jun 7 10:18:06 2026 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off sidmax -c sidmax Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (20030): Parallel compilation is enabled and will use 16 of the 24 processors detected Info (12021): Found 2 design units, including 1 entities, in source file audio_signal_detector.vhd Info (12022): Found design unit 1: audio_signal_detector-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/audio_signal_detector.vhd Line: 31 Info (12023): Found entity 1: audio_signal_detector File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/audio_signal_detector.vhd Line: 18 Info (12021): Found 2 design units, including 1 entities, in source file flash_controller.vhd Info (12022): Found design unit 1: flash_controller-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/flash_controller.vhd Line: 54 Info (12023): Found entity 1: flash_controller File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/flash_controller.vhd Line: 19 Info (12021): Found 2 design units, including 1 entities, in source file stereo_detect.vhd Info (12022): Found design unit 1: stereo_detect-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/stereo_detect.vhd Line: 24 Info (12023): Found entity 1: stereo_detect File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/stereo_detect.vhd Line: 13 Info (12021): Found 2 design units, including 1 entities, in source file slave_timing_6502.vhd Info (12022): Found design unit 1: slave_timing_6502-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/slave_timing_6502.vhd Line: 40 Info (12023): Found entity 1: slave_timing_6502 File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/slave_timing_6502.vhd Line: 6 Info (12021): Found 2 design units, including 1 entities, in source file complete_address_decoder.vhdl Info (12022): Found design unit 1: complete_address_decoder-tree File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/complete_address_decoder.vhdl Line: 30 Info (12023): Found entity 1: complete_address_decoder File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/complete_address_decoder.vhdl Line: 12 Info (12021): Found 2 design units, including 1 entities, in source file syncreset_enable_divider.vhd Info (12022): Found design unit 1: syncreset_enable_divider-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/syncreset_enable_divider.vhd Line: 25 Info (12023): Found entity 1: syncreset_enable_divider File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/syncreset_enable_divider.vhd Line: 12 Info (12021): Found 2 design units, including 1 entities, in source file enable_divider.vhdl Info (12022): Found design unit 1: enable_divider-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/enable_divider.vhdl Line: 24 Info (12023): Found entity 1: enable_divider File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/enable_divider.vhdl Line: 12 Info (12021): Found 2 design units, including 1 entities, in source file delay_line.vhdl Info (12022): Found design unit 1: delay_line-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/delay_line.vhdl Line: 26 Info (12023): Found entity 1: delay_line File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/delay_line.vhdl Line: 12 Info (12021): Found 2 design units, including 1 entities, in source file wide_delay_line.vhdl Info (12022): Found design unit 1: wide_delay_line-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/wide_delay_line.vhdl Line: 26 Info (12023): Found entity 1: wide_delay_line File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/wide_delay_line.vhdl Line: 12 Info (12021): Found 2 design units, including 1 entities, in source file latch_delay_line.vhdl Info (12022): Found design unit 1: latch_delay_line-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/latch_delay_line.vhdl Line: 26 Info (12023): Found entity 1: latch_delay_line File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/latch_delay_line.vhdl Line: 12 Info (12021): Found 2 design units, including 1 entities, in source file sigmadelta_1storder.vhd Info (12022): Found design unit 1: sigmadelta_1storder-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sigmadelta_1storder.vhd Line: 27 Info (12023): Found entity 1: sigmadelta_1storder File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sigmadelta_1storder.vhd Line: 16 Info (12021): Found 2 design units, including 1 entities, in source file sigmadelta_2ndorder.vhd Info (12022): Found design unit 1: sigmadelta_2ndorder-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sigmadelta_2ndorder.vhd Line: 27 Info (12023): Found entity 1: sigmadelta_2ndorder File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sigmadelta_2ndorder.vhd Line: 14 Info (12021): Found 2 design units, including 1 entities, in source file sigmadelta_2ndorder_dither.vhd Info (12022): Found design unit 1: sigmadelta_2ndorder_dither-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sigmadelta_2ndorder_dither.vhd Line: 32 Info (12023): Found entity 1: sigmadelta_2ndorder_dither File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sigmadelta_2ndorder_dither.vhd Line: 14 Info (12021): Found 2 design units, including 1 entities, in source file sigmadelta_dither.vhd Info (12022): Found design unit 1: sigmadelta_dither-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sigmadelta_dither.vhd Line: 32 Info (12023): Found entity 1: sigmadelta_dither File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sigmadelta_dither.vhd Line: 14 Info (12021): Found 2 design units, including 1 entities, in source file filtered_sigmadelta.vhd Info (12022): Found design unit 1: filtered_sigmadelta-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/filtered_sigmadelta.vhd Line: 34 Info (12023): Found entity 1: filtered_sigmadelta File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/filtered_sigmadelta.vhd Line: 13 Info (12021): Found 2 design units, including 1 entities, in source file generic_ram_infer.vhdl Info (12022): Found design unit 1: generic_ram_infer-rtl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/generic_ram_infer.vhdl Line: 30 Info (12023): Found entity 1: generic_ram_infer File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/generic_ram_infer.vhdl Line: 12 Info (12021): Found 2 design units, including 1 entities, in source file m9k_grouped.vhdl Info (12022): Found design unit 1: m9k_grouped-rtl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/m9k_grouped.vhdl Line: 38 Info (12023): Found entity 1: m9k_grouped File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/m9k_grouped.vhdl Line: 14 Info (12021): Found 2 design units, including 1 entities, in source file simple_low_pass_filter.vhdl Info (12022): Found design unit 1: simple_low_pass_filter-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/simple_low_pass_filter.vhdl Line: 29 Info (12023): Found entity 1: simple_low_pass_filter File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/simple_low_pass_filter.vhdl Line: 19 Info (12021): Found 2 design units, including 1 entities, in source file pokey/pokey_poly_17_9.vhdl Info (12022): Found design unit 1: pokey_poly_17_9-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/pokey/pokey_poly_17_9.vhdl Line: 27 Info (12023): Found entity 1: pokey_poly_17_9 File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/pokey/pokey_poly_17_9.vhdl Line: 12 Info (12021): Found 2 design units, including 1 entities, in source file pokey/pokey_poly_5.vhdl Info (12022): Found design unit 1: pokey_poly_5-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/pokey/pokey_poly_5.vhdl Line: 24 Info (12023): Found entity 1: pokey_poly_5 File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/pokey/pokey_poly_5.vhdl Line: 12 Info (12021): Found 2 design units, including 1 entities, in source file pokey/pokey_poly_4.vhdl Info (12022): Found design unit 1: pokey_poly_4-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/pokey/pokey_poly_4.vhdl Line: 24 Info (12023): Found entity 1: pokey_poly_4 File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/pokey/pokey_poly_4.vhdl Line: 12 Info (12021): Found 2 design units, including 1 entities, in source file pokey/pokey_noise_filter.vhdl Info (12022): Found design unit 1: pokey_noise_filter-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/pokey/pokey_noise_filter.vhdl Line: 32 Info (12023): Found entity 1: pokey_noise_filter File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/pokey/pokey_noise_filter.vhdl Line: 12 Info (12021): Found 2 design units, including 1 entities, in source file pokey/pokey_mixer_mux.vhdl Info (12022): Found design unit 1: pokey_mixer_mux-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/pokey/pokey_mixer_mux.vhdl Line: 36 Info (12023): Found entity 1: pokey_mixer_mux File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/pokey/pokey_mixer_mux.vhdl Line: 13 Info (12021): Found 2 design units, including 1 entities, in source file pokey/pokey_mixer.vhdl Info (12022): Found design unit 1: pokey_mixer-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/pokey/pokey_mixer.vhdl Line: 24 Info (12023): Found entity 1: pokey_mixer File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/pokey/pokey_mixer.vhdl Line: 13 Info (12021): Found 2 design units, including 1 entities, in source file pokey/pokey_keyboard_scanner.vhdl Info (12022): Found design unit 1: pokey_keyboard_scanner-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/pokey/pokey_keyboard_scanner.vhdl Line: 33 Info (12023): Found entity 1: pokey_keyboard_scanner File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/pokey/pokey_keyboard_scanner.vhdl Line: 12 Info (12021): Found 2 design units, including 1 entities, in source file pokey/pokey_countdown_timer.vhdl Info (12022): Found design unit 1: pokey_countdown_timer-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/pokey/pokey_countdown_timer.vhdl Line: 28 Info (12023): Found entity 1: pokey_countdown_timer File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/pokey/pokey_countdown_timer.vhdl Line: 12 Info (12021): Found 2 design units, including 1 entities, in source file pokey/pokey.vhdl Info (12022): Found design unit 1: pokey-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/pokey/pokey.vhdl Line: 63 Info (12023): Found entity 1: pokey File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/pokey/pokey.vhdl Line: 14 Info (12021): Found 2 design units, including 1 entities, in source file phi_mult.vhdl Info (12022): Found design unit 1: phi_mult-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/phi_mult.vhdl Line: 21 Info (12023): Found entity 1: phi_mult File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/phi_mult.vhdl Line: 12 Info (12021): Found 2 design units, including 1 entities, in source file synchronizer.vhdl Info (12022): Found design unit 1: synchronizer-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/synchronizer.vhdl Line: 21 Info (12023): Found entity 1: synchronizer File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/synchronizer.vhdl Line: 12 Info (12021): Found 1 design units, including 0 entities, in source file audiotypes.vhdl Info (12022): Found design unit 1: AudioTypes File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/audiotypes.vhdl Line: 5 Info (12021): Found 2 design units, including 1 entities, in source file mixer.vhdl Info (12022): Found design unit 1: mixer-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/mixer.vhdl Line: 51 Info (12023): Found entity 1: mixer File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/mixer.vhdl Line: 17 Info (12021): Found 2 design units, including 1 entities, in source file clockgensid.vhd Info (12022): Found design unit 1: clockgensid-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/clockgensid.vhd Line: 35 Info (12023): Found entity 1: clockgensid File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/clockgensid.vhd Line: 17 Info (12021): Found 2 design units, including 1 entities, in source file spdif_transmitter.vhdl Info (12022): Found design unit 1: spdif_transmitter-behavioral File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/spdif_transmitter.vhdl Line: 16 Info (12023): Found entity 1: spdif_transmitter File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/spdif_transmitter.vhdl Line: 7 Info (12021): Found 2 design units, including 1 entities, in source file sidmax.vhd Info (12022): Found design unit 1: sidmax-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sidmax.vhd Line: 93 Info (12023): Found entity 1: sidmax File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sidmax.vhd Line: 18 Info (12021): Found 2 design units, including 1 entities, in source file PSG/envelope.vhdl Info (12022): Found design unit 1: PSG_envelope-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/PSG/envelope.vhdl Line: 28 Info (12023): Found entity 1: PSG_envelope File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/PSG/envelope.vhdl Line: 12 Info (12021): Found 2 design units, including 1 entities, in source file PSG/noise.vhdl Info (12022): Found design unit 1: PSG_noise-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/PSG/noise.vhdl Line: 24 Info (12023): Found entity 1: PSG_noise File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/PSG/noise.vhdl Line: 12 Info (12021): Found 2 design units, including 1 entities, in source file PSG/top.vhdl Info (12022): Found design unit 1: PSG_top-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/PSG/top.vhdl Line: 49 Info (12023): Found entity 1: PSG_top File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/PSG/top.vhdl Line: 18 Info (12021): Found 2 design units, including 1 entities, in source file PSG/freqdiv.vhdl Info (12022): Found design unit 1: PSG_freqdiv-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/PSG/freqdiv.vhdl Line: 31 Info (12023): Found entity 1: PSG_freqdiv File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/PSG/freqdiv.vhdl Line: 12 Info (12021): Found 2 design units, including 1 entities, in source file PSG/mixer.vhdl Info (12022): Found design unit 1: PSG_mixer-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/PSG/mixer.vhdl Line: 29 Info (12023): Found entity 1: PSG_mixer File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/PSG/mixer.vhdl Line: 12 Info (12021): Found 2 design units, including 1 entities, in source file PSG/volume.vhdl Info (12022): Found design unit 1: PSG_volume-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/PSG/volume.vhdl Line: 28 Info (12023): Found entity 1: PSG_volume File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/PSG/volume.vhdl Line: 12 Info (12021): Found 2 design units, including 1 entities, in source file PSG/volume_profile.vhdl Info (12022): Found design unit 1: PSG_volume_profile-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/PSG/volume_profile.vhdl Line: 41 Info (12023): Found entity 1: PSG_volume_profile File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/PSG/volume_profile.vhdl Line: 13 Info (12021): Found 2 design units, including 1 entities, in source file SID/top.vhdl Info (12022): Found design unit 1: SID_top-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/top.vhdl Line: 64 Info (12023): Found entity 1: SID_top File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/top.vhdl Line: 17 Info (12021): Found 2 design units, including 1 entities, in source file SID/oscillator.vhdl Info (12022): Found design unit 1: SID_oscillator-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/oscillator.vhdl Line: 31 Info (12023): Found entity 1: SID_oscillator File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/oscillator.vhdl Line: 12 Info (12021): Found 2 design units, including 1 entities, in source file SID/wavegen.vhdl Info (12022): Found design unit 1: SID_wavegen-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/wavegen.vhdl Line: 43 Info (12023): Found entity 1: SID_wavegen File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/wavegen.vhdl Line: 16 Info (12021): Found 2 design units, including 1 entities, in source file SID/envelope.vhdl Info (12022): Found design unit 1: SID_envelope-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/envelope.vhdl Line: 36 Info (12023): Found entity 1: SID_envelope File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/envelope.vhdl Line: 13 Info (12021): Found 2 design units, including 1 entities, in source file SID/envelope_tapmatch.vhdl Info (12022): Found design unit 1: SID_envelope_tapmatch-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/envelope_tapmatch.vhdl Line: 31 Info (12023): Found entity 1: SID_envelope_tapmatch File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/envelope_tapmatch.vhdl Line: 13 Info (12021): Found 2 design units, including 1 entities, in source file SID/amplitudeModulator.vhdl Info (12022): Found design unit 1: SID_amplitudeModulator-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/amplitudeModulator.vhdl Line: 29 Info (12023): Found entity 1: SID_amplitudeModulator File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/amplitudeModulator.vhdl Line: 12 Info (12021): Found 2 design units, including 1 entities, in source file SID/preFilterSum.vhdl Info (12022): Found design unit 1: SID_preFilterSum-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/preFilterSum.vhdl Line: 31 Info (12023): Found entity 1: SID_preFilterSum File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/preFilterSum.vhdl Line: 12 Info (12021): Found 2 design units, including 1 entities, in source file SID/filter.vhdl Info (12022): Found design unit 1: SID_filter-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/filter.vhdl Line: 147 Info (12023): Found entity 1: SID_filter File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/filter.vhdl Line: 48 Info (12021): Found 2 design units, including 1 entities, in source file SID/f_distortion.vhdl Info (12022): Found design unit 1: SID_f_distortion-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/f_distortion.vhdl Line: 24 Info (12023): Found entity 1: SID_f_distortion File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/f_distortion.vhdl Line: 12 Info (12021): Found 2 design units, including 1 entities, in source file SID/f_distortion_mux.vhdl Info (12022): Found design unit 1: SID_f_distortion_mux-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/f_distortion_mux.vhdl Line: 33 Info (12023): Found entity 1: SID_f_distortion_mux File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/f_distortion_mux.vhdl Line: 12 Info (12021): Found 2 design units, including 1 entities, in source file SID/postFilterSum.vhdl Info (12022): Found design unit 1: SID_postFilterSum-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/postFilterSum.vhdl Line: 30 Info (12023): Found entity 1: SID_postFilterSum File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/postFilterSum.vhdl Line: 12 Info (12021): Found 2 design units, including 1 entities, in source file sample/channel.vhdl Info (12022): Found design unit 1: sample_channel-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sample/channel.vhdl Line: 33 Info (12023): Found entity 1: sample_channel File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sample/channel.vhdl Line: 13 Info (12021): Found 2 design units, including 1 entities, in source file sample/adpcm.vhdl Info (12022): Found design unit 1: sample_adpcm-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sample/adpcm.vhdl Line: 39 Info (12023): Found entity 1: sample_adpcm File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sample/adpcm.vhdl Line: 13 Info (12021): Found 2 design units, including 1 entities, in source file sample/top.vhdl Info (12022): Found design unit 1: sample_top-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sample/top.vhdl Line: 46 Info (12023): Found entity 1: sample_top File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sample/top.vhdl Line: 17 Info (12021): Found 2 design units, including 1 entities, in source file covox/top.vhdl Info (12022): Found design unit 1: covox_top-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/covox/top.vhdl Line: 33 Info (12023): Found entity 1: covox_top File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/covox/top.vhdl Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file sigma_delta/sigma_delta_adc.sv Info (12023): Found entity 1: sigma_delta_adc File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sigma_delta/sigma_delta_adc.sv Line: 5 Info (12021): Found 1 design units, including 1 entities, in source file sigma_delta/cic_comb.sv Info (12023): Found entity 1: cic_comb File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sigma_delta/cic_comb.sv Line: 11 Info (12021): Found 1 design units, including 1 entities, in source file sigma_delta/cic_integrator.sv Info (12023): Found entity 1: cic_integrator File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sigma_delta/cic_integrator.sv Line: 11 Info (12021): Found 1 design units, including 1 entities, in source file sigma_delta/fir_compensator.sv Info (12023): Found entity 1: fir_compensator File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sigma_delta/fir_compensator.sv Line: 19 Info (12021): Found 2 design units, including 1 entities, in source file int_osc/synthesis/int_osc.vhd Info (12022): Found design unit 1: int_osc-rtl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/int_osc/synthesis/int_osc.vhd Line: 16 Info (12023): Found entity 1: int_osc File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/int_osc/synthesis/int_osc.vhd Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file int_osc/synthesis/submodules/altera_int_osc.v Info (12023): Found entity 1: altera_int_osc File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/int_osc/synthesis/submodules/altera_int_osc.v Line: 38 Info (12021): Found 2 design units, including 1 entities, in source file pll.vhd Info (12022): Found design unit 1: pll-SYN File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/pll.vhd Line: 55 Info (12023): Found entity 1: pll File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/pll.vhd Line: 43 Info (12021): Found 2 design units, including 1 entities, in source file flash/synthesis/flash.vhd Info (12022): Found design unit 1: flash-rtl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/flash/synthesis/flash.vhd Line: 29 Info (12023): Found entity 1: flash File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/flash/synthesis/flash.vhd Line: 9 Info (12021): Found 7 design units, including 7 entities, in source file flash/synthesis/submodules/altera_onchip_flash_util.v Info (12023): Found entity 1: altera_onchip_flash_address_range_check File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/flash/synthesis/submodules/altera_onchip_flash_util.v Line: 38 Info (12023): Found entity 2: altera_onchip_flash_address_write_protection_check File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/flash/synthesis/submodules/altera_onchip_flash_util.v Line: 55 Info (12023): Found entity 3: altera_onchip_flash_s_address_write_protection_check File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/flash/synthesis/submodules/altera_onchip_flash_util.v Line: 109 Info (12023): Found entity 4: altera_onchip_flash_a_address_write_protection_check File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/flash/synthesis/submodules/altera_onchip_flash_util.v Line: 147 Info (12023): Found entity 5: altera_onchip_flash_convert_address File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/flash/synthesis/submodules/altera_onchip_flash_util.v Line: 197 Info (12023): Found entity 6: altera_onchip_flash_convert_sector File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/flash/synthesis/submodules/altera_onchip_flash_util.v Line: 219 Info (12023): Found entity 7: altera_onchip_flash_counter File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/flash/synthesis/submodules/altera_onchip_flash_util.v Line: 244 Info (12021): Found 1 design units, including 1 entities, in source file flash/synthesis/submodules/altera_onchip_flash.v Info (12023): Found entity 1: altera_onchip_flash File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/flash/synthesis/submodules/altera_onchip_flash.v Line: 38 Info (12021): Found 1 design units, including 1 entities, in source file flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v Info (12023): Found entity 1: altera_onchip_flash_avmm_data_controller File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v Line: 38 Info (12021): Found 1 design units, including 1 entities, in source file flash/synthesis/submodules/altera_onchip_flash_avmm_csr_controller.v Info (12023): Found entity 1: altera_onchip_flash_avmm_csr_controller File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/flash/synthesis/submodules/altera_onchip_flash_avmm_csr_controller.v Line: 38 Info (12021): Found 1 design units, including 1 entities, in source file flash/synthesis/submodules/rtl/altera_onchip_flash_block.v Info (12023): Found entity 1: altera_onchip_flash_block File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/flash/synthesis/submodules/rtl/altera_onchip_flash_block.v Line: 38 Info (12021): Found 2 design units, including 1 entities, in source file lvds_tx.vhd Info (12022): Found design unit 1: lvds_tx-rtl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/lvds_tx.vhd Line: 18 Info (12023): Found entity 1: lvds_tx File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/lvds_tx.vhd Line: 11 Info (12021): Found 1 design units, including 1 entities, in source file lvds_tx/altera_soft_lvds_tx_uCmMXfGB.v Info (12023): Found entity 1: altera_soft_lvds_tx_uCmMXfGB File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/lvds_tx/altera_soft_lvds_tx_uCmMXfGB.v Line: 29 Info (12021): Found 2 design units, including 1 entities, in source file lvds_rx.vhd Info (12022): Found design unit 1: lvds_rx-rtl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/lvds_rx.vhd Line: 19 Info (12023): Found entity 1: lvds_rx File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/lvds_rx.vhd Line: 11 Info (12021): Found 1 design units, including 1 entities, in source file lvds_rx/altera_soft_lvds_rx_uCmNW05P.v Info (12023): Found entity 1: altera_soft_lvds_rx_uCmNW05P File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/lvds_rx/altera_soft_lvds_rx_uCmNW05P.v Line: 29 Info (12127): Elaborating entity "sidmax" for the top level hierarchy Warning (10036): Verilog HDL or VHDL warning at sidmax.vhd(203): object "SIGMADELTA_DITHER2" assigned a value but never read File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sidmax.vhd Line: 203 Warning (10541): VHDL Signal Declaration warning at sidmax.vhd(399): used implicit default value for signal "CLK49152" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sidmax.vhd Line: 399 Warning (10541): VHDL Signal Declaration warning at sidmax.vhd(401): used implicit default value for signal "adc_reg" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sidmax.vhd Line: 401 Warning (10036): Verilog HDL or VHDL warning at sidmax.vhd(402): object "adc_next" assigned a value but never read File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sidmax.vhd Line: 402 Warning (10541): VHDL Signal Declaration warning at sidmax.vhd(404): used implicit default value for signal "adc_use_reg" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sidmax.vhd Line: 404 Warning (10036): Verilog HDL or VHDL warning at sidmax.vhd(405): object "adc_use_next" assigned a value but never read File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sidmax.vhd Line: 405 Warning (10541): VHDL Signal Declaration warning at sidmax.vhd(407): used implicit default value for signal "adc_frozen_reg" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sidmax.vhd Line: 407 Warning (10036): Verilog HDL or VHDL warning at sidmax.vhd(408): object "adc_frozen_next" assigned a value but never read File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sidmax.vhd Line: 408 Warning (10541): VHDL Signal Declaration warning at sidmax.vhd(412): used implicit default value for signal "adc_in_signed" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sidmax.vhd Line: 412 Warning (10445): VHDL Subtype or Type Declaration warning at sidmax.vhd(522): subtype or type has null range File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sidmax.vhd Line: 522 Warning (10296): VHDL warning at sidmax.vhd(522): ignored assignment of value to null range File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sidmax.vhd Line: 522 Warning (10445): VHDL Subtype or Type Declaration warning at sidmax.vhd(525): subtype or type has null range File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sidmax.vhd Line: 525 Warning (10296): VHDL warning at sidmax.vhd(525): ignored assignment of value to null range File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sidmax.vhd Line: 525 Critical Warning (10920): VHDL Incomplete Partial Association warning at sidmax.vhd(499): port or argument "flash_req_request" has 1/8 unassociated elements File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sidmax.vhd Line: 499 Critical Warning (10920): VHDL Incomplete Partial Association warning at sidmax.vhd(499): port or argument "flash_req_complete_slow" has 1/8 unassociated elements File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sidmax.vhd Line: 499 Warning (10492): VHDL Process Statement warning at sidmax.vhd(1595): signal "ADC_VOLUME_REG" is read inside the Process Statement but isn't in the Process Statement's sensitivity list File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sidmax.vhd Line: 1595 Warning (10492): VHDL Process Statement warning at sidmax.vhd(1597): signal "SIO_DATA_VOLUME_REG" is read inside the Process Statement but isn't in the Process Statement's sensitivity list File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sidmax.vhd Line: 1597 Info (12128): Elaborating entity "int_osc" for hierarchy "int_osc:oscillator" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sidmax.vhd Line: 468 Info (12128): Elaborating entity "altera_int_osc" for hierarchy "int_osc:oscillator|altera_int_osc:int_osc_0" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/int_osc/synthesis/int_osc.vhd Line: 31 Info (12128): Elaborating entity "flash_controller" for hierarchy "flash_controller:\flash_on:flash_controller_inst" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sidmax.vhd Line: 499 Info (12128): Elaborating entity "flash" for hierarchy "flash_controller:\flash_on:flash_controller_inst|flash:flash1" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/flash_controller.vhd Line: 141 Warning (10296): VHDL warning at flash.vhd(102): ignored assignment of value to null range File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/flash/synthesis/flash.vhd Line: 102 Warning (10296): VHDL warning at flash.vhd(103): ignored assignment of value to null range File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/flash/synthesis/flash.vhd Line: 103 Info (12128): Elaborating entity "altera_onchip_flash" for hierarchy "flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/flash/synthesis/flash.vhd Line: 100 Info (12128): Elaborating entity "altera_onchip_flash_avmm_csr_controller" for hierarchy "flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/flash/synthesis/submodules/altera_onchip_flash.v Line: 203 Info (12128): Elaborating entity "altera_onchip_flash_avmm_data_controller" for hierarchy "flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/flash/synthesis/submodules/altera_onchip_flash.v Line: 282 Warning (10036): Verilog HDL or VHDL warning at altera_onchip_flash_avmm_data_controller.v(197): object "avmm_read_state" assigned a value but never read File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v Line: 197 Warning (10036): Verilog HDL or VHDL warning at altera_onchip_flash_avmm_data_controller.v(203): object "flash_seq_read_ardin" assigned a value but never read File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v Line: 203 Warning (10036): Verilog HDL or VHDL warning at altera_onchip_flash_avmm_data_controller.v(205): object "flash_ardin_align_reg" assigned a value but never read File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v Line: 205 Warning (10036): Verilog HDL or VHDL warning at altera_onchip_flash_avmm_data_controller.v(206): object "flash_ardin_align_backup_reg" assigned a value but never read File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v Line: 206 Warning (10036): Verilog HDL or VHDL warning at altera_onchip_flash_avmm_data_controller.v(208): object "avmm_burstcount_reg" assigned a value but never read File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v Line: 208 Info (12128): Elaborating entity "altera_std_synchronizer" for hierarchy "flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_std_synchronizer:stdsync_busy" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v Line: 570 Info (12130): Elaborated megafunction instantiation "flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_std_synchronizer:stdsync_busy" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v Line: 570 Info (12133): Instantiated megafunction "flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_std_synchronizer:stdsync_busy" with the following parameter: File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v Line: 570 Info (12134): Parameter "depth" = "2" Info (12128): Elaborating entity "lpm_shiftreg" for hierarchy "flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|lpm_shiftreg:ufm_data_shiftreg" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v Line: 1183 Info (12130): Elaborated megafunction instantiation "flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|lpm_shiftreg:ufm_data_shiftreg" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v Line: 1183 Info (12133): Instantiated megafunction "flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|lpm_shiftreg:ufm_data_shiftreg" with the following parameter: File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v Line: 1183 Info (12134): Parameter "lpm_type" = "LPM_SHIFTREG" Info (12134): Parameter "lpm_width" = "32" Info (12134): Parameter "lpm_direction" = "LEFT" Info (12128): Elaborating entity "altera_onchip_flash_address_range_check" for hierarchy "flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_onchip_flash_address_range_check:address_range_checker" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v Line: 1193 Info (12128): Elaborating entity "altera_onchip_flash_convert_address" for hierarchy "flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_onchip_flash_convert_address:address_convertor" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v Line: 1204 Info (12128): Elaborating entity "altera_onchip_flash_a_address_write_protection_check" for hierarchy "flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_onchip_flash_a_address_write_protection_check:access_address_write_protection_checker" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v Line: 1246 Info (12128): Elaborating entity "altera_onchip_flash_s_address_write_protection_check" for hierarchy "flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_onchip_flash_s_address_write_protection_check:sector_address_write_protection_checker" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v Line: 1256 Info (12128): Elaborating entity "altera_onchip_flash_convert_sector" for hierarchy "flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_onchip_flash_convert_sector:sector_convertor" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v Line: 1267 Info (12128): Elaborating entity "altera_onchip_flash_block" for hierarchy "flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_block:altera_onchip_flash_block" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/flash/synthesis/submodules/altera_onchip_flash.v Line: 327 Info (12128): Elaborating entity "synchronizer" for hierarchy "synchronizer:synchronizer_fancy_enable" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sidmax.vhd Line: 597 Info (12128): Elaborating entity "pll" for hierarchy "pll:pll_inst" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sidmax.vhd Line: 605 Info (12128): Elaborating entity "altpll" for hierarchy "pll:pll_inst|altpll:altpll_component" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/pll.vhd Line: 154 Info (12130): Elaborated megafunction instantiation "pll:pll_inst|altpll:altpll_component" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/pll.vhd Line: 154 Info (12133): Instantiated megafunction "pll:pll_inst|altpll:altpll_component" with the following parameter: File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/pll.vhd Line: 154 Info (12134): Parameter "bandwidth_type" = "AUTO" Info (12134): Parameter "clk0_divide_by" = "3" Info (12134): Parameter "clk0_duty_cycle" = "50" Info (12134): Parameter "clk0_multiply_by" = "2" Info (12134): Parameter "clk0_phase_shift" = "0" Info (12134): Parameter "clk1_divide_by" = "3" Info (12134): Parameter "clk1_duty_cycle" = "50" Info (12134): Parameter "clk1_multiply_by" = "4" Info (12134): Parameter "clk1_phase_shift" = "0" Info (12134): Parameter "clk2_divide_by" = "9" Info (12134): Parameter "clk2_duty_cycle" = "50" Info (12134): Parameter "clk2_multiply_by" = "11" Info (12134): Parameter "clk2_phase_shift" = "0" Info (12134): Parameter "inclk0_input_frequency" = "11446" Info (12134): Parameter "intended_device_family" = "MAX 10" Info (12134): Parameter "lpm_hint" = "CBX_MODULE_PREFIX=pll" Info (12134): Parameter "lpm_type" = "altpll" Info (12134): Parameter "operation_mode" = "NO_COMPENSATION" Info (12134): Parameter "pll_type" = "AUTO" Info (12134): Parameter "port_activeclock" = "PORT_UNUSED" Info (12134): Parameter "port_areset" = "PORT_UNUSED" Info (12134): Parameter "port_clkbad0" = "PORT_UNUSED" Info (12134): Parameter "port_clkbad1" = "PORT_UNUSED" Info (12134): Parameter "port_clkloss" = "PORT_UNUSED" Info (12134): Parameter "port_clkswitch" = "PORT_UNUSED" Info (12134): Parameter "port_configupdate" = "PORT_UNUSED" Info (12134): Parameter "port_fbin" = "PORT_UNUSED" Info (12134): Parameter "port_inclk0" = "PORT_USED" Info (12134): Parameter "port_inclk1" = "PORT_UNUSED" Info (12134): Parameter "port_locked" = "PORT_USED" Info (12134): Parameter "port_pfdena" = "PORT_UNUSED" Info (12134): Parameter "port_phasecounterselect" = "PORT_UNUSED" Info (12134): Parameter "port_phasedone" = "PORT_UNUSED" Info (12134): Parameter "port_phasestep" = "PORT_UNUSED" Info (12134): Parameter "port_phaseupdown" = "PORT_UNUSED" Info (12134): Parameter "port_pllena" = "PORT_UNUSED" Info (12134): Parameter "port_scanaclr" = "PORT_UNUSED" Info (12134): Parameter "port_scanclk" = "PORT_UNUSED" Info (12134): Parameter "port_scanclkena" = "PORT_UNUSED" Info (12134): Parameter "port_scandata" = "PORT_UNUSED" Info (12134): Parameter "port_scandataout" = "PORT_UNUSED" Info (12134): Parameter "port_scandone" = "PORT_UNUSED" Info (12134): Parameter "port_scanread" = "PORT_UNUSED" Info (12134): Parameter "port_scanwrite" = "PORT_UNUSED" Info (12134): Parameter "port_clk0" = "PORT_USED" Info (12134): Parameter "port_clk1" = "PORT_USED" Info (12134): Parameter "port_clk2" = "PORT_USED" Info (12134): Parameter "port_clk3" = "PORT_UNUSED" Info (12134): Parameter "port_clk4" = "PORT_UNUSED" Info (12134): Parameter "port_clk5" = "PORT_UNUSED" Info (12134): Parameter "port_clkena0" = "PORT_UNUSED" Info (12134): Parameter "port_clkena1" = "PORT_UNUSED" Info (12134): Parameter "port_clkena2" = "PORT_UNUSED" Info (12134): Parameter "port_clkena3" = "PORT_UNUSED" Info (12134): Parameter "port_clkena4" = "PORT_UNUSED" Info (12134): Parameter "port_clkena5" = "PORT_UNUSED" Info (12134): Parameter "port_extclk0" = "PORT_UNUSED" Info (12134): Parameter "port_extclk1" = "PORT_UNUSED" Info (12134): Parameter "port_extclk2" = "PORT_UNUSED" Info (12134): Parameter "port_extclk3" = "PORT_UNUSED" Info (12134): Parameter "self_reset_on_loss_lock" = "OFF" Info (12134): Parameter "width_clock" = "5" Info (12021): Found 1 design units, including 1 entities, in source file db/pll_altpll.v Info (12023): Found entity 1: pll_altpll File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/db/pll_altpll.v Line: 30 Info (12128): Elaborating entity "pll_altpll" for hierarchy "pll:pll_inst|altpll:altpll_component|pll_altpll:auto_generated" File: /home/markw/intelFPGA_lite/25.1std/quartus/libraries/megafunctions/altpll.tdf Line: 898 Info (12128): Elaborating entity "slave_timing_6502" for hierarchy "slave_timing_6502:bus_adapt" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sidmax.vhd Line: 619 Info (12128): Elaborating entity "stereo_detect" for hierarchy "stereo_detect:\auto_stereo:a4" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sidmax.vhd Line: 655 Info (12128): Elaborating entity "pokey_mixer_mux" for hierarchy "pokey_mixer_mux:pokey_mixer_both" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sidmax.vhd Line: 732 Info (12128): Elaborating entity "pokey" for hierarchy "pokey:\POKEY_ON:0:pokeyx" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sidmax.vhd Line: 777 Info (12128): Elaborating entity "complete_address_decoder" for hierarchy "pokey:\POKEY_ON:0:pokeyx|complete_address_decoder:decode_addr1" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/pokey/pokey.vhdl Line: 621 Info (12128): Elaborating entity "wide_delay_line" for hierarchy "pokey:\POKEY_ON:0:pokeyx|wide_delay_line:audf0_delay" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/pokey/pokey.vhdl Line: 657 Warning (10445): VHDL Subtype or Type Declaration warning at wide_delay_line.vhdl(47): subtype or type has null range File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/wide_delay_line.vhdl Line: 47 Info (12128): Elaborating entity "pokey_countdown_timer" for hierarchy "pokey:\POKEY_ON:0:pokeyx|pokey_countdown_timer:timer0" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/pokey/pokey.vhdl Line: 674 Info (12128): Elaborating entity "delay_line" for hierarchy "pokey:\POKEY_ON:0:pokeyx|pokey_countdown_timer:timer0|delay_line:underflow0_delay" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/pokey/pokey_countdown_timer.vhdl Line: 62 Info (12128): Elaborating entity "latch_delay_line" for hierarchy "pokey:\POKEY_ON:0:pokeyx|latch_delay_line:twotone_del" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/pokey/pokey.vhdl Line: 701 Info (12128): Elaborating entity "latch_delay_line" for hierarchy "pokey:\POKEY_ON:0:pokeyx|latch_delay_line:stimer_delay" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/pokey/pokey.vhdl Line: 914 Info (12128): Elaborating entity "pokey_noise_filter" for hierarchy "pokey:\POKEY_ON:0:pokeyx|pokey_noise_filter:pokey_noise_filter0" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/pokey/pokey.vhdl Line: 921 Info (12128): Elaborating entity "syncreset_enable_divider" for hierarchy "pokey:\POKEY_ON:0:pokeyx|syncreset_enable_divider:enable_64_div" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/pokey/pokey.vhdl Line: 981 Info (12128): Elaborating entity "syncreset_enable_divider" for hierarchy "pokey:\POKEY_ON:0:pokeyx|syncreset_enable_divider:enable_15_div" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/pokey/pokey.vhdl Line: 985 Info (12128): Elaborating entity "pokey_poly_17_9" for hierarchy "pokey:\POKEY_ON:0:pokeyx|pokey_poly_17_9:poly_17_19_lfsr" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/pokey/pokey.vhdl Line: 992 Info (12128): Elaborating entity "pokey_poly_5" for hierarchy "pokey:\POKEY_ON:0:pokeyx|pokey_poly_5:poly_5_lfsr" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/pokey/pokey.vhdl Line: 995 Info (12128): Elaborating entity "pokey_poly_4" for hierarchy "pokey:\POKEY_ON:0:pokeyx|pokey_poly_4:poly_4_lfsr" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/pokey/pokey.vhdl Line: 998 Info (12128): Elaborating entity "delay_line" for hierarchy "pokey:\POKEY_ON:0:pokeyx|delay_line:serout_clock_delay" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/pokey/pokey.vhdl Line: 1044 Info (12128): Elaborating entity "delay_line" for hierarchy "pokey:\POKEY_ON:0:pokeyx|delay_line:serin_clock_delay" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/pokey/pokey.vhdl Line: 1048 Info (12128): Elaborating entity "clockgensid" for hierarchy "clockgensid:clockgen1" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sidmax.vhd Line: 802 Info (12128): Elaborating entity "SID_f_distortion_mux" for hierarchy "SID_f_distortion_mux:f_distortion_mux" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sidmax.vhd Line: 831 Info (12128): Elaborating entity "SID_f_distortion" for hierarchy "SID_f_distortion_mux:f_distortion_mux|SID_f_distortion:f_distortion" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/f_distortion_mux.vhdl Line: 50 Info (12128): Elaborating entity "SID_top" for hierarchy "SID_top:sid1" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sidmax.vhd Line: 850 Info (12128): Elaborating entity "complete_address_decoder" for hierarchy "SID_top:sid1|complete_address_decoder:decode_addr1" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/top.vhdl Line: 340 Info (12128): Elaborating entity "SID_oscillator" for hierarchy "SID_top:sid1|SID_oscillator:osc_a" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/top.vhdl Line: 571 Info (12128): Elaborating entity "SID_wavegen" for hierarchy "SID_top:sid1|SID_wavegen:wavegen_a" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/top.vhdl Line: 631 Info (12128): Elaborating entity "SID_envelope" for hierarchy "SID_top:sid1|SID_envelope:envelope_a" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/top.vhdl Line: 708 Info (12128): Elaborating entity "SID_envelope_tapmatch" for hierarchy "SID_top:sid1|SID_envelope_tapmatch:envelope_tapmatcher" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/top.vhdl Line: 771 Info (12128): Elaborating entity "SID_amplitudeModulator" for hierarchy "SID_top:sid1|SID_amplitudeModulator:vol_abc" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/top.vhdl Line: 789 Info (12128): Elaborating entity "SID_preFilterSum" for hierarchy "SID_top:sid1|SID_preFilterSum:prefilter" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/top.vhdl Line: 805 Info (12128): Elaborating entity "SID_filter" for hierarchy "SID_top:sid1|SID_filter:variable_state_filter" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/top.vhdl Line: 966 Info (12128): Elaborating entity "SID_postFilterSum" for hierarchy "SID_top:sid1|SID_postFilterSum:postfilter" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/top.vhdl Line: 986 Info (12128): Elaborating entity "PSG_top" for hierarchy "PSG_top:\psg_on:PSG_1" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sidmax.vhd Line: 975 Info (12128): Elaborating entity "PSG_freqdiv" for hierarchy "PSG_top:\psg_on:PSG_1|PSG_freqdiv:core_ticker" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/PSG/top.vhdl Line: 318 Info (12128): Elaborating entity "PSG_freqdiv" for hierarchy "PSG_top:\psg_on:PSG_1|PSG_freqdiv:channel_a_ticker" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/PSG/top.vhdl Line: 335 Info (12128): Elaborating entity "PSG_freqdiv" for hierarchy "PSG_top:\psg_on:PSG_1|PSG_freqdiv:noise_preticker" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/PSG/top.vhdl Line: 388 Info (12128): Elaborating entity "PSG_freqdiv" for hierarchy "PSG_top:\psg_on:PSG_1|PSG_freqdiv:noise_ticker" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/PSG/top.vhdl Line: 404 Info (12128): Elaborating entity "PSG_noise" for hierarchy "PSG_top:\psg_on:PSG_1|PSG_noise:noise" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/PSG/top.vhdl Line: 420 Info (12128): Elaborating entity "PSG_mixer" for hierarchy "PSG_top:\psg_on:PSG_1|PSG_mixer:mix_a" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/PSG/top.vhdl Line: 432 Info (12128): Elaborating entity "PSG_envelope" for hierarchy "PSG_top:\psg_on:PSG_1|PSG_envelope:envelope" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/PSG/top.vhdl Line: 481 Info (12128): Elaborating entity "PSG_freqdiv" for hierarchy "PSG_top:\psg_on:PSG_1|PSG_envelope:envelope|PSG_freqdiv:envelope_ticker" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/PSG/envelope.vhdl Line: 49 Info (12128): Elaborating entity "PSG_volume" for hierarchy "PSG_top:\psg_on:PSG_1|PSG_volume:vol_a" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/PSG/top.vhdl Line: 497 Info (12128): Elaborating entity "PSG_volume_profile" for hierarchy "PSG_volume_profile:\psg_on:vol_profile1" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sidmax.vhd Line: 1007 Info (12128): Elaborating entity "sample_top" for hierarchy "sample_top:\sample_on:sample1" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sidmax.vhd Line: 1070 Info (12128): Elaborating entity "sample_adpcm" for hierarchy "sample_top:\sample_on:sample1|sample_adpcm:adpcm_decoder" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sample/top.vhdl Line: 257 Info (12128): Elaborating entity "sample_channel" for hierarchy "sample_top:\sample_on:sample1|sample_channel:ch0_inst" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sample/top.vhdl Line: 463 Info (12128): Elaborating entity "generic_ram_infer" for hierarchy "generic_ram_infer:\sample_on:normal_ram:sample_ram_inst" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sidmax.vhd Line: 1133 Info (12128): Elaborating entity "mixer" for hierarchy "mixer:mixer1" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sidmax.vhd Line: 1695 Info (12128): Elaborating entity "sigmadelta_dither" for hierarchy "sigmadelta_dither:dac_dithergen" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sidmax.vhd Line: 1728 Info (12128): Elaborating entity "filtered_sigmadelta" for hierarchy "filtered_sigmadelta:dac_0" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sidmax.vhd Line: 1741 Info (12128): Elaborating entity "sigmadelta_2ndorder_dither" for hierarchy "filtered_sigmadelta:dac_0|sigmadelta_2ndorder_dither:\gen_2ndorder_dither_on:dac_2nd_dither" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/filtered_sigmadelta.vhd Line: 121 Warning (10542): VHDL Variable Declaration warning at sigmadelta_2ndorder_dither.vhd(38): used initial value expression for variable "aw" because variable was never assigned a value File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sigmadelta_2ndorder_dither.vhd Line: 38 Info (12128): Elaborating entity "sigma_delta_adc" for hierarchy "sigma_delta_adc:sdelta" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sidmax.vhd Line: 1847 Info (12128): Elaborating entity "cic_integrator" for hierarchy "sigma_delta_adc:sdelta|cic_integrator:gen_cic[0].cic_inst_u0" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sigma_delta/sigma_delta_adc.sv Line: 77 Info (12128): Elaborating entity "cic_comb" for hierarchy "sigma_delta_adc:sdelta|cic_comb:gen_cic[0].cic_inst_u1" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sigma_delta/sigma_delta_adc.sv Line: 86 Info (12128): Elaborating entity "fir_compensator" for hierarchy "sigma_delta_adc:sdelta|fir_compensator:gen_fir.fir_comp_u0" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sigma_delta/sigma_delta_adc.sv Line: 105 Warning (10230): Verilog HDL assignment warning at fir_compensator.sv(96): truncated value with size 32 to match size of target (22) File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sigma_delta/fir_compensator.sv Line: 96 Info (12128): Elaborating entity "lvds_tx" for hierarchy "lvds_tx:lvds_tx0" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sidmax.vhd Line: 1859 Info (12128): Elaborating entity "altera_soft_lvds_tx_uCmMXfGB" for hierarchy "lvds_tx:lvds_tx0|altera_soft_lvds_tx_uCmMXfGB:lvds_tx_inst" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/lvds_tx.vhd Line: 28 Info (12128): Elaborating entity "lvds_rx" for hierarchy "lvds_rx:lvds_rx0" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sidmax.vhd Line: 1865 Info (12128): Elaborating entity "altera_soft_lvds_rx_uCmNW05P" for hierarchy "lvds_rx:lvds_rx0|altera_soft_lvds_rx_uCmNW05P:lvds_rx_inst" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/lvds_rx.vhd Line: 30 Info (12128): Elaborating entity "simple_low_pass_filter" for hierarchy "simple_low_pass_filter:adcfilter" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sidmax.vhd Line: 1915 Info (19000): Inferred 1 megafunctions from design logic Info (276029): Inferred altsyncram megafunction from the following design logic: "generic_ram_infer:\sample_on:normal_ram:sample_ram_inst|ram_block_rtl_0" Info (286033): Parameter OPERATION_MODE set to SINGLE_PORT Info (286033): Parameter WIDTH_A set to 8 Info (286033): Parameter WIDTHAD_A set to 16 Info (286033): Parameter NUMWORDS_A set to 43008 Info (286033): Parameter OUTDATA_REG_A set to UNREGISTERED Info (286033): Parameter ADDRESS_ACLR_A set to NONE Info (286033): Parameter OUTDATA_ACLR_A set to NONE Info (286033): Parameter INDATA_ACLR_A set to NONE Info (286033): Parameter WRCONTROL_ACLR_A set to NONE Info (278001): Inferred 17 megafunctions from design logic Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "clockgensid:clockgen1|Mult0" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/clockgensid.vhd Line: 102 Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "sample_top:\sample_on:sample1|sample_adpcm:adpcm_decoder|Mult0" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sample/adpcm.vhdl Line: 343 Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "sample_top:\sample_on:sample1|Mult3" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sample/top.vhdl Line: 547 Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "sample_top:\sample_on:sample1|Mult2" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sample/top.vhdl Line: 546 Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "SID_top:sid2|SID_postFilterSum:postfilter|Mult0" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/postFilterSum.vhdl Line: 87 Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "sample_top:\sample_on:sample1|Mult1" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sample/top.vhdl Line: 545 Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "sample_top:\sample_on:sample1|Mult0" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sample/top.vhdl Line: 544 Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "SID_top:sid1|SID_postFilterSum:postfilter|Mult0" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/postFilterSum.vhdl Line: 87 Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "SID_top:sid2|SID_amplitudeModulator:vol_abc|Mult0" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/amplitudeModulator.vhdl Line: 65 Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "SID_top:sid2|SID_filter:variable_state_filter|Mult4" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/filter.vhdl Line: 220 Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "SID_top:sid1|SID_amplitudeModulator:vol_abc|Mult0" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/amplitudeModulator.vhdl Line: 65 Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "SID_top:sid1|SID_filter:variable_state_filter|Mult4" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/filter.vhdl Line: 220 Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "SID_top:sid2|SID_filter:variable_state_filter|Mult3" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/filter.vhdl Line: 213 Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "SID_top:sid1|SID_filter:variable_state_filter|Mult3" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/filter.vhdl Line: 213 Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "SID_top:sid2|SID_filter:variable_state_filter|Mult0" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/filter.vhdl Line: 198 Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "SID_top:sid1|SID_filter:variable_state_filter|Mult0" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/filter.vhdl Line: 198 Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "SID_f_distortion_mux:f_distortion_mux|SID_f_distortion:f_distortion|Mult0" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/f_distortion.vhdl Line: 84 Info (12130): Elaborated megafunction instantiation "generic_ram_infer:\sample_on:normal_ram:sample_ram_inst|altsyncram:ram_block_rtl_0" Info (12133): Instantiated megafunction "generic_ram_infer:\sample_on:normal_ram:sample_ram_inst|altsyncram:ram_block_rtl_0" with the following parameter: Info (12134): Parameter "OPERATION_MODE" = "SINGLE_PORT" Info (12134): Parameter "WIDTH_A" = "8" Info (12134): Parameter "WIDTHAD_A" = "16" Info (12134): Parameter "NUMWORDS_A" = "43008" Info (12134): Parameter "OUTDATA_REG_A" = "UNREGISTERED" Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE" Info (12134): Parameter "OUTDATA_ACLR_A" = "NONE" Info (12134): Parameter "INDATA_ACLR_A" = "NONE" Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_6t31.tdf Info (12023): Found entity 1: altsyncram_6t31 File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/db/altsyncram_6t31.tdf Line: 34 Info (12021): Found 1 design units, including 1 entities, in source file db/decode_f7a.tdf Info (12023): Found entity 1: decode_f7a File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/db/decode_f7a.tdf Line: 23 Info (12021): Found 1 design units, including 1 entities, in source file db/decode_8j9.tdf Info (12023): Found entity 1: decode_8j9 File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/db/decode_8j9.tdf Line: 23 Info (12021): Found 1 design units, including 1 entities, in source file db/mux_v1b.tdf Info (12023): Found entity 1: mux_v1b File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/db/mux_v1b.tdf Line: 23 Info (12130): Elaborated megafunction instantiation "clockgensid:clockgen1|lpm_mult:Mult0" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/clockgensid.vhd Line: 102 Info (12133): Instantiated megafunction "clockgensid:clockgen1|lpm_mult:Mult0" with the following parameter: File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/clockgensid.vhd Line: 102 Info (12134): Parameter "LPM_WIDTHA" = "6" Info (12134): Parameter "LPM_WIDTHB" = "9" Info (12134): Parameter "LPM_WIDTHP" = "15" Info (12134): Parameter "LPM_WIDTHR" = "15" Info (12134): Parameter "LPM_WIDTHS" = "1" Info (12134): Parameter "LPM_REPRESENTATION" = "UNSIGNED" Info (12134): Parameter "INPUT_A_IS_CONSTANT" = "NO" Info (12134): Parameter "INPUT_B_IS_CONSTANT" = "NO" Info (12134): Parameter "MAXIMIZE_SPEED" = "5" Info (12021): Found 1 design units, including 1 entities, in source file db/mult_uks.tdf Info (12023): Found entity 1: mult_uks File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/db/mult_uks.tdf Line: 29 Info (12130): Elaborated megafunction instantiation "sample_top:\sample_on:sample1|sample_adpcm:adpcm_decoder|lpm_mult:Mult0" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sample/adpcm.vhdl Line: 343 Info (12133): Instantiated megafunction "sample_top:\sample_on:sample1|sample_adpcm:adpcm_decoder|lpm_mult:Mult0" with the following parameter: File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sample/adpcm.vhdl Line: 343 Info (12134): Parameter "LPM_WIDTHA" = "5" Info (12134): Parameter "LPM_WIDTHB" = "16" Info (12134): Parameter "LPM_WIDTHP" = "21" Info (12134): Parameter "LPM_WIDTHR" = "21" Info (12134): Parameter "LPM_WIDTHS" = "1" Info (12134): Parameter "LPM_REPRESENTATION" = "SIGNED" Info (12134): Parameter "INPUT_A_IS_CONSTANT" = "NO" Info (12134): Parameter "INPUT_B_IS_CONSTANT" = "NO" Info (12134): Parameter "MAXIMIZE_SPEED" = "5" Info (12021): Found 1 design units, including 1 entities, in source file db/mult_5fs.tdf Info (12023): Found entity 1: mult_5fs File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/db/mult_5fs.tdf Line: 29 Info (12130): Elaborated megafunction instantiation "sample_top:\sample_on:sample1|lpm_mult:Mult3" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sample/top.vhdl Line: 547 Info (12133): Instantiated megafunction "sample_top:\sample_on:sample1|lpm_mult:Mult3" with the following parameter: File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sample/top.vhdl Line: 547 Info (12134): Parameter "LPM_WIDTHA" = "13" Info (12134): Parameter "LPM_WIDTHB" = "7" Info (12134): Parameter "LPM_WIDTHP" = "20" Info (12134): Parameter "LPM_WIDTHR" = "20" Info (12134): Parameter "LPM_WIDTHS" = "1" Info (12134): Parameter "LPM_REPRESENTATION" = "SIGNED" Info (12134): Parameter "INPUT_A_IS_CONSTANT" = "NO" Info (12134): Parameter "INPUT_B_IS_CONSTANT" = "NO" Info (12134): Parameter "MAXIMIZE_SPEED" = "6" Info (12021): Found 1 design units, including 1 entities, in source file db/mult_4fs.tdf Info (12023): Found entity 1: mult_4fs File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/db/mult_4fs.tdf Line: 29 Info (12130): Elaborated megafunction instantiation "SID_top:sid2|SID_postFilterSum:postfilter|lpm_mult:Mult0" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/postFilterSum.vhdl Line: 87 Info (12133): Instantiated megafunction "SID_top:sid2|SID_postFilterSum:postfilter|lpm_mult:Mult0" with the following parameter: File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/postFilterSum.vhdl Line: 87 Info (12134): Parameter "LPM_WIDTHA" = "18" Info (12134): Parameter "LPM_WIDTHB" = "8" Info (12134): Parameter "LPM_WIDTHP" = "26" Info (12134): Parameter "LPM_WIDTHR" = "26" Info (12134): Parameter "LPM_WIDTHS" = "1" Info (12134): Parameter "LPM_REPRESENTATION" = "SIGNED" Info (12134): Parameter "INPUT_A_IS_CONSTANT" = "NO" Info (12134): Parameter "INPUT_B_IS_CONSTANT" = "NO" Info (12134): Parameter "MAXIMIZE_SPEED" = "6" Info (12021): Found 1 design units, including 1 entities, in source file db/mult_gfs.tdf Info (12023): Found entity 1: mult_gfs File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/db/mult_gfs.tdf Line: 29 Info (12130): Elaborated megafunction instantiation "SID_top:sid2|SID_amplitudeModulator:vol_abc|lpm_mult:Mult0" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/amplitudeModulator.vhdl Line: 65 Info (12133): Instantiated megafunction "SID_top:sid2|SID_amplitudeModulator:vol_abc|lpm_mult:Mult0" with the following parameter: File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/amplitudeModulator.vhdl Line: 65 Info (12134): Parameter "LPM_WIDTHA" = "9" Info (12134): Parameter "LPM_WIDTHB" = "12" Info (12134): Parameter "LPM_WIDTHP" = "21" Info (12134): Parameter "LPM_WIDTHR" = "21" Info (12134): Parameter "LPM_WIDTHS" = "1" Info (12134): Parameter "LPM_REPRESENTATION" = "SIGNED" Info (12134): Parameter "INPUT_A_IS_CONSTANT" = "NO" Info (12134): Parameter "INPUT_B_IS_CONSTANT" = "NO" Info (12134): Parameter "MAXIMIZE_SPEED" = "6" Info (12021): Found 1 design units, including 1 entities, in source file db/mult_6fs.tdf Info (12023): Found entity 1: mult_6fs File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/db/mult_6fs.tdf Line: 29 Info (12130): Elaborated megafunction instantiation "SID_top:sid2|SID_filter:variable_state_filter|lpm_mult:Mult4" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/filter.vhdl Line: 220 Info (12133): Instantiated megafunction "SID_top:sid2|SID_filter:variable_state_filter|lpm_mult:Mult4" with the following parameter: File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/filter.vhdl Line: 220 Info (12134): Parameter "LPM_WIDTHA" = "14" Info (12134): Parameter "LPM_WIDTHB" = "36" Info (12134): Parameter "LPM_WIDTHP" = "50" Info (12134): Parameter "LPM_WIDTHR" = "50" Info (12134): Parameter "LPM_WIDTHS" = "1" Info (12134): Parameter "LPM_REPRESENTATION" = "SIGNED" Info (12134): Parameter "INPUT_A_IS_CONSTANT" = "NO" Info (12134): Parameter "INPUT_B_IS_CONSTANT" = "NO" Info (12134): Parameter "MAXIMIZE_SPEED" = "5" Info (12021): Found 1 design units, including 1 entities, in source file db/mult_pgs.tdf Info (12023): Found entity 1: mult_pgs File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/db/mult_pgs.tdf Line: 31 Info (12130): Elaborated megafunction instantiation "SID_top:sid2|SID_filter:variable_state_filter|lpm_mult:Mult0" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/filter.vhdl Line: 198 Info (12133): Instantiated megafunction "SID_top:sid2|SID_filter:variable_state_filter|lpm_mult:Mult0" with the following parameter: File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/filter.vhdl Line: 198 Info (12134): Parameter "LPM_WIDTHA" = "36" Info (12134): Parameter "LPM_WIDTHB" = "18" Info (12134): Parameter "LPM_WIDTHP" = "54" Info (12134): Parameter "LPM_WIDTHR" = "54" Info (12134): Parameter "LPM_WIDTHS" = "1" Info (12134): Parameter "LPM_REPRESENTATION" = "SIGNED" Info (12134): Parameter "INPUT_A_IS_CONSTANT" = "NO" Info (12134): Parameter "INPUT_B_IS_CONSTANT" = "NO" Info (12134): Parameter "MAXIMIZE_SPEED" = "5" Info (12021): Found 1 design units, including 1 entities, in source file db/mult_1hs.tdf Info (12023): Found entity 1: mult_1hs File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/db/mult_1hs.tdf Line: 31 Info (12130): Elaborated megafunction instantiation "SID_f_distortion_mux:f_distortion_mux|SID_f_distortion:f_distortion|lpm_mult:Mult0" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/f_distortion.vhdl Line: 84 Info (12133): Instantiated megafunction "SID_f_distortion_mux:f_distortion_mux|SID_f_distortion:f_distortion|lpm_mult:Mult0" with the following parameter: File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/SID/f_distortion.vhdl Line: 84 Info (12134): Parameter "LPM_WIDTHA" = "13" Info (12134): Parameter "LPM_WIDTHB" = "12" Info (12134): Parameter "LPM_WIDTHP" = "25" Info (12134): Parameter "LPM_WIDTHR" = "25" Info (12134): Parameter "LPM_WIDTHS" = "1" Info (12134): Parameter "LPM_REPRESENTATION" = "UNSIGNED" Info (12134): Parameter "INPUT_A_IS_CONSTANT" = "NO" Info (12134): Parameter "INPUT_B_IS_CONSTANT" = "NO" Info (12134): Parameter "MAXIMIZE_SPEED" = "6" Info (12021): Found 1 design units, including 1 entities, in source file db/mult_ons.tdf Info (12023): Found entity 1: mult_ons File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/db/mult_ons.tdf Line: 29 Info (13014): Ignored 502 buffer(s) Info (13019): Ignored 502 SOFT buffer(s) Warning (13027): Removed fan-outs from the following always-disabled I/O buffers Warning (13028): Removed fan-out from the always-disabled I/O buffer "EXT[4]" to the node "EXT[4]" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sidmax.vhd Line: 73 Info (13000): Registers with preset signals will power-up high File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sidmax.vhd Line: 1273 Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back Warning (13024): Output pins are stuck at VCC or GND Warning (13410): Pin "ADC_TX_P" is stuck at GND File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sidmax.vhd Line: 86 Info (286030): Timing-Driven Synthesis is running Info (17049): 203 registers lost all their fanouts during netlist optimizations. Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" Info (16011): Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL Warning (15899): PLL "pll:pll_inst|altpll:altpll_component|pll_altpll:auto_generated|pll1" has parameters clk2_multiply_by and clk2_divide_by specified but port CLK[2] is not connected File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/db/pll_altpll.v Line: 46 Warning (21074): Design contains 1 input pin(s) that do not drive logic Warning (15610): No output dependent on input pin "EXT_IN_P" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sidmax.vhd Line: 88 Info (21057): Implemented 10405 device resources after synthesis - the final resource count might be different Info (21058): Implemented 14 input pins Info (21059): Implemented 5 output pins Info (21060): Implemented 14 bidirectional pins Info (21061): Implemented 10276 logic cells Info (21064): Implemented 48 RAM segments Info (21065): Implemented 1 PLLs Info (21062): Implemented 45 DSP elements Info (21070): Implemented 1 User Flash Memory blocks Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 35 warnings Info: Peak virtual memory: 591 megabytes Info: Processing ended: Sun Jun 7 10:18:22 2026 Info: Elapsed time: 00:00:16 Info: Total CPU time (on all processors): 00:00:20