Timing Analyzer report for sidmax Sun Jun 7 10:19:06 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. Timing Analyzer Summary 3. Parallel Compilation 4. SDC File List 5. Clocks 6. Slow 1200mV 85C Model Fmax Summary 7. Slow 1200mV 85C Model Setup Summary 8. Slow 1200mV 85C Model Hold Summary 9. Slow 1200mV 85C Model Recovery Summary 10. Slow 1200mV 85C Model Removal Summary 11. Slow 1200mV 85C Model Minimum Pulse Width Summary 12. Slow 1200mV 85C Model Metastability Summary 13. Slow 1200mV 0C Model Fmax Summary 14. Slow 1200mV 0C Model Setup Summary 15. Slow 1200mV 0C Model Hold Summary 16. Slow 1200mV 0C Model Recovery Summary 17. Slow 1200mV 0C Model Removal Summary 18. Slow 1200mV 0C Model Minimum Pulse Width Summary 19. Slow 1200mV 0C Model Metastability Summary 20. Fast 1200mV 0C Model Setup Summary 21. Fast 1200mV 0C Model Hold Summary 22. Fast 1200mV 0C Model Recovery Summary 23. Fast 1200mV 0C Model Removal Summary 24. Fast 1200mV 0C Model Minimum Pulse Width Summary 25. Fast 1200mV 0C Model Metastability Summary 26. Multicorner Timing Analysis Summary 27. Board Trace Model Assignments 28. Input Transition Times 29. Signal Integrity Metrics (Slow 1200mv 0c Model) 30. Signal Integrity Metrics (Slow 1200mv 85c Model) 31. Signal Integrity Metrics (Fast 1200mv 0c Model) 32. Setup Transfers 33. Hold Transfers 34. Recovery Transfers 35. Removal Transfers 36. Report TCCS 37. Report RSKM 38. Unconstrained Paths Summary 39. Clock Status Summary 40. Unconstrained Input Ports 41. Unconstrained Output Ports 42. Unconstrained Input Ports 43. Unconstrained Output Ports 44. Timing Analyzer Messages ---------------- ; Legal Notice ; ---------------- Copyright (C) 2025 Altera Corporation. All rights reserved. Your use of Altera Corporation's design tools, logic functions and other software and tools, and any partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, the Altera Quartus Prime License Agreement, the Altera IP License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the Altera Software License Subscription Agreements on the Quartus Prime software download page. +---------------------------------------------------------------------------------+ ; Timing Analyzer Summary ; +-----------------------+---------------------------------------------------------+ ; Quartus Prime Version ; Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; ; Timing Analyzer ; Legacy Timing Analyzer ; ; Revision Name ; sidmax ; ; Device Family ; MAX 10 ; ; Device Name ; 10M08SCU169C8G ; ; Timing Models ; Final ; ; Delay Model ; Combined ; ; Rise/Fall Delays ; Enabled ; +-----------------------+---------------------------------------------------------+ +------------------------------------------+ ; Parallel Compilation ; +----------------------------+-------------+ ; Processors ; Number ; +----------------------------+-------------+ ; Number detected on machine ; 32 ; ; Maximum allowed ; 16 ; ; ; ; ; Average used ; 3.51 ; ; Maximum used ; 16 ; ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; ; Processor 2 ; 19.8% ; ; Processor 3 ; 16.7% ; ; Processor 4 ; 16.6% ; ; Processors 5-16 ; 16.5% ; +----------------------------+-------------+ +----------------------------------------------------------------------------------------+ ; SDC File List ; +----------------------------------------------------+--------+--------------------------+ ; SDC File Path ; Status ; Read at ; +----------------------------------------------------+--------+--------------------------+ ; sidmax.sdc ; OK ; Sun Jun 7 10:19:03 2026 ; ; int_osc/synthesis/submodules/altera_int_osc.sdc ; OK ; Sun Jun 7 10:19:03 2026 ; ; flash/synthesis/submodules/altera_onchip_flash.sdc ; OK ; Sun Jun 7 10:19:03 2026 ; +----------------------------------------------------+--------+--------------------------+ +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Clocks ; +-----------------------------------------------------------------------------------------------+-----------+----------+------------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+----------+--------------------------------------------------------+---------------------------------------------------------------------------------------------------+ ; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ; +-----------------------------------------------------------------------------------------------+-----------+----------+------------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+----------+--------------------------------------------------------+---------------------------------------------------------------------------------------------------+ ; \flash_on:flash_controller_inst|flash1|onchip_flash_0|altera_onchip_flash_block|ufm_block|osc ; Base ; 181.818 ; 5.5 MHz ; 0.000 ; 90.909 ; ; ; ; ; ; ; ; ; ; ; { \flash_on:flash_controller_inst|flash1|onchip_flash_0|altera_onchip_flash_block|ufm_block|osc } ; ; CLK_SLOW ; Base ; 11.446 ; 87.36 MHz ; 0.000 ; 5.723 ; ; ; ; ; ; ; ; ; ; ; { CLK_SLOW } ; ; int_osc_clk ; Base ; 8.620 ; 116.01 MHz ; 0.000 ; 4.310 ; ; ; ; ; ; ; ; ; ; ; { oscillator|int_osc_0|oscillator_dut|clkout } ; ; PHI2 ; Base ; 1000.000 ; 1.0 MHz ; 0.000 ; 500.000 ; ; ; ; ; ; ; ; ; ; ; { PHI2 } ; ; pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Generated ; 17.170 ; 58.24 MHz ; 0.000 ; 8.585 ; 50.00 ; 3 ; 2 ; ; ; ; ; false ; CLK_SLOW ; pll_inst|altpll_component|auto_generated|pll1|inclk[0] ; { pll_inst|altpll_component|auto_generated|pll1|clk[0] } ; ; pll_inst|altpll_component|auto_generated|pll1|clk[1] ; Generated ; 8.585 ; 116.48 MHz ; 0.000 ; 4.292 ; 50.00 ; 3 ; 4 ; ; ; ; ; false ; CLK_SLOW ; pll_inst|altpll_component|auto_generated|pll1|inclk[0] ; { pll_inst|altpll_component|auto_generated|pll1|clk[1] } ; +-----------------------------------------------------------------------------------------------+-----------+----------+------------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+----------+--------------------------------------------------------+---------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Fmax Summary ; +------------+-----------------+------------------------------------------------------+------+ ; Fmax ; Restricted Fmax ; Clock Name ; Note ; +------------+-----------------+------------------------------------------------------+------+ ; 62.6 MHz ; 62.6 MHz ; pll_inst|altpll_component|auto_generated|pll1|clk[0] ; ; ; 104.36 MHz ; 104.36 MHz ; pll_inst|altpll_component|auto_generated|pll1|clk[1] ; ; +------------+-----------------+------------------------------------------------------+------+ This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. +-------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Setup Summary ; +------------------------------------------------------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +------------------------------------------------------+--------+---------------+ ; pll_inst|altpll_component|auto_generated|pll1|clk[1] ; -1.576 ; -5.489 ; ; pll_inst|altpll_component|auto_generated|pll1|clk[0] ; -0.034 ; -0.116 ; +------------------------------------------------------+--------+---------------+ +------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Hold Summary ; +------------------------------------------------------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +------------------------------------------------------+-------+---------------+ ; pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.341 ; 0.000 ; ; pll_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.361 ; 0.000 ; +------------------------------------------------------+-------+---------------+ +------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Recovery Summary ; +------------------------------------------------------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +------------------------------------------------------+-------+---------------+ ; pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 5.674 ; 0.000 ; ; pll_inst|altpll_component|auto_generated|pll1|clk[1] ; 6.116 ; 0.000 ; +------------------------------------------------------+-------+---------------+ +------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Removal Summary ; +------------------------------------------------------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +------------------------------------------------------+-------+---------------+ ; pll_inst|altpll_component|auto_generated|pll1|clk[1] ; 1.471 ; 0.000 ; ; pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 3.125 ; 0.000 ; +------------------------------------------------------+-------+---------------+ +-------------------------------------------------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Minimum Pulse Width Summary ; +-----------------------------------------------------------------------------------------------+---------+---------------+ ; Clock ; Slack ; End Point TNS ; +-----------------------------------------------------------------------------------------------+---------+---------------+ ; pll_inst|altpll_component|auto_generated|pll1|clk[1] ; 1.991 ; 0.000 ; ; CLK_SLOW ; 5.617 ; 0.000 ; ; pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 8.122 ; 0.000 ; ; \flash_on:flash_controller_inst|flash1|onchip_flash_0|altera_onchip_flash_block|ufm_block|osc ; 90.686 ; 0.000 ; ; PHI2 ; 499.745 ; 0.000 ; +-----------------------------------------------------------------------------------------------+---------+---------------+ ----------------------------------------------- ; Slow 1200mV 85C Model Metastability Summary ; ----------------------------------------------- Worst-Case MTBF of Design is 3.17e+05 years or 9.98e+12 seconds. Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. Number of Synchronizer Chains Found: 264 Shortest Synchronizer Chain: 2 Registers Fraction of Chains for which MTBFs Could Not be Calculated: 0.992 Worst Case Available Settling Time: 7.936 ns Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 1.5 Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 3.7 +--------------------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Fmax Summary ; +------------+-----------------+------------------------------------------------------+------+ ; Fmax ; Restricted Fmax ; Clock Name ; Note ; +------------+-----------------+------------------------------------------------------+------+ ; 66.91 MHz ; 66.91 MHz ; pll_inst|altpll_component|auto_generated|pll1|clk[0] ; ; ; 110.04 MHz ; 110.04 MHz ; pll_inst|altpll_component|auto_generated|pll1|clk[1] ; ; +------------+-----------------+------------------------------------------------------+------+ This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. +-------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Setup Summary ; +------------------------------------------------------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +------------------------------------------------------+--------+---------------+ ; pll_inst|altpll_component|auto_generated|pll1|clk[1] ; -1.163 ; -2.570 ; ; pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.245 ; 0.000 ; +------------------------------------------------------+--------+---------------+ +------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Hold Summary ; +------------------------------------------------------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +------------------------------------------------------+-------+---------------+ ; pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.304 ; 0.000 ; ; pll_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.324 ; 0.000 ; +------------------------------------------------------+-------+---------------+ +------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Recovery Summary ; +------------------------------------------------------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +------------------------------------------------------+-------+---------------+ ; pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 6.139 ; 0.000 ; ; pll_inst|altpll_component|auto_generated|pll1|clk[1] ; 6.250 ; 0.000 ; +------------------------------------------------------+-------+---------------+ +------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Removal Summary ; +------------------------------------------------------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +------------------------------------------------------+-------+---------------+ ; pll_inst|altpll_component|auto_generated|pll1|clk[1] ; 1.317 ; 0.000 ; ; pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 2.850 ; 0.000 ; +------------------------------------------------------+-------+---------------+ +-------------------------------------------------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Minimum Pulse Width Summary ; +-----------------------------------------------------------------------------------------------+---------+---------------+ ; Clock ; Slack ; End Point TNS ; +-----------------------------------------------------------------------------------------------+---------+---------------+ ; pll_inst|altpll_component|auto_generated|pll1|clk[1] ; 1.895 ; 0.000 ; ; CLK_SLOW ; 5.636 ; 0.000 ; ; pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 8.124 ; 0.000 ; ; \flash_on:flash_controller_inst|flash1|onchip_flash_0|altera_onchip_flash_block|ufm_block|osc ; 90.672 ; 0.000 ; ; PHI2 ; 499.727 ; 0.000 ; +-----------------------------------------------------------------------------------------------+---------+---------------+ ---------------------------------------------- ; Slow 1200mV 0C Model Metastability Summary ; ---------------------------------------------- Worst-Case MTBF of Design is 1.31e+06 years or 4.12e+13 seconds. Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. Number of Synchronizer Chains Found: 264 Shortest Synchronizer Chain: 2 Registers Fraction of Chains for which MTBFs Could Not be Calculated: 0.992 Worst Case Available Settling Time: 8.192 ns Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 1.5 Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 3.7 +------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Setup Summary ; +------------------------------------------------------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +------------------------------------------------------+-------+---------------+ ; pll_inst|altpll_component|auto_generated|pll1|clk[1] ; 1.374 ; 0.000 ; ; pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 2.576 ; 0.000 ; +------------------------------------------------------+-------+---------------+ +------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Hold Summary ; +------------------------------------------------------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +------------------------------------------------------+-------+---------------+ ; pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.143 ; 0.000 ; ; pll_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.151 ; 0.000 ; +------------------------------------------------------+-------+---------------+ +-------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Recovery Summary ; +------------------------------------------------------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +------------------------------------------------------+--------+---------------+ ; pll_inst|altpll_component|auto_generated|pll1|clk[1] ; 7.436 ; 0.000 ; ; pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 12.504 ; 0.000 ; +------------------------------------------------------+--------+---------------+ +------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Removal Summary ; +------------------------------------------------------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +------------------------------------------------------+-------+---------------+ ; pll_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.624 ; 0.000 ; ; pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 1.235 ; 0.000 ; +------------------------------------------------------+-------+---------------+ +-------------------------------------------------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Minimum Pulse Width Summary ; +-----------------------------------------------------------------------------------------------+---------+---------------+ ; Clock ; Slack ; End Point TNS ; +-----------------------------------------------------------------------------------------------+---------+---------------+ ; pll_inst|altpll_component|auto_generated|pll1|clk[1] ; 2.172 ; 0.000 ; ; CLK_SLOW ; 5.255 ; 0.000 ; ; pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 8.302 ; 0.000 ; ; \flash_on:flash_controller_inst|flash1|onchip_flash_0|altera_onchip_flash_block|ufm_block|osc ; 90.684 ; 0.000 ; ; PHI2 ; 499.229 ; 0.000 ; +-----------------------------------------------------------------------------------------------+---------+---------------+ ---------------------------------------------- ; Fast 1200mV 0C Model Metastability Summary ; ---------------------------------------------- Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. Number of Synchronizer Chains Found: 264 Shortest Synchronizer Chain: 2 Registers Fraction of Chains for which MTBFs Could Not be Calculated: 0.992 Worst Case Available Settling Time: 10.721 ns Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 1.5 Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 3.7 +------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Multicorner Timing Analysis Summary ; +------------------------------------------------------------------------------------------------+--------+-------+----------+---------+---------------------+ ; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; +------------------------------------------------------------------------------------------------+--------+-------+----------+---------+---------------------+ ; Worst-case Slack ; -1.576 ; 0.143 ; 5.674 ; 0.624 ; 1.895 ; ; CLK_SLOW ; N/A ; N/A ; N/A ; N/A ; 5.255 ; ; PHI2 ; N/A ; N/A ; N/A ; N/A ; 499.229 ; ; \flash_on:flash_controller_inst|flash1|onchip_flash_0|altera_onchip_flash_block|ufm_block|osc ; N/A ; N/A ; N/A ; N/A ; 90.672 ; ; pll_inst|altpll_component|auto_generated|pll1|clk[0] ; -0.034 ; 0.143 ; 5.674 ; 1.235 ; 8.122 ; ; pll_inst|altpll_component|auto_generated|pll1|clk[1] ; -1.576 ; 0.151 ; 6.116 ; 0.624 ; 1.895 ; ; Design-wide TNS ; -5.605 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; ; CLK_SLOW ; N/A ; N/A ; N/A ; N/A ; 0.000 ; ; PHI2 ; N/A ; N/A ; N/A ; N/A ; 0.000 ; ; \flash_on:flash_controller_inst|flash1|onchip_flash_0|altera_onchip_flash_block|ufm_block|osc ; N/A ; N/A ; N/A ; N/A ; 0.000 ; ; pll_inst|altpll_component|auto_generated|pll1|clk[0] ; -0.116 ; 0.000 ; 0.000 ; 0.000 ; 0.000 ; ; pll_inst|altpll_component|auto_generated|pll1|clk[1] ; -5.489 ; 0.000 ; 0.000 ; 0.000 ; 0.000 ; +------------------------------------------------------------------------------------------------+--------+-------+----------+---------+---------------------+ +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Board Trace Model Assignments ; +--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ ; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ; +--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ ; CLK_OUT ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; AUDIO_INT ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; AUDIO_LEFT ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; AUDIO_RIGHT ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; ADC_TX_P ; LVDS ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; 100 Ohm ; n/a ; n/a ; n/a ; ; D[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; D[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; D[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; D[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; D[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; D[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; D[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; D[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; EXT[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; EXT[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; EXT[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; EXT[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; POTX_RESET ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; POTY_RESET ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; ~ALTERA_TDO~ ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; ADC_TX_P(n) ; LVDS ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; 100 Ohm ; n/a ; n/a ; n/a ; +--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +--------------------------------------------------------------------------------+ ; Input Transition Times ; +--------------------+-----------------------+-----------------+-----------------+ ; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; +--------------------+-----------------------+-----------------+-----------------+ ; EXT_IN_P ; LVDS ; 2000 ps ; 2000 ps ; ; D[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; D[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; D[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; D[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; D[4] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; D[5] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; D[6] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; D[7] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; EXT[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; EXT[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; EXT[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; EXT[4] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; POTX_RESET ; 2.5 V ; 2000 ps ; 2000 ps ; ; POTY_RESET ; 2.5 V ; 2000 ps ; 2000 ps ; ; RST_N ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; CLK_SLOW ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; PHI2 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; A[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; A[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; A[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; A[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; A[4] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; W_N ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; VDDREDUCED_P ; LVDS ; 2000 ps ; 2000 ps ; ; CS_N ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; POTY_P ; LVDS ; 2000 ps ; 2000 ps ; ; POTX_P ; LVDS ; 2000 ps ; 2000 ps ; ; ~ALTERA_TMS~ ; 3.3 V Schmitt Trigger ; 2640 ps ; 2640 ps ; ; ~ALTERA_TCK~ ; 3.3 V Schmitt Trigger ; 2640 ps ; 2640 ps ; ; ~ALTERA_TDI~ ; 3.3 V Schmitt Trigger ; 2640 ps ; 2640 ps ; ; ~ALTERA_nCONFIG~ ; 3.3 V Schmitt Trigger ; 2640 ps ; 2640 ps ; ; ~ALTERA_nSTATUS~ ; 3.3 V Schmitt Trigger ; 2640 ps ; 2640 ps ; ; ~ALTERA_CONF_DONE~ ; 3.3 V Schmitt Trigger ; 2640 ps ; 2640 ps ; ; EXT_IN_P(n) ; LVDS ; 2000 ps ; 2000 ps ; ; VDDREDUCED_P(n) ; LVDS ; 2000 ps ; 2000 ps ; ; POTY_P(n) ; LVDS ; 2000 ps ; 2000 ps ; ; POTX_P(n) ; LVDS ; 2000 ps ; 2000 ps ; +--------------------+-----------------------+-----------------+-----------------+ +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Signal Integrity Metrics (Slow 1200mv 0c Model) ; +--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; +--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ; CLK_OUT ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 4.02e-08 V ; 3.12 V ; -0.042 V ; 0.21 V ; 0.194 V ; 8.53e-10 s ; 1.01e-09 s ; No ; No ; 3.08 V ; 4.02e-08 V ; 3.12 V ; -0.042 V ; 0.21 V ; 0.194 V ; 8.53e-10 s ; 1.01e-09 s ; No ; No ; ; AUDIO_INT ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.08e-08 V ; 3.19 V ; -0.126 V ; 0.218 V ; 0.383 V ; 4.51e-10 s ; 4.73e-10 s ; No ; No ; 3.08 V ; 2.08e-08 V ; 3.19 V ; -0.126 V ; 0.218 V ; 0.383 V ; 4.51e-10 s ; 4.73e-10 s ; No ; No ; ; AUDIO_LEFT ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.08e-08 V ; 3.19 V ; -0.128 V ; 0.216 V ; 0.383 V ; 4.51e-10 s ; 4.73e-10 s ; No ; No ; 3.08 V ; 2.08e-08 V ; 3.19 V ; -0.128 V ; 0.216 V ; 0.383 V ; 4.51e-10 s ; 4.73e-10 s ; No ; No ; ; AUDIO_RIGHT ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.08e-08 V ; 3.19 V ; -0.128 V ; 0.216 V ; 0.383 V ; 4.51e-10 s ; 4.73e-10 s ; No ; No ; 3.08 V ; 2.08e-08 V ; 3.19 V ; -0.128 V ; 0.216 V ; 0.383 V ; 4.51e-10 s ; 4.73e-10 s ; No ; No ; ; ADC_TX_P ; LVDS ; 0 s ; 0 s ; 0.298 V ; -0.298 V ; - ; - ; - ; - ; 1.14e-10 s ; 1.14e-10 s ; Yes ; Yes ; 0.298 V ; -0.298 V ; - ; - ; - ; - ; 1.14e-10 s ; 1.14e-10 s ; Yes ; Yes ; ; D[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.08e-08 V ; 3.19 V ; -0.128 V ; 0.216 V ; 0.383 V ; 4.51e-10 s ; 4.73e-10 s ; No ; No ; 3.08 V ; 2.08e-08 V ; 3.19 V ; -0.128 V ; 0.216 V ; 0.383 V ; 4.51e-10 s ; 4.73e-10 s ; No ; No ; ; D[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.08e-08 V ; 3.19 V ; -0.126 V ; 0.218 V ; 0.383 V ; 4.51e-10 s ; 4.73e-10 s ; No ; No ; 3.08 V ; 2.08e-08 V ; 3.19 V ; -0.126 V ; 0.218 V ; 0.383 V ; 4.51e-10 s ; 4.73e-10 s ; No ; No ; ; D[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.08e-08 V ; 3.19 V ; -0.126 V ; 0.218 V ; 0.383 V ; 4.51e-10 s ; 4.73e-10 s ; No ; No ; 3.08 V ; 2.08e-08 V ; 3.19 V ; -0.126 V ; 0.218 V ; 0.383 V ; 4.51e-10 s ; 4.73e-10 s ; No ; No ; ; D[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.08e-08 V ; 3.09 V ; -0.0047 V ; 0.291 V ; 0.288 V ; 4.58e-09 s ; 4.89e-09 s ; No ; No ; 3.08 V ; 2.08e-08 V ; 3.09 V ; -0.0047 V ; 0.291 V ; 0.288 V ; 4.58e-09 s ; 4.89e-09 s ; No ; No ; ; D[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.08e-08 V ; 3.19 V ; -0.126 V ; 0.218 V ; 0.383 V ; 4.51e-10 s ; 4.73e-10 s ; No ; No ; 3.08 V ; 2.08e-08 V ; 3.19 V ; -0.126 V ; 0.218 V ; 0.383 V ; 4.51e-10 s ; 4.73e-10 s ; No ; No ; ; D[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.08e-08 V ; 3.19 V ; -0.126 V ; 0.218 V ; 0.383 V ; 4.51e-10 s ; 4.73e-10 s ; No ; No ; 3.08 V ; 2.08e-08 V ; 3.19 V ; -0.126 V ; 0.218 V ; 0.383 V ; 4.51e-10 s ; 4.73e-10 s ; No ; No ; ; D[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.08e-08 V ; 3.19 V ; -0.126 V ; 0.218 V ; 0.383 V ; 4.51e-10 s ; 4.73e-10 s ; No ; No ; 3.08 V ; 2.08e-08 V ; 3.19 V ; -0.126 V ; 0.218 V ; 0.383 V ; 4.51e-10 s ; 4.73e-10 s ; No ; No ; ; D[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.08e-08 V ; 3.19 V ; -0.128 V ; 0.216 V ; 0.383 V ; 4.51e-10 s ; 4.73e-10 s ; No ; No ; 3.08 V ; 2.08e-08 V ; 3.19 V ; -0.128 V ; 0.216 V ; 0.383 V ; 4.51e-10 s ; 4.73e-10 s ; No ; No ; ; EXT[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.08e-08 V ; 3.19 V ; -0.128 V ; 0.216 V ; 0.383 V ; 4.51e-10 s ; 4.73e-10 s ; No ; No ; 3.08 V ; 2.08e-08 V ; 3.19 V ; -0.128 V ; 0.216 V ; 0.383 V ; 4.51e-10 s ; 4.73e-10 s ; No ; No ; ; EXT[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.08e-08 V ; 3.19 V ; -0.128 V ; 0.216 V ; 0.383 V ; 4.51e-10 s ; 4.73e-10 s ; No ; No ; 3.08 V ; 2.08e-08 V ; 3.19 V ; -0.128 V ; 0.216 V ; 0.383 V ; 4.51e-10 s ; 4.73e-10 s ; No ; No ; ; EXT[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.08e-08 V ; 3.19 V ; -0.128 V ; 0.216 V ; 0.383 V ; 4.51e-10 s ; 4.73e-10 s ; No ; No ; 3.08 V ; 2.08e-08 V ; 3.19 V ; -0.128 V ; 0.216 V ; 0.383 V ; 4.51e-10 s ; 4.73e-10 s ; No ; No ; ; EXT[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.08e-08 V ; 3.19 V ; -0.126 V ; 0.218 V ; 0.383 V ; 4.51e-10 s ; 4.73e-10 s ; No ; No ; 3.08 V ; 2.08e-08 V ; 3.19 V ; -0.126 V ; 0.218 V ; 0.383 V ; 4.51e-10 s ; 4.73e-10 s ; No ; No ; ; POTX_RESET ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.47e-09 V ; 2.39 V ; -0.0854 V ; 0.162 V ; 0.204 V ; 4.62e-10 s ; 4.54e-10 s ; No ; Yes ; 2.32 V ; 4.47e-09 V ; 2.39 V ; -0.0854 V ; 0.162 V ; 0.204 V ; 4.62e-10 s ; 4.54e-10 s ; No ; Yes ; ; POTY_RESET ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.47e-09 V ; 2.39 V ; -0.0854 V ; 0.162 V ; 0.204 V ; 4.62e-10 s ; 4.54e-10 s ; No ; Yes ; 2.32 V ; 4.47e-09 V ; 2.39 V ; -0.0854 V ; 0.162 V ; 0.204 V ; 4.62e-10 s ; 4.54e-10 s ; No ; Yes ; ; ~ALTERA_TDO~ ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.08e-08 V ; 3.19 V ; -0.126 V ; 0.218 V ; 0.383 V ; 4.51e-10 s ; 4.73e-10 s ; No ; No ; 3.08 V ; 2.08e-08 V ; 3.19 V ; -0.126 V ; 0.218 V ; 0.383 V ; 4.51e-10 s ; 4.73e-10 s ; No ; No ; ; ADC_TX_P(n) ; LVDS ; 0 s ; 0 s ; 0.298 V ; -0.298 V ; - ; - ; - ; - ; 1.14e-10 s ; 1.14e-10 s ; Yes ; Yes ; 0.298 V ; -0.298 V ; - ; - ; - ; - ; 1.14e-10 s ; 1.14e-10 s ; Yes ; Yes ; +--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Signal Integrity Metrics (Slow 1200mv 85c Model) ; +--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; +--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ; CLK_OUT ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.5e-06 V ; 3.1 V ; -0.0179 V ; 0.19 V ; 0.192 V ; 1.04e-09 s ; 1.19e-09 s ; Yes ; No ; 3.08 V ; 2.5e-06 V ; 3.1 V ; -0.0179 V ; 0.19 V ; 0.192 V ; 1.04e-09 s ; 1.19e-09 s ; Yes ; No ; ; AUDIO_INT ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.3e-06 V ; 3.15 V ; -0.0682 V ; 0.279 V ; 0.237 V ; 4.81e-10 s ; 6.4e-10 s ; Yes ; No ; 3.08 V ; 1.3e-06 V ; 3.15 V ; -0.0682 V ; 0.279 V ; 0.237 V ; 4.81e-10 s ; 6.4e-10 s ; Yes ; No ; ; AUDIO_LEFT ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.3e-06 V ; 3.15 V ; -0.0684 V ; 0.28 V ; 0.237 V ; 4.81e-10 s ; 6.4e-10 s ; Yes ; No ; 3.08 V ; 1.3e-06 V ; 3.15 V ; -0.0684 V ; 0.28 V ; 0.237 V ; 4.81e-10 s ; 6.4e-10 s ; Yes ; No ; ; AUDIO_RIGHT ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.3e-06 V ; 3.15 V ; -0.0684 V ; 0.28 V ; 0.237 V ; 4.81e-10 s ; 6.4e-10 s ; Yes ; No ; 3.08 V ; 1.3e-06 V ; 3.15 V ; -0.0684 V ; 0.28 V ; 0.237 V ; 4.81e-10 s ; 6.4e-10 s ; Yes ; No ; ; ADC_TX_P ; LVDS ; 0 s ; 0 s ; 0.26 V ; -0.26 V ; - ; - ; - ; - ; 1.19e-10 s ; 1.19e-10 s ; Yes ; Yes ; 0.26 V ; -0.26 V ; - ; - ; - ; - ; 1.19e-10 s ; 1.19e-10 s ; Yes ; Yes ; ; D[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.3e-06 V ; 3.15 V ; -0.0684 V ; 0.28 V ; 0.237 V ; 4.81e-10 s ; 6.4e-10 s ; Yes ; No ; 3.08 V ; 1.3e-06 V ; 3.15 V ; -0.0684 V ; 0.28 V ; 0.237 V ; 4.81e-10 s ; 6.4e-10 s ; Yes ; No ; ; D[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.3e-06 V ; 3.15 V ; -0.0682 V ; 0.279 V ; 0.237 V ; 4.81e-10 s ; 6.4e-10 s ; Yes ; No ; 3.08 V ; 1.3e-06 V ; 3.15 V ; -0.0682 V ; 0.279 V ; 0.237 V ; 4.81e-10 s ; 6.4e-10 s ; Yes ; No ; ; D[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.3e-06 V ; 3.15 V ; -0.0682 V ; 0.279 V ; 0.237 V ; 4.81e-10 s ; 6.4e-10 s ; Yes ; No ; 3.08 V ; 1.3e-06 V ; 3.15 V ; -0.0682 V ; 0.279 V ; 0.237 V ; 4.81e-10 s ; 6.4e-10 s ; Yes ; No ; ; D[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.3e-06 V ; 3.09 V ; -0.00259 V ; 0.276 V ; 0.25 V ; 5.46e-09 s ; 6.08e-09 s ; No ; Yes ; 3.08 V ; 1.3e-06 V ; 3.09 V ; -0.00259 V ; 0.276 V ; 0.25 V ; 5.46e-09 s ; 6.08e-09 s ; No ; Yes ; ; D[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.3e-06 V ; 3.15 V ; -0.0682 V ; 0.279 V ; 0.237 V ; 4.81e-10 s ; 6.4e-10 s ; Yes ; No ; 3.08 V ; 1.3e-06 V ; 3.15 V ; -0.0682 V ; 0.279 V ; 0.237 V ; 4.81e-10 s ; 6.4e-10 s ; Yes ; No ; ; D[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.3e-06 V ; 3.15 V ; -0.0682 V ; 0.279 V ; 0.237 V ; 4.81e-10 s ; 6.4e-10 s ; Yes ; No ; 3.08 V ; 1.3e-06 V ; 3.15 V ; -0.0682 V ; 0.279 V ; 0.237 V ; 4.81e-10 s ; 6.4e-10 s ; Yes ; No ; ; D[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.3e-06 V ; 3.15 V ; -0.0682 V ; 0.279 V ; 0.237 V ; 4.81e-10 s ; 6.4e-10 s ; Yes ; No ; 3.08 V ; 1.3e-06 V ; 3.15 V ; -0.0682 V ; 0.279 V ; 0.237 V ; 4.81e-10 s ; 6.4e-10 s ; Yes ; No ; ; D[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.3e-06 V ; 3.15 V ; -0.0684 V ; 0.28 V ; 0.237 V ; 4.81e-10 s ; 6.4e-10 s ; Yes ; No ; 3.08 V ; 1.3e-06 V ; 3.15 V ; -0.0684 V ; 0.28 V ; 0.237 V ; 4.81e-10 s ; 6.4e-10 s ; Yes ; No ; ; EXT[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.3e-06 V ; 3.15 V ; -0.0684 V ; 0.28 V ; 0.237 V ; 4.81e-10 s ; 6.4e-10 s ; Yes ; No ; 3.08 V ; 1.3e-06 V ; 3.15 V ; -0.0684 V ; 0.28 V ; 0.237 V ; 4.81e-10 s ; 6.4e-10 s ; Yes ; No ; ; EXT[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.3e-06 V ; 3.15 V ; -0.0684 V ; 0.28 V ; 0.237 V ; 4.81e-10 s ; 6.4e-10 s ; Yes ; No ; 3.08 V ; 1.3e-06 V ; 3.15 V ; -0.0684 V ; 0.28 V ; 0.237 V ; 4.81e-10 s ; 6.4e-10 s ; Yes ; No ; ; EXT[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.3e-06 V ; 3.15 V ; -0.0684 V ; 0.28 V ; 0.237 V ; 4.81e-10 s ; 6.4e-10 s ; Yes ; No ; 3.08 V ; 1.3e-06 V ; 3.15 V ; -0.0684 V ; 0.28 V ; 0.237 V ; 4.81e-10 s ; 6.4e-10 s ; Yes ; No ; ; EXT[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.3e-06 V ; 3.15 V ; -0.0682 V ; 0.279 V ; 0.237 V ; 4.81e-10 s ; 6.4e-10 s ; Yes ; No ; 3.08 V ; 1.3e-06 V ; 3.15 V ; -0.0682 V ; 0.279 V ; 0.237 V ; 4.81e-10 s ; 6.4e-10 s ; Yes ; No ; ; POTX_RESET ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.66e-07 V ; 2.36 V ; -0.0486 V ; 0.228 V ; 0.114 V ; 5.12e-10 s ; 6.11e-10 s ; Yes ; No ; 2.32 V ; 4.66e-07 V ; 2.36 V ; -0.0486 V ; 0.228 V ; 0.114 V ; 5.12e-10 s ; 6.11e-10 s ; Yes ; No ; ; POTY_RESET ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.66e-07 V ; 2.36 V ; -0.0486 V ; 0.228 V ; 0.114 V ; 5.12e-10 s ; 6.11e-10 s ; Yes ; No ; 2.32 V ; 4.66e-07 V ; 2.36 V ; -0.0486 V ; 0.228 V ; 0.114 V ; 5.12e-10 s ; 6.11e-10 s ; Yes ; No ; ; ~ALTERA_TDO~ ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.3e-06 V ; 3.15 V ; -0.0682 V ; 0.279 V ; 0.237 V ; 4.81e-10 s ; 6.4e-10 s ; Yes ; No ; 3.08 V ; 1.3e-06 V ; 3.15 V ; -0.0682 V ; 0.279 V ; 0.237 V ; 4.81e-10 s ; 6.4e-10 s ; Yes ; No ; ; ADC_TX_P(n) ; LVDS ; 0 s ; 0 s ; 0.26 V ; -0.26 V ; - ; - ; - ; - ; 1.19e-10 s ; 1.19e-10 s ; Yes ; Yes ; 0.26 V ; -0.26 V ; - ; - ; - ; - ; 1.19e-10 s ; 1.19e-10 s ; Yes ; Yes ; +--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Signal Integrity Metrics (Fast 1200mv 0c Model) ; +--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; +--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ; CLK_OUT ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 9.71e-07 V ; 3.53 V ; -0.0288 V ; 0.252 V ; 0.333 V ; 6.56e-10 s ; 7.2e-10 s ; No ; Yes ; 3.46 V ; 9.71e-07 V ; 3.53 V ; -0.0288 V ; 0.252 V ; 0.333 V ; 6.56e-10 s ; 7.2e-10 s ; No ; Yes ; ; AUDIO_INT ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 5.04e-07 V ; 3.64 V ; -0.0201 V ; 0.391 V ; 0.088 V ; 2.79e-10 s ; 3.95e-10 s ; No ; Yes ; 3.46 V ; 5.04e-07 V ; 3.64 V ; -0.0201 V ; 0.391 V ; 0.088 V ; 2.79e-10 s ; 3.95e-10 s ; No ; Yes ; ; AUDIO_LEFT ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 5.04e-07 V ; 3.65 V ; -0.0209 V ; 0.391 V ; 0.09 V ; 2.79e-10 s ; 3.95e-10 s ; No ; Yes ; 3.46 V ; 5.04e-07 V ; 3.65 V ; -0.0209 V ; 0.391 V ; 0.09 V ; 2.79e-10 s ; 3.95e-10 s ; No ; Yes ; ; AUDIO_RIGHT ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 5.04e-07 V ; 3.65 V ; -0.0209 V ; 0.391 V ; 0.09 V ; 2.79e-10 s ; 3.95e-10 s ; No ; Yes ; 3.46 V ; 5.04e-07 V ; 3.65 V ; -0.0209 V ; 0.391 V ; 0.09 V ; 2.79e-10 s ; 3.95e-10 s ; No ; Yes ; ; ADC_TX_P ; LVDS ; 0 s ; 0 s ; 0.462 V ; -0.462 V ; - ; - ; - ; - ; 1.18e-10 s ; 1.18e-10 s ; Yes ; Yes ; 0.462 V ; -0.462 V ; - ; - ; - ; - ; 1.18e-10 s ; 1.18e-10 s ; Yes ; Yes ; ; D[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 5.04e-07 V ; 3.65 V ; -0.0209 V ; 0.391 V ; 0.09 V ; 2.79e-10 s ; 3.95e-10 s ; No ; Yes ; 3.46 V ; 5.04e-07 V ; 3.65 V ; -0.0209 V ; 0.391 V ; 0.09 V ; 2.79e-10 s ; 3.95e-10 s ; No ; Yes ; ; D[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 5.04e-07 V ; 3.64 V ; -0.0201 V ; 0.391 V ; 0.088 V ; 2.79e-10 s ; 3.95e-10 s ; No ; Yes ; 3.46 V ; 5.04e-07 V ; 3.64 V ; -0.0201 V ; 0.391 V ; 0.088 V ; 2.79e-10 s ; 3.95e-10 s ; No ; Yes ; ; D[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 5.04e-07 V ; 3.64 V ; -0.0201 V ; 0.391 V ; 0.088 V ; 2.79e-10 s ; 3.95e-10 s ; No ; Yes ; 3.46 V ; 5.04e-07 V ; 3.64 V ; -0.0201 V ; 0.391 V ; 0.088 V ; 2.79e-10 s ; 3.95e-10 s ; No ; Yes ; ; D[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 5.04e-07 V ; 3.48 V ; -0.00709 V ; 0.333 V ; 0.272 V ; 3.62e-09 s ; 4.03e-09 s ; No ; Yes ; 3.46 V ; 5.04e-07 V ; 3.48 V ; -0.00709 V ; 0.333 V ; 0.272 V ; 3.62e-09 s ; 4.03e-09 s ; No ; Yes ; ; D[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 5.04e-07 V ; 3.64 V ; -0.0201 V ; 0.391 V ; 0.088 V ; 2.79e-10 s ; 3.95e-10 s ; No ; Yes ; 3.46 V ; 5.04e-07 V ; 3.64 V ; -0.0201 V ; 0.391 V ; 0.088 V ; 2.79e-10 s ; 3.95e-10 s ; No ; Yes ; ; D[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 5.04e-07 V ; 3.64 V ; -0.0201 V ; 0.391 V ; 0.088 V ; 2.79e-10 s ; 3.95e-10 s ; No ; Yes ; 3.46 V ; 5.04e-07 V ; 3.64 V ; -0.0201 V ; 0.391 V ; 0.088 V ; 2.79e-10 s ; 3.95e-10 s ; No ; Yes ; ; D[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 5.04e-07 V ; 3.64 V ; -0.0201 V ; 0.391 V ; 0.088 V ; 2.79e-10 s ; 3.95e-10 s ; No ; Yes ; 3.46 V ; 5.04e-07 V ; 3.64 V ; -0.0201 V ; 0.391 V ; 0.088 V ; 2.79e-10 s ; 3.95e-10 s ; No ; Yes ; ; D[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 5.04e-07 V ; 3.65 V ; -0.0209 V ; 0.391 V ; 0.09 V ; 2.79e-10 s ; 3.95e-10 s ; No ; Yes ; 3.46 V ; 5.04e-07 V ; 3.65 V ; -0.0209 V ; 0.391 V ; 0.09 V ; 2.79e-10 s ; 3.95e-10 s ; No ; Yes ; ; EXT[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 5.04e-07 V ; 3.65 V ; -0.0209 V ; 0.391 V ; 0.09 V ; 2.79e-10 s ; 3.95e-10 s ; No ; Yes ; 3.46 V ; 5.04e-07 V ; 3.65 V ; -0.0209 V ; 0.391 V ; 0.09 V ; 2.79e-10 s ; 3.95e-10 s ; No ; Yes ; ; EXT[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 5.04e-07 V ; 3.65 V ; -0.0209 V ; 0.391 V ; 0.09 V ; 2.79e-10 s ; 3.95e-10 s ; No ; Yes ; 3.46 V ; 5.04e-07 V ; 3.65 V ; -0.0209 V ; 0.391 V ; 0.09 V ; 2.79e-10 s ; 3.95e-10 s ; No ; Yes ; ; EXT[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 5.04e-07 V ; 3.65 V ; -0.0209 V ; 0.391 V ; 0.09 V ; 2.79e-10 s ; 3.95e-10 s ; No ; Yes ; 3.46 V ; 5.04e-07 V ; 3.65 V ; -0.0209 V ; 0.391 V ; 0.09 V ; 2.79e-10 s ; 3.95e-10 s ; No ; Yes ; ; EXT[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 5.04e-07 V ; 3.64 V ; -0.0201 V ; 0.391 V ; 0.088 V ; 2.79e-10 s ; 3.95e-10 s ; No ; Yes ; 3.46 V ; 5.04e-07 V ; 3.64 V ; -0.0201 V ; 0.391 V ; 0.088 V ; 2.79e-10 s ; 3.95e-10 s ; No ; Yes ; ; POTX_RESET ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.77 V ; -0.0486 V ; 0.285 V ; 0.06 V ; 2.8e-10 s ; 3.04e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.77 V ; -0.0486 V ; 0.285 V ; 0.06 V ; 2.8e-10 s ; 3.04e-10 s ; No ; Yes ; ; POTY_RESET ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.77 V ; -0.0486 V ; 0.285 V ; 0.06 V ; 2.8e-10 s ; 3.04e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.77 V ; -0.0486 V ; 0.285 V ; 0.06 V ; 2.8e-10 s ; 3.04e-10 s ; No ; Yes ; ; ~ALTERA_TDO~ ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 5.04e-07 V ; 3.64 V ; -0.0201 V ; 0.391 V ; 0.088 V ; 2.79e-10 s ; 3.95e-10 s ; No ; Yes ; 3.46 V ; 5.04e-07 V ; 3.64 V ; -0.0201 V ; 0.391 V ; 0.088 V ; 2.79e-10 s ; 3.95e-10 s ; No ; Yes ; ; ADC_TX_P(n) ; LVDS ; 0 s ; 0 s ; 0.462 V ; -0.462 V ; - ; - ; - ; - ; 1.18e-10 s ; 1.18e-10 s ; Yes ; Yes ; 0.462 V ; -0.462 V ; - ; - ; - ; - ; 1.18e-10 s ; 1.18e-10 s ; Yes ; Yes ; +--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Setup Transfers ; +-----------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------+------------+------------+----------+----------+ ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; +-----------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------+------------+------------+----------+----------+ ; \flash_on:flash_controller_inst|flash1|onchip_flash_0|altera_onchip_flash_block|ufm_block|osc ; \flash_on:flash_controller_inst|flash1|onchip_flash_0|altera_onchip_flash_block|ufm_block|osc ; 2 ; 0 ; 0 ; 0 ; ; PHI2 ; pll_inst|altpll_component|auto_generated|pll1|clk[0] ; false path ; false path ; 0 ; 0 ; ; pll_inst|altpll_component|auto_generated|pll1|clk[0] ; pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 35044194 ; 0 ; 0 ; 0 ; ; pll_inst|altpll_component|auto_generated|pll1|clk[1] ; pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 877 ; 78 ; 0 ; 0 ; ; \flash_on:flash_controller_inst|flash1|onchip_flash_0|altera_onchip_flash_block|ufm_block|osc ; pll_inst|altpll_component|auto_generated|pll1|clk[1] ; 2 ; 0 ; 0 ; 0 ; ; pll_inst|altpll_component|auto_generated|pll1|clk[0] ; pll_inst|altpll_component|auto_generated|pll1|clk[1] ; 5961 ; 0 ; 0 ; 0 ; ; pll_inst|altpll_component|auto_generated|pll1|clk[1] ; pll_inst|altpll_component|auto_generated|pll1|clk[1] ; 10516 ; 208 ; 180 ; 0 ; +-----------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------+------------+------------+----------+----------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Hold Transfers ; +-----------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------+------------+------------+----------+----------+ ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; +-----------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------+------------+------------+----------+----------+ ; \flash_on:flash_controller_inst|flash1|onchip_flash_0|altera_onchip_flash_block|ufm_block|osc ; \flash_on:flash_controller_inst|flash1|onchip_flash_0|altera_onchip_flash_block|ufm_block|osc ; 2 ; 0 ; 0 ; 0 ; ; PHI2 ; pll_inst|altpll_component|auto_generated|pll1|clk[0] ; false path ; false path ; 0 ; 0 ; ; pll_inst|altpll_component|auto_generated|pll1|clk[0] ; pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 35044194 ; 0 ; 0 ; 0 ; ; pll_inst|altpll_component|auto_generated|pll1|clk[1] ; pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 877 ; 78 ; 0 ; 0 ; ; \flash_on:flash_controller_inst|flash1|onchip_flash_0|altera_onchip_flash_block|ufm_block|osc ; pll_inst|altpll_component|auto_generated|pll1|clk[1] ; 2 ; 0 ; 0 ; 0 ; ; pll_inst|altpll_component|auto_generated|pll1|clk[0] ; pll_inst|altpll_component|auto_generated|pll1|clk[1] ; 5961 ; 0 ; 0 ; 0 ; ; pll_inst|altpll_component|auto_generated|pll1|clk[1] ; pll_inst|altpll_component|auto_generated|pll1|clk[1] ; 10516 ; 208 ; 180 ; 0 ; +-----------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------+------------+------------+----------+----------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Recovery Transfers ; +------------------------------------------------------+-----------------------------------------------------------------------------------------------+----------+------------+----------+----------+ ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; +------------------------------------------------------+-----------------------------------------------------------------------------------------------+----------+------------+----------+----------+ ; pll_inst|altpll_component|auto_generated|pll1|clk[1] ; \flash_on:flash_controller_inst|flash1|onchip_flash_0|altera_onchip_flash_block|ufm_block|osc ; 4 ; 0 ; 0 ; 0 ; ; PHI2 ; pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0 ; false path ; 0 ; 0 ; ; pll_inst|altpll_component|auto_generated|pll1|clk[0] ; pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 6120 ; 0 ; 0 ; 0 ; ; pll_inst|altpll_component|auto_generated|pll1|clk[1] ; pll_inst|altpll_component|auto_generated|pll1|clk[1] ; 32 ; 0 ; 0 ; 0 ; +------------------------------------------------------+-----------------------------------------------------------------------------------------------+----------+------------+----------+----------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Removal Transfers ; +------------------------------------------------------+-----------------------------------------------------------------------------------------------+----------+------------+----------+----------+ ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; +------------------------------------------------------+-----------------------------------------------------------------------------------------------+----------+------------+----------+----------+ ; pll_inst|altpll_component|auto_generated|pll1|clk[1] ; \flash_on:flash_controller_inst|flash1|onchip_flash_0|altera_onchip_flash_block|ufm_block|osc ; 4 ; 0 ; 0 ; 0 ; ; PHI2 ; pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0 ; false path ; 0 ; 0 ; ; pll_inst|altpll_component|auto_generated|pll1|clk[0] ; pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 6120 ; 0 ; 0 ; 0 ; ; pll_inst|altpll_component|auto_generated|pll1|clk[1] ; pll_inst|altpll_component|auto_generated|pll1|clk[1] ; 32 ; 0 ; 0 ; 0 ; +------------------------------------------------------+-----------------------------------------------------------------------------------------------+----------+------------+----------+----------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. --------------- ; Report TCCS ; --------------- No dedicated SERDES Transmitter circuitry present in device or used in design --------------- ; Report RSKM ; --------------- No non-DPA dedicated SERDES Receiver circuitry present in device or used in design +------------------------------------------------+ ; Unconstrained Paths Summary ; +---------------------------------+-------+------+ ; Property ; Setup ; Hold ; +---------------------------------+-------+------+ ; Illegal Clocks ; 0 ; 0 ; ; Unconstrained Clocks ; 1 ; 1 ; ; Unconstrained Input Ports ; 22 ; 22 ; ; Unconstrained Input Port Paths ; 4934 ; 4934 ; ; Unconstrained Output Ports ; 15 ; 15 ; ; Unconstrained Output Port Paths ; 31 ; 31 ; +---------------------------------+-------+------+ +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Clock Status Summary ; +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------+-----------+---------------+ ; Target ; Clock ; Type ; Status ; +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------+-----------+---------------+ ; CLK_SLOW ; CLK_SLOW ; Base ; Constrained ; ; PHI2 ; PHI2 ; Base ; Constrained ; ; \flash_on:flash_controller_inst|flash1|onchip_flash_0|altera_onchip_flash_block|ufm_block|osc ; \flash_on:flash_controller_inst|flash1|onchip_flash_0|altera_onchip_flash_block|ufm_block|osc ; Base ; Constrained ; ; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|flash_se_neg_reg ; ; Base ; Unconstrained ; ; oscillator|int_osc_0|oscillator_dut|clkout ; int_osc_clk ; Base ; Constrained ; ; pll_inst|altpll_component|auto_generated|pll1|clk[0] ; pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Generated ; Constrained ; ; pll_inst|altpll_component|auto_generated|pll1|clk[1] ; pll_inst|altpll_component|auto_generated|pll1|clk[1] ; Generated ; Constrained ; +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------+-----------+---------------+ +-----------------------------------------------------------------------------------------------------+ ; Unconstrained Input Ports ; +--------------+--------------------------------------------------------------------------------------+ ; Input Port ; Comment ; +--------------+--------------------------------------------------------------------------------------+ ; A[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; A[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; A[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; A[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; A[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; CS_N ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; D[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; D[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; D[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; D[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; D[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; D[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; D[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; D[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; EXT[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; EXT[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; EXT[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; POTX_P ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; POTY_P ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; RST_N ; Partially constrained ; ; VDDREDUCED_P ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; W_N ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +--------------+--------------------------------------------------------------------------------------+ +-----------------------------------------------------------------------------------------------------+ ; Unconstrained Output Ports ; +-------------+---------------------------------------------------------------------------------------+ ; Output Port ; Comment ; +-------------+---------------------------------------------------------------------------------------+ ; AUDIO_INT ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; AUDIO_LEFT ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; AUDIO_RIGHT ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; CLK_OUT ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; D[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; D[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; D[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; D[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; D[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; D[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; D[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; D[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; EXT[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; POTX_RESET ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; POTY_RESET ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +-------------+---------------------------------------------------------------------------------------+ +-----------------------------------------------------------------------------------------------------+ ; Unconstrained Input Ports ; +--------------+--------------------------------------------------------------------------------------+ ; Input Port ; Comment ; +--------------+--------------------------------------------------------------------------------------+ ; A[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; A[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; A[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; A[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; A[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; CS_N ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; D[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; D[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; D[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; D[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; D[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; D[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; D[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; D[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; EXT[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; EXT[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; EXT[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; POTX_P ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; POTY_P ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; RST_N ; Partially constrained ; ; VDDREDUCED_P ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; W_N ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +--------------+--------------------------------------------------------------------------------------+ +-----------------------------------------------------------------------------------------------------+ ; Unconstrained Output Ports ; +-------------+---------------------------------------------------------------------------------------+ ; Output Port ; Comment ; +-------------+---------------------------------------------------------------------------------------+ ; AUDIO_INT ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; AUDIO_LEFT ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; AUDIO_RIGHT ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; CLK_OUT ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; D[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; D[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; D[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; D[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; D[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; D[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; D[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; D[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; EXT[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; POTX_RESET ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; POTY_RESET ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +-------------+---------------------------------------------------------------------------------------+ +--------------------------+ ; Timing Analyzer Messages ; +--------------------------+ Info: ******************************************************************* Info: Running Quartus Prime Timing Analyzer Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition Info: Processing started: Sun Jun 7 10:19:02 2026 Info: Command: quartus_sta sidmax -c sidmax Info: qsta_default_script.tcl version: #1 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (20030): Parallel compilation is enabled and will use 16 of the 24 processors detected Info (21077): Low junction temperature is 0 degrees C Info (21077): High junction temperature is 85 degrees C Info (332164): Evaluating HDL-embedded SDC commands Info (332165): Entity altera_std_synchronizer Info (332166): set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}] Info (332104): Reading SDC File: 'sidmax.sdc' Info (332110): Deriving PLL clocks Info (332110): create_clock -period 181.818 -name {\flash_on:flash_controller_inst|flash1|onchip_flash_0|altera_onchip_flash_block|ufm_block|osc} {\flash_on:flash_controller_inst|flash1|onchip_flash_0|altera_onchip_flash_block|ufm_block|osc} Info (332110): create_generated_clock -source {pll_inst|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 3 -multiply_by 2 -duty_cycle 50.00 -name {pll_inst|altpll_component|auto_generated|pll1|clk[0]} {pll_inst|altpll_component|auto_generated|pll1|clk[0]} Info (332110): create_generated_clock -source {pll_inst|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 3 -multiply_by 4 -duty_cycle 50.00 -name {pll_inst|altpll_component|auto_generated|pll1|clk[1]} {pll_inst|altpll_component|auto_generated|pll1|clk[1]} Info (332151): Clock uncertainty is not calculated until you update the timing netlist. Warning (332174): Ignored filter at sidmax.sdc(7): pll_inst|altpll_component|auto_generated|pll1|clk[2] could not be matched with a clock File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sidmax.sdc Line: 7 Warning (332054): Assignment set_clock_groups is accepted but has some problems at sidmax.sdc(7): Argument -group with value pll_inst|altpll_component|auto_generated|pll1|clk[2] could not match any element of the following types: ( clk ) File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sidmax.sdc Line: 7 Info (332050): set_clock_groups -asynchronous \ -group { PHI2 } \ -group { CLK_SLOW } \ -group { \ pll_inst|altpll_component|auto_generated|pll1|clk[0] \ pll_inst|altpll_component|auto_generated|pll1|clk[1] \ } \ -group { pll_inst|altpll_component|auto_generated|pll1|clk[2] } File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_v1_M08_131M08SF_full/sidmax.sdc Line: 7 Info (332104): Reading SDC File: 'int_osc/synthesis/submodules/altera_int_osc.sdc' Info (332104): Reading SDC File: 'flash/synthesis/submodules/altera_onchip_flash.sdc' Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON Info: Analyzing Slow 1200mV 85C Model Info: Can't run Report Timing Closure Recommendations. The current device family is not supported. Critical Warning (332148): Timing requirements not met Info (332146): Worst-case setup slack is -1.576 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): -1.576 -5.489 pll_inst|altpll_component|auto_generated|pll1|clk[1] Info (332119): -0.034 -0.116 pll_inst|altpll_component|auto_generated|pll1|clk[0] Info (332146): Worst-case hold slack is 0.341 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.341 0.000 pll_inst|altpll_component|auto_generated|pll1|clk[0] Info (332119): 0.361 0.000 pll_inst|altpll_component|auto_generated|pll1|clk[1] Info (332146): Worst-case recovery slack is 5.674 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 5.674 0.000 pll_inst|altpll_component|auto_generated|pll1|clk[0] Info (332119): 6.116 0.000 pll_inst|altpll_component|auto_generated|pll1|clk[1] Info (332146): Worst-case removal slack is 1.471 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 1.471 0.000 pll_inst|altpll_component|auto_generated|pll1|clk[1] Info (332119): 3.125 0.000 pll_inst|altpll_component|auto_generated|pll1|clk[0] Info (332146): Worst-case minimum pulse width slack is 1.991 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 1.991 0.000 pll_inst|altpll_component|auto_generated|pll1|clk[1] Info (332119): 5.617 0.000 CLK_SLOW Info (332119): 8.122 0.000 pll_inst|altpll_component|auto_generated|pll1|clk[0] Info (332119): 90.686 0.000 \flash_on:flash_controller_inst|flash1|onchip_flash_0|altera_onchip_flash_block|ufm_block|osc Info (332119): 499.745 0.000 PHI2 Info (332114): Report Metastability: Found 264 synchronizer chains. Info (332114): Worst-Case MTBF of Design is 3.17e+05 years or 9.98e+12 seconds. Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. Info (332114): Number of Synchronizer Chains Found: 264 Info (332114): Shortest Synchronizer Chain: 2 Registers Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.992 Info (332114): Worst Case Available Settling Time: 7.936 ns Info (332114): Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. Info (332114): - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 1.5 Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 3.7 Info: Analyzing Slow 1200mV 0C Model Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. Critical Warning (332148): Timing requirements not met Info (332146): Worst-case setup slack is -1.163 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): -1.163 -2.570 pll_inst|altpll_component|auto_generated|pll1|clk[1] Info (332119): 0.245 0.000 pll_inst|altpll_component|auto_generated|pll1|clk[0] Info (332146): Worst-case hold slack is 0.304 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.304 0.000 pll_inst|altpll_component|auto_generated|pll1|clk[0] Info (332119): 0.324 0.000 pll_inst|altpll_component|auto_generated|pll1|clk[1] Info (332146): Worst-case recovery slack is 6.139 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 6.139 0.000 pll_inst|altpll_component|auto_generated|pll1|clk[0] Info (332119): 6.250 0.000 pll_inst|altpll_component|auto_generated|pll1|clk[1] Info (332146): Worst-case removal slack is 1.317 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 1.317 0.000 pll_inst|altpll_component|auto_generated|pll1|clk[1] Info (332119): 2.850 0.000 pll_inst|altpll_component|auto_generated|pll1|clk[0] Info (332146): Worst-case minimum pulse width slack is 1.895 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 1.895 0.000 pll_inst|altpll_component|auto_generated|pll1|clk[1] Info (332119): 5.636 0.000 CLK_SLOW Info (332119): 8.124 0.000 pll_inst|altpll_component|auto_generated|pll1|clk[0] Info (332119): 90.672 0.000 \flash_on:flash_controller_inst|flash1|onchip_flash_0|altera_onchip_flash_block|ufm_block|osc Info (332119): 499.727 0.000 PHI2 Info (332114): Report Metastability: Found 264 synchronizer chains. Info (332114): Worst-Case MTBF of Design is 1.31e+06 years or 4.12e+13 seconds. Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. Info (332114): Number of Synchronizer Chains Found: 264 Info (332114): Shortest Synchronizer Chain: 2 Registers Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.992 Info (332114): Worst Case Available Settling Time: 8.192 ns Info (332114): Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. Info (332114): - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 1.5 Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 3.7 Info: Analyzing Fast 1200mV 0C Model Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. Info (332146): Worst-case setup slack is 1.374 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 1.374 0.000 pll_inst|altpll_component|auto_generated|pll1|clk[1] Info (332119): 2.576 0.000 pll_inst|altpll_component|auto_generated|pll1|clk[0] Info (332146): Worst-case hold slack is 0.143 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.143 0.000 pll_inst|altpll_component|auto_generated|pll1|clk[0] Info (332119): 0.151 0.000 pll_inst|altpll_component|auto_generated|pll1|clk[1] Info (332146): Worst-case recovery slack is 7.436 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 7.436 0.000 pll_inst|altpll_component|auto_generated|pll1|clk[1] Info (332119): 12.504 0.000 pll_inst|altpll_component|auto_generated|pll1|clk[0] Info (332146): Worst-case removal slack is 0.624 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.624 0.000 pll_inst|altpll_component|auto_generated|pll1|clk[1] Info (332119): 1.235 0.000 pll_inst|altpll_component|auto_generated|pll1|clk[0] Info (332146): Worst-case minimum pulse width slack is 2.172 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 2.172 0.000 pll_inst|altpll_component|auto_generated|pll1|clk[1] Info (332119): 5.255 0.000 CLK_SLOW Info (332119): 8.302 0.000 pll_inst|altpll_component|auto_generated|pll1|clk[0] Info (332119): 90.684 0.000 \flash_on:flash_controller_inst|flash1|onchip_flash_0|altera_onchip_flash_block|ufm_block|osc Info (332119): 499.229 0.000 PHI2 Info (332114): Report Metastability: Found 264 synchronizer chains. Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. Info (332114): Number of Synchronizer Chains Found: 264 Info (332114): Shortest Synchronizer Chain: 2 Registers Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.992 Info (332114): Worst Case Available Settling Time: 10.721 ns Info (332114): Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. Info (332114): - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 1.5 Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 3.7 Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements Info: Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings Info: Peak virtual memory: 715 megabytes Info: Processing ended: Sun Jun 7 10:19:06 2026 Info: Elapsed time: 00:00:04 Info: Total CPU time (on all processors): 00:00:12