EclaireXL

So I decided to rewrite the address decoding and priority access to fix the timing issues. Currently the 'address decoder' has a load of random stuff in it. Multiple bus masters come in (6502, dma and antic) and it chooses who has priority then maps the data output from back to the internal bus. There is not real bi-directional internal bus, its all constructed via a bunch of multiplexors. Mixed into all this we have the cartridge logic and the turbo freezer. Not to mention waiting for PBI access at original machine speed. Anyway its all pretty complicated and I'm trying to design it then write it this time! I originally spent time on the custom chip logic then wired them together as quickly as possible - in a pretty hacky way.

This is quite a beast to do so it will take a few weeks. I got off to a decent start, then... We've just had the Paléo festival here so not had much time in the last week. Next week though I have two weeks holiday - staying with the inlaws. I won't have the eclaireXL with me but I hope I'll have a day in there to get the decoder written. Its hard to know since we've got quite a lot planned.