Revision 120
Added by markw about 11 years ago
| pll.cmp | ||
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(
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inclk0 : IN STD_LOGIC := '0';
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c0 : OUT STD_LOGIC ;
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c1 : OUT STD_LOGIC ;
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c2 : OUT STD_LOGIC ;
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locked : OUT STD_LOGIC
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);
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end component;
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Added SDRAM. Worked!!