Revision 120
Added by markw about 11 years ago
pll.vhd | ||
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(
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inclk0 : IN STD_LOGIC := '0';
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c0 : OUT STD_LOGIC ;
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c1 : OUT STD_LOGIC ;
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c2 : OUT STD_LOGIC ;
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locked : OUT STD_LOGIC
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);
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END pll;
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... | ... | |
SIGNAL sub_wire1 : STD_LOGIC ;
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SIGNAL sub_wire2 : STD_LOGIC ;
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SIGNAL sub_wire3 : STD_LOGIC ;
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SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0);
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SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0);
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SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0);
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SIGNAL sub_wire4 : STD_LOGIC ;
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SIGNAL sub_wire5 : STD_LOGIC ;
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SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0);
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SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0);
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SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0);
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... | ... | |
clk0_duty_cycle : NATURAL;
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clk0_multiply_by : NATURAL;
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clk0_phase_shift : STRING;
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clk1_divide_by : NATURAL;
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clk1_duty_cycle : NATURAL;
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clk1_multiply_by : NATURAL;
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clk1_phase_shift : STRING;
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clk2_divide_by : NATURAL;
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clk2_duty_cycle : NATURAL;
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clk2_multiply_by : NATURAL;
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clk2_phase_shift : STRING;
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compensate_clock : STRING;
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inclk0_input_frequency : NATURAL;
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intended_device_family : STRING;
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... | ... | |
END COMPONENT;
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BEGIN
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sub_wire5_bv(0 DOWNTO 0) <= "0";
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sub_wire5 <= To_stdlogicvector(sub_wire5_bv);
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sub_wire1 <= sub_wire0(0);
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c0 <= sub_wire1;
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sub_wire7_bv(0 DOWNTO 0) <= "0";
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sub_wire7 <= To_stdlogicvector(sub_wire7_bv);
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sub_wire4 <= sub_wire0(2);
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sub_wire3 <= sub_wire0(0);
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sub_wire1 <= sub_wire0(1);
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c1 <= sub_wire1;
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locked <= sub_wire2;
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sub_wire3 <= inclk0;
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sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3;
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c0 <= sub_wire3;
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c2 <= sub_wire4;
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sub_wire5 <= inclk0;
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sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5;
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altpll_component : altpll
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GENERIC MAP (
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bandwidth_type => "AUTO",
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clk0_divide_by => 11,
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clk0_duty_cycle => 50,
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clk0_multiply_by => 78,
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clk0_multiply_by => 156,
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clk0_phase_shift => "0",
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clk1_divide_by => 11,
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clk1_duty_cycle => 50,
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clk1_multiply_by => 78,
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clk1_phase_shift => "0",
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clk2_divide_by => 11,
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clk2_duty_cycle => 50,
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clk2_multiply_by => 156,
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clk2_phase_shift => "4407",
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compensate_clock => "CLK0",
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inclk0_input_frequency => 125000,
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intended_device_family => "Cyclone III",
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... | ... | |
port_scanread => "PORT_UNUSED",
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port_scanwrite => "PORT_UNUSED",
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port_clk0 => "PORT_USED",
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port_clk1 => "PORT_UNUSED",
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port_clk2 => "PORT_UNUSED",
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port_clk1 => "PORT_USED",
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port_clk2 => "PORT_USED",
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port_clk3 => "PORT_UNUSED",
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port_clk4 => "PORT_UNUSED",
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port_clk5 => "PORT_UNUSED",
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... | ... | |
width_clock => 5
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)
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PORT MAP (
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inclk => sub_wire4,
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inclk => sub_wire6,
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clk => sub_wire0,
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locked => sub_wire2
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);
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... | ... | |
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
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-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
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-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "11"
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-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "11"
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-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "11"
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-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
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-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "56.727272"
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-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
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-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
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-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "113.454544"
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-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "56.727272"
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-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "113.454544"
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-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
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-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
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-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
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... | ... | |
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
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-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
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-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
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-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
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-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
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-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
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-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
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-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "78"
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-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
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-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
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-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "156"
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-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "78"
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-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "156"
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-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
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-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "56.75000000"
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-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
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-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000"
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-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
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-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
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-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
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-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
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-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
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-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
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-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
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-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
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-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
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-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
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-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "180.00000000"
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-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
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-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
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-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
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-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
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-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
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-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
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-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
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... | ... | |
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
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-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
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-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
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-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
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-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
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-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
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-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
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-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
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-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
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-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
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-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
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-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
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-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
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-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
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-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
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-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
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-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
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-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
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-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "11"
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-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
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-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "78"
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-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "156"
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-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
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-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "11"
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-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
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-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "78"
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-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
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-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "11"
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-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
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-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "156"
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-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "4407"
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-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
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-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "125000"
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-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
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... | ... | |
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
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-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
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-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
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-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
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-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
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-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
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-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
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-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
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-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
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-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
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... | ... | |
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
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-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
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-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
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-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
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-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
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-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
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-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
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-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
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-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
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-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
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-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
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-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
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-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
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-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
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Added SDRAM. Worked!!