Revision 126
Added by markw about 11 years ago
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-- Multi purpose FPGA expansion for the Commodore 64 computer
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--
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-- -----------------------------------------------------------------------
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-- Copyright 2005-2010 by Peter Wendrich (pwsoft@syntiac.com)
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-- Copyright 2005-2012 by Peter Wendrich (pwsoft@syntiac.com)
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-- http://www.syntiac.com/chameleon.html
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-- -----------------------------------------------------------------------
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--
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| ... | ... | |
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--constant phaseShift : integer := 5; -- Number of cycles that FPGA runs ahead of measured phi.
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constant phaseShift : integer := 8; -- Number of cycles that FPGA runs ahead of measured phi.
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constant guardBits : integer := 4; -- Extra bits to reduce rounding errors in calculations
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signal phiReg1 : std_logic;
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signal phiReg2 : std_logic;
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signal phiReg3 : std_logic;
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signal phiSync : boolean;
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signal phi2_n_reg : unsigned(7 downto 0);
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signal phiSync : std_logic := '0';
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signal locCnt : unsigned(7 downto 0) := (others => '0');
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signal fracCnt : unsigned(guardBits-1 downto 0) := (others => '0');
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| ... | ... | |
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signal localPost3 : std_logic := '0';
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signal localPost4 : std_logic := '0';
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begin
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-- Copy of input phi (deglitched)
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phiBuffer <= phiReg3;
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-- Average phi length
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phiLength <= avgLen((7+guardBits) downto guardBits);
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| ... | ... | |
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process(clk) is
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begin
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if rising_edge(clk) then
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phiReg1 <= phiIn;
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phiReg2 <= phiReg1;
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phiReg3 <= phiReg2;
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phiSync <= '0';
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phi2_n_reg <= phi2_n_reg(phi2_n_reg'high-1 downto 0) & phi2_n;
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-- Detect falling edge of phi2 (is rising edge here as phi2_n input is inverted).
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if phi2_n_reg = "00000001" then
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phiSync <= '1';
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end if;
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end if;
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end process;
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phiSync <= (phiReg1 = '0') and (phiReg2 = '0') and (phiReg3 = '1');
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-- Determine cycle length
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process(clk) is
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| ... | ... | |
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-- NTSC mode 1.022727 Mhz
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avgLen <= to_unsigned(1643, 8+guardBits);
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end if;
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if (phiReg1 = '0') and (phiReg2 = '0') and (phiReg3 = '0') then
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if (phi2_n_reg(1) = '1') and (phi2_n_reg(2) = '1') and (phi2_n_reg(3) = '1') then
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docking_station <= '1';
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end if;
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no_clock <= '1';
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end if;
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if phiSync then
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if phiSync = '1' then
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avgDelta <= signed("0" & c64Cnt) - signed("0" & avgLen((7+guardBits) downto guardBits));
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c64Cnt <= (others => '0');
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end if;
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Switched to using Peters chameleon_io module. Great, gives c64 joystick and cdtv support!