Index: firmware_eclairexl/mist/diskio_sectorrequest.c
===================================================================
--- firmware_eclairexl/mist/diskio_sectorrequest.c	(revision 1315)
+++ firmware_eclairexl/mist/diskio_sectorrequest.c	(nonexistent)
@@ -1,202 +0,0 @@
-#include "diskio.h"
-
-#include "regs.h"
-
-#include "printf.h"
-extern int debug_pos;
-
-void mmcReadCached(u32 sector);
-u32 n_actual_mmc_sector;
-unsigned char * mmc_sector_buffer;
-
-void mmcReadCached(u32 sector)
-{
-	//debug("mmcReadCached");
-	//plotnext(toatarichar(' '));
-	//plotnextnumber(sector);
-	//debug("\n");
-	if(sector==n_actual_mmc_sector) return;
-	//debug("mmcReadREAL");
-	//plotnext(toatarichar(' '));
-	//plotnextnumber(sector);
-	//debug("\n");
-
-	//u08 ret,retry;
-	//predtim nez nacte jiny, musi ulozit soucasny
-	// TODO mmcWriteCachedFlush();
-	//az ted nacte novy
-	//retry=0; //zkusi to maximalne 256x
-	/*do
-	{
-		ret = mmcRead(sector);	//vraci 0 kdyz ok
-		retry--;
-	} while (ret && retry);
-	while(ret); //a pokud se vubec nepovedlo, tady zustane zablokovany cely SDrive!
-*/
-
-	//printf("Reading sector:%d", sector);
-	*zpu_out4 = sector|0x04000000;
-	while (!*zpu_in4)
-	{
-		// Wait until ready
-	}
-	*zpu_out4 = 0;
-	//printf(" RD1 ");
-	while (*zpu_in4)
-	{
-		// Wait until ready cleared
-	}
-
-	//printf(" RD2 ");
-
-	n_actual_mmc_sector=sector;
-}
-
-
-/*-----------------------------------------------------------------------*/
-/* Initialize Disk Drive                                                 */
-/*-----------------------------------------------------------------------*/
-
-DSTATUS disk_initialize (void)
-{
-	DSTATUS stat;
-
-	n_actual_mmc_sector = 0xffffffff;
-	//do
-	//{
-	//	mmcInit();
-	//}
-	//while(mmcReset());	//dokud nenulove, tak smycka (return 0 => ok!)
-
-	//set_spi_clock_freq();
-
-	// no longer in ram (yet!), misuse will break us...
-	mmc_sector_buffer = (unsigned char *)0x4000;  // 512 bytes in the middle of memory space!
-
-	stat = RES_OK;
-
-	return stat;
-}
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Read Partial Sector                                                   */
-/*-----------------------------------------------------------------------*/
-
-DRESULT disk_readp (
-	BYTE* dest,			/* Pointer to the destination object */
-	DWORD sector,		/* Sector number (LBA) */
-	WORD sofs,			/* Offset in the sector */
-	WORD count			/* Byte count (bit15:destination) */
-)
-{
-	DRESULT res;
-
-	/*debug("readp:");
-	plotnextnumber(sector);
-	debug(" ");
-	plotnextnumber((int)dest);
-	debug(" ");
-	plotnextnumber(sofs);
-	debug(" ");
-	plotnextnumber(count);
-	debug(" ");
-	plotnextnumber(atari_sector_buffer);
-	debug(" ");
-	plotnextnumber(mmc_sector_buffer);
-	debug("\n");
-	*/
-	// Put your code here
-	mmcReadCached(sector);
-	for(;count>0;++sofs,--count)
-	{
-		unsigned char x = mmc_sector_buffer[sofs];
-		//printf("char:%02x loc:%d", x,sofs);
-		*dest++ = x;
-	}
-
-	res = RES_OK;
-
-	return res;
-}
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Write Partial Sector                                                  */
-/*-----------------------------------------------------------------------*/
-
-DRESULT disk_writep (const BYTE* buff, DWORD sofs, DWORD count)
-{
-	DRESULT res;
-
-	int i=sofs;
-	int end=sofs+count;
-	int pos = 0;
-
-/*	debug_pos = 0;
-	printf("WP:%x %d %d"),buff,sofs,count;
-	debug_pos = -1;*/
-
-	for (;i!=end;++i,++pos)
-	{
-                unsigned char temp = buff[pos];
-
-                unsigned int volatile* addr = (unsigned int volatile *)&mmc_sector_buffer[i&~3];
-                unsigned int prev = *(unsigned int volatile*)addr;
-                ((char unsigned *)&prev)[i&3] = temp;
-                *addr = prev;
-		
-		//mmc_sector_buffer[i] = buff[pos];
-		//printf("char:%c loc:%d,", buff[pos],i);
-	}
-
-/*	debug_pos = 40;
-	printf("WP DONE:%x %d %d"),buff,sofs,count;
-	debug_pos = -1;*/
-
-	res = RES_OK;
-
-	return res;
-}
-
-void disk_writeflush()
-{
-/*	// Finalize write process
-	int retry=16; //zkusi to maximalne 16x
-	int ret;
-	//printf(":WSECT:%d",n_actual_mmc_sector);
-	do
-	{
-		ret = mmcWrite(n_actual_mmc_sector); //vraci 0 kdyz ok
-		retry--;
-	} while (ret && retry);
-	//printf(":WD:");
-*/
-
-	/*debug_pos = 0;
-	printf("WF");
-	debug_pos = -1;*/
-
-	//printf(" WTF:%d:%x ", n_actual_mmc_sector, ((unsigned int *)mmc_sector_buffer)[0]);
-
-	*zpu_out4 = n_actual_mmc_sector|0x08000000;
-	while (!*zpu_in4)
-	{
-		// Wait until ready
-	}
-	*zpu_out4 = 0;
-	//printf(" PT1 ");
-	while (*zpu_in4)
-	{
-		// Wait until ready cleared
-	}
-
-	//printf(" PT2 ");
-
-	/*debug_pos = 40;
-	printf("DONE");
-	debug_pos = -1;*/
-}
-
Index: firmware_eclairexl/Makefile
===================================================================
--- firmware_eclairexl/Makefile	(revision 1315)
+++ firmware_eclairexl/Makefile	(revision 1316)
@@ -123,7 +123,7 @@
 MCCTV_5200_OBJ = $(patsubst %.c,$(MCCTV_5200_BUILD_DIR)/%.o,$(MCCTV_5200_SRC))
 
 MIST_PRJ = MIST
-MIST_SRC = $(COMMON_SRC) $(SDCARD_SRC) $(A800_SRC) mist/dirs.c sdram_common/rom_location.c sdfakeflash/sdflash.c mcc/spibase.c
+MIST_SRC = fileutils.c uart/uart.c hexdump.c common/utils.c printf/printf.c a800/freeze.c atari_drive_emulator.c atx.c atx_eclaire.c libgcc_divmod.c mist/dirs.c mist/mainmenu.c mist/file.c sdram_common/rom_location.c
 MIST_OBJ = $(patsubst %.c,$(MIST_BUILD_DIR)/%.o,$(MIST_SRC))
 
 MIST_5200_PRJ = MIST_5200
@@ -323,7 +323,7 @@
 
 $(MIST_BUILD_DIR)/%.o: %.c Makefile
 	mkdir -p `dirname $@`
-	$(CC) -I$(MIST_DIR) $(CFLAGS) -DNO_VID2I2C -DMAX_VIDEO_MODE=3 -DMIST_VIDEO_MODE -o $@ -c $<
+	$(CC) -I$(MIST_DIR) $(CFLAGS) -DNO_FLASH -DNO_VID2I2C -DMAX_VIDEO_MODE=3 -DMIST -o $@ -c $<
 
 $(MIST_5200_BUILD_DIR)/%.o: %.c Makefile
 	mkdir -p `dirname $@`
Index: firmware_eclairexl/main.h
===================================================================
--- firmware_eclairexl/main.h	(revision 1315)
+++ firmware_eclairexl/main.h	(revision 1316)
@@ -94,7 +94,9 @@
 // reserve 2 bits for extending cart_select
 BIT_REG(,0x01,25,freezer_enable,zpu_out1)
 BIT_REG(,0x03,26,key_type,zpu_out1) // ansi,iso,custom1,custom2
+#ifndef MIST
 BIT_REG(,0x07,28,turbo_drive,zpu_out1) 
+#endif
 BIT_REG(,0x01,31,turbo_6502_vblank_only,zpu_out1) 
 
 BIT_REG(,0x07,0,video,zpu_out6) // 4 bits,3 used... what to do...
@@ -121,6 +123,20 @@
 BIT_REG_RO(,0x1,18,sd_detect,zpu_in1) // sd_detect
 BIT_REG_RO(,0x1,19,sd_writeprotect,zpu_in1) // sd_writeprotect
 
+//MiST file IO
+#ifdef MIST
+BIT_REG_RO(,0x07,26,turbo_drive,zpu_in1)
+BIT_REG_RO(,0x1,29,sd_ack,zpu_in1)
+BIT_REG_RO(,0x3,30,sd_mounted,zpu_in1)
+
+BIT_REG(,0x3,30,sd_read,zpu_out3)
+BIT_REG(,0x3,28,sd_write,zpu_out3)
+BIT_REG(,0x1,18,sd_secbuf_rd,zpu_out3)
+BIT_REG(,0x1,17,sd_secbuf_we,zpu_out3)
+BIT_REG(,0x1ff,8,sd_secbuf_addr,zpu_out3)
+BIT_REG(,0xff,0,sd_secbuf_d,zpu_out3)
+#endif
+
 #define VIDEO_RGB 0
 #define VIDEO_SCANDOUBLE 1
 #define VIDEO_SVIDEO 2
@@ -323,7 +339,9 @@
 	set_cart_select(0);
 	set_freezer_enable(0);
 	set_key_type(0);
+#ifndef MIST
 	set_turbo_drive(0);
+#endif
 	set_atari800mode(0);
 
 	*atari_colbk = 0xc8;
@@ -432,7 +450,6 @@
 
 char const * get_video_mode(int video_mode)
 {
-#ifndef MIST_VIDEO_MODE
 	static char const * videotxt[] = 
 	{
 		"RGB",
@@ -443,18 +460,6 @@
 		"VGA",
 		"COMPOSITE"
 	};
-#else
-	static char const * videotxt[] = 
-	{
-		"RGB",
-		"SCANDOUBLE",
-		"YPBPR 240",
-		"YPBPR 480",
-		"",
-		"",
-		""
-	};
-#endif
 	return videotxt[video_mode];
 }
 
Index: firmware_eclairexl/mist/file.c
===================================================================
--- firmware_eclairexl/mist/file.c	(nonexistent)
+++ firmware_eclairexl/mist/file.c	(revision 1316)
@@ -0,0 +1,188 @@
+#include "integer.h"
+#include "regs.h"
+#include "file.h"
+#include "simplefile.h"
+
+/* these constants are just to satisfy menu.h */
+char const * fil_type_rom;
+char const * fil_type_bin;
+char const * fil_type_car;
+char const * fil_type_mem;
+char const * fil_type_rpd;
+
+
+int file_struct_size()
+{
+	return sizeof(struct SimpleFile);
+}
+
+void file_init(struct SimpleFile * file)
+{
+	file->num = 0;
+	file->size = 0;
+	file->type = 0;
+	file->is_readonly = 1;
+	file->offset = -1;
+}
+
+char *fname = "";
+char const * file_name(struct SimpleFile * file)
+{
+	return fname;
+}
+
+enum SimpleFileStatus file_open_name_in_dir(struct SimpleDirEntry * entry, char const * filename, struct SimpleFile * file)
+{
+	return SimpleFile_FAIL;
+}
+
+enum SimpleFileStatus file_open_name(char const * path, struct SimpleFile * file)
+{
+	return SimpleFile_FAIL;
+}
+
+enum SimpleFileStatus dir_init(void * mem, int space)
+{
+	return SimpleFile_FAIL;
+}
+
+struct SimpleDirEntry * dir_entries(char const * dirPath)
+{
+	return NULL;
+}
+
+DWORD cur_offset;
+int cur_file;
+BYTE sect_buffer[512];
+
+BYTE cache_read(DWORD offset, int file)
+{
+	if(((offset & ~0x1FF) != (cur_offset & ~0x1FF)) || (cur_file != file))
+	{
+		int i;
+
+		*zpu_out2 = offset >> 9;
+
+		set_sd_read(0);
+		set_sd_read(1 << file);
+		while(!get_sd_ack()) {};
+		set_sd_read(0);
+
+		set_sd_secbuf_rd(1);
+		for(i=0; i<512; i++) {
+			set_sd_secbuf_addr(i);
+			sect_buffer[i] = *zpu_in2;
+		}
+		set_sd_secbuf_rd(0);
+
+		cur_offset = offset;
+		cur_file = file;
+	}
+	return sect_buffer[offset & 0x1FF];
+}
+
+void cache_write(int file)
+{
+	int i;
+
+	*zpu_out2 = cur_offset >> 9;
+
+	set_sd_secbuf_we(1);
+	for(i=0; i<512; i++) {
+		set_sd_secbuf_addr(i);
+		set_sd_secbuf_d(sect_buffer[i]);
+	}
+	set_sd_secbuf_we(0);
+
+	set_sd_write(0);
+	set_sd_write(1 << file);
+	while(!get_sd_ack()) {};
+	set_sd_write(0);
+	while(get_sd_ack()) {};
+}
+
+void file_reset()
+{
+	cur_file = -1;
+	cur_offset = -1;
+}
+
+int file_size(struct SimpleFile * file)
+{
+	return file->size;
+}
+
+int file_readonly(struct SimpleFile * file)
+{
+	return file->is_readonly;
+}
+
+int file_type(struct SimpleFile * file)
+{
+	return file->type;
+}
+
+enum SimpleFileStatus file_read(struct SimpleFile *file, void *buffer, int bytes, int *bytesread)
+{
+	if((file->offset >= 0) && (file->size > file->offset) && (bytes > 0))
+	{
+		if((file->offset + bytes) > file->size) bytes = file->size - file->offset;
+		*bytesread = bytes;
+
+		while(bytes--) *(unsigned char *)buffer++ = cache_read(file->offset++, file->num); 
+		return SimpleFile_OK;
+	}
+
+	*bytesread = 0;
+	return SimpleFile_FAIL;
+}
+
+enum SimpleFileStatus file_seek(struct SimpleFile * file, int offsetFromStart)
+{
+	if((file->size > 0) && (file->size >= offsetFromStart))
+	{
+		file->offset = offsetFromStart;
+		return SimpleFile_OK;
+	}
+	return SimpleFile_FAIL;
+}
+
+enum SimpleFileStatus file_write(struct SimpleFile *file, void *buffer, int bytes, int *byteswritten)
+{
+	if((file->offset >= 0) && (file->size > file->offset) && (bytes > 0))
+	{
+		if((file->offset + bytes) > file->size) bytes = file->size - file->offset;
+		*byteswritten = bytes;
+
+		while(bytes>0)
+		{
+			cache_read(file->offset, file->num);
+			do
+			{
+				sect_buffer[file->offset & 0x1FF] = *(unsigned char*) buffer;
+				bytes--;
+				file->offset++;
+				buffer++;
+			}
+			while((file->offset & 0x1FF) && (bytes>0));
+			cache_write(file->num);
+		}
+		return SimpleFile_OK;
+	}
+	
+	return SimpleFile_FAIL;
+}
+
+enum SimpleFileStatus file_write_flush()
+{
+	return SimpleFile_FAIL;
+}
+
+int file_mount(struct SimpleFile * file, unsigned char num, int size)
+{
+	file->num = num;
+	file->offset = -1;
+	file->size = size;
+	file->is_readonly = 0;
+	file_reset();
+}
Index: firmware_eclairexl/mist/file.h
===================================================================
--- firmware_eclairexl/mist/file.h	(nonexistent)
+++ firmware_eclairexl/mist/file.h	(revision 1316)
@@ -0,0 +1,13 @@
+#ifndef _FILE_H_
+#define _FILE_H_
+
+struct SimpleFile
+{
+	int num;
+	int offset;
+	int is_readonly;
+	int size;
+	int type;
+};
+
+#endif
\ No newline at end of file
Index: firmware_eclairexl/mist/mainmenu.c
===================================================================
--- firmware_eclairexl/mist/mainmenu.c	(nonexistent)
+++ firmware_eclairexl/mist/mainmenu.c	(revision 1316)
@@ -0,0 +1,274 @@
+#include "main.h" //!!!
+#include "atari_drive_emulator.h"
+#include "log.h"
+#include "utils.h"
+#include "sd_direct/spi.h"
+#include "printf.h"
+#include "menu.h"
+
+unsigned char freezer_rom_present;
+unsigned char sd_present;
+unsigned char sel_profile;
+unsigned char sd_mounted;
+
+void mainmenu()
+{
+	int i;
+	*atari_colbk = 0xb8;
+	*atari_colbk = 0x38;
+	freezer_rom_present = 0;
+
+	sd_mounted = 0;
+	for (i=0; i!=NUM_FILES; ++i)
+	{
+		file_init(files[i]);
+	}
+
+	sel_profile = 1;
+
+	init_drive_emulator();
+	reboot(1);
+	run_drive_emulator();
+}
+#ifdef DEBUG_SUPPORT
+struct EditNumberState
+{
+	unsigned char col;
+	unsigned char mask;
+	unsigned char defaultShift;
+};
+
+struct DebugMenuData
+{
+	struct EditNumberState state[2];
+};
+
+void initDebugMenuData(struct DebugMenuData * menuData2)
+{
+	menuData2->state[0].col = 0;
+	menuData2->state[0].mask = 0x3;
+	menuData2->state[0].defaultShift = 12;
+	menuData2->state[1].col = 0;
+	menuData2->state[1].mask = 0x1;
+	menuData2->state[1].defaultShift = 4;
+}
+
+void menuDisplayEditNumber(unsigned int num, struct EditNumberState * state)
+{
+	int shift = state->defaultShift;
+	int i=0;
+	int adj = debug_adjust;
+
+	printf("0x");
+	while(shift>=0)
+	{
+		int val = num;
+		val = (val>> shift)&0xf;
+		
+		if (state->col == i)
+			debug_adjust = adj^128;
+		else
+			debug_adjust = adj;
+		printf("%1x",val);
+		shift = shift-4;
+		i=i+1;
+	}
+
+	debug_adjust = adj;
+}
+
+void menuPrintDebugAddress(void * menuData, void * itemData)
+{
+	printf("Addr:");
+	struct DebugMenuData * menuData2 = (struct DebugMenuData *)(menuData);
+	menuDisplayEditNumber(get_debug_addr(),&menuData2->state[0]);
+}
+void menuPrintDebugData(void * menuData, void * itemData)
+{
+	printf("Data:");
+	struct DebugMenuData * menuData2 = (struct DebugMenuData *)(menuData);
+	menuDisplayEditNumber(get_debug_data(),&menuData2->state[1]);
+}
+void menuPrintDebugMode(void * menuData, void * itemData)
+{
+	printf("Mode:");
+	if (get_debug_read_mode())
+		printf("Read ");
+	if (get_debug_write_mode())
+		printf("Write ");
+	if (get_debug_data_match())
+		printf("Match ");
+}
+
+bool hexDigitToNumber(unsigned char digit, int *val)
+{
+	if (digit>='0' && digit<='9')
+	{
+		*val = digit-'0';
+		return true;
+	}
+	else if (digit>='A' && digit<='F')
+	{
+		*val = 10 + digit-'A';
+		return true;
+	}
+	return false;
+}
+
+bool menuEditNumber(struct EditNumberState * state, struct joystick_status * joy, unsigned int * data)
+{
+	unsigned int val = 0;
+	unsigned int mask = 0;
+	int i;
+	int shift = state->defaultShift;
+	bool res = false;
+	if (hexDigitToNumber(joy->keyPressed_,&val))
+	{
+		//key pressed, store the number in the current location
+		for (i=0;i!=state->col;++i)
+			shift = shift-4;
+
+		mask = 0xf;
+		val = val<<shift;
+		mask = mask<<shift;
+
+		*data = ((*data)&~mask) | val;
+
+		state->col = state->col+1;
+		res = true;
+	}
+	else if (joy->keyPressed_==-1)
+	{
+		// delete pressed, move back one place
+		state->col = state->col-1;
+	}
+
+	state->col = state->col & state->mask; // sanitize col
+
+	return res;
+}
+
+void menuDebugAddress(void * menuData, struct joystick_status * joy, int j)
+{
+	int i;
+	struct DebugMenuData * menuData2 = (struct DebugMenuData *)(menuData);
+	
+	unsigned int addr = get_debug_addr();
+	if (menuEditNumber(&menuData2->state[j],joy,&addr))
+		set_debug_addr(addr);
+}
+void menuDebugData(void * menuData, struct joystick_status * joy, int j)
+{
+	int i;
+	struct DebugMenuData * menuData2 = (struct DebugMenuData *)(menuData);
+
+	unsigned int data = get_debug_data();
+
+	if (menuEditNumber(&menuData2->state[j],joy,&data))
+		set_debug_data(data);
+}
+void menuDebugHotkeys(void * menuData, unsigned char keyPressed)
+{
+	switch (keyPressed)
+	{
+	case 'R':
+		set_debug_read_mode(!get_debug_read_mode());
+		break;
+	case 'W':
+		set_debug_write_mode(!get_debug_write_mode());
+		break;
+	case 'M':
+		set_debug_data_match(!get_debug_data_match());
+		break;
+	}
+}
+
+int debug_menu()
+{
+	struct MenuEntry entries[] = 
+	{
+		{&menuPrintDebugAddress,0,&menuDebugAddress,MENU_FLAG_KEYPRESS},
+		{&menuPrintDebugData,1,&menuDebugData,MENU_FLAG_KEYPRESS},
+		{&menuPrintDebugMode,0,0,MENU_FLAG_KEYPRESS},
+		{0,0,0,0}, //blank line
+		{0,"Exit",0,MENU_FLAG_EXIT},
+		{0,0,0,MENU_FLAG_FINAL} //blank line
+	};
+
+	struct DebugMenuData menuData;
+	initDebugMenuData(&menuData);
+	return display_menu("Debug",&entries[0], &menuDebugHotkeys, &menuData);
+}
+#endif
+
+void update_keys()
+{
+	#ifdef LINUX_BUILD
+		check_keys();
+	#endif
+	#ifdef USB
+		usb_poll(&usb_porta);
+	#endif
+	#ifdef USB2
+		usb_poll(&usb_portb);
+	#endif
+}
+
+void actions()
+{
+	update_keys();
+	// Check for new mounts
+	unsigned char sd_new_mounted = get_sd_mounted();
+	if ((sd_mounted & 0x01) != (sd_new_mounted & 0x01))
+	{
+		int size = *(int*)zpu_in2;
+		if (size) {
+			file_mount(files[0], 0, size);
+			set_drive_status(0,files[0]);
+		} else {
+			// remove
+			file_init(files[0]);
+			set_drive_status(0, 0);
+		}
+	}
+	if ((sd_mounted & 0x02) != (sd_new_mounted & 0x02))
+	{
+		int size = *(int*)zpu_in2;
+		if (size) {
+			file_mount(files[1], 1, size);
+			set_drive_status(1,files[1]);
+		} else {
+			// remove
+			file_init(files[1]);
+			set_drive_status(1, 0);
+		}
+	}
+	sd_mounted = sd_new_mounted;
+
+	// Hot keys
+	if (get_hotkey_softboot())
+	{
+		reboot(0);
+	}
+	else if (get_hotkey_coldboot())
+	{
+		reboot(1);
+
+		do
+		{
+			update_keys();
+		}
+		while (get_hotkey_coldboot());
+	} else if (get_hotkey_settings())
+		// cold boot with disk unload
+	{
+		set_drive_status(0, 0);
+		set_drive_status(1, 0);
+		reboot(1);
+		do
+		{
+			update_keys();
+		}
+		while (get_hotkey_settings());
+	}
+}
Index: mist/DualPortRAM.vhd
===================================================================
--- mist/DualPortRAM.vhd	(nonexistent)
+++ mist/DualPortRAM.vhd	(revision 1316)
@@ -0,0 +1,63 @@
+-- Generic dual-port RAM implementation -
+-- will hopefully work for both Altera and Xilinx parts
+
+library ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+ENTITY DualPortRAM IS
+	GENERIC
+	(
+		addrbits : integer := 9;
+		databits : integer := 7
+	);
+	PORT
+	(
+		address_a		: IN STD_LOGIC_VECTOR (addrbits-1 downto 0);
+		address_b		: IN STD_LOGIC_VECTOR (addrbits-1 downto 0);
+		clock		: IN STD_LOGIC  := '1';
+		data_a		: IN STD_LOGIC_VECTOR (databits-1 downto 0);
+		data_b		: IN STD_LOGIC_VECTOR (databits-1 downto 0);
+		wren_a		: IN STD_LOGIC  := '0';
+		wren_b		: IN STD_LOGIC  := '0';
+		q_a		: OUT STD_LOGIC_VECTOR (databits-1 downto 0);
+		q_b		: OUT STD_LOGIC_VECTOR (databits-1 downto 0)
+	);
+END DualPortRAM;
+
+architecture arch of DualPortRAM is
+
+type ram_type is array(natural range ((2**addrbits)-1) downto 0) of std_logic_vector(databits-1 downto 0);
+shared variable ram : ram_type;
+
+begin
+
+-- Port A
+process (clock)
+begin
+	if (clock'event and clock = '1') then
+		if wren_a='1' then
+			ram(to_integer(unsigned(address_a))) := data_a;
+			q_a <= data_a;
+		else
+			q_a <= ram(to_integer(unsigned(address_a)));
+		end if;
+	end if;
+end process;
+
+-- Port B
+process (clock)
+begin
+	if (clock'event and clock = '1') then
+		if wren_b='1' then
+			ram(to_integer(unsigned(address_b))) := data_b;
+			q_b <= data_b;
+		else
+			q_b <= ram(to_integer(unsigned(address_b)));
+		end if;
+	end if;
+end process;
+
+
+end architecture;
Index: mist/atari800core.qsf
===================================================================
--- mist/atari800core.qsf	(revision 1315)
+++ mist/atari800core.qsf	(revision 1316)
@@ -28,7 +28,7 @@
 set_global_assignment -name TOP_LEVEL_ENTITY atari800core_mist
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.2
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:27:29  OCTOBER 30, 2007"
-set_global_assignment -name LAST_QUARTUS_VERSION "12.1 SP1.33"
+set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26"
 set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
 set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
 set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
@@ -124,12 +124,11 @@
 
 set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE BALANCED
 set_global_assignment -name SMART_RECOMPILE ON
-set_global_assignment -name ENABLE_SIGNALTAP ON
-set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
+set_global_assignment -name ENABLE_SIGNALTAP OFF
 set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
 set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
 set_global_assignment -name FMAX_REQUIREMENT "114 MHz"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
 set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
 set_global_assignment -name USE_CONFIGURATION_DEVICE ON
@@ -137,11 +136,10 @@
 set_global_assignment -name TSU_REQUIREMENT "2 ns"
 set_global_assignment -name TCO_REQUIREMENT "2 ns"
 set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
 set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION OFF
 set_global_assignment -name AUTO_RAM_RECOGNITION ON
 set_global_assignment -name AUTO_ROM_RECOGNITION ON
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
 set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
 set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
@@ -154,9 +152,6 @@
 set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA OFF
 
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY out
-set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 4.0
-set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 4.0
-set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY OFF
 
 #set_parameter -name ENABLE_RUNTIME_MOD YES -to "Minimig1:minimig|amiga_boot:BOOTROM1|altsyncram:Ram0_rtl_10"
 #set_parameter -name INSTANCE_NAME mig -to "Minimig1:minimig|amiga_boot:BOOTROM1|altsyncram:Ram0_rtl_10"
@@ -245,80 +240,81 @@
 set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[14]
 set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[15]
 
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[0]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[1]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[2]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[3]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[4]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[5]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[6]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[7]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[8]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[9]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[10]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[11]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[12]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[0]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[1]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[2]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[3]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[4]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[5]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[6]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[7]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[8]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[9]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[10]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[11]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[12]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[13]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[14]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[15]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_BA[0]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_BA[1]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQML
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQMH
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nRAS
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nCAS
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nWE
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nCS
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_CKE
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_CLK
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[0]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[1]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[2]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[3]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[4]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[5]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[6]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[7]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[8]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[9]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[10]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[11]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[12]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[0]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[1]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[2]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[3]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[4]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[5]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[6]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[7]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[8]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[9]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[10]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[11]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[12]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[13]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[14]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[15]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_BA[0]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_BA[1]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQML
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQMH
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_nRAS
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_nCAS
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_nWE
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_nCS
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_CKE
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_CLK
 
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[5]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[4]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[3]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[2]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[1]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[0]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[5]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[4]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[3]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[2]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[1]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[0]
 
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[5]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[4]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[3]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[2]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[1]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[0]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[5]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[4]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[3]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[2]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[1]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[0]
 
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[5]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[4]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[3]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[2]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[1]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[0]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[5]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[4]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[3]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[2]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[1]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[0]
 
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
 
+set_global_assignment -name VHDL_FILE atari800core_mist.vhd
+set_global_assignment -name SDC_FILE atari800core.sdc
+set_global_assignment -name VERILOG_FILE user_io.v
+set_global_assignment -name VERILOG_FILE data_io.v
+set_global_assignment -name VERILOG_FILE osd.v
 set_global_assignment -name QIP_FILE zpu_rom.qip
-set_global_assignment -name SDC_FILE atari800core.sdc
-set_global_assignment -name QIP_FILE mist_sector_buffer.qip
-set_global_assignment -name VHDL_FILE atari800core_mist.vhd
+set_global_assignment -name VHDL_FILE DualPortRAM.vhd
 set_global_assignment -name VHDL_FILE switch_pal_ntsc.vhd
-set_global_assignment -name VERILOG_FILE user_io.v
-set_global_assignment -name VERILOG_FILE sd_card.v
 set_global_assignment -name QIP_FILE pll_pal.qip
 set_global_assignment -name QIP_FILE pll_downstream_pal.qip
 set_global_assignment -name QIP_FILE video_pll_reconfig.qip
-set_global_assignment -name QIP_FILE video_pll_reconfig_pal.qip
 set_global_assignment -name QIP_FILE clkctrl.qip
 set_global_assignment -name QIP_FILE pll_reconfig.qip
-
+set_global_assignment -name QIP_FILE pal_rom.qip
+set_global_assignment -name QIP_FILE ntsc_rom.qip
Index: mist/atari800core.sdc
===================================================================
--- mist/atari800core.sdc	(revision 1315)
+++ mist/atari800core.sdc	(revision 1316)
@@ -1,14 +1,124 @@
-create_clock -period 27MHz [get_ports CLOCK_27[0]]
-derive_pll_clocks
-create_generated_clock -name sdclk_pin -source [get_pins {clock|altpll_component|auto_generated|pll1|clk[2]}] [get_ports {SDRAM_CLK}]
-derive_clock_uncertainty
-set_input_delay -clock sdclk_pin -max 6.4 [get_ports SDRAM_DQ*]
-set_input_delay -clock sdclk_pin -min 3.2 [get_ports SDRAM_DQ*]
-set_output_delay -clock sdclk_pin -max 1.5 [get_ports SDRAM_*]
-set_output_delay -clock sdclk_pin -min -0.8 [get_ports SDRAM_*]
-set_multicycle_path -from [get_clocks {sdclk_pin}] -to [get_clocks {clock|altpll_component|auto_generated|pll1|clk[0]}] -setup -end 2
+## Generated SDC file "hello_led.out.sdc"
 
-set sys_clk "clk"
-create_clock -name {clk_27} -period 37.037 -waveform { 0.000 18.500 } [get_ports {CLOCK_27[0]}]
+## Copyright (C) 1991-2011 Altera Corporation
+## Your use of Altera Corporation's design tools, logic functions 
+## and other software and tools, and its AMPP partner logic 
+## functions, and any output files from any of the foregoing 
+## (including device programming or simulation files), and any 
+## associated documentation or information are expressly subject 
+## to the terms and conditions of the Altera Program License 
+## Subscription Agreement, Altera MegaCore Function License 
+## Agreement, or other applicable license agreement, including, 
+## without limitation, that your use is for the sole purpose of 
+## programming logic devices manufactured by Altera and sold by 
+## Altera or its authorized distributors.  Please refer to the 
+## applicable agreement for further details.
+
+
+## VENDOR  "Altera"
+## PROGRAM "Quartus II"
+## VERSION "Version 11.1 Build 216 11/23/2011 Service Pack 1 SJ Web Edition"
+
+## DATE    "Fri Jul 06 23:05:47 2012"
+
+##
+## DEVICE  "EP3C25Q240C8"
+##
+
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -name clk_27 -period 37.037 [get_ports {CLOCK_27[0]}]
 create_clock -name {SPI_SCK}  -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
-set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks $sys_clk]
+
+set sdram_clk "pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]"
+set mem_clk   "pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]"
+set sys_clk   "pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]"
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+derive_pll_clocks
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+derive_clock_uncertainty;
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+# SDRAM is clocked from sd1clk_pin, but the SDRAM controller uses memclk
+set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports SDRAM_CLK] -max 6.4 [get_ports SDRAM_DQ[*]]
+set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports SDRAM_CLK] -min 3.2 [get_ports SDRAM_DQ[*]]
+
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports SDRAM_CLK] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
+set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports SDRAM_CLK] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
+
+set_output_delay -clock [get_clocks $sys_clk] -max 0 [get_ports {VGA_*}]
+set_output_delay -clock [get_clocks $sys_clk] -min -5 [get_ports {VGA_*}]
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll_switcher|*}]
+set_clock_groups -asynchronous -group [get_clocks {clk_27}] -group [get_clocks {pll_switcher|*}]
+set_clock_groups -asynchronous -group [get_clocks {reconfig_pll|*}] -group [get_clocks {pll_switcher|*}]
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+set_false_path -to [get_ports {UART_TX}]
+set_false_path -to [get_ports {AUDIO_L}]
+set_false_path -to [get_ports {AUDIO_R}]
+set_false_path -to [get_ports {LED}]
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+set_multicycle_path -to {VGA_*[*]} -setup 2
+set_multicycle_path -to {VGA_*[*]} -hold 1
+
+set_multicycle_path -from [get_clocks $sdram_clk] -to [get_clocks $mem_clk] -setup 2
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
Index: mist/atari800core_mist.vhd
===================================================================
--- mist/atari800core_mist.vhd	(revision 1315)
+++ mist/atari800core_mist.vhd	(revision 1316)
@@ -64,6 +64,26 @@
 );
 end component;
 
+component osd
+generic ( OSD_COLOR : integer := 1 );  -- blue
+port (
+	clk_sys     : in std_logic;
+	R_in        : in std_logic_vector(5 downto 0);
+	G_in        : in std_logic_vector(5 downto 0);
+	B_in        : in std_logic_vector(5 downto 0);
+	HSync       : in std_logic;
+	VSync       : in std_logic;
+
+	R_out       : out std_logic_vector(5 downto 0);
+	G_out       : out std_logic_vector(5 downto 0);
+	B_out       : out std_logic_vector(5 downto 0);
+
+	SPI_SCK     : in std_logic;
+	SPI_SS3     : in std_logic;
+	SPI_DI      : in std_logic
+);
+end component osd;
+
 COMPONENT rgb2ypbpr
 PORT (
         red     :        IN std_logic_vector(5 DOWNTO 0);
@@ -76,11 +96,13 @@
 END COMPONENT;
 
 component user_io
-	GENERIC(
-		STRLEN : in integer := 0
-	);
+	GENERIC (
+		STRLEN : integer := 0;
+		PS2DIV : integer := 1500 );
 	PORT(
-		-- conf_str? how to do in vhdl...
+		clk_sys : in std_logic;
+		clk_sd : in std_logic;
+		conf_str : in std_logic_vector(8*STRLEN-1 downto 0);
 
 		-- mist spi to firmware
 		SPI_CLK : in std_logic;
@@ -95,10 +117,14 @@
 		JOYSTICK_ANALOG_1 : out std_logic_vector(15 downto 0);
 		BUTTONS : out std_logic_vector(1 downto 0);
 		SWITCHES : out std_logic_vector(1 downto 0);
-		STATUS : out std_logic_vector(7 downto 0); -- what is this?
+		STATUS : out std_logic_vector(63 downto 0);
 
+		-- video switches
+		scandoubler_disable: out std_logic;
+		ypbpr: out std_logic;
+		no_csync: out std_logic;
+
 		-- ps2
-		PS2_CLK : in std_logic; --12-16khz
 		PS2_KBD_CLK : out std_logic;
 		PS2_KBD_DATA : out std_logic;
 
@@ -108,48 +134,43 @@
 
 		-- connection to sd card emulation
 		sd_lba : in std_logic_vector(31 downto 0);
-		sd_rd : in std_logic;
-		sd_wr : in std_logic;
+		sd_rd : in std_logic_vector(1 downto 0);
+		sd_wr : in std_logic_vector(1 downto 0);
 		sd_ack : out std_logic;
+		sd_ack_conf : out std_logic;
 		sd_conf : in std_logic;
 		sd_sdhc : in std_logic;
 		sd_dout : out std_logic_vector(7 downto 0);
 		sd_dout_strobe : out std_logic;
 		sd_din : in std_logic_vector(7 downto 0);
-		sd_din_strobe : out std_logic
+		sd_din_strobe : out std_logic;
+		sd_buff_addr : out std_logic_vector(8 downto 0);
+		img_size    : out std_logic_vector(31 downto 0);
+		img_mounted : out std_logic_vector(1 downto 0)
 	  );
 	end component;
 
-	component sd_card
-	PORT (
-		-- link to user_io for io controller
-		io_lba : out std_logic_vector(31 downto 0);
-		io_rd : out std_logic;
-		io_wr : out std_logic;
-		io_ack : in std_logic;
-		io_conf : out std_logic;
-		io_sdhc : out std_logic;
-		
-		-- data coming in from io controller
-		io_din : in std_logic_vector(7 downto 0);
-		io_din_strobe : in std_logic;
-		
-		-- data going out to io controller
-		io_dout : out std_logic_vector(7 downto 0);
-		io_dout_strobe : in std_logic;
-		
-		-- configuration input
-		allow_sdhc : in std_logic;
-	
-		sd_cs : in std_logic;
-		sd_sck : in std_logic;
-		sd_sdi : in std_logic;
-		sd_sdo : out std_logic
-	); 
-	end component;
+	component data_io
+	port (
+		clk_sys : in std_logic;
 
+		SPI_SCK : in std_logic;
+		SPI_SS2 : in std_logic;
+		SPI_DI  : in std_logic;
+
+		ioctl_wait     : in std_logic;
+		ioctl_download : out std_logic;
+		ioctl_index    : out std_logic_vector(7 downto 0);
+		ioctl_wr       : out std_logic;
+		ioctl_addr     : out std_logic_vector(24 downto 0);
+		ioctl_dout     : out std_logic_vector(15 downto 0)
+	);
+	end component data_io;
+
+
   signal AUDIO_L_PCM : std_logic_vector(15 downto 0);
   signal AUDIO_R_PCM : std_logic_vector(15 downto 0);
+  signal AUDIO_R_PCM_IN : std_logic_vector(19 downto 0);
 
   signal VGA_VS_RAW : std_logic;
   signal VGA_HS_RAW : std_logic;
@@ -180,6 +201,7 @@
 
   signal mist_buttons : std_logic_vector(1 downto 0);
   signal mist_switches : std_logic_vector(1 downto 0);
+  signal mist_status   : std_logic_vector(63 downto 0);
 
   signal		JOY1 :  STD_LOGIC_VECTOR(5 DOWNTO 0);
   signal		JOY2 :  STD_LOGIC_VECTOR(5 DOWNTO 0);
@@ -213,18 +235,32 @@
 
 	-- dma/virtual drive
 	signal DMA_ADDR_FETCH : std_logic_vector(23 downto 0);
+	signal DMA_ADDR_FETCH_IOCTL : std_logic_vector(23 downto 0);
+	signal DMA_ADDR_FETCH_ZPU : std_logic_vector(23 downto 0);
 	signal DMA_WRITE_DATA : std_logic_vector(31 downto 0);
+	signal DMA_WRITE_DATA_IOCTL : std_logic_vector(31 downto 0);
+	signal DMA_WRITE_DATA_ZPU : std_logic_vector(31 downto 0);
 	signal DMA_FETCH : std_logic;
+	signal DMA_FETCH_ZPU : std_logic;
+	signal DMA_FETCH_IOCTL : std_logic;
 	signal DMA_32BIT_WRITE_ENABLE : std_logic;
+	signal DMA_32BIT_WRITE_ENABLE_ZPU : std_logic;
 	signal DMA_16BIT_WRITE_ENABLE : std_logic;
+	signal DMA_16BIT_WRITE_ENABLE_ZPU : std_logic;
+	signal DMA_16BIT_WRITE_ENABLE_IOCTL : std_logic;
 	signal DMA_8BIT_WRITE_ENABLE : std_logic;
+	signal DMA_8BIT_WRITE_ENABLE_ZPU : std_logic;
 	signal DMA_READ_ENABLE : std_logic;
+	signal DMA_READ_ENABLE_ZPU : std_logic;
 	signal DMA_MEMORY_READY : std_logic;
+	signal DMA_MEMORY_READY_ZPU : std_logic;
 	signal DMA_MEMORY_DATA : std_logic_vector(31 downto 0);
 
 	signal ZPU_ADDR_ROM : std_logic_vector(15 downto 0);
 	signal ZPU_ROM_DATA :  std_logic_vector(31 downto 0);
 
+	signal ZPU_IN1  : std_logic_vector(31 downto 0);
+	signal ZPU_IN2  : std_logic_vector(31 downto 0);
 	signal ZPU_OUT1 : std_logic_vector(31 downto 0);
 	signal ZPU_OUT2 : std_logic_vector(31 downto 0);
 	signal ZPU_OUT3 : std_logic_vector(31 downto 0);
@@ -244,14 +280,17 @@
 	SIGNAL speed_6502 : std_logic_vector(5 downto 0);
 	signal turbo_vblank_only : std_logic;
 	signal emulated_cartridge_select: std_logic_vector(5 downto 0);
+	signal cart_type_byte : std_logic_vector(7 downto 0);
 	signal key_type : std_logic;
 	signal atari800mode : std_logic;
+	signal turbo_drive : std_logic_vector(2 downto 0);
 
 	-- connection to sd card emulation
 	signal sd_lba : std_logic_vector(31 downto 0);
-	signal sd_rd : std_logic;
-	signal sd_wr : std_logic;
+	signal sd_rd : std_logic_vector(1 downto 0);
+	signal sd_wr : std_logic_vector(1 downto 0);
 	signal sd_ack : std_logic;
+	signal sd_ack_conf : std_logic;
 	signal sd_conf : std_logic;
 	signal sd_sdhc : std_logic;
 	signal sd_dout : std_logic_vector(7 downto 0);
@@ -258,14 +297,40 @@
 	signal sd_dout_strobe : std_logic;
 	signal sd_din : std_logic_vector(7 downto 0);
 	signal sd_din_strobe : std_logic;
+	signal sd_buff_addr: std_logic_vector(8 downto 0);
+	signal img_size    : std_logic_vector(31 downto 0);
+	signal img_mounted : std_logic_vector(1 downto 0);
 
+	signal zpu_secbuf_addr : std_logic_vector(8 downto 0);
+	signal zpu_secbuf_d : std_logic_vector(7 downto 0);
+	signal zpu_secbuf_we : std_logic;
+	signal zpu_secbuf_q	: std_logic_vector(7 downto 0);
+
 	signal mist_sd_sdo : std_logic;
 	signal mist_sd_sck : std_logic;
 	signal mist_sd_sdi : std_logic;
 	signal mist_sd_cs : std_logic;
 
+	-- data io
+	signal rom_loaded      : std_logic;
+	type ioctl_t is (
+		IOCTL_IDLE,
+		IOCTL_UNLOAD,
+		IOCTL_WRITE,
+		IOCTL_ACK);
+	signal ioctl_state     : ioctl_t;
+	signal ioctl_download  : std_logic;
+	signal ioctl_download_D: std_logic;
+	signal ioctl_index     : std_logic_vector(7 downto 0);
+	signal ioctl_wr        : std_logic;
+	signal ioctl_addr      : std_logic_vector(24 downto 0);
+	signal ioctl_dout      : std_logic_vector(15 downto 0);
+	signal reset_load      : std_logic;
+	signal cold_reset      : std_logic;
+	signal zpu_cold_reset  : std_logic;
+	signal zpu_unl_reset   : std_logic;
+
 	-- ps2
-	signal SLOW_PS2_CLK : std_logic; -- around 16KHz
 	signal PS2_KEYS : STD_LOGIC_VECTOR(511 downto 0);
 	signal PS2_KEYS_NEXT : STD_LOGIC_VECTOR(511 downto 0);
 
@@ -286,22 +351,67 @@
 	signal pal : std_logic;
 	signal scandouble : std_logic;
 	signal scanlines : std_logic;
-	signal csync : std_logic;
 	signal video_mode : std_logic_vector(2 downto 0);
+	signal scandoubler_disable : std_logic;
 	signal ypbpr : std_logic;
+	signal no_csync : std_logic;
+	signal sd_hs         : std_logic;
+  signal sd_vs         : std_logic;
+  signal sd_red_o      : std_logic_vector(5 downto 0);
+  signal sd_green_o    : std_logic_vector(5 downto 0);
+  signal sd_blue_o     : std_logic_vector(5 downto 0);
+  signal osd_red_o     : std_logic_vector(5 downto 0);
+  signal osd_green_o   : std_logic_vector(5 downto 0);
+  signal osd_blue_o    : std_logic_vector(5 downto 0);  
+  signal vga_y_o       : std_logic_vector(5 downto 0);
+  signal vga_pb_o      : std_logic_vector(5 downto 0);
+  signal vga_pr_o      : std_logic_vector(5 downto 0);
 
 	-- pll reconfig
 	signal CLK_RECONFIG_PLL : std_logic;
 	signal CLK_RECONFIG_PLL_LOCKED : std_logic;
 
-	-- ypbpr
-	signal SCANDOUBLE_B :  STD_LOGIC_VECTOR(5 DOWNTO 0);
-	signal SCANDOUBLE_G :  STD_LOGIC_VECTOR(5 DOWNTO 0);
-	signal SCANDOUBLE_R :  STD_LOGIC_VECTOR(5 DOWNTO 0);
-	signal vga_y_o      : std_logic_vector(5 downto 0);
-	signal vga_pb_o     : std_logic_vector(5 downto 0);
-	signal vga_pr_o     : std_logic_vector(5 downto 0);
+	constant SDRAM_BASE    : unsigned(23 downto 0) := x"800000";
+	constant CARTRIDGE_MEM : unsigned(23 downto 0) := x"D00000";
+	constant SDRAM_ROM_ADDR : unsigned(23 downto 0):= x"F00000";
 
+	constant CONF_STR : string :=
+		"A800XL;;"&
+		"F,ROM,Load ROM;"&
+		"F,ROMCAR,Load Cart;"&
+		"S0,ATRXEX,Load Disk 1;"&
+		"S1,ATRXEX,Load Disk 2;"&
+		"P1,Video;"&
+		"P2,System;"&
+		"P1O5,Video,NTSC,PAL;"&
+		"P1O6,Scanlines,Off,On;"&
+		"P2O8A,CPU Speed,1x,2x,4x,8x,16x;"&
+		"P2OB,Turbo at VBL only,Off,On;"&
+		"P2OC,Machine,XL/XE,400/800;"&
+		"P2ODF,XL/XE Memory,64K,128K,320KB Compy,320KB Rambo,576K Compy,576K Rambo,1088K,4MB;"&
+		"P2OGI,400/800 Memory,8K,16K,32K,48K,52K;"&
+		"P2OJ,Keyboard,ISO,ANSI;"&
+		"P2OKM,Drive speed,Standard,Fast-6,Fast-5,Fast-4,Fast-3,Fast-2,Fast-1,Fast-0;"&
+		"P2ON,Dual Pokey,No,Yes;"&
+		"T1,Reset;"&
+		"T2,Cold reset;"&
+		"T3,Cold reset with unload;";
+
+	-- convert string to std_logic_vector to be given to user_io
+	function to_slv(s: string) return std_logic_vector is
+		constant ss: string(1 to s'length) := s;
+		variable rval: std_logic_vector(1 to 8 * s'length);
+		variable p: integer;
+		variable c: integer;
+	begin
+		for i in ss'range loop
+			p := 8 * i;
+			c := character'pos(ss(i));
+			rval(p - 7 to p) := std_logic_vector(to_unsigned(c,8));
+		end loop;
+		return rval;
+	end function;
+
 BEGIN 
 -- hack for paddles
 	process(clk,RESET_N)
@@ -332,12 +442,19 @@
 -- mist spi io
 	spi_do <= spi_miso_io when CONF_DATA0 ='0' else 'Z';
 
-my_user_io : user_io
+	sd_conf <= '0';
+	sd_sdhc <= '1';
+
+	my_user_io : user_io
+	GENERIC map (STRLEN => CONF_STR'length)
 	PORT map(
-	   SPI_CLK => SPI_SCK,
-	   SPI_SS_IO => CONF_DATA0,
-	   SPI_MISO => SPI_miso_io,
-	   SPI_MOSI => SPI_DI,
+		clk_sys => CLK,
+		clk_sd => CLK,
+		SPI_CLK => SPI_SCK,
+		SPI_SS_IO => CONF_DATA0,
+		SPI_MISO => SPI_miso_io,
+		SPI_MOSI => SPI_DI,
+		conf_str => to_slv(CONF_STR),
 		JOYSTICK_0 => joy2,
 		JOYSTICK_1 => joy1,
 		JOYSTICK_ANALOG_0(15 downto 8) => joy2x,
@@ -346,12 +463,14 @@
 		JOYSTICK_ANALOG_1(7 downto 0) => joy1y,
 		BUTTONS => mist_buttons,
 		SWITCHES => mist_switches,
-		STATUS => open,
+		STATUS => mist_status,
+		scandoubler_disable => scandoubler_disable,
+		ypbpr => ypbpr,
+		no_csync => no_csync,
 
-		PS2_CLK => SLOW_PS2_CLK,
 		PS2_KBD_CLK => ps2_clk,
 		PS2_KBD_DATA => ps2_dat,
-	
+
 		SERIAL_DATA => (others=>'0'),
 		SERIAL_STROBE => '0',
 
@@ -359,39 +478,20 @@
 		sd_rd => sd_rd,
 		sd_wr => sd_wr,
 		sd_ack => sd_ack,
+		sd_ack_conf => sd_ack_conf,
 		sd_conf => sd_conf,
 		sd_sdhc => sd_sdhc,
 		sd_dout => sd_dout,
 		sd_dout_strobe => sd_dout_strobe,
 		sd_din => sd_din,
-		sd_din_strobe => sd_din_strobe
-	  );
+		sd_din_strobe => sd_din_strobe,
+		sd_buff_addr => sd_buff_addr,
+		img_mounted => img_mounted,
+		img_size => img_size
+	);
 
-my_sd_card : sd_card
-	PORT map (
-		io_lba => sd_lba,
-		io_rd => sd_rd,
-		io_wr => sd_wr,
-		io_ack => sd_ack,
-		io_conf => sd_conf,
-		io_sdhc => sd_sdhc,
-		
-		io_din => sd_dout,
-		io_din_strobe => sd_dout_strobe,
-		
-		io_dout => sd_din,
-		io_dout_strobe => sd_din_strobe,
-		
-		allow_sdhc => '1',
-	
-		sd_cs => mist_sd_cs,
-		sd_sck => mist_sd_sck,
-		sd_sdi => mist_sd_sdi,
-		sd_sdo => mist_sd_sdo
-	); 
-	  
--- PS2 to pokey
-keyboard_map1 : entity work.ps2_to_atari800
+	-- PS2 to pokey
+	keyboard_map1 : entity work.ps2_to_atari800
 	PORT MAP
 	( 
 		CLK => clk,
@@ -404,7 +504,7 @@
  		ATARI_KEYBOARD_OUT => atari_keyboard,
 
 		KEY_TYPE => key_type,
-		
+
 		KEYBOARD_SCAN => KEYBOARD_SCAN,
 		KEYBOARD_RESPONSE => KEYBOARD_RESPONSE,
 
@@ -411,67 +511,79 @@
 		CONSOL_START => CONSOL_START_RAW,
 		CONSOL_SELECT => CONSOL_SELECT_RAW,
 		CONSOL_OPTION => CONSOL_OPTION_RAW,
-		
+
 		FKEYS => FKEYS,
 		FREEZER_ACTIVATE => freezer_activate,
-		
+
 		PS2_KEYS_NEXT_OUT => ps2_keys_next,
 		PS2_KEYS => ps2_keys
 	);
 
-CONSOL_START <= CONSOL_START_RAW or (mist_buttons(1) and not(joy1_n(4)));
-joy_still <= joy1_n(3) and joy1_n(2) and joy1_n(1) and joy1_n(0);
-CONSOL_SELECT <= CONSOL_SELECT_RAW or (mist_buttons(1) and joy1_n(4) and not(joy_still));
-CONSOL_OPTION <= CONSOL_OPTION_RAW or (mist_buttons(1) and joy1_n(4) and joy_still);
-	 
-dac_left : hq_dac
-port map
-(
-  reset => not(reset_n),
-  clk => clk,
-  clk_ena => '1',
-  pcm_in => AUDIO_L_PCM&"0000",
-  dac_out => audio_l
-);
+	CONSOL_START <= CONSOL_START_RAW or (mist_buttons(1) and not(joy1_n(4)));
+	joy_still <= joy1_n(3) and joy1_n(2) and joy1_n(1) and joy1_n(0);
+	CONSOL_SELECT <= CONSOL_SELECT_RAW or (mist_buttons(1) and joy1_n(4) and not(joy_still));
+	CONSOL_OPTION <= CONSOL_OPTION_RAW or (mist_buttons(1) and joy1_n(4) and joy_still);
 
-dac_right : hq_dac
-port map
-(
-  reset => not(reset_n),
-  clk => clk,
-  clk_ena => '1',
-  pcm_in => AUDIO_R_PCM&"0000",
-  dac_out => audio_r
-);
+	dac_left : hq_dac
+	port map
+	(
+		reset => not(reset_n),
+		clk => clk,
+		clk_ena => '1',
+		pcm_in => AUDIO_L_PCM&"0000",
+		dac_out => audio_l
+	);
 
-reconfig_pll : entity work.pll_reconfig -- This only exists to generate reset!!
-PORT MAP(inclk0 => CLOCK_27(0),
-		 c0 => CLK_RECONFIG_PLL,
-		 locked => CLK_RECONFIG_PLL_LOCKED);
+	AUDIO_R_PCM_IN <= AUDIO_R_PCM&"0000" when mist_status(23) = '1' else AUDIO_L_PCM&"0000";
+	
+	dac_right : hq_dac
+	port map
+	(
+		reset => not(reset_n),
+		clk => clk,
+		clk_ena => '1',
+		pcm_in => AUDIO_R_PCM_IN,
+		dac_out => audio_r
+	);
+	
+	reconfig_pll : entity work.pll_reconfig -- This only exists to generate reset!!
+	PORT MAP(inclk0 => CLOCK_27(0),
+		c0 => CLK_RECONFIG_PLL,
+		locked => CLK_RECONFIG_PLL_LOCKED);
 
+	process (CLK_RECONFIG_PLL, CLK_RECONFIG_PLL_LOCKED)
+	begin
+		if CLK_RECONFIG_PLL_LOCKED = '0' then
+			rom_loaded <= '0';
+		elsif rising_edge(CLK_RECONFIG_PLL) then
+			if ioctl_download = '1' then -- FIXME: synchronize
+				rom_loaded <= '1';
+			end if;
+		end if;
+	end process;
+
 	pll_switcher : work.switch_pal_ntsc
-	    GENERIC MAP
-	    (
-	        CLOCKS => 4,
+	GENERIC MAP
+	(
+		CLOCKS => 4,
 		SYNC_ON => 1
-	    )
-	    PORT MAP
-	    (
-	        RECONFIG_CLK => CLK_RECONFIG_PLL,
-	        RESET_N => CLK_RECONFIG_PLL_LOCKED,
-	
-	        PAL => PAL,
-	
-	        INPUT_CLK => CLOCK_27(0),
-	        PLL_CLKS(0) => CLK_SDRAM,
-	        PLL_CLKS(1) => CLK,
-	        PLL_CLKS(2) => SDRAM_CLK,
-		PLL_CLKS(3) => SLOW_PS2_CLK,
-	
+	)
+	PORT MAP
+	(
+		RECONFIG_CLK => CLK_RECONFIG_PLL,
+		RESET_N => CLK_RECONFIG_PLL_LOCKED,
+
+		PAL => PAL,
+		SWITCH_ENA => not ioctl_download and rom_loaded,
+		INPUT_CLK => CLOCK_27(0),
+		PLL_CLKS(0) => CLK_SDRAM,
+		PLL_CLKS(1) => CLK,
+		PLL_CLKS(2) => SDRAM_CLK,
+
 		RESET_N_OUT => RESET_N
-	    );
+	);
 
-atarixl_simple_sdram1 : entity work.atari800core_simple_sdram
+	atarixl_simple_sdram1 : entity work.atari800core_simple_sdram
 	GENERIC MAP
 	(
 		cycle_length => 32,
@@ -537,7 +649,7 @@
 		MEMORY_READY_DMA => dma_memory_ready,
 		DMA_MEMORY_DATA => dma_memory_data, 
 
-   		RAM_SELECT => ram_select,
+		RAM_SELECT => ram_select,
 		PAL => PAL,
 		HALT => pause_atari,
 		THROTTLE_COUNT_6502 => speed_6502,
@@ -547,53 +659,201 @@
 		freezer_activate => freezer_activate
 	);
 
-sdram_adaptor : entity work.sdram_statemachine
-GENERIC MAP(ADDRESS_WIDTH => 22,
-			AP_BIT => 10,
-			COLUMN_WIDTH => 8,
-			ROW_WIDTH => 12
-			)
-PORT MAP(CLK_SYSTEM => CLK,
-		 CLK_SDRAM => CLK_SDRAM,
-		 RESET_N =>  RESET_N,
-		 READ_EN => SDRAM_READ_ENABLE,
-		 WRITE_EN => SDRAM_WRITE_ENABLE,
-		 REQUEST => SDRAM_REQUEST,
-		 BYTE_ACCESS => SDRAM_WIDTH_8BIT_ACCESS,
-		 WORD_ACCESS => SDRAM_WIDTH_16BIT_ACCESS,
-		 LONGWORD_ACCESS => SDRAM_WIDTH_32BIT_ACCESS,
-		 REFRESH => SDRAM_REFRESH,
-		 ADDRESS_IN => SDRAM_ADDR,
-		 DATA_IN => SDRAM_DI,
-		 SDRAM_DQ => SDRAM_DQ,
-		 COMPLETE => SDRAM_REQUEST_COMPLETE,
-		 SDRAM_BA0 => SDRAM_BA(0),
-		 SDRAM_BA1 => SDRAM_BA(1),
-		 SDRAM_CKE => SDRAM_CKE,
-		 SDRAM_CS_N => SDRAM_nCS,
-		 SDRAM_RAS_N => SDRAM_nRAS,
-		 SDRAM_CAS_N => SDRAM_nCAS,
-		 SDRAM_WE_N => SDRAM_nWE,
-		 SDRAM_ldqm => SDRAM_DQML,
-		 SDRAM_udqm => SDRAM_DQMH,
-		 DATA_OUT => SDRAM_DO,
-		 SDRAM_ADDR => SDRAM_A(11 downto 0),
-		 reset_client_n => SDRAM_RESET_N
-		 );
+	sdram_adaptor : entity work.sdram_statemachine
+	GENERIC MAP(ADDRESS_WIDTH => 22,
+		AP_BIT => 10,
+		COLUMN_WIDTH => 8,
+		ROW_WIDTH => 12
+	)
+	PORT MAP(CLK_SYSTEM => CLK,
+		CLK_SDRAM => CLK_SDRAM,
+		RESET_N =>  RESET_N,
+		READ_EN => SDRAM_READ_ENABLE,
+		WRITE_EN => SDRAM_WRITE_ENABLE,
+		REQUEST => SDRAM_REQUEST,
+		BYTE_ACCESS => SDRAM_WIDTH_8BIT_ACCESS,
+		WORD_ACCESS => SDRAM_WIDTH_16BIT_ACCESS,
+		LONGWORD_ACCESS => SDRAM_WIDTH_32BIT_ACCESS,
+		REFRESH => SDRAM_REFRESH,
+		ADDRESS_IN => SDRAM_ADDR,
+		DATA_IN => SDRAM_DI,
+		SDRAM_DQ => SDRAM_DQ,
+		COMPLETE => SDRAM_REQUEST_COMPLETE,
+		SDRAM_BA0 => SDRAM_BA(0),
+		SDRAM_BA1 => SDRAM_BA(1),
+		SDRAM_CKE => SDRAM_CKE,
+		SDRAM_CS_N => SDRAM_nCS,
+		SDRAM_RAS_N => SDRAM_nRAS,
+		SDRAM_CAS_N => SDRAM_nCAS,
+		SDRAM_WE_N => SDRAM_nWE,
+		SDRAM_ldqm => SDRAM_DQML,
+		SDRAM_udqm => SDRAM_DQMH,
+		DATA_OUT => SDRAM_DO,
+		SDRAM_ADDR => SDRAM_A(11 downto 0),
+		reset_client_n => SDRAM_RESET_N
+	);
 		 
-SDRAM_A(12) <= '0';
---SDRAM_REFRESH <= '0'; -- TODO
+	SDRAM_A(12) <= '0';
 
--- Until SDRAM enabled... TODO
---SDRAM_nCS <= '1';
---SDRAM_DQ <= (others=>'Z');
+	mist_data_io: data_io
+	port map (
+		clk_sys => CLK,
 
---SDRAM_CKE <= '1';		 
-LED <= zpu_sio_rxd;
+		SPI_SCK => SPI_SCK,
+		SPI_SS2 => SPI_SS2,
+		SPI_DI  => SPI_DI,
 
---VGA_HS <= not(VGA_HS_RAW xor VGA_VS_RAW);
---VGA_VS <= not(VGA_VS_RAW);
+		ioctl_wait     => '0',
+		ioctl_download => ioctl_download,
+		ioctl_index    => ioctl_index,
+		ioctl_wr       => ioctl_wr,
+		ioctl_addr     => ioctl_addr,
+		ioctl_dout     => ioctl_dout
+	);
 
+	dma_read_enable <= '0' when ioctl_state /= IOCTL_IDLE else dma_read_enable_zpu;
+	dma_addr_fetch <= dma_addr_fetch_ioctl when ioctl_state /= IOCTL_IDLE else dma_addr_fetch_zpu;
+	dma_write_data <= dma_write_data_ioctl when ioctl_state /= IOCTL_IDLE else dma_write_data_zpu;
+	dma_fetch <= dma_fetch_ioctl when ioctl_state /= IOCTL_IDLE else dma_fetch_zpu;
+	dma_8bit_write_enable <= '0' when ioctl_state /= IOCTL_IDLE else dma_8bit_write_enable_zpu;
+	dma_16bit_write_enable <= dma_16bit_write_enable_ioctl when ioctl_state /= IOCTL_IDLE else dma_16bit_write_enable_zpu;
+	dma_32bit_write_enable <= '0' when ioctl_state /= IOCTL_IDLE else dma_32bit_write_enable_zpu;
+	dma_memory_ready_zpu <= '0' when ioctl_state /= IOCTL_IDLE else dma_memory_ready;
+
+	emulated_cartridge_select <=
+		     "000001" when cart_type_byte = x"01" -- standard 8k
+		else "100001" when cart_type_byte = x"02" -- standard 16k
+		else "001101" when cart_type_byte = x"08" -- Williams 64k
+		else "001010" when cart_type_byte = x"09" -- Express 64
+		else "001001" when cart_type_byte = x"0a" -- Diamond 64
+		else "001000" when cart_type_byte = x"0b" -- SDX64
+		else "110000" when cart_type_byte = x"0c" -- XEGS 32k
+		else "110001" when cart_type_byte = x"0d" -- XEGS 64k
+		else "110010" when cart_type_byte = x"0e" -- XEGS 128k
+		else "000100" when cart_type_byte = x"0f" -- OSS 16
+		else "001100" when cart_type_byte = x"11" -- ATRAX 128
+		else "001101" when cart_type_byte = x"16" -- Williams 32k (=Williams 64k)
+		else "110011" when cart_type_byte = x"17" -- XEGS 256
+		else "110100" when cart_type_byte = x"18" -- XEGS 512
+		else "110101" when cart_type_byte = x"19" -- XEGS 1024
+		else "101000" when cart_type_byte = x"1a" -- MEGA 16
+		else "101001" when cart_type_byte = x"1b" -- MEGA 32
+		else "101010" when cart_type_byte = x"1c" -- MEGA 64
+		else "101011" when cart_type_byte = x"1d" -- MEGA 128
+		else "101100" when cart_type_byte = x"1e" -- MEGA 256
+		else "101101" when cart_type_byte = x"1f" -- MEGA 512
+		else "101110" when cart_type_byte = x"20" -- MEGA 1024
+		else "111000" when cart_type_byte = x"21" -- SXEGS 32
+		else "111001" when cart_type_byte = x"22" -- SXEGS 64
+		else "111010" when cart_type_byte = x"23" -- SXEGS 128
+		else "111011" when cart_type_byte = x"24" -- SXEGS 256
+		else "111100" when cart_type_byte = x"25" -- SXEGS 512
+		else "111101" when cart_type_byte = x"26" -- SXEGS 1024
+		else "100011" when cart_type_byte = x"28" -- BLIZZARD 16
+		else "000010" when cart_type_byte = x"29" -- ATARIMAX 128
+		else "000011" when cart_type_byte = x"2a" -- ATARIMAX 1024
+		else "100100" when cart_type_byte = x"38" -- SIC 512
+		else "000000";
+
+	process (CLK, RESET_N)
+		variable sdram_a: unsigned(23 downto 0);
+	begin
+		if RESET_N = '0' then
+			ioctl_state <= IOCTL_IDLE;
+			reset_load <= '0';
+		elsif rising_edge(CLK) then
+			ioctl_download_D <= ioctl_download;
+			case ioctl_state is
+
+			when IOCTL_IDLE =>
+				reset_load <= '0';
+				dma_fetch_ioctl <= '0';
+				dma_16bit_write_enable_ioctl <= '0';
+				if cold_reset = '1' then
+					-- reset with unload
+					cart_type_byte <= (others => '0');
+					dma_addr_fetch_ioctl <= std_logic_vector(SDRAM_BASE);
+					ioctl_state <= IOCTL_UNLOAD;
+				elsif ioctl_download_D = '0' and ioctl_download = '1' then
+					-- cart loading starts
+					ioctl_state <= IOCTL_WRITE;
+					cart_type_byte <= (others => '0');
+				end if;
+
+			when IOCTL_UNLOAD =>
+				if dma_fetch_ioctl = '1' then
+					if dma_memory_ready = '1' then
+						dma_fetch_ioctl <= '0';
+						dma_16bit_write_enable_ioctl <= '0';
+						dma_addr_fetch_ioctl <= std_logic_vector(unsigned(dma_addr_fetch_ioctl) + 2);
+					end if;
+				elsif dma_addr_fetch_ioctl = std_logic_vector(SDRAM_BASE + x"10000") then
+					ioctl_state <= IOCTL_IDLE;
+					reset_load <= '1';
+				else
+					dma_fetch_ioctl <= '1';
+					dma_16bit_write_enable_ioctl <= '1';
+					dma_write_data_ioctl <= (others => '0');
+				end if;
+
+			when IOCTL_WRITE =>
+				if ioctl_download = '0' then
+					-- end of download
+					ioctl_state <= IOCTL_IDLE;
+					reset_load <= '1';
+					if ioctl_index = x"02" then
+						-- ROM file type detection from size
+						if    ioctl_addr = '0'&x"002000" then cart_type_byte <= x"01"; -- standard 8k
+						elsif ioctl_addr = '0'&x"004000" then cart_type_byte <= x"02"; -- standard 16k
+						elsif ioctl_addr = '0'&x"008000" then cart_type_byte <= x"0c"; -- Atari XEGS 32k
+						elsif ioctl_addr = '0'&x"010000" then cart_type_byte <= x"0d"; -- Atari XEGS 64k
+						elsif ioctl_addr = '0'&x"020000" then cart_type_byte <= x"0e"; -- Atari XEGS 128k
+						elsif ioctl_addr = '0'&x"100000" then cart_type_byte <= x"2a"; -- Atarimax 1024k
+						end if;
+					end if;
+				elsif ioctl_wr = '1' then
+					-- new word arrived from IO controller
+					if (ioctl_index = x"42" and unsigned(ioctl_addr) = 6) then
+						-- CAR header type field
+						cart_type_byte <= ioctl_dout(15 downto 8);
+					elsif (ioctl_index = x"42" and unsigned(ioctl_addr) < 16) then
+						-- skip CAR header
+						null;
+					else
+						dma_fetch_ioctl <= '1';
+						dma_16bit_write_enable_ioctl <= '1';
+						dma_write_data_ioctl <= ioctl_dout & ioctl_dout;
+						if ioctl_index(7 downto 1) = "0000000" then -- 0 or 1
+							-- BASIC + OS ROM
+							sdram_a := unsigned(ioctl_addr(23 downto 0)) + SDRAM_ROM_ADDR;
+						else
+							sdram_a := unsigned(ioctl_addr(23 downto 0)) + CARTRIDGE_MEM;
+						end if;
+						if ioctl_index = x"42" then
+							sdram_a := sdram_a - 16;
+						end if;
+						dma_addr_fetch_ioctl <= std_logic_vector(sdram_a);
+						ioctl_state <= IOCTL_ACK;
+					end if;
+				end if;
+
+			when IOCTL_ACK =>
+				if dma_memory_ready = '1' then
+					dma_fetch_ioctl <= '0';
+					dma_16bit_write_enable_ioctl <= '0';
+					ioctl_state <= IOCTL_WRITE;
+				end if;
+
+			when others => null;
+
+			end case;
+		end if;
+	end process;
+
+	LED <= zpu_sio_rxd;
+
+	scandouble <= not scandoubler_disable;
+
 	process(clk,RESET_N,SDRAM_RESET_N,reset_atari)
 	begin
 		if ((RESET_N and SDRAM_RESET_N and not(reset_atari))='0') then
@@ -616,7 +876,7 @@
 		RESET_N => RESET_N and SDRAM_RESET_N and not(reset_atari),
 		
 		VGA => scandouble,
-		COMPOSITE_ON_HSYNC => csync or ypbpr,
+		COMPOSITE_ON_HSYNC => '0', -- OSD needs separate sync, handle csync in the final mix
 
 		colour_enable => half_scandouble_enable_reg,
 		doubled_enable => '1',
@@ -630,33 +890,106 @@
 		csync_in => VGA_CS_RAW,
 		
 		-- TO TV...
-		R => SCANDOUBLE_R,
-		G => SCANDOUBLE_G,
-		B => SCANDOUBLE_B,
+		R => sd_red_o,
+		G => sd_green_o,
+		B => sd_blue_o,
 		
-		VSYNC => VGA_VS,
-		HSYNC => VGA_HS
+		VSYNC => sd_vs,
+		HSYNC => sd_hs
 	);
 
-rgb2component: rgb2ypbpr
-port map (
-        red => SCANDOUBLE_R,
-        green => SCANDOUBLE_G,
-        blue => SCANDOUBLE_B,
-        y => vga_y_o,
-        pb => vga_pb_o,
-        pr => vga_pr_o
-);
+	osd_inst: osd
+	port map (
+		clk_sys     => CLK,
+		SPI_SCK     => SPI_SCK,
+		SPI_SS3     => SPI_SS3,
+		SPI_DI      => SPI_DI,
 
-VGA_R <= vga_pr_o when ypbpr='1' else SCANDOUBLE_R;
-VGA_G <= vga_y_o  when ypbpr='1' else SCANDOUBLE_G;
-VGA_B <= vga_pb_o when ypbpr='1' else SCANDOUBLE_B;
+		R_in        => sd_red_o,
+		G_in        => sd_green_o,
+		B_in        => sd_blue_o,
+		HSync       => sd_hs,
+		VSync       => sd_vs,
 
-zpu: entity work.zpucore
+		R_out       => osd_red_o,
+		G_out       => osd_green_o,
+		B_out       => osd_blue_o
+	);
+
+	rgb2ypbpr_inst: rgb2ypbpr
+	port map (
+		red => osd_red_o,
+		green => osd_green_o,
+		blue => osd_blue_o,
+		y => vga_y_o,
+		pb => vga_pb_o,
+		pr => vga_pr_o
+	);
+
+	VGA_R <= vga_pr_o when ypbpr='1' else osd_red_o;
+	VGA_G <= vga_y_o  when ypbpr='1' else osd_green_o;
+	VGA_B <= vga_pb_o when ypbpr='1' else osd_blue_o;
+	-- If 15kHz Video - composite sync to VGA_HS and VGA_VS high for MiST RGB cable
+	VGA_HS <= not (sd_hs xor sd_vs) when (scandoubler_disable='1' and no_csync='0') or ypbpr='1' else sd_hs;
+	VGA_VS <= '1' when (scandoubler_disable='1' and no_csync='0') or ypbpr='1' else sd_vs;
+
+	sector_buffer: entity work.DualPortRAM
+	generic map (
+		addrbits => 9,
+		databits => 8
+	)
+	port map (
+		clock => CLK,
+		-- Port A - IO Controller side
+		address_a => sd_buff_addr,
+		data_a => sd_dout,
+		wren_a => sd_dout_strobe,
+		q_a => sd_din,
+		-- Port B - ZPU side
+		address_b => zpu_secbuf_addr,
+		data_b => zpu_secbuf_d,
+		wren_b => zpu_secbuf_we,
+		q_b => zpu_secbuf_q
+	);
+
+	process (CLK, RESET_N)
+	begin
+		if RESET_N = '0' then
+			zpu_in1(31 downto 29) <= "000";
+			zpu_secbuf_we <= '0';
+		elsif rising_edge(CLK) then
+			sd_lba <= zpu_out2;
+			sd_rd <= zpu_out3(31 downto 30);
+			sd_wr <= zpu_out3(29 downto 28);
+
+			zpu_secbuf_addr <= zpu_out3(16 downto 8);
+			zpu_secbuf_d <= zpu_out3(7 downto 0);
+			zpu_secbuf_we <= zpu_out3(17);
+
+			if img_mounted(0) = '1' then
+				zpu_in2 <= img_size;
+				zpu_in1(30) <= not zpu_in1(30);
+			elsif img_mounted(1) = '1' then
+				zpu_in2 <= img_size;
+				zpu_in1(31) <= not zpu_in1(31);
+			elsif zpu_out3(18) = '1' then
+				zpu_in2 <= X"000000"&zpu_secbuf_q;
+			end if;
+			zpu_in1(29) <= sd_ack;
+
+		end if;
+	end process;
+
+	zpu_in1(28 downto 0) <= 
+			turbo_drive&X"00"&
+			(atari_keyboard(28))&ps2_keys(16#5A#)&ps2_keys(16#174#)&ps2_keys(16#16B#)&ps2_keys(16#172#)&ps2_keys(16#175#)& -- (esc)FLRDU
+				'0'&zpu_unl_reset&zpu_cold_reset&FKEYS(8 downto 0);
+
+	zpu: entity work.zpucore
 	GENERIC MAP
 	(
 		platform => 1,
-		spi_clock_div => 16,	-- 28MHz/2. Max for SD cards is 25MHz...
+		spi_clock_div => 4,	-- 28MHz/2. Max for SD cards is 25MHz...
 		nMHz_clock_div => 27,
 		memory => 8192
 	)
@@ -667,14 +1000,14 @@
 		RESET_N => RESET_N and sdram_reset_n,
 
 		-- dma bus master (with many waitstates...)
-		ZPU_ADDR_FETCH => dma_addr_fetch,
-		ZPU_DATA_OUT => dma_write_data,
-		ZPU_FETCH => dma_fetch,
-		ZPU_32BIT_WRITE_ENABLE => dma_32bit_write_enable,
-		ZPU_16BIT_WRITE_ENABLE => dma_16bit_write_enable,
-		ZPU_8BIT_WRITE_ENABLE => dma_8bit_write_enable,
-		ZPU_READ_ENABLE => dma_read_enable,
-		ZPU_MEMORY_READY => dma_memory_ready,
+		ZPU_ADDR_FETCH => dma_addr_fetch_zpu,
+		ZPU_DATA_OUT => dma_write_data_zpu,
+		ZPU_FETCH => dma_fetch_zpu,
+		ZPU_32BIT_WRITE_ENABLE => dma_32bit_write_enable_zpu,
+		ZPU_16BIT_WRITE_ENABLE => dma_16bit_write_enable_zpu,
+		ZPU_8BIT_WRITE_ENABLE => dma_8bit_write_enable_zpu,
+		ZPU_READ_ENABLE => dma_read_enable_zpu,
+		ZPU_MEMORY_READY => dma_memory_ready_zpu,
 		ZPU_MEMORY_DATA => dma_memory_data, 
 
 		-- rom bus master
@@ -704,11 +1037,13 @@
 
 		-- external control
 		-- switches etc. sector DMA blah blah.
-		ZPU_IN1 => X"000"&
-			"00"&
-			(atari_keyboard(28))&ps2_keys(16#5A#)&ps2_keys(16#174#)&ps2_keys(16#16B#)&ps2_keys(16#172#)&ps2_keys(16#175#)& -- (esc)FLRDU
-				(FKEYS(11) or (mist_buttons(0) and not(joy1_n(4))))&(FKEYS(10) or (mist_buttons(0) and joy1_n(4) and joy_still))&(FKEYS(9) or (mist_buttons(0) and joy1_n(4) and not(joy_still)))&FKEYS(8 downto 0),
-		ZPU_IN2 => X"00000000",
+		ZPU_IN1 => zpu_in1,
+
+--		ZPU_IN1 => X"000"&
+--			"00"&
+--			(atari_keyboard(28))&ps2_keys(16#5A#)&ps2_keys(16#174#)&ps2_keys(16#16B#)&ps2_keys(16#172#)&ps2_keys(16#175#)& -- (esc)FLRDU
+--				(FKEYS(11) or (mist_buttons(0) and not(joy1_n(4))))&(FKEYS(10) or (mist_buttons(0) and joy1_n(4) and joy_still))&(FKEYS(9) or (mist_buttons(0) and joy1_n(4) and not(joy_still)))&FKEYS(8 downto 0),
+		ZPU_IN2 => zpu_in2,
 		ZPU_IN3 => atari_keyboard(31 downto 0),
 		ZPU_IN4 => atari_keyboard(63 downto 32),
 
@@ -720,60 +1055,37 @@
 		ZPU_OUT6 => zpu_out6 --video mode
 	);
 
-	pause_atari <= zpu_out1(0);
-	reset_atari <= zpu_out1(1);
-	speed_6502 <= zpu_out1(7 downto 2);
-	ram_select <= zpu_out1(10 downto 8);
-	atari800mode <= zpu_out1(11);
-	emulated_cartridge_select <= zpu_out1(22 downto 17);
-	freezer_enable <= zpu_out1(25);
-	key_type <= zpu_out1(26);
+	zpu_cold_reset <= mist_status(2) or FKEYS(9);
+	zpu_unl_reset <= mist_status(3) or FKEYS(10);
 
-	turbo_vblank_only <= zpu_out1(31);
+	cold_reset  <= zpu_cold_reset or zpu_unl_reset;
+	reset_atari <= mist_status(1) or mist_buttons(1) or zpu_out1(1) or reset_load;
+	speed_6502 <= "000001" when mist_status(10 downto 8) = "000" else
+	              "000010" when mist_status(10 downto 8) = "001" else
+	              "000100" when mist_status(10 downto 8) = "010" else
+	              "001000" when mist_status(10 downto 8) = "011" else
+	              "010000";
 
-	video_mode <= zpu_out6(2 downto 0);
-	PAL <= zpu_out6(4);
-	scanlines <= zpu_out6(5);
-	csync <= zpu_out6(6);
+	turbo_vblank_only <= mist_status(11);
 
-process(video_mode)
-begin
-	SCANDOUBLE <= '0';
-	YPBPR <= '0';
+	atari800mode <= mist_status(12);
+	ram_select <= mist_status(15 downto 13) when atari800mode = '0' else mist_status(18 downto 16);
+	PAL <= mist_status(5);
+	scanlines <= mist_status(6);
+	key_type <= mist_status(19);
+	turbo_drive <= mist_status(22 downto 20);
 
-	-- original RGB
-	-- scandoubled RGB (works on some vga devices...)
-	-- ypbpr
-	-- scandoubled ypbpr
+	pause_atari <= '1' when zpu_out1(0) = '1' or ioctl_state /= IOCTL_IDLE else '0';
+	freezer_enable <= zpu_out1(25);
 
-	case video_mode is
-		when "000" =>
-		when "001" =>
-			SCANDOUBLE <= '1';
-		when "010" => 
-			YPBPR <= '1';
-		when "011" =>
-			SCANDOUBLE <= '1';
-			YPBPR <= '1';
-		when "100" =>
-			-- not supported
-		when "101" =>
-			-- not supported
-		when "110" => -- composite
-			-- not supported
-
-		when others =>
-	end case;
-end process;
-
 	zpu_rom1: entity work.zpu_rom
 	port map(
 	        clock => clk,
-	        address => zpu_addr_rom(14 downto 2),
+	        address => zpu_addr_rom(13 downto 2),
 	        q => zpu_rom_data
 	);
 
-enable_179_clock_div_zpu_pokey : entity work.enable_divider
+	enable_179_clock_div_zpu_pokey : entity work.enable_divider
 	generic map (COUNT=>32) -- cycle_length
 	port map(clk=>clk,reset_n=>reset_n,enable_in=>'1',enable_out=>zpu_pokey_enable);
 
Index: mist/build.sh
===================================================================
--- mist/build.sh	(revision 1315)
+++ mist/build.sh	(revision 1316)
@@ -40,6 +40,7 @@
 	`cp *.vhdl $dir`;
 	`cp *.vhd $dir`;
 	`cp ntsc.mif  pal.mif $dir`;
+	`cp pal_rom.* ntsc_rom.* $dir`;
 	`cp zpu_rom.* $dir`;
 	`cp atari800core.sdc $dir`;
 	`mkdir $dir/common`;
@@ -50,6 +51,11 @@
 	`cp -r ../common/components/* ./$dir/common/components`;
 	`mv ./$dir/common/components/*cyclone3/* ./$dir/common/components/`;
 	`cp ../common/zpu/* ./$dir/common/zpu`;
+	`rm ./$dir/common/a8core/atari800core_helloworld.vhd`;
+	`rm ./$dir/common/a8core/atari800nx_core_simple_sdram.vhd`;
+	`rm ./$dir/common/a8core/atari800xl.vhd`;
+	`rm ./$dir/common/a8core/internalromram_fast.vhd`;
+	`rm ./$dir/common/a8core/internalromram_simple.vhd`;
 
 	chdir $dir;
 	`../makeqsf ../atari800core.qsf ./common/a8core ./common/components ./common/zpu`;
Index: mist/data_io.v
===================================================================
--- mist/data_io.v	(nonexistent)
+++ mist/data_io.v	(revision 1316)
@@ -0,0 +1,144 @@
+//
+// data_io.v
+//
+// data_io for the MiST board
+// http://code.google.com/p/mist-board/
+//
+// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
+// Copyright (c) 2015-2017 Sorgelig
+// Copyright (c) 2019 György Szombathelyi
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+///////////////////////////////////////////////////////////////////////
+
+module data_io
+(
+	// Global clock. It should be around 100MHz (higher is better).
+	input             clk_sys,
+
+	// Global SPI clock from ARM. 24MHz
+	input             SPI_SCK,
+	input             SPI_SS2,
+	input             SPI_DI,
+
+	// ARM -> FPGA download
+	input             ioctl_wait,
+	output reg        ioctl_download = 0, // signal indicating an active download
+	output reg  [7:0] ioctl_index,        // menu index used to upload the file
+	output reg        ioctl_wr = 0,
+	output reg [24:0] ioctl_addr,
+	output reg [15:0] ioctl_dout
+);
+
+///////////////////////////////   DOWNLOADING   ///////////////////////////////
+
+localparam UIO_FILE_TX      = 8'h53;
+localparam UIO_FILE_TX_DAT  = 8'h54;
+localparam UIO_FILE_INDEX   = 8'h55;
+// SPI receiver IO -> FPGA
+
+reg       spi_receiver_strobe_r = 0;
+reg       spi_transfer_end_r = 1;
+reg [7:0] spi_byte_in;
+
+// data_io has its own SPI interface to the io controller
+// Read at spi_sck clock domain, assemble bytes for transferring to clk_sys
+always@(posedge SPI_SCK or posedge SPI_SS2) begin
+
+	reg  [6:0] sbuf;
+	reg  [2:0] bit_cnt;
+
+	if(SPI_SS2) begin
+		spi_transfer_end_r <= 1;
+		bit_cnt <= 0;
+	end else begin
+		spi_transfer_end_r <= 0;
+		
+		bit_cnt <= bit_cnt + 1'd1;
+
+		if(bit_cnt != 7)
+			sbuf[6:0] <= { sbuf[5:0], SPI_DI };
+
+		// finished reading a byte, prepare to transfer to clk_sys
+        if(bit_cnt == 7) begin
+			spi_byte_in <= { sbuf, SPI_DI};
+			spi_receiver_strobe_r <= ~spi_receiver_strobe_r;
+		end
+	end
+end
+
+always @(posedge clk_sys) begin
+
+	reg        spi_receiver_strobe;
+	reg        spi_transfer_end;
+	reg        spi_receiver_strobeD;
+	reg        spi_transfer_endD;
+	reg  [7:0] acmd;
+	reg  [2:0] abyte_cnt;   // counts bytes
+	reg [24:0] addr;
+	reg        wr_int;
+	reg        clkrefD;
+	reg        hi;
+
+	//synchronize between SPI and sys clock domains
+	spi_receiver_strobeD <= spi_receiver_strobe_r;
+	spi_receiver_strobe <= spi_receiver_strobeD;
+	spi_transfer_endD <= spi_transfer_end_r;
+	spi_transfer_end <= spi_transfer_endD;
+
+	if (~spi_transfer_endD & spi_transfer_end) begin
+		abyte_cnt <= 3'd0;
+	end else if (spi_receiver_strobeD ^ spi_receiver_strobe) begin
+		if(~&abyte_cnt) abyte_cnt <= abyte_cnt + 1'd1;
+
+		if(abyte_cnt == 0) begin
+			acmd <= spi_byte_in;
+			hi <= 0;
+		end else begin
+			case (acmd)
+				UIO_FILE_TX: begin
+				// prepare 
+					if(spi_byte_in) begin
+						addr <= 0;
+						ioctl_download <= 1; 
+					end else begin
+						ioctl_addr <= addr;
+						ioctl_download <= 0;
+					end
+				end
+
+				// transfer
+				UIO_FILE_TX_DAT: begin
+					ioctl_addr <= addr;
+					if (hi) ioctl_dout[15:8] <= spi_byte_in; else ioctl_dout[7:0] <= spi_byte_in;
+					hi <= ~hi;
+					if (hi) wr_int <= 1;
+				end
+
+				// expose file (menu) index
+				UIO_FILE_INDEX: ioctl_index <= spi_byte_in;
+			endcase
+		end
+	end
+
+	ioctl_wr <= 0;
+	if (wr_int & ~ioctl_wait) begin
+		addr <= addr + 2'd2;
+		ioctl_wr <= 1;
+		wr_int <= 0;
+	end
+end
+
+endmodule
Index: mist/ntsc_rom.qip
===================================================================
--- mist/ntsc_rom.qip	(nonexistent)
+++ mist/ntsc_rom.qip	(revision 1316)
@@ -0,0 +1,3 @@
+set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "ntsc_rom.vhd"]
Index: mist/ntsc_rom.vhd
===================================================================
--- mist/ntsc_rom.vhd	(nonexistent)
+++ mist/ntsc_rom.vhd	(revision 1316)
@@ -0,0 +1,147 @@
+-- megafunction wizard: %ROM: 1-PORT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram 
+
+-- ============================================================
+-- File Name: ntsc_rom.vhd
+-- Megafunction Name(s):
+-- 			altsyncram
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.4 Build 182 03/12/2014 Patches 4.26 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2014 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.altera_mf_components.all;
+
+ENTITY ntsc_rom IS
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		clock		: IN STD_LOGIC  := '1';
+		rden		: IN STD_LOGIC  := '1';
+		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+END ntsc_rom;
+
+
+ARCHITECTURE SYN OF ntsc_rom IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+
+BEGIN
+	q    <= sub_wire0(7 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_aclr_a => "NONE",
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		init_file => "ntsc.mif",
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 256,
+		operation_mode => "ROM",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => "CLOCK0",
+		widthad_a => 8,
+		width_a => 8,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		address_a => address,
+		clock0 => clock,
+		rden_a => rden,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: Clken NUMERIC "0"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING "ntsc.mif"
+-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
+-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
+-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
+-- Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
+-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
+-- Retrieval info: PRIVATE: rden NUMERIC "1"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: INIT_FILE STRING "ntsc.mif"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+-- Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
+-- Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden"
+-- Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: @rden_a 0 0 0 0 rden 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ntsc_rom.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ntsc_rom.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ntsc_rom.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ntsc_rom.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ntsc_rom_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
Index: mist/osd.v
===================================================================
--- mist/osd.v	(nonexistent)
+++ mist/osd.v	(revision 1316)
@@ -0,0 +1,196 @@
+// A simple OSD implementation. Can be hooked up between a cores
+// VGA output and the physical VGA pins
+
+module osd (
+	// OSDs pixel clock, should be synchronous to cores pixel clock to
+	// avoid jitter.
+	input        clk_sys,
+
+	// SPI interface
+	input        SPI_SCK,
+	input        SPI_SS3,
+	input        SPI_DI,
+
+	input  [1:0] rotate, //[0] - rotate [1] - left or right
+
+	// VGA signals coming from core
+	input  [5:0] R_in,
+	input  [5:0] G_in,
+	input  [5:0] B_in,
+	input        HSync,
+	input        VSync,
+
+	// VGA signals going to video connector
+	output [5:0] R_out,
+	output [5:0] G_out,
+	output [5:0] B_out
+);
+
+parameter OSD_X_OFFSET = 10'd0;
+parameter OSD_Y_OFFSET = 10'd0;
+parameter OSD_COLOR    = 3'd0;
+
+localparam OSD_WIDTH   = 10'd256;
+localparam OSD_HEIGHT  = 10'd128;
+
+// *********************************************************************************
+// spi client
+// *********************************************************************************
+
+// this core supports only the display related OSD commands
+// of the minimig
+reg        osd_enable;
+(* ramstyle = "no_rw_check" *) reg  [7:0] osd_buffer[2047:0];  // the OSD buffer itself
+
+// the OSD has its own SPI interface to the io controller
+always@(posedge SPI_SCK, posedge SPI_SS3) begin
+	reg  [4:0] cnt;
+	reg [10:0] bcnt;
+	reg  [7:0] sbuf;
+	reg  [7:0] cmd;
+
+	if(SPI_SS3) begin
+		cnt  <= 0;
+		bcnt <= 0;
+	end else begin
+		sbuf <= {sbuf[6:0], SPI_DI};
+
+		// 0:7 is command, rest payload
+		if(cnt < 15) cnt <= cnt + 1'd1;
+			else cnt <= 8;
+
+		if(cnt == 7) begin
+			cmd <= {sbuf[6:0], SPI_DI};
+
+			// lower three command bits are line address
+			bcnt <= {sbuf[1:0], SPI_DI, 8'h00};
+
+			// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
+			if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI;
+		end
+
+		// command 0x20: OSDCMDWRITE
+		if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin
+			osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI};
+			bcnt <= bcnt + 1'd1;
+		end
+	end
+end
+
+// *********************************************************************************
+// video timing and sync polarity anaylsis
+// *********************************************************************************
+
+// horizontal counter
+reg  [9:0] h_cnt;
+reg  [9:0] hs_low, hs_high;
+wire       hs_pol = hs_high < hs_low;
+wire [9:0] dsp_width = hs_pol ? hs_low : hs_high;
+
+// vertical counter
+reg  [9:0] v_cnt;
+reg  [9:0] vs_low, vs_high;
+wire       vs_pol = vs_high < vs_low;
+wire [9:0] dsp_height = vs_pol ? vs_low : vs_high;
+
+wire doublescan = (dsp_height>350);
+
+reg ce_pix;
+always @(posedge clk_sys) begin
+	integer cnt = 0;
+	integer pixsz, pixcnt;
+	reg hs;
+
+	cnt <= cnt + 1;
+	hs <= HSync;
+
+	pixcnt <= pixcnt + 1;
+	if(pixcnt == pixsz) pixcnt <= 0;
+	ce_pix <= !pixcnt;
+
+	if(hs && ~HSync) begin
+		cnt    <= 0;
+		if (cnt <= 512) pixsz = 0;
+		else pixsz  <= (cnt >> 9) - 1;
+		pixcnt <= 0;
+		ce_pix <= 1;
+	end
+end
+
+always @(posedge clk_sys) begin
+	reg hsD, hsD2;
+	reg vsD, vsD2;
+
+	if(ce_pix) begin
+		// bring hsync into local clock domain
+		hsD <= HSync;
+		hsD2 <= hsD;
+
+		// falling edge of HSync
+		if(!hsD && hsD2) begin
+			h_cnt <= 0;
+			hs_high <= h_cnt;
+		end
+
+		// rising edge of HSync
+		else if(hsD && !hsD2) begin
+			h_cnt <= 0;
+			hs_low <= h_cnt;
+			v_cnt <= v_cnt + 1'd1;
+		end else begin
+			h_cnt <= h_cnt + 1'd1;
+		end
+
+		vsD <= VSync;
+		vsD2 <= vsD;
+
+		// falling edge of VSync
+		if(!vsD && vsD2) begin
+			v_cnt <= 0;
+			vs_high <= v_cnt;
+		end
+
+		// rising edge of VSync
+		else if(vsD && !vsD2) begin
+			v_cnt <= 0;
+			vs_low <= v_cnt;
+		end
+	end
+end
+
+// area in which OSD is being displayed
+wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET;
+wire [9:0] h_osd_end   = h_osd_start + OSD_WIDTH;
+wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<<doublescan))>> 1) + OSD_Y_OFFSET;
+wire [9:0] v_osd_end   = v_osd_start + (OSD_HEIGHT<<doublescan);
+wire [9:0] osd_hcnt    = h_cnt - h_osd_start;
+wire [9:0] osd_vcnt    = v_cnt - v_osd_start;
+wire [9:0] osd_hcnt_next  = osd_hcnt + 2'd1;  // one pixel offset for osd pixel
+wire [9:0] osd_hcnt_next2 = osd_hcnt + 2'd2;  // two pixel offset for osd byte address register
+reg        osd_de;
+
+reg [10:0] osd_buffer_addr;
+wire [7:0] osd_byte = osd_buffer[osd_buffer_addr];
+reg        osd_pixel;
+
+always @(posedge clk_sys) begin
+	if(ce_pix) begin
+		osd_buffer_addr <= rotate[0] ? {rotate[1] ? osd_hcnt_next2[7:5] : ~osd_hcnt_next2[7:5],
+		                                rotate[1] ? (doublescan ? ~osd_vcnt[7:0] : ~{osd_vcnt[6:0], 1'b0}) :
+		                                            (doublescan ?  osd_vcnt[7:0]  : {osd_vcnt[6:0], 1'b0})} :
+		                               {doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt_next2[7:0]};
+
+		osd_pixel <= rotate[0]  ? osd_byte[rotate[1] ? osd_hcnt_next[4:2] : ~osd_hcnt_next[4:2]] :
+		                          osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]];
+
+		osd_de <= osd_enable &&
+		    (HSync != hs_pol) && ((h_cnt + 1'd1) >= h_osd_start) && ((h_cnt + 1'd1) < h_osd_end) &&
+		    (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end);
+	end
+end
+
+assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]};
+assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]};
+assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]};
+
+endmodule
Index: mist/pal_rom.qip
===================================================================
--- mist/pal_rom.qip	(nonexistent)
+++ mist/pal_rom.qip	(revision 1316)
@@ -0,0 +1,3 @@
+set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pal_rom.vhd"]
Index: mist/pal_rom.vhd
===================================================================
--- mist/pal_rom.vhd	(nonexistent)
+++ mist/pal_rom.vhd	(revision 1316)
@@ -0,0 +1,147 @@
+-- megafunction wizard: %ROM: 1-PORT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram 
+
+-- ============================================================
+-- File Name: pal_rom.vhd
+-- Megafunction Name(s):
+-- 			altsyncram
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.4 Build 182 03/12/2014 Patches 4.26 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2014 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.altera_mf_components.all;
+
+ENTITY pal_rom IS
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		clock		: IN STD_LOGIC  := '1';
+		rden		: IN STD_LOGIC  := '1';
+		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+END pal_rom;
+
+
+ARCHITECTURE SYN OF pal_rom IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+
+BEGIN
+	q    <= sub_wire0(7 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_aclr_a => "NONE",
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		init_file => "pal.mif",
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 256,
+		operation_mode => "ROM",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => "CLOCK0",
+		widthad_a => 8,
+		width_a => 8,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		address_a => address,
+		clock0 => clock,
+		rden_a => rden,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: Clken NUMERIC "0"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING "pal.mif"
+-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
+-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
+-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
+-- Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
+-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
+-- Retrieval info: PRIVATE: rden NUMERIC "1"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: INIT_FILE STRING "pal.mif"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+-- Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
+-- Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden"
+-- Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: @rden_a 0 0 0 0 rden 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pal_rom.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pal_rom.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pal_rom.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pal_rom.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pal_rom_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
Index: mist/switch_pal_ntsc.vhd
===================================================================
--- mist/switch_pal_ntsc.vhd	(revision 1315)
+++ mist/switch_pal_ntsc.vhd	(revision 1316)
@@ -28,6 +28,7 @@
         RESET_N : IN STD_LOGIC;
 
         PAL : IN STD_LOGIC;
+        SWITCH_ENA : in STD_LOGIC;
 
         INPUT_CLK : IN STD_LOGIC;
         PLL_CLKS : OUT STD_LOGIC_VECTOR(CLOCKS-1 downto 0);
@@ -47,25 +48,14 @@
     signal pll_reconfig_scandataout : std_logic;
     signal pll_reconfig_scandone : std_logic;
     signal pll_reconfig_busy : std_logic;
-    
-    signal pll_reconfig_areset_pal : std_logic;
-    signal pll_reconfig_configupdate_pal : std_logic;
-    signal pll_reconfig_scanclk_pal : std_logic;
-    signal pll_reconfig_scanclkena_pal : std_logic;
-    signal pll_reconfig_scandata_pal : std_logic;
-    signal pll_reconfig_scandataout_pal : std_logic;
-    signal pll_reconfig_scandone_pal : std_logic;
-    signal pll_reconfig_busy_pal : std_logic;
+    signal pll_reconfig_rom_address : std_logic_vector(7 downto 0);
+    signal pll_reconfig_rom_q : std_logic;
+    signal q_reconfig_pal : std_logic_vector(7 downto 0);
+    signal q_reconfig_ntsc : std_logic_vector(7 downto 0);
 
-    signal pll_reconfig_areset_ntsc : std_logic;
-    signal pll_reconfig_configupdate_ntsc : std_logic;
-    signal pll_reconfig_scanclk_ntsc : std_logic;
-    signal pll_reconfig_scanclkena_ntsc : std_logic;
-    signal pll_reconfig_scandata_ntsc : std_logic;
-    signal pll_reconfig_scandataout_ntsc : std_logic;
-    signal pll_reconfig_scandone_ntsc : std_logic;
-    signal pll_reconfig_busy_ntsc : std_logic;
-
+    signal pll_reconfig_write_rom_ena : std_logic;
+    signal pll_reconfig_write_from_rom : std_logic;
+    signal pll_reconfig_write_from_rom_next : std_logic;
     signal pll_pause_counter_reg : std_logic_vector(29 downto 0);
     signal pll_pause_counter_next : std_logic_vector(29 downto 0);    
     
@@ -75,19 +65,21 @@
     
     signal pll_state_reg : std_logic_vector(3 downto 0);
     signal pll_state_next : std_logic_vector(3 downto 0);
+
     constant PLL_STATE_WAIT : std_logic_vector(3 downto 0) := "0000";
-    constant PLL_STATE_DISABLE : std_logic_vector(3 downto 0) := "0001";
-    constant PLL_STATE_DISABLE_WAIT1 : std_logic_vector(3 downto 0) := "0010";
-    constant PLL_STATE_DISABLE_WAIT2 : std_logic_vector(3 downto 0) := "0011";
-    constant PLL_STATE_DISABLE_WAIT3 : std_logic_vector(3 downto 0) := "0100";
-    constant PLL_STATE_DISABLE_WAIT4 : std_logic_vector(3 downto 0) := "0101";
-    constant PLL_STATE_RECONFIG1 : std_logic_vector(3 downto 0) := "0110";
-    constant PLL_STATE_RECONFIG1_WAIT_CONFIG : std_logic_vector(3 downto 0) := "0111";
-    constant PLL_STATE_RECONFIG1_WAIT_LOCK : std_logic_vector(3 downto 0) := "1000";
-    constant PLL_STATE_PAUSE1 : std_logic_vector(3 downto 0) := "1001";  
+    constant PLL_STATE_WAIT_RECONF_ROM : std_logic_vector(3 downto 0) := "0001";
+    constant PLL_STATE_RECONF_ROM : std_logic_vector(3 downto 0) := "0010";
+    constant PLL_STATE_DISABLE : std_logic_vector(3 downto 0) := "0011";
+    constant PLL_STATE_DISABLE_WAIT1 : std_logic_vector(3 downto 0) := "0100";
+    constant PLL_STATE_DISABLE_WAIT2 : std_logic_vector(3 downto 0) := "0101";
+    constant PLL_STATE_DISABLE_WAIT3 : std_logic_vector(3 downto 0) := "0110";
+    constant PLL_STATE_DISABLE_WAIT4 : std_logic_vector(3 downto 0) := "0111";
+    constant PLL_STATE_RECONFIG1 : std_logic_vector(3 downto 0) := "1000";
+    constant PLL_STATE_RECONFIG1_WAIT_CONFIG : std_logic_vector(3 downto 0) := "1001";
+    constant PLL_STATE_RECONFIG1_WAIT_LOCK : std_logic_vector(3 downto 0) := "1010";
+    constant PLL_STATE_PAUSE1 : std_logic_vector(3 downto 0) := "1011";
     
     signal pll_trigger_reconfig : std_logic;  
-    signal pll_trigger_reconfig_downstream : std_logic;  
     
     signal pll_upstream_reset : std_logic;
     signal pll_upstream_reset_pal : std_logic;
@@ -125,6 +117,7 @@
              scandataout => pll_reconfig_scandataout,
              scandone => pll_reconfig_scandone         
              );
+
     generic_pll2 : entity work.pll_downstream_pal
     PORT MAP(inclk0 => CLK_PLL1,
              c0 => CLK_RAW(0),
@@ -135,49 +128,11 @@
              areset => pll_downstream_reset,
              locked => PLL_LOCKED
              );
-     
-     process(reconfig_to_pal_reg,
-        pll_reconfig_scanclk_pal, pll_reconfig_scanclkena_pal, pll_reconfig_busy_pal, pll_reconfig_areset_pal,pll_reconfig_scandata_pal,pll_reconfig_configupdate_pal,
-        pll_reconfig_scanclk_ntsc, pll_reconfig_scanclkena_ntsc, pll_reconfig_busy_ntsc, pll_reconfig_areset_ntsc,pll_reconfig_scandata_ntsc,pll_reconfig_configupdate_ntsc,
-        pll_upstream_reset,pll_reconfig_scandone,pll_reconfig_scandataout
-    )
-     begin
-        pll_upstream_reset_pal<= '0';
-        pll_upstream_reset_ntsc <= '0';            
-        pll_reconfig_scandone_pal <= '0';
-        pll_reconfig_scandone_ntsc <= '0';
-        pll_reconfig_scandataout_pal <= '0';
-        pll_reconfig_scandataout_ntsc <= '0';
-     
-        if (reconfig_to_pal_reg='1') then
-            pll_reconfig_scanclk<=pll_reconfig_scanclk_pal;
-            pll_reconfig_scanclkena<=pll_reconfig_scanclkena_pal;
-            pll_reconfig_scandata<= pll_reconfig_scandata_pal;
-            pll_reconfig_busy <= pll_reconfig_busy_pal;
-            pll_reconfig_areset <= pll_reconfig_areset_pal;                
-            pll_reconfig_configupdate <= pll_reconfig_configupdate_pal;
-                            
-            pll_upstream_reset_pal <= pll_upstream_reset;
-            pll_reconfig_scandone_pal <= pll_reconfig_scandone;
-            pll_reconfig_scandataout_pal <= pll_reconfig_scandataout;                
-        else
-            pll_reconfig_scanclk<=pll_reconfig_scanclk_ntsc;
-            pll_reconfig_scanclkena<=pll_reconfig_scanclkena_ntsc;
-            pll_reconfig_scandata<= pll_reconfig_scandata_ntsc;
-            pll_reconfig_busy <= pll_reconfig_busy_ntsc;
-            pll_reconfig_areset <= pll_reconfig_areset_ntsc;        
-            pll_reconfig_configupdate <= pll_reconfig_configupdate_ntsc;                
-            
-            pll_upstream_reset_ntsc <= pll_upstream_reset;
-            pll_reconfig_scandone_ntsc  <= pll_reconfig_scandone;
-            pll_reconfig_scandataout_ntsc <= pll_reconfig_scandataout;
-        end if;
-     end process;
-             
+
      generic_pll1_reconfig : entity work.video_pll_reconfig
      PORT MAP
      ( 
-         busy    => pll_reconfig_busy_ntsc,
+         busy    => pll_reconfig_busy,
          clock => RECONFIG_CLK,
          counter_param    => (OTHERS => '0'),
          counter_type    => (OTHERS => '0'),
@@ -185,43 +140,43 @@
          read_param    => '0',
          write_param => '0',
          --data_out    :    OUT  STD_LOGIC_VECTOR (8 DOWNTO 0);
-         pll_areset    => pll_reconfig_areset_ntsc,
-         pll_areset_in    => pll_upstream_reset_ntsc,
-         pll_configupdate    => pll_reconfig_configupdate_ntsc,
-         pll_scanclk => pll_reconfig_scanclk_ntsc,
-         pll_scanclkena => pll_reconfig_scanclkena_ntsc,
-         pll_scandata => pll_reconfig_scandata_ntsc,
+         pll_areset    => pll_reconfig_areset,
+         pll_areset_in    => pll_upstream_reset,
+         pll_configupdate    => pll_reconfig_configupdate,
+         pll_scanclk => pll_reconfig_scanclk,
+         pll_scanclkena => pll_reconfig_scanclkena,
+         pll_scandata => pll_reconfig_scandata,
          pll_scandataout => pll_reconfig_scandataout,
          pll_scandone    => pll_reconfig_scandone,
-         
-         reconfig => pll_trigger_reconfig,
-         reset => not(RESET_N)
-     );     
 
-     generic_pll1_reconfig_pal : entity work.video_pll_reconfig_pal
-     PORT MAP
-     ( 
-         busy    => pll_reconfig_busy_pal,
-         clock => RECONFIG_CLK,
-         counter_param    => (OTHERS => '0'),
-         counter_type    => (OTHERS => '0'),
-         data_in    => (OTHERS => '0'),
-         read_param    => '0',
-         write_param => '0',
-         --data_out    :    OUT  STD_LOGIC_VECTOR (8 DOWNTO 0);
-         pll_areset    => pll_reconfig_areset_pal,
-         pll_areset_in    => pll_upstream_reset_pal,
-         pll_configupdate    => pll_reconfig_configupdate_pal,
-         pll_scanclk => pll_reconfig_scanclk_pal,
-         pll_scanclkena => pll_reconfig_scanclkena_pal,
-         pll_scandata => pll_reconfig_scandata_pal,
-         pll_scandataout => pll_reconfig_scandataout,
-         pll_scandone    => pll_reconfig_scandone,
-         
+         reset_rom_address => '0',
+         rom_address_out => pll_reconfig_rom_address,
+         rom_data_in => pll_reconfig_rom_q,
+         write_from_rom => pll_reconfig_write_from_rom,
+         write_rom_ena => pll_reconfig_write_rom_ena,
+
          reconfig => pll_trigger_reconfig,
          reset => not(RESET_N)
-     ); 
+     );
 
+     pll_rom_pal : entity work.pal_rom
+     port map(
+       address => pll_reconfig_rom_address,
+       clock => RECONFIG_CLK,
+       rden => pll_reconfig_write_rom_ena,
+       q => q_reconfig_pal
+      );
+
+     pll_rom_ntsc : entity work.ntsc_rom
+     port map(
+       address => pll_reconfig_rom_address,
+       clock => RECONFIG_CLK,
+       rden => pll_reconfig_write_rom_ena,
+       q => q_reconfig_ntsc
+     );
+
+     pll_reconfig_rom_q <= q_reconfig_pal(0) when reconfig_to_pal_reg = '1' else q_reconfig_ntsc(0);
+
      process(RECONFIG_CLK,RESET_N)
      begin
         if (RESET_N='0') then
@@ -228,6 +183,7 @@
             pll_state_reg <= PLL_STATE_WAIT;
             pll_pause_counter_reg<= (others=>'0');
             pll_enable_reg<='0';
+						pll_reconfig_write_from_rom <= '0';
             reset_n_reg <= '0';
             
             reconfig_to_pal_reg <= '1';
@@ -236,6 +192,7 @@
             pll_state_reg <= pll_state_next;
             pll_pause_counter_reg <= pll_pause_counter_next;
             pll_enable_reg <= pll_enable_next;
+						pll_reconfig_write_from_rom <= pll_reconfig_write_from_rom_next;
             reset_n_reg <= reset_n_next;        
     
             reconfig_to_pal_reg <= reconfig_to_pal_next;
@@ -243,79 +200,92 @@
      end process;        
      
     pal_synchronizer : entity work.synchronizer
-              port map (clk=>RECONFIG_CLK, raw=>pal, sync=>pal_fpga_sync);                   
+              port map (clk=>RECONFIG_CLK, raw=>pal, sync=>pal_fpga_sync);
      
     process (pll_state_reg, pal_fpga_sync, pll_pause_counter_reg,pll_enable_reg, PLL_LOCKED1, PLL_LOCKED, pll_reconfig_busy,reconfig_to_pal_reg)
     begin
-              pll_state_next <= pll_state_reg;
-              reset_n_next <= '1';
-              reconfig_to_pal_next <= reconfig_to_pal_reg;
-              
-              pll_pause_counter_next <= std_logic_vector(unsigned(pll_pause_counter_reg)+1);                        
+        pll_reconfig_write_from_rom_next <= '0';
+        pll_state_next <= pll_state_reg;
+        reset_n_next <= '1';
+        reconfig_to_pal_next <= reconfig_to_pal_reg;
 
-              pll_trigger_reconfig <= '0';
-              pll_trigger_reconfig_downstream <= '0';
-              pll_downstream_reset <= '0';
-              pll_upstream_reset <= '0';
-              
-              pll_enable_next <= pll_enable_reg;                                                          
+        pll_pause_counter_next <= std_logic_vector(unsigned(pll_pause_counter_reg)+1);                        
 
-              case pll_state_reg is
-                         when PLL_STATE_WAIT =>
-                                    pll_enable_next <= '1';
-                                    reset_n_next <= PLL_LOCKED;
-                                    if (not(pal_fpga_sync = reconfig_to_pal_reg) and PLL_LOCKED='1' and PLL_LOCKED1='1') then
-                                              reconfig_to_pal_next <= pal_fpga_sync;
-                                              pll_state_next <= PLL_STATE_DISABLE;
-                                              pll_enable_next <= '0';
-                                    end if;
+        pll_trigger_reconfig <= '0';
+        pll_downstream_reset <= '0';
+        pll_upstream_reset <= '0';
 
-                                    
-                         -- Wait for pll_enable_next to make through synchronizer
-              when PLL_STATE_DISABLE =>        
-                                    pll_state_next <= PLL_STATE_DISABLE_WAIT1;                                                    
-                                    
-              when PLL_STATE_DISABLE_WAIT1 =>        
-                                    pll_state_next <= PLL_STATE_DISABLE_WAIT2;            
+        pll_enable_next <= pll_enable_reg;
 
-              when PLL_STATE_DISABLE_WAIT2 =>        
-                                    pll_state_next <= PLL_STATE_DISABLE_WAIT3;
+        case pll_state_reg is
+              when PLL_STATE_WAIT =>
+                  pll_enable_next <= '1';
+                  if SWITCH_ENA = '1' then
+                      reset_n_next <= PLL_LOCKED;
+                      if (not(pal_fpga_sync = reconfig_to_pal_reg) and PLL_LOCKED='1' and PLL_LOCKED1='1') then
+                          reconfig_to_pal_next <= pal_fpga_sync;
+                          pll_state_next <= PLL_STATE_WAIT_RECONF_ROM;
+                          pll_reconfig_write_from_rom_next <= '1';
+                      end if;
+                  end if;
 
-              when PLL_STATE_DISABLE_WAIT3 =>        
-                                    pll_state_next <= PLL_STATE_DISABLE_WAIT4;                                        
+              when PLL_STATE_WAIT_RECONF_ROM =>
+                  pll_state_next <= PLL_STATE_RECONF_ROM;
+
+              when PLL_STATE_RECONF_ROM =>        
+                  if (pll_reconfig_busy = '0') then
+                      pll_state_next <= PLL_STATE_DISABLE;                                                    
+                      pll_pause_counter_next <= (others=>'0');
+                  end if;
                                     
-              when PLL_STATE_DISABLE_WAIT4 =>        
-                                    pll_state_next <= PLL_STATE_RECONFIG1;                                                
+              when PLL_STATE_DISABLE =>
+                  if (pll_pause_counter_reg(16)='1') then
+                      pll_enable_next <= '0';
+                      pll_state_next <= PLL_STATE_DISABLE_WAIT1;
+                  end if;
                                     
-                         -- Set params for upstream pll and reset downstream pll
-              when PLL_STATE_RECONFIG1 =>        
-												pll_trigger_reconfig <= '1';
-                                    pll_downstream_reset <= '1';
-                                    pll_state_next <= PLL_STATE_RECONFIG1_WAIT_CONFIG;
-                                                                         
-              when PLL_STATE_RECONFIG1_WAIT_CONFIG =>        
-                                    --pll_downstream_reset <= '1';
-                                    if (pll_reconfig_busy = '0') then                                        
-                                        pll_state_next <= PLL_STATE_RECONFIG1_WAIT_LOCK;
-                                    end if;    
+              -- Wait for pll_enable_next to make through synchronizer
+              when PLL_STATE_DISABLE_WAIT1 =>
+                  pll_state_next <= PLL_STATE_DISABLE_WAIT2;
 
+              when PLL_STATE_DISABLE_WAIT2 =>
+                  pll_state_next <= PLL_STATE_DISABLE_WAIT3;
+
+              when PLL_STATE_DISABLE_WAIT3 =>
+                  pll_state_next <= PLL_STATE_DISABLE_WAIT4;
+
+              when PLL_STATE_DISABLE_WAIT4 =>
+                  pll_state_next <= PLL_STATE_RECONFIG1;
+
+              -- Set params for upstream pll and reset downstream pll
+              when PLL_STATE_RECONFIG1 =>
+                  pll_trigger_reconfig <= '1';
+                  pll_downstream_reset <= '1';
+                  pll_state_next <= PLL_STATE_RECONFIG1_WAIT_CONFIG;
+
+              when PLL_STATE_RECONFIG1_WAIT_CONFIG =>
+                  --pll_downstream_reset <= '1';
+                  if (pll_reconfig_busy = '0') then
+                      pll_state_next <= PLL_STATE_RECONFIG1_WAIT_LOCK;
+                  end if;
+
               when PLL_STATE_RECONFIG1_WAIT_LOCK =>
-                                    --pll_downstream_reset <= '1';
-                                    if (PLL_LOCKED1 = '1') then
-                                        pll_state_next <= PLL_STATE_PAUSE1;
-                                        pll_pause_counter_next <= (others=>'0');
-                                        --pll_downstream_reset <= '0';
-                                    end if;                    
-                                
+                  --pll_downstream_reset <= '1';
+                  if (PLL_LOCKED1 = '1') then
+                      pll_state_next <= PLL_STATE_PAUSE1;
+                      pll_pause_counter_next <= (others=>'0');
+                      --pll_downstream_reset <= '0';
+                  end if;
+
               when PLL_STATE_PAUSE1 =>
-                                    if (pll_pause_counter_reg(24)='1') then
-                                        pll_state_next <= PLL_STATE_WAIT;
-                                    end if;                                        
+                  if (pll_pause_counter_reg(16)='1') then
+                      pll_state_next <= PLL_STATE_WAIT;
+                  end if;
 
               when others =>
-                                    pll_state_next <= PLL_STATE_WAIT;
+                  pll_state_next <= PLL_STATE_WAIT;
 
-              end case;                 
+              end case;
 
     end process;
 
Index: mist/user_io.v
===================================================================
--- mist/user_io.v	(revision 1315)
+++ mist/user_io.v	(revision 1316)
@@ -7,7 +7,7 @@
 // Copyright (c) 2014 Till Harbaum <till@harbaum.org>
 //
 // This source file is free software: you can redistribute it and/or modify
-// it under the terms of the Lesser GNU General Public License as published
+// it under the terms of the GNU General Public License as published
 // by the Free Software Foundation, either version 3 of the License, or
 // (at your option) any later version.
 //
@@ -22,182 +22,256 @@
 
 // parameter STRLEN and the actual length of conf_str have to match
  
-module user_io #(parameter STRLEN=0) (
+module user_io #(parameter STRLEN=0, parameter PS2DIV=100, parameter ROM_DIRECT_UPLOAD=0) (
 	input [(8*STRLEN)-1:0] conf_str,
+	output       [9:0]  conf_addr, // RAM address for config string, if STRLEN=0
+	input        [7:0]  conf_chr,
 
-	input      		SPI_CLK,
-	input      		SPI_SS_IO,
-	output     		reg SPI_MISO,
-	input      		SPI_MOSI,
-	
-	output reg [5:0] 	joystick_0,
-	output reg [5:0] 	joystick_1,
-	output reg [15:0] joystick_analog_0,
-	output reg [15:0] joystick_analog_1,
-	output [1:0] 		buttons,
-	output [1:0] 		switches,
+	input               clk_sys, // clock for system-related messages (kbd, joy, etc...)
+	input               clk_sd,  // clock for SD-card related messages
 
-	output reg [7:0]   status,
+	input               SPI_CLK,
+	input               SPI_SS_IO,
+	output reg          SPI_MISO,
+	input               SPI_MOSI,
 
+	output reg   [31:0] joystick_0,
+	output reg   [31:0] joystick_1,
+	output reg   [31:0] joystick_2,
+	output reg   [31:0] joystick_3,
+	output reg   [31:0] joystick_4,
+	output reg   [15:0] joystick_analog_0,
+	output reg   [15:0] joystick_analog_1,
+	output        [1:0] buttons,
+	output        [1:0] switches,
+	output              scandoubler_disable,
+	output              ypbpr,
+	output              no_csync,
+	output reg   [63:0] status,
+	output reg    [6:0] core_mod, // core variant, sent before the config string is requested
+	// RTC data from IO controller
+	// sec, min, hour, date, month, year, day (BCD)
+	output reg   [63:0] rtc,
+
 	// connection to sd card emulation
-	input [31:0]  sd_lba,
-	input         sd_rd,
-	input         sd_wr,
-	output reg	  sd_ack,
-	input         sd_conf,
-	input         sd_sdhc,
-	output reg [7:0]  sd_dout,
-	output reg	  sd_dout_strobe,
-	input [7:0]   sd_din,
-	output reg 	  sd_din_strobe,
-	
+	input        [31:0] sd_lba,
+	input         [1:0] sd_rd,
+	input         [1:0] sd_wr,
+	output reg          sd_ack,
+	output reg          sd_ack_conf,
+	input               sd_conf,
+	input               sd_sdhc,
+	output reg    [7:0] sd_dout, // valid on rising edge of sd_dout_strobe
+	output reg          sd_dout_strobe,
+	input         [7:0] sd_din,
+	output reg          sd_din_strobe,
+	output reg    [8:0] sd_buff_addr,
 
-	// ps2 keyboard emulation
-	input 	  		ps2_clk,				// 12-16khz provided by core
-	output	 		ps2_kbd_clk,
-	output reg 		ps2_kbd_data,
+	output reg    [1:0] img_mounted, // rising edge if a new image is mounted
+	output reg   [31:0] img_size,    // size of image in bytes
 
-	// serial com port 
-	input [7:0]		serial_data,
-	input				serial_strobe
+	// ps2 keyboard/mouse emulation
+	output              ps2_kbd_clk,
+	output reg          ps2_kbd_data,
+	output              ps2_mouse_clk,
+	output reg          ps2_mouse_data,
+
+	// keyboard data
+	output reg          key_pressed,  // 1-make (pressed), 0-break (released)
+	output reg          key_extended, // extended code
+	output reg    [7:0] key_code,     // key scan code
+	output reg          key_strobe,   // key data valid
+
+	// mouse data
+	output reg    [8:0] mouse_x,
+	output reg    [8:0] mouse_y,
+	output reg    [3:0] mouse_z,
+	output reg    [7:0] mouse_flags,  // YOvfl, XOvfl, dy8, dx8, 1, mbtn, rbtn, lbtn
+	output reg          mouse_strobe, // mouse data is valid on mouse_strobe
+	output reg          mouse_idx,    // which mouse?
+
+	// serial com port
+	input [7:0]         serial_data,
+	input               serial_strobe
 );
 
-reg [6:0]         sbuf;
-reg [7:0]         cmd;
-reg [2:0] 	      bit_cnt;    // counts bits 0-7 0-7 ...
-reg [7:0]         byte_cnt;   // counts bytes
-reg [5:0]         joystick0;
-reg [5:0]         joystick1;
-reg [3:0] 	      but_sw;
-reg [2:0]         stick_idx;
+reg [6:0]     sbuf;
+reg [7:0]     cmd;
+reg [2:0]     bit_cnt;    // counts bits 0-7 0-7 ...
+reg [9:0]     byte_cnt;   // counts bytes
+reg [7:0]     but_sw;
+reg [2:0]     stick_idx;
 
 assign buttons = but_sw[1:0];
 assign switches = but_sw[3:2];
+assign scandoubler_disable = but_sw[4];
+assign ypbpr = but_sw[5];
+assign no_csync = but_sw[6];
 
+assign conf_addr = byte_cnt;
+
 // this variant of user_io is for 8 bit cores (type == a4) only
-wire [7:0] core_type = 8'ha4;
+// bit 4 indicates ROM direct upload capability
+wire [7:0] core_type = ROM_DIRECT_UPLOAD ? 8'hb4 : 8'ha4;
 
+wire drive_sel = sd_rd[1] | sd_wr[1];
 // command byte read by the io controller
-wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd };
+wire [7:0] sd_cmd = { 4'h6, sd_conf, sd_sdhc, sd_wr[drive_sel], sd_rd[drive_sel] };
 
-// filter spi clock. the 8 bit gate delay is ~2.5ns in total
-wire [7:0] spi_sck_D = { spi_sck_D[6:0], SPI_CLK } /* synthesis keep */;
-wire spi_sck = (spi_sck && spi_sck_D != 8'h00) || (!spi_sck && spi_sck_D == 8'hff);
+wire spi_sck = SPI_CLK;
 
-// drive MISO only when transmitting core id
-always@(negedge spi_sck or posedge SPI_SS_IO) begin
-	if(SPI_SS_IO == 1) begin
-	   SPI_MISO <= 1'bZ;
-	end else begin
+// ---------------- PS2 ---------------------
+// 8 byte fifos to store ps2 bytes
+localparam PS2_FIFO_BITS = 3;
 
-		// first byte returned is always core type, further bytes are 
-		// command dependent
-      if(byte_cnt == 0) begin
-		  SPI_MISO <= core_type[~bit_cnt];
+reg ps2_clk;
+always @(negedge clk_sys) begin
+	integer cnt;
+	cnt <= cnt + 1'd1;
+	if(cnt == PS2DIV) begin
+		ps2_clk <= ~ps2_clk;
+		cnt <= 0;
+	end
+end
 
+// keyboard
+reg [7:0] ps2_kbd_fifo [(2**PS2_FIFO_BITS)-1:0];
+reg [PS2_FIFO_BITS-1:0] ps2_kbd_wptr;
+reg [PS2_FIFO_BITS-1:0] ps2_kbd_rptr;
+
+// ps2 transmitter state machine
+reg [3:0] ps2_kbd_tx_state;
+reg [7:0] ps2_kbd_tx_byte;
+reg ps2_kbd_parity;
+
+assign ps2_kbd_clk = ps2_clk || (ps2_kbd_tx_state == 0);
+
+// ps2 transmitter
+// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
+reg ps2_kbd_r_inc;
+always@(posedge clk_sys) begin : ps2_kbd
+	reg ps2_clkD;
+
+	ps2_clkD <= ps2_clk;
+	if (~ps2_clkD & ps2_clk) begin
+		ps2_kbd_r_inc <= 1'b0;
+
+		if(ps2_kbd_r_inc)
+			ps2_kbd_rptr <= ps2_kbd_rptr + 1'd1;
+
+		// transmitter is idle?
+		if(ps2_kbd_tx_state == 0) begin
+			// data in fifo present?
+			if(ps2_kbd_wptr != ps2_kbd_rptr) begin
+				// load tx register from fifo
+				ps2_kbd_tx_byte <= ps2_kbd_fifo[ps2_kbd_rptr];
+				ps2_kbd_r_inc <= 1'b1;
+
+				// reset parity
+				ps2_kbd_parity <= 1'b1;
+
+				// start transmitter
+				ps2_kbd_tx_state <= 4'd1;
+
+				// put start bit on data line
+				ps2_kbd_data <= 1'b0;			// start bit is 0
+			end
 		end else begin
-			// reading serial fifo
-		   if(cmd == 8'h1b) begin
-				// send alternating flag byte and data
-				if(byte_cnt[0]) 	SPI_MISO <= serial_out_status[~bit_cnt];
-				else					SPI_MISO <= serial_out_byte[~bit_cnt];
+
+			// transmission of 8 data bits
+			if((ps2_kbd_tx_state >= 1)&&(ps2_kbd_tx_state < 9)) begin
+				ps2_kbd_data <= ps2_kbd_tx_byte[0];			  // data bits
+				ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down
+				if(ps2_kbd_tx_byte[0]) 
+					ps2_kbd_parity <= !ps2_kbd_parity;
 			end
+
+			// transmission of parity
+			if(ps2_kbd_tx_state == 9)
+				ps2_kbd_data <= ps2_kbd_parity;
 			
-			// reading config string
-		   else if(cmd == 8'h14) begin
-				// returning a byte from string
-				if(byte_cnt < STRLEN + 1)
-					SPI_MISO <= conf_str[{STRLEN - byte_cnt,~bit_cnt}];
-				else
-					SPI_MISO <= 1'b0;
-			end
-			
-			// reading sd card status
-		   else if(cmd == 8'h16) begin
-				if(byte_cnt == 1)
-					SPI_MISO <= sd_cmd[~bit_cnt];
-				else if((byte_cnt >= 2) && (byte_cnt < 6))
-					SPI_MISO <= sd_lba[{5-byte_cnt, ~bit_cnt}];
-				else
-					SPI_MISO <= 1'b0;
-			end
-			
-			// reading sd card write data
-		   else if(cmd == 8'h18)
-				SPI_MISO <= sd_din[~bit_cnt];
-				
-			else
-				SPI_MISO <= 1'b0;
+			// transmission of stop bit
+			if(ps2_kbd_tx_state == 10)
+				ps2_kbd_data <= 1'b1;			// stop bit is 1
+
+			// advance state machine
+			if(ps2_kbd_tx_state < 11)
+				ps2_kbd_tx_state <= ps2_kbd_tx_state + 4'd1;
+			else	
+				ps2_kbd_tx_state <= 4'd0;
 		end
-   end
+	end
 end
 
-// 8 byte fifo to store ps2 bytes
-localparam PS2_FIFO_BITS = 3;
-reg [7:0] ps2_fifo [(2**PS2_FIFO_BITS)-1:0];
-reg [PS2_FIFO_BITS-1:0] ps2_wptr;
-reg [PS2_FIFO_BITS-1:0] ps2_rptr;
+// mouse
+reg [7:0] ps2_mouse_fifo [(2**PS2_FIFO_BITS)-1:0];
+reg [PS2_FIFO_BITS-1:0] ps2_mouse_wptr;
+reg [PS2_FIFO_BITS-1:0] ps2_mouse_rptr;
 
 // ps2 transmitter state machine
-reg [3:0] ps2_tx_state;
-reg [7:0] ps2_tx_byte;
-reg ps2_parity;
+reg [3:0] ps2_mouse_tx_state;
+reg [7:0] ps2_mouse_tx_byte;
+reg ps2_mouse_parity;
 
-assign ps2_kbd_clk = ps2_clk || (ps2_tx_state == 0);
+assign ps2_mouse_clk = ps2_clk || (ps2_mouse_tx_state == 0);
 
 // ps2 transmitter
 // Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
-reg ps2_r_inc;
-always@(posedge ps2_clk) begin
-	ps2_r_inc <= 1'b0;
-	
-	if(ps2_r_inc)
-		ps2_rptr <= ps2_rptr + 1;
+reg ps2_mouse_r_inc;
+always@(posedge clk_sys) begin : ps2_mouse
+	reg ps2_clkD;
 
-	// transmitter is idle?
-	if(ps2_tx_state == 0) begin
-		// data in fifo present?
-		if(ps2_wptr != ps2_rptr) begin
-			// load tx register from fifo
-			ps2_tx_byte <= ps2_fifo[ps2_rptr];
-			ps2_r_inc <= 1'b1;
-			
-			// reset parity
-			ps2_parity <= 1'b1;
-			
-			// start transmitter
-			ps2_tx_state <= 4'd1;
+	ps2_clkD <= ps2_clk;
+	if (~ps2_clkD & ps2_clk) begin
+		ps2_mouse_r_inc <= 1'b0;
 
-			// put start bit on data line
-			ps2_kbd_data <= 1'b0;			// start bit is 0
-		end
-	end else begin
-	
-		// transmission of 8 data bits
-		if((ps2_tx_state >= 1)&&(ps2_tx_state < 9)) begin
-			ps2_kbd_data <= ps2_tx_byte[0];			  // data bits
-			ps2_tx_byte[6:0] <= ps2_tx_byte[7:1]; // shift down
-			if(ps2_tx_byte[0]) 
-				ps2_parity <= !ps2_parity;
-		end
+		if(ps2_mouse_r_inc)
+			ps2_mouse_rptr <= ps2_mouse_rptr + 1'd1;
 
-		// transmission of parity
-		if(ps2_tx_state == 9)
-			ps2_kbd_data <= ps2_parity;
-			
-		// transmission of stop bit
-		if(ps2_tx_state == 10)
-			ps2_kbd_data <= 1'b1;			// stop bit is 1
+		// transmitter is idle?
+		if(ps2_mouse_tx_state == 0) begin
+			// data in fifo present?
+			if(ps2_mouse_wptr != ps2_mouse_rptr) begin
+				// load tx register from fifo
+				ps2_mouse_tx_byte <= ps2_mouse_fifo[ps2_mouse_rptr];
+				ps2_mouse_r_inc <= 1'b1;
 
-		// advance state machine
-		if(ps2_tx_state < 11)
-			ps2_tx_state <= ps2_tx_state + 4'd1;
-		else	
-			ps2_tx_state <= 4'd0;
-	
+				// reset parity
+				ps2_mouse_parity <= 1'b1;
+
+				// start transmitter
+				ps2_mouse_tx_state <= 4'd1;
+
+				// put start bit on data line
+				ps2_mouse_data <= 1'b0;			// start bit is 0
+			end
+		end else begin
+
+			// transmission of 8 data bits
+			if((ps2_mouse_tx_state >= 1)&&(ps2_mouse_tx_state < 9)) begin
+				ps2_mouse_data <= ps2_mouse_tx_byte[0];			  // data bits
+				ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down
+				if(ps2_mouse_tx_byte[0]) 
+					ps2_mouse_parity <= !ps2_mouse_parity;
+			end
+
+			// transmission of parity
+			if(ps2_mouse_tx_state == 9)
+				ps2_mouse_data <= ps2_mouse_parity;
+
+			// transmission of stop bit
+			if(ps2_mouse_tx_state == 10)
+				ps2_mouse_data <= 1'b1;			// stop bit is 1
+
+			// advance state machine
+			if(ps2_mouse_tx_state < 11)
+				ps2_mouse_tx_state <= ps2_mouse_tx_state + 4'd1;
+			else	
+				ps2_mouse_tx_state <= 4'd0;
+		end
 	end
 end
-  
+
 // fifo to receive serial data from core to be forwarded to io controller
 
 // 16 byte fifo to store serial bytes
@@ -212,16 +286,16 @@
 
 // status[0] is reset signal from io controller and is thus used to flush
 // the fifo
-always @(posedge serial_strobe or posedge status[0]) begin
+always @(posedge serial_strobe or posedge status[0]) begin : serial_out
 	if(status[0] == 1) begin
 		serial_out_wptr <= 0;
 	end else begin 
 		serial_out_fifo[serial_out_wptr] <= serial_data;
-		serial_out_wptr <= serial_out_wptr + 1;
+		serial_out_wptr <= serial_out_wptr + 1'd1;
 	end
 end 
 
-always@(negedge spi_sck or posedge status[0]) begin
+always@(negedge spi_sck or posedge status[0]) begin : serial_in
 	if(status[0] == 1) begin
 		serial_out_rptr <= 0;
 	end else begin
@@ -228,105 +302,302 @@
 		if((byte_cnt != 0) && (cmd == 8'h1b)) begin
 			// read last bit -> advance read pointer
 			if((bit_cnt == 7) && !byte_cnt[0] && serial_out_data_available)
-				serial_out_rptr <= serial_out_rptr + 1;
+				serial_out_rptr <= serial_out_rptr + 1'd1;
 		end
 	end
 end
 
-// SPI receiver
-always@(posedge spi_sck or posedge SPI_SS_IO) begin
 
+// SPI bit and byte counters
+always@(posedge spi_sck or posedge SPI_SS_IO) begin : spi_counter
 	if(SPI_SS_IO == 1) begin
-	   bit_cnt <= 3'd0;
-	   byte_cnt <= 8'd0;
-		sd_ack <= 1'b0;
-		sd_dout_strobe <= 1'b0;
-		sd_din_strobe <= 1'b0;
+		bit_cnt <= 0;
+		byte_cnt <= 0;
 	end else begin
-		sd_dout_strobe <= 1'b0;
-		sd_din_strobe <= 1'b0;
-		
-		sbuf[6:0] <= { sbuf[5:0], SPI_MOSI };
-		bit_cnt <= bit_cnt + 3'd1;
-		if((bit_cnt == 7)&&(byte_cnt != 8'd255)) 
+		if((bit_cnt == 7)&&(~&byte_cnt)) 
 			byte_cnt <= byte_cnt + 8'd1;
 
-		// finished reading command byte
-      if(bit_cnt == 7) begin
-			if(byte_cnt == 0) begin
-				cmd <= { sbuf, SPI_MOSI};
-			
-				// fetch first byte when sectore FPGA->IO command has been seen
-				if({ sbuf, SPI_MOSI} == 8'h18)
-					sd_din_strobe <= 1'b1;
-					
-				if(({ sbuf, SPI_MOSI} == 8'h17) || ({ sbuf, SPI_MOSI} == 8'h18))
-					sd_ack <= 1'b1;
-					
-			end else begin
-			
+		bit_cnt <= bit_cnt + 1'd1;
+	end
+end
+
+// SPI transmitter FPGA -> IO
+reg [7:0] spi_byte_out;
+
+always@(negedge spi_sck or posedge SPI_SS_IO) begin : spi_byteout
+	if(SPI_SS_IO == 1) begin
+	   SPI_MISO <= 1'bZ;
+	end else begin
+		SPI_MISO <= spi_byte_out[~bit_cnt];
+	end
+end
+
+always@(posedge spi_sck or posedge SPI_SS_IO) begin : spi_transmitter
+	reg [31:0] sd_lba_r;
+	reg  [7:0] drive_sel_r;
+
+	if(SPI_SS_IO == 1) begin
+		spi_byte_out <= core_type;
+	end else begin
+		// read the command byte to choose the response
+		if(bit_cnt == 7) begin
+			if(!byte_cnt) cmd <= {sbuf, SPI_MOSI};
+
+			spi_byte_out <= 0;
+			case({(!byte_cnt) ? {sbuf, SPI_MOSI} : cmd})
+			// reading config string
+			8'h14: if (STRLEN == 0) spi_byte_out <= conf_chr; else
+			       if(byte_cnt < STRLEN) spi_byte_out <= conf_str[(STRLEN - byte_cnt - 1)<<3 +:8];
+
+			// reading sd card status
+			8'h16: if(byte_cnt == 0) begin
+					spi_byte_out <= sd_cmd;
+					sd_lba_r <= sd_lba;
+					drive_sel_r <= {7'b0, drive_sel};
+				end 
+				else if(byte_cnt == 1) spi_byte_out <= drive_sel_r;
+				else if(byte_cnt < 6) spi_byte_out <= sd_lba_r[(5-byte_cnt)<<3 +:8];
+
+			// reading sd card write data
+			8'h18: spi_byte_out <= sd_din;
+
+			8'h1b:
+				// send alternating flag byte and data
+				if(byte_cnt[0]) spi_byte_out <= serial_out_status;
+				else spi_byte_out <= serial_out_byte;
+
+			endcase
+		end
+	end
+end
+
+// SPI receiver IO -> FPGA
+
+reg       spi_receiver_strobe_r = 0;
+reg       spi_transfer_end_r = 1;
+reg [7:0] spi_byte_in;
+
+// Read at spi_sck clock domain, assemble bytes for transferring to clk_sys
+always@(posedge spi_sck or posedge SPI_SS_IO) begin : spi_receiver
+
+	if(SPI_SS_IO == 1) begin
+		spi_transfer_end_r <= 1;
+	end else begin
+		spi_transfer_end_r <= 0;
+
+		if(bit_cnt != 7)
+			sbuf[6:0] <= { sbuf[5:0], SPI_MOSI };
+
+		// finished reading a byte, prepare to transfer to clk_sys
+		if(bit_cnt == 7) begin
+			spi_byte_in <= { sbuf, SPI_MOSI};
+			spi_receiver_strobe_r <= ~spi_receiver_strobe_r;
+		end
+	end
+end
+
+// Process bytes from SPI at the clk_sys domain
+always @(posedge clk_sys) begin : cmd_block
+
+	reg       spi_receiver_strobe;
+	reg       spi_transfer_end;
+	reg       spi_receiver_strobeD;
+	reg       spi_transfer_endD;
+	reg [7:0] acmd;
+	reg [7:0] abyte_cnt;   // counts bytes
+
+	reg [7:0] mouse_flags_r;
+	reg [7:0] mouse_x_r;
+	reg [7:0] mouse_y_r;
+
+	reg       key_pressed_r;
+	reg       key_extended_r;
+
+	//synchronize between SPI and sys clock domains
+	spi_receiver_strobeD <= spi_receiver_strobe_r;
+	spi_receiver_strobe <= spi_receiver_strobeD;
+	spi_transfer_endD	<= spi_transfer_end_r;
+	spi_transfer_end	<= spi_transfer_endD;
+
+	key_strobe <= 0;
+	mouse_strobe <= 0;
+
+	if (spi_transfer_end) begin
+		abyte_cnt <= 8'd0;
+	end else if (spi_receiver_strobeD ^ spi_receiver_strobe) begin
+
+		if(~&abyte_cnt) 
+			abyte_cnt <= abyte_cnt + 8'd1;
+
+		if(abyte_cnt == 0) begin
+			acmd <= spi_byte_in;
+		end else begin
+			case(acmd)
 				// buttons and switches
-				if(cmd == 8'h01)
-					but_sw <= { sbuf[2:0], SPI_MOSI }; 
+				8'h01: but_sw <= spi_byte_in;
+				8'h60: if (abyte_cnt < 5) joystick_0[(abyte_cnt-1)<<3 +:8] <= spi_byte_in;
+				8'h61: if (abyte_cnt < 5) joystick_1[(abyte_cnt-1)<<3 +:8] <= spi_byte_in;
+				8'h62: if (abyte_cnt < 5) joystick_2[(abyte_cnt-1)<<3 +:8] <= spi_byte_in;
+				8'h63: if (abyte_cnt < 5) joystick_3[(abyte_cnt-1)<<3 +:8] <= spi_byte_in;
+				8'h64: if (abyte_cnt < 5) joystick_4[(abyte_cnt-1)<<3 +:8] <= spi_byte_in;
+				8'h70,8'h71: begin
+					// store incoming ps2 mouse bytes
+					if (abyte_cnt < 4) begin
+						ps2_mouse_fifo[ps2_mouse_wptr] <= spi_byte_in;
+						ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1;
+					end
 
-				if(cmd == 8'h02)
-					joystick_0 <= { sbuf[4:0], SPI_MOSI };
-				 
-				if(cmd == 8'h03)
-					joystick_1 <= { sbuf[4:0], SPI_MOSI };
-				 
-				if(cmd == 8'h05) begin
-					// store incoming keyboard bytes in 
-					ps2_fifo[ps2_wptr] <= { sbuf, SPI_MOSI }; 
-					ps2_wptr <= ps2_wptr + 1;
+					if (abyte_cnt == 1) mouse_flags_r <= spi_byte_in;
+					else if (abyte_cnt == 2) mouse_x_r <= spi_byte_in;
+					else if (abyte_cnt == 3) mouse_y_r <= spi_byte_in;
+					else if (abyte_cnt == 4) begin
+						// flags: YOvfl, XOvfl, dy8, dx8, 1, mbtn, rbtn, lbtn
+						mouse_flags <= mouse_flags_r;
+						mouse_x <= { mouse_flags_r[4], mouse_x_r };
+						mouse_y <= { mouse_flags_r[5], mouse_y_r };
+						mouse_z <= spi_byte_in[3:0];
+						mouse_idx <= acmd[0];
+						mouse_strobe <= 1;
+					end
 				end
-				
-				if(cmd == 8'h15)
-					status <= { sbuf[6:0], SPI_MOSI };
-				
-				// send sector IO -> FPGA
-				if(cmd == 8'h17) begin
-					// flag that download begins
-					sd_dout <= { sbuf, SPI_MOSI};
-					sd_dout_strobe <= 1'b1;
+				8'h05: begin
+					// store incoming ps2 keyboard bytes 
+					ps2_kbd_fifo[ps2_kbd_wptr] <= spi_byte_in;
+					ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1;
+					if (abyte_cnt == 1) begin
+						key_extended_r <= 0;
+						key_pressed_r <= 1;
+					end
+					if (spi_byte_in == 8'he0) key_extended_r <= 1'b1;
+					else if (spi_byte_in == 8'hf0) key_pressed_r <= 1'b0;
+					else begin
+						key_extended <= key_extended_r && abyte_cnt != 1;
+						key_pressed <= key_pressed_r || abyte_cnt == 1;
+						key_code <= spi_byte_in;
+						key_strobe <= 1'b1;
+					end
 				end
-				
-				// send sector FPGA -> IO
-				if(cmd == 8'h18)
-					sd_din_strobe <= 1'b1;
-				
-				// send SD config IO -> FPGA
-				if(cmd == 8'h19) begin
-					// flag that download begins
-					sd_dout <= { sbuf, SPI_MOSI};
-					// sd card knows data is config if sd_dout_strobe is asserted
-					// with sd_ack still being inactive (low)
-					sd_dout_strobe <= 1'b1;
-				end
-				
+
 				// joystick analog
-				if(cmd == 8'h1a) begin
-					// first byte is joystick indes
-					if(byte_cnt == 1)
-						stick_idx <= { sbuf[1:0], SPI_MOSI };
-					else if(byte_cnt == 2) begin
+				8'h1a: begin
+					// first byte is joystick index
+					if(abyte_cnt == 1)
+						stick_idx <= spi_byte_in[2:0];
+					else if(abyte_cnt == 2) begin
 						// second byte is x axis
 						if(stick_idx == 0)
-							joystick_analog_0[15:8] <= { sbuf, SPI_MOSI };
+							joystick_analog_0[15:8] <= spi_byte_in;
 						else if(stick_idx == 1)
-							joystick_analog_1[15:8] <= { sbuf, SPI_MOSI };
-					end else if(byte_cnt == 3) begin
+							joystick_analog_1[15:8] <= spi_byte_in;
+					end else if(abyte_cnt == 3) begin
 						// third byte is y axis
 						if(stick_idx == 0)
-							joystick_analog_0[7:0] <= { sbuf, SPI_MOSI };
+							joystick_analog_0[7:0] <= spi_byte_in;
 						else if(stick_idx == 1)
-							joystick_analog_1[7:0] <= { sbuf, SPI_MOSI };
+							joystick_analog_1[7:0] <= spi_byte_in;
 					end
 				end
 
+				8'h15: status <= spi_byte_in;
+
+				// status, 64bit version
+				8'h1e: if(abyte_cnt<9) status[(abyte_cnt-1)<<3 +:8] <= spi_byte_in;
+
+				// core variant
+				8'h21: core_mod <= spi_byte_in[6:0];
+
+				// RTC
+				8'h22: if(abyte_cnt<9) rtc[(abyte_cnt-1)<<3 +:8] <= spi_byte_in;
+			endcase
+		end
+	end
+end
+
+
+// Process SD-card related bytes from SPI at the clk_sd domain
+always @(posedge clk_sd) begin : sd_block
+
+	reg       spi_receiver_strobe;
+	reg       spi_transfer_end;
+	reg       spi_receiver_strobeD;
+	reg       spi_transfer_endD;
+	reg [1:0] sd_wrD;
+	reg [7:0] acmd;
+	reg [7:0] abyte_cnt;   // counts bytes
+
+	//synchronize between SPI and sd clock domains
+	spi_receiver_strobeD <= spi_receiver_strobe_r;
+	spi_receiver_strobe <= spi_receiver_strobeD;
+	spi_transfer_endD	<= spi_transfer_end_r;
+	spi_transfer_end	<= spi_transfer_endD;
+
+	if(sd_dout_strobe) begin
+		sd_dout_strobe<= 0;
+		if(~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1;
+	end
+
+	sd_din_strobe<= 0;
+	sd_wrD <= sd_wr;
+	// fetch the first byte immediately after the write command seen
+	if ((~sd_wrD[0] & sd_wr[0]) || (~sd_wrD[1] & sd_wrD[1])) begin
+		sd_buff_addr <= 0;
+		sd_din_strobe <= 1;
+	end
+
+	img_mounted <= 0;
+
+	if (spi_transfer_end) begin
+		abyte_cnt <= 8'd0;
+		sd_ack <= 1'b0;
+		sd_ack_conf <= 1'b0;
+		sd_dout_strobe <= 1'b0;
+		sd_din_strobe <= 1'b0;
+		sd_buff_addr <= 0;
+	end else if (spi_receiver_strobeD ^ spi_receiver_strobe) begin
+
+		if(~&abyte_cnt) 
+			abyte_cnt <= abyte_cnt + 8'd1;
+
+		if(abyte_cnt == 0) begin
+			acmd <= spi_byte_in;
+
+			if(spi_byte_in == 8'h18) begin
+				sd_din_strobe <= 1'b1;
+				if(~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1;
 			end
+
+			if(spi_byte_in == 8'h19)
+				sd_ack_conf <= 1'b1;
+			if((spi_byte_in == 8'h17) || (spi_byte_in == 8'h18))
+				sd_ack <= 1'b1;
+
+		end else begin
+			case(acmd)
+
+				// send sector IO -> FPGA
+				8'h17,
+				// send SD config IO -> FPGA
+				8'h19: begin
+					// flag that download begins
+					sd_dout_strobe <= 1'b1;
+					sd_dout <= spi_byte_in;
+				end
+
+				// send sector FPGA -> IO
+				8'h18: begin
+					if(~&sd_buff_addr) begin
+						sd_din_strobe <= 1'b1;
+						sd_buff_addr <= sd_buff_addr + 1'b1;
+					end
+				end
+
+				8'h1c: img_mounted[spi_byte_in[0]] <= 1;
+
+				// send image info
+				8'h1d: if(abyte_cnt<5) img_size[(abyte_cnt-1)<<3 +:8] <= spi_byte_in;
+			endcase
 		end
 	end
 end
-   
+
 endmodule
Index: mist/video_pll_reconfig.cmp
===================================================================
--- mist/video_pll_reconfig.cmp	(revision 1315)
+++ mist/video_pll_reconfig.cmp	(revision 1316)
@@ -1,4 +1,4 @@
---Copyright (C) 1991-2013 Altera Corporation
+--Copyright (C) 1991-2014 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 
@@ -26,6 +26,9 @@
 		read_param		: IN STD_LOGIC ;
 		reconfig		: IN STD_LOGIC ;
 		reset		: IN STD_LOGIC ;
+		reset_rom_address		: IN STD_LOGIC  := '0';
+		rom_data_in		: IN STD_LOGIC  := '0';
+		write_from_rom		: IN STD_LOGIC  := '0';
 		write_param		: IN STD_LOGIC ;
 		busy		: OUT STD_LOGIC ;
 		data_out		: OUT STD_LOGIC_VECTOR (8 DOWNTO 0);
@@ -33,6 +36,8 @@
 		pll_configupdate		: OUT STD_LOGIC ;
 		pll_scanclk		: OUT STD_LOGIC ;
 		pll_scanclkena		: OUT STD_LOGIC ;
-		pll_scandata		: OUT STD_LOGIC 
+		pll_scandata		: OUT STD_LOGIC ;
+		rom_address_out		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+		write_rom_ena		: OUT STD_LOGIC 
 	);
 end component;
Index: mist/video_pll_reconfig.qip
===================================================================
--- mist/video_pll_reconfig.qip	(revision 1315)
+++ mist/video_pll_reconfig.qip	(revision 1316)
@@ -1,4 +1,4 @@
 set_global_assignment -name IP_TOOL_NAME "ALTPLL_RECONFIG"
-set_global_assignment -name IP_TOOL_VERSION "13.0"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
 set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "video_pll_reconfig.vhd"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "video_pll_reconfig.cmp"]
Index: mist/video_pll_reconfig.vhd
===================================================================
--- mist/video_pll_reconfig.vhd	(revision 1315)
+++ mist/video_pll_reconfig.vhd	(revision 1316)
@@ -14,11 +14,11 @@
 -- ************************************************************
 -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 --
--- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
+-- 13.1.4 Build 182 03/12/2014 Patches 4.26 SJ Web Edition
 -- ************************************************************
 
 
---Copyright (C) 1991-2013 Altera Corporation
+--Copyright (C) 1991-2014 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 
@@ -33,8 +33,8 @@
 --applicable agreement for further details.
 
 
---altpll_reconfig CBX_AUTO_BLACKBOX="ALL" device_family="Cyclone III" init_from_rom="NO" scan_init_file="./ntsc.mif" busy clock counter_param counter_type data_in data_out pll_areset pll_areset_in pll_configupdate pll_scanclk pll_scanclkena pll_scandata pll_scandataout pll_scandone read_param reconfig reset write_param
---VERSION_BEGIN 13.0 cbx_altpll_reconfig 2013:06:12:18:04:00:SJ cbx_altsyncram 2013:06:12:18:04:00:SJ cbx_cycloneii 2013:06:12:18:04:00:SJ cbx_lpm_add_sub 2013:06:12:18:04:00:SJ cbx_lpm_compare 2013:06:12:18:04:00:SJ cbx_lpm_counter 2013:06:12:18:04:00:SJ cbx_lpm_decode 2013:06:12:18:04:00:SJ cbx_lpm_mux 2013:06:12:18:04:00:SJ cbx_mgl 2013:06:12:18:04:42:SJ cbx_stratix 2013:06:12:18:04:00:SJ cbx_stratixii 2013:06:12:18:04:00:SJ cbx_stratixiii 2013:06:12:18:04:00:SJ cbx_stratixv 2013:06:12:18:04:00:SJ cbx_util_mgl 2013:06:12:18:04:00:SJ  VERSION_END
+--altpll_reconfig CBX_AUTO_BLACKBOX="ALL" device_family="Cyclone III" init_from_rom="NO" scan_init_file="./ntsc.mif" busy clock counter_param counter_type data_in data_out pll_areset pll_areset_in pll_configupdate pll_scanclk pll_scanclkena pll_scandata pll_scandataout pll_scandone read_param reconfig reset reset_rom_address rom_address_out rom_data_in write_from_rom write_param write_rom_ena
+--VERSION_BEGIN 13.1 cbx_altpll_reconfig 2014:03:12:18:15:29:SJ cbx_altsyncram 2014:03:12:18:15:29:SJ cbx_cycloneii 2014:03:12:18:15:29:SJ cbx_lpm_add_sub 2014:03:12:18:15:29:SJ cbx_lpm_compare 2014:03:12:18:15:29:SJ cbx_lpm_counter 2014:03:12:18:15:29:SJ cbx_lpm_decode 2014:03:12:18:15:29:SJ cbx_lpm_mux 2014:03:12:18:15:30:SJ cbx_mgl 2014:03:12:21:10:00:SJ cbx_stratix 2014:03:12:18:15:31:SJ cbx_stratixii 2014:03:12:18:15:31:SJ cbx_stratixiii 2014:03:12:18:15:32:SJ cbx_stratixv 2014:03:12:18:15:32:SJ cbx_util_mgl 2014:03:12:18:15:30:SJ  VERSION_END
 
  LIBRARY altera_mf;
  USE altera_mf.all;
@@ -45,11 +45,11 @@
  LIBRARY lpm;
  USE lpm.all;
 
---synthesis_resources = altsyncram 1 lpm_add_sub 2 lpm_compare 1 lpm_counter 7 lpm_decode 1 lut 3 reg 80 
+--synthesis_resources = altsyncram 1 lpm_add_sub 2 lpm_compare 1 lpm_counter 8 lpm_decode 1 lut 3 reg 102 
  LIBRARY ieee;
  USE ieee.std_logic_1164.all;
 
- ENTITY  video_pll_reconfig_pllrcfg_6bu IS 
+ ENTITY  video_pll_reconfig_pllrcfg_op51 IS 
 	 PORT 
 	 ( 
 		 busy	:	OUT  STD_LOGIC;
@@ -69,11 +69,16 @@
 		 read_param	:	IN  STD_LOGIC := '0';
 		 reconfig	:	IN  STD_LOGIC := '0';
 		 reset	:	IN  STD_LOGIC;
-		 write_param	:	IN  STD_LOGIC := '0'
+		 reset_rom_address	:	IN  STD_LOGIC := '0';
+		 rom_address_out	:	OUT  STD_LOGIC_VECTOR (7 DOWNTO 0);
+		 rom_data_in	:	IN  STD_LOGIC := '0';
+		 write_from_rom	:	IN  STD_LOGIC := '0';
+		 write_param	:	IN  STD_LOGIC := '0';
+		 write_rom_ena	:	OUT  STD_LOGIC
 	 ); 
- END video_pll_reconfig_pllrcfg_6bu;
+ END video_pll_reconfig_pllrcfg_op51;
 
- ARCHITECTURE RTL OF video_pll_reconfig_pllrcfg_6bu IS
+ ARCHITECTURE RTL OF video_pll_reconfig_pllrcfg_op51 IS
 
 	 ATTRIBUTE synthesis_clearbox : natural;
 	 ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 2;
@@ -85,6 +90,16 @@
 	 SIGNAL  wire_le_comb10_combout	:	STD_LOGIC;
 	 SIGNAL  wire_le_comb8_combout	:	STD_LOGIC;
 	 SIGNAL  wire_le_comb9_combout	:	STD_LOGIC;
+	 SIGNAL	 addr_from_rom	:	STD_LOGIC_VECTOR(7 DOWNTO 0)
+	 -- synopsys translate_off
+	  := (OTHERS => '0')
+	 -- synopsys translate_on
+	 ;
+	 SIGNAL	 addr_from_rom2	:	STD_LOGIC_VECTOR(7 DOWNTO 0)
+	 -- synopsys translate_off
+	  := (OTHERS => '0')
+	 -- synopsys translate_on
+	 ;
 	 SIGNAL	 areset_init_state_1	:	STD_LOGIC
 	 -- synopsys translate_off
 	  := '0'
@@ -115,7 +130,7 @@
 	  := '0'
 	 -- synopsys translate_on
 	 ;
-	 SIGNAL  wire_C1_ena_state_w_lg_q1766w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_C1_ena_state_w_lg_q1786w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
 	 SIGNAL	 C2_data_state	:	STD_LOGIC
 	 -- synopsys translate_off
 	  := '0'
@@ -126,7 +141,7 @@
 	  := '0'
 	 -- synopsys translate_on
 	 ;
-	 SIGNAL  wire_C2_ena_state_w_lg_q1767w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_C2_ena_state_w_lg_q1787w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
 	 SIGNAL	 C3_data_state	:	STD_LOGIC
 	 -- synopsys translate_off
 	  := '0'
@@ -157,7 +172,7 @@
 	  := '0'
 	 -- synopsys translate_on
 	 ;
-	 SIGNAL  wire_configupdate3_state_w_lg_q1842w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_configupdate3_state_w_lg_q1879w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
 	 SIGNAL	 configupdate_state	:	STD_LOGIC
 	 -- synopsys translate_off
 	  := '0'
@@ -180,15 +195,15 @@
 	 ;
 	 ATTRIBUTE ALTERA_ATTRIBUTE OF idle_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
 
-	 SIGNAL  wire_idle_state_w_lg_w_lg_w_lg_w_lg_q1731w1732w1733w1734w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
-	 SIGNAL  wire_idle_state_w_lg_w_lg_w_lg_q1731w1732w1733w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
-	 SIGNAL  wire_idle_state_w_lg_w_lg_q1731w1732w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
-	 SIGNAL  wire_idle_state_w_lg_q1731w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_idle_state_w_lg_w_lg_w_lg_w_lg_q1743w1744w1745w1746w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_idle_state_w_lg_w_lg_w_lg_q1743w1744w1745w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_idle_state_w_lg_w_lg_q1743w1744w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_idle_state_w_lg_q1743w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
 	 SIGNAL  wire_idle_state_w_lg_q1672w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
-	 SIGNAL  wire_idle_state_w1735w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
-	 SIGNAL  wire_idle_state_w_lg_w1735w1736w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
-	 SIGNAL  wire_idle_state_w_lg_w_lg_w1735w1736w1737w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
-	 SIGNAL  wire_idle_state_w_lg_w_lg_w_lg_w1735w1736w1737w1738w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_idle_state_w1747w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_idle_state_w_lg_w1747w1748w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_idle_state_w_lg_w_lg_w1747w1748w1749w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_idle_state_w_lg_w_lg_w_lg_w1747w1748w1749w1750w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
 	 SIGNAL	 nominal_data0	:	STD_LOGIC
 	 -- synopsys translate_off
 	  := '0'
@@ -286,7 +301,7 @@
 	 ;
 	 ATTRIBUTE ALTERA_ATTRIBUTE OF read_data_nominal_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
 
-	 SIGNAL  wire_read_data_nominal_state_w_lg_q1752w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_read_data_nominal_state_w_lg_q1772w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
 	 SIGNAL  wire_read_data_nominal_state_w_lg_q1686w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
 	 SIGNAL	 read_data_state	:	STD_LOGIC
 	 -- synopsys translate_off
@@ -295,7 +310,7 @@
 	 ;
 	 ATTRIBUTE ALTERA_ATTRIBUTE OF read_data_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
 
-	 SIGNAL  wire_read_data_state_w_lg_q1745w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_read_data_state_w_lg_q1765w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
 	 SIGNAL  wire_read_data_state_w_lg_q1678w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
 	 SIGNAL	 read_first_nominal_state	:	STD_LOGIC
 	 -- synopsys translate_off
@@ -304,7 +319,7 @@
 	 ;
 	 ATTRIBUTE ALTERA_ATTRIBUTE OF read_first_nominal_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
 
-	 SIGNAL  wire_read_first_nominal_state_w_lg_q1753w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_read_first_nominal_state_w_lg_q1773w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
 	 SIGNAL  wire_read_first_nominal_state_w_lg_q1684w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
 	 SIGNAL	 read_first_state	:	STD_LOGIC
 	 -- synopsys translate_off
@@ -313,8 +328,11 @@
 	 ;
 	 ATTRIBUTE ALTERA_ATTRIBUTE OF read_first_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
 
-	 SIGNAL  wire_read_first_state_w_lg_q1746w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_read_first_state_w_lg_q1766w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
 	 SIGNAL  wire_read_first_state_w_lg_q1676w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_read_first_state_w_lg_w_lg_w_lg_q1894w1895w1896w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_read_first_state_w_lg_w_lg_q1894w1895w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_read_first_state_w_lg_q1894w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
 	 SIGNAL	 read_init_nominal_state	:	STD_LOGIC
 	 -- synopsys translate_off
 	  := '0'
@@ -331,7 +349,7 @@
 	 ATTRIBUTE ALTERA_ATTRIBUTE OF read_init_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
 
 	 SIGNAL  wire_read_init_state_w_lg_q1674w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
-	 SIGNAL  wire_read_init_state_w_lg_q1848w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_read_init_state_w_lg_q1891w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
 	 SIGNAL	 read_last_nominal_state	:	STD_LOGIC
 	 -- synopsys translate_off
 	  := '0'
@@ -339,7 +357,7 @@
 	 ;
 	 ATTRIBUTE ALTERA_ATTRIBUTE OF read_last_nominal_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
 
-	 SIGNAL  wire_read_last_nominal_state_w_lg_q1865w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_read_last_nominal_state_w_lg_q1917w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
 	 SIGNAL  wire_read_last_nominal_state_w_lg_q1688w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
 	 SIGNAL	 read_last_state	:	STD_LOGIC
 	 -- synopsys translate_off
@@ -372,7 +390,7 @@
 	 ;
 	 ATTRIBUTE ALTERA_ATTRIBUTE OF reconfig_post_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
 
-	 SIGNAL  wire_reconfig_post_state_w_lg_q1829w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_reconfig_post_state_w_lg_q1849w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
 	 SIGNAL  wire_reconfig_post_state_w_lg_q1706w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
 	 SIGNAL	 reconfig_seq_data_state	:	STD_LOGIC
 	 -- synopsys translate_off
@@ -389,8 +407,8 @@
 	 ;
 	 ATTRIBUTE ALTERA_ATTRIBUTE OF reconfig_seq_ena_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
 
-	 SIGNAL  wire_reconfig_seq_ena_state_w_lg_q1856w	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
-	 SIGNAL  wire_reconfig_seq_ena_state_w_lg_q1857w	:	STD_LOGIC_VECTOR (5 DOWNTO 0);
+	 SIGNAL  wire_reconfig_seq_ena_state_w_lg_q1903w	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  wire_reconfig_seq_ena_state_w_lg_q1904w	:	STD_LOGIC_VECTOR (5 DOWNTO 0);
 	 SIGNAL  wire_reconfig_seq_ena_state_w_lg_q1702w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
 	 SIGNAL	 reconfig_wait_state	:	STD_LOGIC
 	 -- synopsys translate_off
@@ -399,7 +417,7 @@
 	 ;
 	 ATTRIBUTE ALTERA_ATTRIBUTE OF reconfig_wait_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
 
-	 SIGNAL  wire_reconfig_wait_state_w_lg_q1833w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_reconfig_wait_state_w_lg_q1853w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
 	 SIGNAL  wire_reconfig_wait_state_w_lg_q1708w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
 	 SIGNAL	 reset_state	:	STD_LOGIC
 	 -- synopsys translate_off
@@ -409,6 +427,69 @@
 	 ATTRIBUTE ALTERA_ATTRIBUTE OF reset_state : SIGNAL IS "POWER_UP_LEVEL=HIGH";
 
 	 SIGNAL  wire_reset_state_w_lg_q1671w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 rom_data_state	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF rom_data_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
+
+	 SIGNAL  wire_rom_data_state_w_lg_q1868w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_rom_data_state_w_lg_q1889w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_rom_data_state_w_lg_w_lg_q1897w1933w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_rom_data_state_w_lg_q1716w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_rom_data_state_w_lg_w_lg_q1897w1898w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_rom_data_state_w_lg_w_lg_q1929w1930w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_rom_data_state_w_lg_q1897w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_rom_data_state_w_lg_q1929w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 rom_first_state	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF rom_first_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
+
+	 SIGNAL  wire_rom_first_state_w_lg_w_lg_w_lg_w_lg_q1943w1944w1945w1947w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_rom_first_state_w_lg_q1712w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_rom_first_state_w_lg_w_lg_w_lg_q1943w1944w1945w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_rom_first_state_w_lg_w_lg_q1943w1944w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_rom_first_state_w_lg_w_lg_q1885w1886w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_rom_first_state_w_lg_q1943w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_rom_first_state_w_lg_q1885w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 rom_init_state	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF rom_init_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
+
+	 SIGNAL  wire_rom_init_state_w_lg_q1710w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 rom_last_state	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF rom_last_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
+
+	 SIGNAL  wire_rom_last_state_w_lg_q1753w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_rom_last_state_w_lg_q1720w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 rom_second_last_state	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF rom_second_last_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
+
+	 SIGNAL  wire_rom_second_last_state_w_lg_q1754w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_rom_second_last_state_w_lg_q1718w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 rom_second_state	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF rom_second_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
+
+	 SIGNAL  wire_rom_second_state_w_lg_q1714w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
 	 SIGNAL	 shift_reg0	:	STD_LOGIC
 	 -- synopsys translate_off
 	  := '0'
@@ -543,7 +624,7 @@
 	 ;
 	 ATTRIBUTE ALTERA_ATTRIBUTE OF write_data_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
 
-	 SIGNAL  wire_write_data_state_w_lg_q1726w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_write_data_state_w_lg_q1738w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
 	 SIGNAL  wire_write_data_state_w_lg_q1692w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
 	 SIGNAL	 write_init_nominal_state	:	STD_LOGIC
 	 -- synopsys translate_off
@@ -561,7 +642,7 @@
 	 ATTRIBUTE ALTERA_ATTRIBUTE OF write_init_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
 
 	 SIGNAL  wire_write_init_state_w_lg_q1690w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
-	 SIGNAL  wire_write_init_state_w_lg_q1853w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_write_init_state_w_lg_q1900w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
 	 SIGNAL	 write_nominal_state	:	STD_LOGIC
 	 -- synopsys translate_off
 	  := '0'
@@ -569,7 +650,7 @@
 	 ;
 	 ATTRIBUTE ALTERA_ATTRIBUTE OF write_nominal_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
 
-	 SIGNAL  wire_write_nominal_state_w_lg_q1725w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_write_nominal_state_w_lg_q1737w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
 	 SIGNAL  wire_write_nominal_state_w_lg_q1696w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
 	 SIGNAL  wire_add_sub5_w_lg_w_result_range214w215w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
 	 SIGNAL  wire_add_sub5_w_lg_w_result_range221w222w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
@@ -601,22 +682,28 @@
 	 SIGNAL  wire_cntr1_q	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
 	 SIGNAL  wire_cntr12_q	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
 	 SIGNAL  wire_cntr13_q	:	STD_LOGIC_VECTOR (5 DOWNTO 0);
-	 SIGNAL  wire_cntr14_q	:	STD_LOGIC_VECTOR (4 DOWNTO 0);
-	 SIGNAL  wire_cntr15_q	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  wire_cntr14_q	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  wire_cntr15_q	:	STD_LOGIC_VECTOR (4 DOWNTO 0);
+	 SIGNAL  wire_cntr16_q	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
 	 SIGNAL  wire_cntr2_q	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
 	 SIGNAL  wire_cntr3_q	:	STD_LOGIC_VECTOR (4 DOWNTO 0);
 	 SIGNAL  wire_decode11_eq	:	STD_LOGIC_VECTOR (4 DOWNTO 0);
-	 SIGNAL  wire_w_lg_addr_counter_out1880w	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
-	 SIGNAL  wire_w_lg_addr_decoder_out1854w	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
-	 SIGNAL  wire_w_lg_c0_wire1808w	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
-	 SIGNAL  wire_w_lg_c1_wire1806w	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
-	 SIGNAL  wire_w_lg_c2_wire1804w	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
-	 SIGNAL  wire_w_lg_c3_wire1802w	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
-	 SIGNAL  wire_w_lg_c4_wire1800w	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
-	 SIGNAL  wire_w_lg_read_addr_counter_out1879w	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
-	 SIGNAL  wire_w_lg_read_addr_decoder_out1849w	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
-	 SIGNAL  wire_w_lg_reconfig_addr_counter_out1877w	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
-	 SIGNAL  wire_w_lg_rotate_addr_counter_out1878w	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  wire_w_lg_w_lg_read_addr_counter_out1934w1935w	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  wire_w_lg_w_lg_rom_width_counter_enable1931w1932w	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  wire_w_lg_addr_counter_out1938w	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  wire_w_lg_addr_decoder_out1901w	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  wire_w_lg_c0_wire1828w	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  wire_w_lg_c1_wire1826w	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  wire_w_lg_c2_wire1824w	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  wire_w_lg_c3_wire1822w	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  wire_w_lg_c4_wire1820w	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  wire_w_lg_read_addr_counter_out1887w	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  wire_w_lg_read_addr_counter_out1934w	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  wire_w_lg_read_addr_decoder_out1893w	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  wire_w_lg_reconfig_addr_counter_out1936w	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  wire_w_lg_rom_data_in1946w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_rom_width_counter_enable1931w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_rotate_addr_counter_out1937w	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
 	 SIGNAL  wire_w_lg_shift_reg_load_enable187w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
 	 SIGNAL  wire_w_lg_shift_reg_load_enable179w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
 	 SIGNAL  wire_w_lg_shift_reg_load_enable171w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
@@ -626,21 +713,25 @@
 	 SIGNAL  wire_w_lg_shift_reg_load_enable139w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
 	 SIGNAL  wire_w_lg_shift_reg_load_enable131w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
 	 SIGNAL  wire_w_lg_shift_reg_load_enable123w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_shift_reg_serial_out1948w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
 	 SIGNAL  wire_w_lg_w_counter_param_latch_range294w379w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
 	 SIGNAL  wire_w_lg_w_counter_type_latch_range284w710w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
-	 SIGNAL  wire_w_lg_dummy_scandataout1873w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
-	 SIGNAL  wire_w_lg_pll_scandone1875w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_dummy_scandataout1925w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_pll_scandone1927w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_read_addr_counter_done1867w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
 	 SIGNAL  wire_w_lg_read_nominal_out216w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
-	 SIGNAL  wire_w_lg_read_param1730w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
-	 SIGNAL  wire_w_lg_reconfig1728w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
-	 SIGNAL  wire_w_lg_reconfig_done1832w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
-	 SIGNAL  wire_w_lg_reconfig_post_done1828w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
-	 SIGNAL  wire_w_lg_reconfig_width_counter_done1825w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_read_param1742w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_reconfig1740w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_reconfig_done1852w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_reconfig_post_done1848w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_reconfig_width_counter_done1845w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
 	 SIGNAL  wire_w_lg_reset1w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
-	 SIGNAL  wire_w_lg_rotate_width_counter_done1776w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
-	 SIGNAL  wire_w_lg_width_counter_done1744w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
-	 SIGNAL  wire_w_lg_write_from_rom1727w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
-	 SIGNAL  wire_w_lg_write_param1729w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_reset_rom_address1752w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_rom_width_counter_done1888w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_rotate_width_counter_done1796w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_width_counter_done1764w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_write_from_rom1739w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_write_param1741w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
 	 SIGNAL  wire_w_lg_w_counter_param_latch_range296w297w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
 	 SIGNAL  wire_w_lg_w_counter_type_latch_range286w530w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
 	 SIGNAL  wire_w_lg_w_lg_w_lg_w1329w1392w1452w1516w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
@@ -671,7 +762,7 @@
 	 SIGNAL  wire_w_lg_w_lg_shift_reg_load_enable60w61w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
 	 SIGNAL  wire_w_lg_w_lg_w423w570w637w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
 	 SIGNAL  wire_w_lg_w_lg_w571w672w784w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
-	 SIGNAL  wire_w_lg_dummy_scandataout1874w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_dummy_scandataout1926w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
 	 SIGNAL  wire_w_lg_shift_reg_load_enable60w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
 	 SIGNAL  wire_w_lg_w301w378w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
 	 SIGNAL  wire_w_lg_w381w495w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
@@ -688,6 +779,7 @@
 	 SIGNAL  c2_wire :	STD_LOGIC_VECTOR (7 DOWNTO 0);
 	 SIGNAL  c3_wire :	STD_LOGIC_VECTOR (7 DOWNTO 0);
 	 SIGNAL  c4_wire :	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  const_scan_chain_size :	STD_LOGIC_VECTOR (7 DOWNTO 0);
 	 SIGNAL  counter_param_latch :	STD_LOGIC_VECTOR (2 DOWNTO 0);
 	 SIGNAL  counter_type_latch :	STD_LOGIC_VECTOR (3 DOWNTO 0);
 	 SIGNAL  cuda_combout_wire :	STD_LOGIC_VECTOR (2 DOWNTO 0);
@@ -695,6 +787,7 @@
 	 SIGNAL  encode_out :	STD_LOGIC_VECTOR (2 DOWNTO 0);
 	 SIGNAL  input_latch_enable :	STD_LOGIC;
 	 SIGNAL  power_up :	STD_LOGIC;
+	 SIGNAL  read_addr_counter_done :	STD_LOGIC;
 	 SIGNAL  read_addr_counter_enable :	STD_LOGIC;
 	 SIGNAL  read_addr_counter_out :	STD_LOGIC_VECTOR (7 DOWNTO 0);
 	 SIGNAL  read_addr_counter_sload :	STD_LOGIC;
@@ -711,6 +804,10 @@
 	 SIGNAL  reconfig_width_counter_enable :	STD_LOGIC;
 	 SIGNAL  reconfig_width_counter_sload :	STD_LOGIC;
 	 SIGNAL  reconfig_width_counter_sload_value :	STD_LOGIC_VECTOR (5 DOWNTO 0);
+	 SIGNAL  rom_width_counter_done :	STD_LOGIC;
+	 SIGNAL  rom_width_counter_enable :	STD_LOGIC;
+	 SIGNAL  rom_width_counter_sload :	STD_LOGIC;
+	 SIGNAL  rom_width_counter_sload_value :	STD_LOGIC_VECTOR (7 DOWNTO 0);
 	 SIGNAL  rotate_addr_counter_enable :	STD_LOGIC;
 	 SIGNAL  rotate_addr_counter_out :	STD_LOGIC_VECTOR (7 DOWNTO 0);
 	 SIGNAL  rotate_addr_counter_sload :	STD_LOGIC;
@@ -794,7 +891,6 @@
 	 SIGNAL  width_counter_sload_value :	STD_LOGIC_VECTOR (4 DOWNTO 0);
 	 SIGNAL  width_decoder_out :	STD_LOGIC_VECTOR (4 DOWNTO 0);
 	 SIGNAL  width_decoder_select :	STD_LOGIC_VECTOR (7 DOWNTO 0);
-	 SIGNAL  write_from_rom	:	STD_LOGIC;
 	 SIGNAL  wire_w_counter_param_latch_range294w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
 	 SIGNAL  wire_w_counter_param_latch_range296w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
 	 SIGNAL  wire_w_counter_type_latch_range284w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
@@ -808,11 +904,11 @@
 	 SIGNAL  wire_w_data_in_range138w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
 	 SIGNAL  wire_w_data_in_range130w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
 	 SIGNAL  wire_w_data_in_range122w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
-	 SIGNAL  wire_w_rotate_decoder_wires_range1807w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
-	 SIGNAL  wire_w_rotate_decoder_wires_range1805w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
-	 SIGNAL  wire_w_rotate_decoder_wires_range1803w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
-	 SIGNAL  wire_w_rotate_decoder_wires_range1801w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
-	 SIGNAL  wire_w_rotate_decoder_wires_range1799w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_rotate_decoder_wires_range1827w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_rotate_decoder_wires_range1825w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_rotate_decoder_wires_range1823w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_rotate_decoder_wires_range1821w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_rotate_decoder_wires_range1819w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
 	 SIGNAL  wire_w_shift_reg_width_select_range261w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
 	 SIGNAL  wire_w_shift_reg_width_select_range263w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
 	 SIGNAL  wire_w_shift_reg_width_select_range266w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
@@ -1022,38 +1118,49 @@
 
 	wire_gnd <= '0';
 	loop0 : FOR i IN 0 TO 7 GENERATE 
-		wire_w_lg_addr_counter_out1880w(i) <= addr_counter_out(i) AND addr_counter_enable;
+		wire_w_lg_w_lg_read_addr_counter_out1934w1935w(i) <= wire_w_lg_read_addr_counter_out1934w(i) AND wire_rom_data_state_w_lg_w_lg_q1897w1933w(0);
 	END GENERATE loop0;
 	loop1 : FOR i IN 0 TO 7 GENERATE 
-		wire_w_lg_addr_decoder_out1854w(i) <= addr_decoder_out(i) AND wire_write_init_state_w_lg_q1853w(0);
+		wire_w_lg_w_lg_rom_width_counter_enable1931w1932w(i) <= wire_w_lg_rom_width_counter_enable1931w(0) AND addr_from_rom2(i);
 	END GENERATE loop1;
 	loop2 : FOR i IN 0 TO 7 GENERATE 
-		wire_w_lg_c0_wire1808w(i) <= c0_wire(i) AND wire_w_rotate_decoder_wires_range1807w(0);
+		wire_w_lg_addr_counter_out1938w(i) <= addr_counter_out(i) AND addr_counter_enable;
 	END GENERATE loop2;
 	loop3 : FOR i IN 0 TO 7 GENERATE 
-		wire_w_lg_c1_wire1806w(i) <= c1_wire(i) AND wire_w_rotate_decoder_wires_range1805w(0);
+		wire_w_lg_addr_decoder_out1901w(i) <= addr_decoder_out(i) AND wire_write_init_state_w_lg_q1900w(0);
 	END GENERATE loop3;
 	loop4 : FOR i IN 0 TO 7 GENERATE 
-		wire_w_lg_c2_wire1804w(i) <= c2_wire(i) AND wire_w_rotate_decoder_wires_range1803w(0);
+		wire_w_lg_c0_wire1828w(i) <= c0_wire(i) AND wire_w_rotate_decoder_wires_range1827w(0);
 	END GENERATE loop4;
 	loop5 : FOR i IN 0 TO 7 GENERATE 
-		wire_w_lg_c3_wire1802w(i) <= c3_wire(i) AND wire_w_rotate_decoder_wires_range1801w(0);
+		wire_w_lg_c1_wire1826w(i) <= c1_wire(i) AND wire_w_rotate_decoder_wires_range1825w(0);
 	END GENERATE loop5;
 	loop6 : FOR i IN 0 TO 7 GENERATE 
-		wire_w_lg_c4_wire1800w(i) <= c4_wire(i) AND wire_w_rotate_decoder_wires_range1799w(0);
+		wire_w_lg_c2_wire1824w(i) <= c2_wire(i) AND wire_w_rotate_decoder_wires_range1823w(0);
 	END GENERATE loop6;
 	loop7 : FOR i IN 0 TO 7 GENERATE 
-		wire_w_lg_read_addr_counter_out1879w(i) <= read_addr_counter_out(i) AND read_addr_counter_enable;
+		wire_w_lg_c3_wire1822w(i) <= c3_wire(i) AND wire_w_rotate_decoder_wires_range1821w(0);
 	END GENERATE loop7;
 	loop8 : FOR i IN 0 TO 7 GENERATE 
-		wire_w_lg_read_addr_decoder_out1849w(i) <= read_addr_decoder_out(i) AND wire_read_init_state_w_lg_q1848w(0);
+		wire_w_lg_c4_wire1820w(i) <= c4_wire(i) AND wire_w_rotate_decoder_wires_range1819w(0);
 	END GENERATE loop8;
 	loop9 : FOR i IN 0 TO 7 GENERATE 
-		wire_w_lg_reconfig_addr_counter_out1877w(i) <= reconfig_addr_counter_out(i) AND reconfig_addr_counter_enable;
+		wire_w_lg_read_addr_counter_out1887w(i) <= read_addr_counter_out(i) AND wire_rom_first_state_w_lg_w_lg_q1885w1886w(0);
 	END GENERATE loop9;
 	loop10 : FOR i IN 0 TO 7 GENERATE 
-		wire_w_lg_rotate_addr_counter_out1878w(i) <= rotate_addr_counter_out(i) AND rotate_addr_counter_enable;
+		wire_w_lg_read_addr_counter_out1934w(i) <= read_addr_counter_out(i) AND read_addr_counter_enable;
 	END GENERATE loop10;
+	loop11 : FOR i IN 0 TO 7 GENERATE 
+		wire_w_lg_read_addr_decoder_out1893w(i) <= read_addr_decoder_out(i) AND wire_read_init_state_w_lg_q1891w(0);
+	END GENERATE loop11;
+	loop12 : FOR i IN 0 TO 7 GENERATE 
+		wire_w_lg_reconfig_addr_counter_out1936w(i) <= reconfig_addr_counter_out(i) AND reconfig_addr_counter_enable;
+	END GENERATE loop12;
+	wire_w_lg_rom_data_in1946w(0) <= rom_data_in AND wire_rom_first_state_w_lg_w_lg_w_lg_q1943w1944w1945w(0);
+	wire_w_lg_rom_width_counter_enable1931w(0) <= rom_width_counter_enable AND wire_rom_data_state_w_lg_w_lg_q1929w1930w(0);
+	loop13 : FOR i IN 0 TO 7 GENERATE 
+		wire_w_lg_rotate_addr_counter_out1937w(i) <= rotate_addr_counter_out(i) AND rotate_addr_counter_enable;
+	END GENERATE loop13;
 	wire_w_lg_shift_reg_load_enable187w(0) <= shift_reg_load_enable AND wire_w_data_in_range186w(0);
 	wire_w_lg_shift_reg_load_enable179w(0) <= shift_reg_load_enable AND wire_w_data_in_range178w(0);
 	wire_w_lg_shift_reg_load_enable171w(0) <= shift_reg_load_enable AND wire_w_data_in_range170w(0);
@@ -1063,21 +1170,25 @@
 	wire_w_lg_shift_reg_load_enable139w(0) <= shift_reg_load_enable AND wire_w_data_in_range138w(0);
 	wire_w_lg_shift_reg_load_enable131w(0) <= shift_reg_load_enable AND wire_w_data_in_range130w(0);
 	wire_w_lg_shift_reg_load_enable123w(0) <= shift_reg_load_enable AND wire_w_data_in_range122w(0);
+	wire_w_lg_shift_reg_serial_out1948w(0) <= shift_reg_serial_out AND wire_rom_first_state_w_lg_w_lg_w_lg_w_lg_q1943w1944w1945w1947w(0);
 	wire_w_lg_w_counter_param_latch_range294w379w(0) <= wire_w_counter_param_latch_range294w(0) AND wire_w_lg_w_counter_param_latch_range296w297w(0);
 	wire_w_lg_w_counter_type_latch_range284w710w(0) <= wire_w_counter_type_latch_range284w(0) AND wire_w_lg_w_counter_type_latch_range286w530w(0);
-	wire_w_lg_dummy_scandataout1873w(0) <= NOT dummy_scandataout;
-	wire_w_lg_pll_scandone1875w(0) <= NOT pll_scandone;
+	wire_w_lg_dummy_scandataout1925w(0) <= NOT dummy_scandataout;
+	wire_w_lg_pll_scandone1927w(0) <= NOT pll_scandone;
+	wire_w_lg_read_addr_counter_done1867w(0) <= NOT read_addr_counter_done;
 	wire_w_lg_read_nominal_out216w(0) <= NOT read_nominal_out;
-	wire_w_lg_read_param1730w(0) <= NOT read_param;
-	wire_w_lg_reconfig1728w(0) <= NOT reconfig;
-	wire_w_lg_reconfig_done1832w(0) <= NOT reconfig_done;
-	wire_w_lg_reconfig_post_done1828w(0) <= NOT reconfig_post_done;
-	wire_w_lg_reconfig_width_counter_done1825w(0) <= NOT reconfig_width_counter_done;
+	wire_w_lg_read_param1742w(0) <= NOT read_param;
+	wire_w_lg_reconfig1740w(0) <= NOT reconfig;
+	wire_w_lg_reconfig_done1852w(0) <= NOT reconfig_done;
+	wire_w_lg_reconfig_post_done1848w(0) <= NOT reconfig_post_done;
+	wire_w_lg_reconfig_width_counter_done1845w(0) <= NOT reconfig_width_counter_done;
 	wire_w_lg_reset1w(0) <= NOT reset;
-	wire_w_lg_rotate_width_counter_done1776w(0) <= NOT rotate_width_counter_done;
-	wire_w_lg_width_counter_done1744w(0) <= NOT width_counter_done;
-	wire_w_lg_write_from_rom1727w(0) <= NOT write_from_rom;
-	wire_w_lg_write_param1729w(0) <= NOT write_param;
+	wire_w_lg_reset_rom_address1752w(0) <= NOT reset_rom_address;
+	wire_w_lg_rom_width_counter_done1888w(0) <= NOT rom_width_counter_done;
+	wire_w_lg_rotate_width_counter_done1796w(0) <= NOT rotate_width_counter_done;
+	wire_w_lg_width_counter_done1764w(0) <= NOT width_counter_done;
+	wire_w_lg_write_from_rom1739w(0) <= NOT write_from_rom;
+	wire_w_lg_write_param1741w(0) <= NOT write_param;
 	wire_w_lg_w_counter_param_latch_range296w297w(0) <= NOT wire_w_counter_param_latch_range296w(0);
 	wire_w_lg_w_counter_type_latch_range286w530w(0) <= NOT wire_w_counter_type_latch_range286w(0);
 	wire_w_lg_w_lg_w_lg_w1329w1392w1452w1516w(0) <= wire_w_lg_w_lg_w1329w1392w1452w(0) OR w1484w;
@@ -1108,7 +1219,7 @@
 	wire_w_lg_w_lg_shift_reg_load_enable60w61w(0) <= wire_w_lg_shift_reg_load_enable60w(0) OR shift_reg_load_nominal_enable;
 	wire_w_lg_w_lg_w423w570w637w(0) <= wire_w_lg_w423w570w(0) OR w605w;
 	wire_w_lg_w_lg_w571w672w784w(0) <= wire_w_lg_w571w672w(0) OR w750w;
-	wire_w_lg_dummy_scandataout1874w(0) <= dummy_scandataout OR wire_w_lg_dummy_scandataout1873w(0);
+	wire_w_lg_dummy_scandataout1926w(0) <= dummy_scandataout OR wire_w_lg_dummy_scandataout1925w(0);
 	wire_w_lg_shift_reg_load_enable60w(0) <= shift_reg_load_enable OR shift_reg_shift_enable;
 	wire_w_lg_w301w378w(0) <= w301w OR w341w;
 	wire_w_lg_w381w495w(0) <= w381w OR w460w;
@@ -1117,8 +1228,8 @@
 	wire_w_lg_w675w885w(0) <= w675w OR w851w;
 	addr_counter_enable <= (write_data_state OR write_nominal_state);
 	addr_counter_out <= wire_cntr1_q;
-	addr_counter_sload <= wire_write_init_state_w_lg_q1853w(0);
-	addr_counter_sload_value <= wire_w_lg_addr_decoder_out1854w;
+	addr_counter_sload <= wire_write_init_state_w_lg_q1900w(0);
+	addr_counter_sload_value <= wire_w_lg_addr_decoder_out1901w;
 	addr_decoder_out <= (((((((((((((((((((((((((((((((((((( "0" & "0" & "0" & "0" & "0" & "0" & "0" & w301w) OR ( "0" & "0" & "0" & "0" & "0" & "0" & w341w & w341w)) OR ( "0" & "0" & "0" & "0" & w381w & "0" & "0" & "0")) OR ( "0" & "0" & "0" & "0" & w423w & "0" & "0" & w423w)) OR ( "0" & "0" & "0" & "0" & w460w & w460w & w460w & "0")) OR ( "0" & "0" & "0" & w496w & "0" & "0" & "0" & w496w)) OR ( "0" & "0" & "0" & w534w & "0" & "0" & w534w & "0")) OR ( "0" & "0" & "0" & w571w & w571w & "0" & w571w & "0")) OR ( "0" & "0" & "0" & w605w & w605w & "0" & w605w & w605w)) OR ( "0" & "0" & w638w & "0" & "0" & "0" & w638w & w638w)) OR ( "0" & "0" & w675w & "0" & "0" & "0" & w675w & w675w)) OR ( "0" & "0" & w713w & "0" & "0" & w713w & "0" & "0")) OR ( "0" & "0" & w750w & "0" & w750w & w750w & "0" & "0")) OR ( "0" & "0" & w785w & "0" & w785w & w785w & "0" & w785w)) OR ( "0" & "0" & w818w & w818w & "0" & w818w & "0" & w818w)) OR ( "0" & "0" & w851w & w851w & "0" & w851w & "0" & w851w)) OR ( "0" & "0" & w888w & w888w & "0" & w888w & w888w & "0")) OR ( "0" & "0" & w921w & w921w & w921w & w921w & w921w & "0")) OR ( "0" & "0" & w952w & w952w & w952w & w952w & w952w & w952w)) OR ( "0" & w981w & "0" & "0" & "0" & w981w & w981w & w981w)) OR ( "0" & w1019w & "0" & "0" & w1019w & "0" & "0" & "0")) OR ( "0" & w1056w & "0" & w1056w & "0" & "0" & "0" & "0")) OR ( "0" & w1092w & "0" & w1092w & "0" & "0" & "0" & w1092w)) OR ( "0" & w1127w & "0" & w1127w & w1127w & "0" & "0" & w1127w)) OR ( "0" & w1163w & "0" & w1163w & w1163w & "0" & w1163w & "0")) OR ( "0" & w1196w & w1196w & "0" & "0" & "0" & w1196w & "0")) OR ( "0" & w1229w & w1229w & "0" & "0" & "0" & w1229w & w1229w)) OR ( "0" & w1262w & w1262w & "0" & w1262w & "0" & w1262w & w1262w)) OR ( "0" & w1297w & w1297w & "0" & w1297w & w1297w & "0" & "0")) OR ( "0" & w1330w & w1330w & w1330w & "0" & w1330w & "0" & "0")) OR ( "0" & w1362w & w1362w & w1362w & "0" & w1362w & "0" & w1362w)) OR ( "0" & w1393w & w1393w & w1393w & w1393w & w1393w & "0" & w1393w)) OR ( "0" & w1424w & w1424w & w1424w & w1424w
  & w1424w & w1424w & "0")) OR ( w1453w & "0" & "0" & "0" & "0" & w1453w & w1453w & "0")) OR ( w1484w & "0" & "0" & "0" & "0" & w1484w & w1484w & w1484w)) OR ( w1517w & "0" & "0" & "0" & w1517w & w1517w & w1517w & w1517w));
 	busy <= (wire_idle_state_w_lg_q1672w(0) OR areset_state);
@@ -1127,23 +1238,25 @@
 	c2_wire <= "01101011";
 	c3_wire <= "01111101";
 	c4_wire <= "10001111";
+	const_scan_chain_size <= "10001111";
 	counter_param_latch <= counter_param_latch_reg;
 	counter_type_latch <= counter_type_latch_reg;
 	cuda_combout_wire <= ( wire_le_comb10_combout & wire_le_comb9_combout & wire_le_comb8_combout);
 	data_out <= ( wire_shift_reg_w_lg_w_lg_q258w259w & wire_shift_reg_w_lg_w_lg_q253w254w & wire_shift_reg_w_lg_w_lg_q248w249w & wire_shift_reg_w_lg_w_lg_q243w244w & wire_shift_reg_w_lg_w_lg_q238w239w & wire_shift_reg_w_lg_w_lg_q233w234w & wire_shift_reg_w_lg_w_lg_q228w229w & wire_shift_reg_w_lg_w_lg_q223w224w & wire_shift_reg_w_lg_w_lg_q217w218w);
 	dummy_scandataout <= pll_scandataout;
-	encode_out <= ( C4_ena_state & wire_C2_ena_state_w_lg_q1767w & wire_C1_ena_state_w_lg_q1766w);
+	encode_out <= ( C4_ena_state & wire_C2_ena_state_w_lg_q1787w & wire_C1_ena_state_w_lg_q1786w);
 	input_latch_enable <= (idle_state AND (write_param OR read_param));
 	pll_areset <= (pll_areset_in OR (areset_state AND reconfig_wait_state));
-	pll_configupdate <= (configupdate_state AND wire_configupdate3_state_w_lg_q1842w(0));
+	pll_configupdate <= (configupdate_state AND wire_configupdate3_state_w_lg_q1879w(0));
 	pll_scanclk <= clock;
-	pll_scanclkena <= ((rotate_width_counter_enable AND wire_w_lg_rotate_width_counter_done1776w(0)) OR reconfig_seq_data_state);
+	pll_scanclkena <= ((rotate_width_counter_enable AND wire_w_lg_rotate_width_counter_done1796w(0)) OR reconfig_seq_data_state);
 	pll_scandata <= (scan_cache_out AND ((rotate_width_counter_enable OR reconfig_seq_data_state) OR reconfig_post_state));
-	power_up <= (((((((((((((((((((wire_reset_state_w_lg_q1671w(0) AND wire_idle_state_w_lg_q1672w(0)) AND wire_read_init_state_w_lg_q1674w(0)) AND wire_read_first_state_w_lg_q1676w(0)) AND wire_read_data_state_w_lg_q1678w(0)) AND wire_read_last_state_w_lg_q1680w(0)) AND wire_read_init_nominal_state_w_lg_q1682w(0)) AND wire_read_first_nominal_state_w_lg_q1684w(0)) AND wire_read_data_nominal_state_w_lg_q1686w(0)) AND wire_read_last_nominal_state_w_lg_q1688w(0)) AND wire_write_init_state_w_lg_q1690w(0)) AND wire_write_data_state_w_lg_q1692w(0)) AND wire_write_init_nominal_state_w_lg_q1694w(0)) AND wire_write_nominal_state_w_lg_q1696w(0)) AND wire_reconfig_init_state_w_lg_q1698w(0)) AND wire_reconfig_counter_state_w_lg_q1700w(0)) AND wire_reconfig_seq_ena_state_w_lg_q1702w(0)) AND wire_reconfig_seq_data_state_w_lg_q1704w(0)) AND wire_reconfig_post_state_w_lg_q1706w(0)) AND wire_reconfig_wait_state_w_lg_q1708w(0));
-	read_addr_counter_enable <= (((read_first_state OR read_data_state) OR read_first_nominal_state) OR read_data_nominal_state);
+	power_up <= (((((((((((((((((((((((((wire_reset_state_w_lg_q1671w(0) AND wire_idle_state_w_lg_q1672w(0)) AND wire_read_init_state_w_lg_q1674w(0)) AND wire_read_first_state_w_lg_q1676w(0)) AND wire_read_data_state_w_lg_q1678w(0)) AND wire_read_last_state_w_lg_q1680w(0)) AND wire_read_init_nominal_state_w_lg_q1682w(0)) AND wire_read_first_nominal_state_w_lg_q1684w(0)) AND wire_read_data_nominal_state_w_lg_q1686w(0)) AND wire_read_last_nominal_state_w_lg_q1688w(0)) AND wire_write_init_state_w_lg_q1690w(0)) AND wire_write_data_state_w_lg_q1692w(0)) AND wire_write_init_nominal_state_w_lg_q1694w(0)) AND wire_write_nominal_state_w_lg_q1696w(0)) AND wire_reconfig_init_state_w_lg_q1698w(0)) AND wire_reconfig_counter_state_w_lg_q1700w(0)) AND wire_reconfig_seq_ena_state_w_lg_q1702w(0)) AND wire_reconfig_seq_data_state_w_lg_q1704w(0)) AND wire_reconfig_post_state_w_lg_q1706w(0)) AND wire_reconfig_wait_state_w_lg_q1708w(0)) AND wire_rom_init_state_w_lg_q1710w(0)) AND wire_rom_first_state_w_lg_q1712w(0)) AND wire_rom_second_state_w_lg_q1714w(0)) AND wire_rom_data_state_w_lg_q1716w(0)) AND wire_rom_second_last_state_w_lg_q1718w(0)) AND wire_rom_last_state_w_lg_q1720w(0));
+	read_addr_counter_done <= (((((((wire_cntr2_q(0) AND wire_cntr2_q(1)) AND wire_cntr2_q(2)) AND wire_cntr2_q(3)) AND (NOT wire_cntr2_q(4))) AND (NOT wire_cntr2_q(5))) AND (NOT wire_cntr2_q(6))) AND wire_cntr2_q(7));
+	read_addr_counter_enable <= (wire_read_first_state_w_lg_w_lg_w_lg_q1894w1895w1896w(0) OR wire_rom_data_state_w_lg_w_lg_q1897w1898w(0));
 	read_addr_counter_out <= wire_cntr2_q;
-	read_addr_counter_sload <= wire_read_init_state_w_lg_q1848w(0);
-	read_addr_counter_sload_value <= wire_w_lg_read_addr_decoder_out1849w;
+	read_addr_counter_sload <= (wire_read_init_state_w_lg_q1891w(0) OR rom_init_state);
+	read_addr_counter_sload_value <= wire_w_lg_read_addr_decoder_out1893w;
 	read_addr_decoder_out <= (((((((((((((((((((((((((((((((((((( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0") OR ( "0" & "0" & "0" & "0" & "0" & "0" & w341w & "0")) OR ( "0" & "0" & "0" & "0" & "0" & w381w & "0" & "0")) OR ( "0" & "0" & "0" & "0" & w423w & "0" & "0" & w423w)) OR ( "0" & "0" & "0" & "0" & w460w & "0" & w460w & "0")) OR ( "0" & "0" & "0" & "0" & w496w & w496w & w496w & w496w)) OR ( "0" & "0" & "0" & w534w & "0" & "0" & w534w & "0")) OR ( "0" & "0" & "0" & w571w & "0" & "0" & w571w & w571w)) OR ( "0" & "0" & "0" & w605w & w605w & "0" & w605w & w605w)) OR ( "0" & "0" & "0" & w638w & w638w & w638w & "0" & "0")) OR ( "0" & "0" & "0" & w675w & "0" & "0" & w675w & "0")) OR ( "0" & "0" & w713w & "0" & "0" & w713w & "0" & "0")) OR ( "0" & "0" & w750w & "0" & "0" & w750w & "0" & w750w)) OR ( "0" & "0" & w785w & "0" & w785w & w785w & "0" & w785w)) OR ( "0" & "0" & w818w & "0" & w818w & w818w & w818w & "0")) OR ( "0" & "0" & w851w & "0" & "0" & w851w & "0" & "0")) OR ( "0" & "0" & w888w & w888w & "0" & w888w & w888w & "0")) OR ( "0" & "0" & w921w & w921w & "0" & w921w & w921w & w921w)) OR ( "0" & "0" & w952w & w952w & w952w & w952w & w952w & w952w)) OR ( "0" & w981w & "0" & "0" & "0" & "0" & "0" & "0")) OR ( "0" & w1019w & "0" & "0" & w1019w & "0" & "0" & "0")) OR ( "0" & w1056w & "0" & "0" & w1056w & "0" & "0" & w1056w)) OR ( "0" & w1092w & "0" & w1092w & "0" & "0" & "0" & w1092w)) OR ( "0" & w1127w & "0" & w1127w & "0" & "0" & w1127w & "0")) OR ( "0" & w1163w & "0" & w1163w & w1163w & "0" & w1163w & "0")) OR ( "0" & w1196w & "0" & w1196w & w1196w & "0" & w1196w & w1196w)) OR ( "0" & w1229w & w1229w & "0" & "0" & "0" & w1229w & w1229w)) OR ( "0" & w1262w & w1262w & "0" & "0" & w1262w & "0" & "0")) OR ( "0" & w1297w & w1297w & "0" & w1297w & w1297w & "0" & "0")) OR ( "0" & w1330w & w1330w & "0" & w1330w & w1330w & "0" & w1330w)) OR ( "0" & w1362w & w1362w & w1362w & "0" & w1362w & "0" & w1362w)) OR ( "0" & w1393w & w1393w & w1393w & "0" & w1393w & w1393w & "0")) OR ( "0" & w1424w & w1424w & w1424w & w1424w & w1424w
  & w1424w & "0")) OR ( "0" & w1453w & w1453w & w1453w & w1453w & w1453w & w1453w & w1453w)) OR ( w1484w & "0" & "0" & "0" & "0" & w1484w & w1484w & w1484w)) OR ( w1517w & "0" & "0" & "0" & w1517w & "0" & "0" & "0"));
 	read_nominal_out <= tmp_nominal_data_out_state;
@@ -1150,26 +1263,31 @@
 	reconfig_addr_counter_enable <= reconfig_seq_data_state;
 	reconfig_addr_counter_out <= wire_cntr12_q;
 	reconfig_addr_counter_sload <= reconfig_seq_ena_state;
-	reconfig_addr_counter_sload_value <= wire_reconfig_seq_ena_state_w_lg_q1856w;
-	reconfig_done <= (wire_w_lg_pll_scandone1875w(0) AND wire_w_lg_dummy_scandataout1874w(0));
+	reconfig_addr_counter_sload_value <= wire_reconfig_seq_ena_state_w_lg_q1903w;
+	reconfig_done <= (wire_w_lg_pll_scandone1927w(0) AND wire_w_lg_dummy_scandataout1926w(0));
 	reconfig_post_done <= pll_scandone;
 	reconfig_width_counter_done <= ((((((NOT wire_cntr13_q(0)) AND (NOT wire_cntr13_q(1))) AND (NOT wire_cntr13_q(2))) AND (NOT wire_cntr13_q(3))) AND (NOT wire_cntr13_q(4))) AND (NOT wire_cntr13_q(5)));
 	reconfig_width_counter_enable <= reconfig_seq_data_state;
 	reconfig_width_counter_sload <= reconfig_seq_ena_state;
-	reconfig_width_counter_sload_value <= wire_reconfig_seq_ena_state_w_lg_q1857w;
+	reconfig_width_counter_sload_value <= wire_reconfig_seq_ena_state_w_lg_q1904w;
+	rom_address_out <= wire_w_lg_read_addr_counter_out1887w;
+	rom_width_counter_done <= ((((((((NOT wire_cntr14_q(0)) AND (NOT wire_cntr14_q(1))) AND (NOT wire_cntr14_q(2))) AND (NOT wire_cntr14_q(3))) AND (NOT wire_cntr14_q(4))) AND (NOT wire_cntr14_q(5))) AND (NOT wire_cntr14_q(6))) AND (NOT wire_cntr14_q(7)));
+	rom_width_counter_enable <= ((rom_data_state OR rom_last_state) OR rom_second_last_state);
+	rom_width_counter_sload <= rom_init_state;
+	rom_width_counter_sload_value <= const_scan_chain_size;
 	rotate_addr_counter_enable <= ((((C0_data_state OR C1_data_state) OR C2_data_state) OR C3_data_state) OR C4_data_state);
-	rotate_addr_counter_out <= wire_cntr15_q;
+	rotate_addr_counter_out <= wire_cntr16_q;
 	rotate_addr_counter_sload <= ((((C0_ena_state OR C1_ena_state) OR C2_ena_state) OR C3_ena_state) OR C4_ena_state);
-	rotate_addr_counter_sload_value <= ((((wire_w_lg_c0_wire1808w OR wire_w_lg_c1_wire1806w) OR wire_w_lg_c2_wire1804w) OR wire_w_lg_c3_wire1802w) OR wire_w_lg_c4_wire1800w);
+	rotate_addr_counter_sload_value <= ((((wire_w_lg_c0_wire1828w OR wire_w_lg_c1_wire1826w) OR wire_w_lg_c2_wire1824w) OR wire_w_lg_c3_wire1822w) OR wire_w_lg_c4_wire1820w);
 	rotate_decoder_wires <= wire_decode11_eq;
-	rotate_width_counter_done <= (((((NOT wire_cntr14_q(0)) AND (NOT wire_cntr14_q(1))) AND (NOT wire_cntr14_q(2))) AND (NOT wire_cntr14_q(3))) AND (NOT wire_cntr14_q(4)));
+	rotate_width_counter_done <= (((((NOT wire_cntr15_q(0)) AND (NOT wire_cntr15_q(1))) AND (NOT wire_cntr15_q(2))) AND (NOT wire_cntr15_q(3))) AND (NOT wire_cntr15_q(4)));
 	rotate_width_counter_enable <= ((((C0_data_state OR C1_data_state) OR C2_data_state) OR C3_data_state) OR C4_data_state);
 	rotate_width_counter_sload <= ((((C0_ena_state OR C1_ena_state) OR C2_ena_state) OR C3_ena_state) OR C4_ena_state);
 	rotate_width_counter_sload_value <= "10010";
-	scan_cache_address <= (((wire_w_lg_addr_counter_out1880w OR wire_w_lg_read_addr_counter_out1879w) OR wire_w_lg_rotate_addr_counter_out1878w) OR wire_w_lg_reconfig_addr_counter_out1877w);
-	scan_cache_in <= shift_reg_serial_out;
+	scan_cache_address <= ((((wire_w_lg_addr_counter_out1938w OR wire_w_lg_rotate_addr_counter_out1937w) OR wire_w_lg_reconfig_addr_counter_out1936w) OR wire_w_lg_w_lg_read_addr_counter_out1934w1935w) OR wire_w_lg_w_lg_rom_width_counter_enable1931w1932w);
+	scan_cache_in <= (wire_w_lg_shift_reg_serial_out1948w(0) OR wire_w_lg_rom_data_in1946w(0));
 	scan_cache_out <= wire_altsyncram4_q_a(0);
-	scan_cache_write_enable <= (write_data_state OR write_nominal_state);
+	scan_cache_write_enable <= ((((write_data_state OR write_nominal_state) OR rom_data_state) OR rom_second_last_state) OR rom_last_state);
 	sel_param_bypass_LF_unused <= (((NOT counter_param_latch(0)) AND wire_w_lg_w_counter_param_latch_range296w297w(0)) AND counter_param_latch(2));
 	sel_param_c <= (((NOT counter_param_latch(0)) AND counter_param_latch(1)) AND (NOT counter_param_latch(2)));
 	sel_param_high_i_postscale <= (((NOT counter_param_latch(0)) AND wire_w_lg_w_counter_param_latch_range296w297w(0)) AND (NOT counter_param_latch(2)));
@@ -1187,7 +1305,7 @@
 	sel_type_vco <= (((counter_type_latch(0) AND counter_type_latch(1)) AND (NOT counter_type_latch(2))) AND (NOT counter_type_latch(3)));
 	seq_addr_wire <= "00110101";
 	seq_sload_value <= "110110";
-	shift_reg_clear <= wire_read_init_state_w_lg_q1848w(0);
+	shift_reg_clear <= wire_read_init_state_w_lg_q1891w(0);
 	shift_reg_load_enable <= ((idle_state AND write_param) AND (NOT ((((((NOT counter_type(3)) AND (NOT counter_type(2))) AND (NOT counter_type(1))) AND counter_param(2)) AND counter_param(1)) AND counter_param(0))));
 	shift_reg_load_nominal_enable <= ((idle_state AND write_param) AND ((((((NOT counter_type(3)) AND (NOT counter_type(2))) AND (NOT counter_type(1))) AND counter_param(2)) AND counter_param(1)) AND counter_param(0)));
 	shift_reg_serial_in <= scan_cache_out;
@@ -1235,12 +1353,12 @@
 	w952w <= (sel_type_c0 AND sel_param_odd_CP_unused);
 	w981w <= (sel_type_c0 AND sel_param_low_r);
 	width_counter_done <= (((((NOT wire_cntr3_q(0)) AND (NOT wire_cntr3_q(1))) AND (NOT wire_cntr3_q(2))) AND (NOT wire_cntr3_q(3))) AND (NOT wire_cntr3_q(4)));
-	width_counter_enable <= ((((read_first_state OR read_data_state) OR write_data_state) OR read_data_nominal_state) OR write_nominal_state);
+	width_counter_enable <= (((wire_read_first_state_w_lg_q1894w(0) OR write_data_state) OR read_data_nominal_state) OR write_nominal_state);
 	width_counter_sload <= (((read_init_state OR write_init_state) OR read_init_nominal_state) OR write_init_nominal_state);
 	width_counter_sload_value <= width_decoder_out;
 	width_decoder_out <= (((((( "0" & "0" & "0" & "0" & "0") OR ( width_decoder_select(2) & "0" & "0" & "0" & width_decoder_select(2))) OR ( "0" & "0" & "0" & "0" & width_decoder_select(3))) OR ( "0" & "0" & width_decoder_select(5) & width_decoder_select(5) & width_decoder_select(5))) OR ( "0" & "0" & "0" & width_decoder_select(6) & "0")) OR ( "0" & "0" & width_decoder_select(7) & "0" & "0"));
 	width_decoder_select <= ( wire_w_lg_w381w495w & w496w & wire_w_lg_w_lg_w_lg_w1361w1422w1483w1550w & w1592w & wire_w_lg_w301w378w & wire_w_lg_w675w885w & w1565w & wire_w_lg_w_lg_w_lg_w1329w1392w1452w1516w);
-	write_from_rom <= '0';
+	write_rom_ena <= (wire_rom_first_state_w_lg_q1885w(0) OR wire_rom_data_state_w_lg_q1889w(0));
 	wire_w_counter_param_latch_range294w(0) <= counter_param_latch(0);
 	wire_w_counter_param_latch_range296w(0) <= counter_param_latch(1);
 	wire_w_counter_type_latch_range284w(0) <= counter_type_latch(0);
@@ -1254,11 +1372,11 @@
 	wire_w_data_in_range138w(0) <= data_in(6);
 	wire_w_data_in_range130w(0) <= data_in(7);
 	wire_w_data_in_range122w(0) <= data_in(8);
-	wire_w_rotate_decoder_wires_range1807w(0) <= rotate_decoder_wires(0);
-	wire_w_rotate_decoder_wires_range1805w(0) <= rotate_decoder_wires(1);
-	wire_w_rotate_decoder_wires_range1803w(0) <= rotate_decoder_wires(2);
-	wire_w_rotate_decoder_wires_range1801w(0) <= rotate_decoder_wires(3);
-	wire_w_rotate_decoder_wires_range1799w(0) <= rotate_decoder_wires(4);
+	wire_w_rotate_decoder_wires_range1827w(0) <= rotate_decoder_wires(0);
+	wire_w_rotate_decoder_wires_range1825w(0) <= rotate_decoder_wires(1);
+	wire_w_rotate_decoder_wires_range1823w(0) <= rotate_decoder_wires(2);
+	wire_w_rotate_decoder_wires_range1821w(0) <= rotate_decoder_wires(3);
+	wire_w_rotate_decoder_wires_range1819w(0) <= rotate_decoder_wires(4);
 	wire_w_shift_reg_width_select_range261w(0) <= shift_reg_width_select(0);
 	wire_w_shift_reg_width_select_range263w(0) <= shift_reg_width_select(1);
 	wire_w_shift_reg_width_select_range266w(0) <= shift_reg_width_select(2);
@@ -1323,6 +1441,16 @@
 	  );
 	PROCESS (clock)
 	BEGIN
+		IF (clock = '1' AND clock'event) THEN addr_from_rom <= read_addr_counter_out;
+		END IF;
+	END PROCESS;
+	PROCESS (clock)
+	BEGIN
+		IF (clock = '1' AND clock'event) THEN addr_from_rom2 <= addr_from_rom;
+		END IF;
+	END PROCESS;
+	PROCESS (clock)
+	BEGIN
 		IF (clock = '1' AND clock'event) THEN areset_init_state_1 <= pll_scandone;
 		END IF;
 	END PROCESS;
@@ -1333,7 +1461,7 @@
 	END PROCESS;
 	PROCESS (clock)
 	BEGIN
-		IF (clock = '1' AND clock'event) THEN C0_data_state <= (C0_ena_state OR (C0_data_state AND wire_w_lg_rotate_width_counter_done1776w(0)));
+		IF (clock = '1' AND clock'event) THEN C0_data_state <= (C0_ena_state OR (C0_data_state AND wire_w_lg_rotate_width_counter_done1796w(0)));
 		END IF;
 	END PROCESS;
 	PROCESS (clock)
@@ -1343,7 +1471,7 @@
 	END PROCESS;
 	PROCESS (clock)
 	BEGIN
-		IF (clock = '1' AND clock'event) THEN C1_data_state <= (C1_ena_state OR (C1_data_state AND wire_w_lg_rotate_width_counter_done1776w(0)));
+		IF (clock = '1' AND clock'event) THEN C1_data_state <= (C1_ena_state OR (C1_data_state AND wire_w_lg_rotate_width_counter_done1796w(0)));
 		END IF;
 	END PROCESS;
 	PROCESS (clock)
@@ -1351,10 +1479,10 @@
 		IF (clock = '1' AND clock'event) THEN C1_ena_state <= (C2_data_state AND rotate_width_counter_done);
 		END IF;
 	END PROCESS;
-	wire_C1_ena_state_w_lg_q1766w(0) <= C1_ena_state OR C3_ena_state;
+	wire_C1_ena_state_w_lg_q1786w(0) <= C1_ena_state OR C3_ena_state;
 	PROCESS (clock)
 	BEGIN
-		IF (clock = '1' AND clock'event) THEN C2_data_state <= (C2_ena_state OR (C2_data_state AND wire_w_lg_rotate_width_counter_done1776w(0)));
+		IF (clock = '1' AND clock'event) THEN C2_data_state <= (C2_ena_state OR (C2_data_state AND wire_w_lg_rotate_width_counter_done1796w(0)));
 		END IF;
 	END PROCESS;
 	PROCESS (clock)
@@ -1362,10 +1490,10 @@
 		IF (clock = '1' AND clock'event) THEN C2_ena_state <= (C3_data_state AND rotate_width_counter_done);
 		END IF;
 	END PROCESS;
-	wire_C2_ena_state_w_lg_q1767w(0) <= C2_ena_state OR C3_ena_state;
+	wire_C2_ena_state_w_lg_q1787w(0) <= C2_ena_state OR C3_ena_state;
 	PROCESS (clock)
 	BEGIN
-		IF (clock = '1' AND clock'event) THEN C3_data_state <= (C3_ena_state OR (C3_data_state AND wire_w_lg_rotate_width_counter_done1776w(0)));
+		IF (clock = '1' AND clock'event) THEN C3_data_state <= (C3_ena_state OR (C3_data_state AND wire_w_lg_rotate_width_counter_done1796w(0)));
 		END IF;
 	END PROCESS;
 	PROCESS (clock)
@@ -1375,7 +1503,7 @@
 	END PROCESS;
 	PROCESS (clock)
 	BEGIN
-		IF (clock = '1' AND clock'event) THEN C4_data_state <= (C4_ena_state OR (C4_data_state AND wire_w_lg_rotate_width_counter_done1776w(0)));
+		IF (clock = '1' AND clock'event) THEN C4_data_state <= (C4_ena_state OR (C4_data_state AND wire_w_lg_rotate_width_counter_done1796w(0)));
 		END IF;
 	END PROCESS;
 	PROCESS (clock)
@@ -1393,7 +1521,7 @@
 		IF (clock = '0' AND clock'event) THEN configupdate3_state <= configupdate2_state;
 		END IF;
 	END PROCESS;
-	wire_configupdate3_state_w_lg_q1842w(0) <= NOT configupdate3_state;
+	wire_configupdate3_state_w_lg_q1879w(0) <= NOT configupdate3_state;
 	PROCESS (clock)
 	BEGIN
 		IF (clock = '1' AND clock'event) THEN configupdate_state <= reconfig_post_state;
@@ -1418,18 +1546,18 @@
 	PROCESS (clock, reset)
 	BEGIN
 		IF (reset = '1') THEN idle_state <= '0';
-		ELSIF (clock = '1' AND clock'event) THEN idle_state <= ((wire_idle_state_w_lg_w_lg_w_lg_w1735w1736w1737w1738w(0) OR (reconfig_wait_state AND reconfig_done)) OR reset_state);
+		ELSIF (clock = '1' AND clock'event) THEN idle_state <= (((((wire_idle_state_w_lg_w_lg_w_lg_w1747w1748w1749w1750w(0) OR (reconfig_wait_state AND reconfig_done)) OR ((rom_data_state AND rom_width_counter_done) AND wire_w_lg_reset_rom_address1752w(0))) OR wire_rom_second_last_state_w_lg_q1754w(0)) OR wire_rom_last_state_w_lg_q1753w(0)) OR reset_state);
 		END IF;
 	END PROCESS;
-	wire_idle_state_w_lg_w_lg_w_lg_w_lg_q1731w1732w1733w1734w(0) <= wire_idle_state_w_lg_w_lg_w_lg_q1731w1732w1733w(0) AND wire_w_lg_write_from_rom1727w(0);
-	wire_idle_state_w_lg_w_lg_w_lg_q1731w1732w1733w(0) <= wire_idle_state_w_lg_w_lg_q1731w1732w(0) AND wire_w_lg_reconfig1728w(0);
-	wire_idle_state_w_lg_w_lg_q1731w1732w(0) <= wire_idle_state_w_lg_q1731w(0) AND wire_w_lg_write_param1729w(0);
-	wire_idle_state_w_lg_q1731w(0) <= idle_state AND wire_w_lg_read_param1730w(0);
+	wire_idle_state_w_lg_w_lg_w_lg_w_lg_q1743w1744w1745w1746w(0) <= wire_idle_state_w_lg_w_lg_w_lg_q1743w1744w1745w(0) AND wire_w_lg_write_from_rom1739w(0);
+	wire_idle_state_w_lg_w_lg_w_lg_q1743w1744w1745w(0) <= wire_idle_state_w_lg_w_lg_q1743w1744w(0) AND wire_w_lg_reconfig1740w(0);
+	wire_idle_state_w_lg_w_lg_q1743w1744w(0) <= wire_idle_state_w_lg_q1743w(0) AND wire_w_lg_write_param1741w(0);
+	wire_idle_state_w_lg_q1743w(0) <= idle_state AND wire_w_lg_read_param1742w(0);
 	wire_idle_state_w_lg_q1672w(0) <= NOT idle_state;
-	wire_idle_state_w1735w(0) <= wire_idle_state_w_lg_w_lg_w_lg_w_lg_q1731w1732w1733w1734w(0) OR read_last_state;
-	wire_idle_state_w_lg_w1735w1736w(0) <= wire_idle_state_w1735w(0) OR wire_write_data_state_w_lg_q1726w(0);
-	wire_idle_state_w_lg_w_lg_w1735w1736w1737w(0) <= wire_idle_state_w_lg_w1735w1736w(0) OR wire_write_nominal_state_w_lg_q1725w(0);
-	wire_idle_state_w_lg_w_lg_w_lg_w1735w1736w1737w1738w(0) <= wire_idle_state_w_lg_w_lg_w1735w1736w1737w(0) OR read_last_nominal_state;
+	wire_idle_state_w1747w(0) <= wire_idle_state_w_lg_w_lg_w_lg_w_lg_q1743w1744w1745w1746w(0) OR read_last_state;
+	wire_idle_state_w_lg_w1747w1748w(0) <= wire_idle_state_w1747w(0) OR wire_write_data_state_w_lg_q1738w(0);
+	wire_idle_state_w_lg_w_lg_w1747w1748w1749w(0) <= wire_idle_state_w_lg_w1747w1748w(0) OR wire_write_nominal_state_w_lg_q1737w(0);
+	wire_idle_state_w_lg_w_lg_w_lg_w1747w1748w1749w1750w(0) <= wire_idle_state_w_lg_w_lg_w1747w1748w1749w(0) OR read_last_nominal_state;
 	PROCESS (clock, reset)
 	BEGIN
 		IF (reset = '1') THEN nominal_data0 <= '0';
@@ -1541,18 +1669,18 @@
 	PROCESS (clock, reset)
 	BEGIN
 		IF (reset = '1') THEN read_data_nominal_state <= '0';
-		ELSIF (clock = '1' AND clock'event) THEN read_data_nominal_state <= (wire_read_first_nominal_state_w_lg_q1753w(0) OR wire_read_data_nominal_state_w_lg_q1752w(0));
+		ELSIF (clock = '1' AND clock'event) THEN read_data_nominal_state <= (wire_read_first_nominal_state_w_lg_q1773w(0) OR wire_read_data_nominal_state_w_lg_q1772w(0));
 		END IF;
 	END PROCESS;
-	wire_read_data_nominal_state_w_lg_q1752w(0) <= read_data_nominal_state AND wire_w_lg_width_counter_done1744w(0);
+	wire_read_data_nominal_state_w_lg_q1772w(0) <= read_data_nominal_state AND wire_w_lg_width_counter_done1764w(0);
 	wire_read_data_nominal_state_w_lg_q1686w(0) <= NOT read_data_nominal_state;
 	PROCESS (clock, reset)
 	BEGIN
 		IF (reset = '1') THEN read_data_state <= '0';
-		ELSIF (clock = '1' AND clock'event) THEN read_data_state <= (wire_read_first_state_w_lg_q1746w(0) OR wire_read_data_state_w_lg_q1745w(0));
+		ELSIF (clock = '1' AND clock'event) THEN read_data_state <= (wire_read_first_state_w_lg_q1766w(0) OR wire_read_data_state_w_lg_q1765w(0));
 		END IF;
 	END PROCESS;
-	wire_read_data_state_w_lg_q1745w(0) <= read_data_state AND wire_w_lg_width_counter_done1744w(0);
+	wire_read_data_state_w_lg_q1765w(0) <= read_data_state AND wire_w_lg_width_counter_done1764w(0);
 	wire_read_data_state_w_lg_q1678w(0) <= NOT read_data_state;
 	PROCESS (clock, reset)
 	BEGIN
@@ -1560,7 +1688,7 @@
 		ELSIF (clock = '1' AND clock'event) THEN read_first_nominal_state <= read_init_nominal_state;
 		END IF;
 	END PROCESS;
-	wire_read_first_nominal_state_w_lg_q1753w(0) <= read_first_nominal_state AND wire_w_lg_width_counter_done1744w(0);
+	wire_read_first_nominal_state_w_lg_q1773w(0) <= read_first_nominal_state AND wire_w_lg_width_counter_done1764w(0);
 	wire_read_first_nominal_state_w_lg_q1684w(0) <= NOT read_first_nominal_state;
 	PROCESS (clock, reset)
 	BEGIN
@@ -1568,8 +1696,11 @@
 		ELSIF (clock = '1' AND clock'event) THEN read_first_state <= read_init_state;
 		END IF;
 	END PROCESS;
-	wire_read_first_state_w_lg_q1746w(0) <= read_first_state AND wire_w_lg_width_counter_done1744w(0);
+	wire_read_first_state_w_lg_q1766w(0) <= read_first_state AND wire_w_lg_width_counter_done1764w(0);
 	wire_read_first_state_w_lg_q1676w(0) <= NOT read_first_state;
+	wire_read_first_state_w_lg_w_lg_w_lg_q1894w1895w1896w(0) <= wire_read_first_state_w_lg_w_lg_q1894w1895w(0) OR read_data_nominal_state;
+	wire_read_first_state_w_lg_w_lg_q1894w1895w(0) <= wire_read_first_state_w_lg_q1894w(0) OR read_first_nominal_state;
+	wire_read_first_state_w_lg_q1894w(0) <= read_first_state OR read_data_state;
 	PROCESS (clock, reset)
 	BEGIN
 		IF (reset = '1') THEN read_init_nominal_state <= '0';
@@ -1584,7 +1715,7 @@
 		END IF;
 	END PROCESS;
 	wire_read_init_state_w_lg_q1674w(0) <= NOT read_init_state;
-	wire_read_init_state_w_lg_q1848w(0) <= read_init_state OR read_init_nominal_state;
+	wire_read_init_state_w_lg_q1891w(0) <= read_init_state OR read_init_nominal_state;
 	PROCESS (clock, reset)
 	BEGIN
 		IF (reset = '1') THEN read_last_nominal_state <= '0';
@@ -1591,7 +1722,7 @@
 		ELSIF (clock = '1' AND clock'event) THEN read_last_nominal_state <= ((read_first_nominal_state AND width_counter_done) OR (read_data_nominal_state AND width_counter_done));
 		END IF;
 	END PROCESS;
-	wire_read_last_nominal_state_w_lg_q1865w(0) <= read_last_nominal_state AND wire_idle_state_w_lg_q1672w(0);
+	wire_read_last_nominal_state_w_lg_q1917w(0) <= read_last_nominal_state AND wire_idle_state_w_lg_q1672w(0);
 	wire_read_last_nominal_state_w_lg_q1688w(0) <= NOT read_last_nominal_state;
 	PROCESS (clock, reset)
 	BEGIN
@@ -1617,15 +1748,15 @@
 	PROCESS (clock, reset)
 	BEGIN
 		IF (reset = '1') THEN reconfig_post_state <= '0';
-		ELSIF (clock = '1' AND clock'event) THEN reconfig_post_state <= ((reconfig_seq_data_state AND reconfig_width_counter_done) OR wire_reconfig_post_state_w_lg_q1829w(0));
+		ELSIF (clock = '1' AND clock'event) THEN reconfig_post_state <= ((reconfig_seq_data_state AND reconfig_width_counter_done) OR wire_reconfig_post_state_w_lg_q1849w(0));
 		END IF;
 	END PROCESS;
-	wire_reconfig_post_state_w_lg_q1829w(0) <= reconfig_post_state AND wire_w_lg_reconfig_post_done1828w(0);
+	wire_reconfig_post_state_w_lg_q1849w(0) <= reconfig_post_state AND wire_w_lg_reconfig_post_done1848w(0);
 	wire_reconfig_post_state_w_lg_q1706w(0) <= NOT reconfig_post_state;
 	PROCESS (clock, reset)
 	BEGIN
 		IF (reset = '1') THEN reconfig_seq_data_state <= '0';
-		ELSIF (clock = '1' AND clock'event) THEN reconfig_seq_data_state <= (reconfig_seq_ena_state OR (reconfig_seq_data_state AND wire_w_lg_reconfig_width_counter_done1825w(0)));
+		ELSIF (clock = '1' AND clock'event) THEN reconfig_seq_data_state <= (reconfig_seq_ena_state OR (reconfig_seq_data_state AND wire_w_lg_reconfig_width_counter_done1845w(0)));
 		END IF;
 	END PROCESS;
 	wire_reconfig_seq_data_state_w_lg_q1704w(0) <= NOT reconfig_seq_data_state;
@@ -1635,20 +1766,20 @@
 		ELSIF (clock = '1' AND clock'event) THEN reconfig_seq_ena_state <= tmp_seq_ena_state;
 		END IF;
 	END PROCESS;
-	loop11 : FOR i IN 0 TO 7 GENERATE 
-		wire_reconfig_seq_ena_state_w_lg_q1856w(i) <= reconfig_seq_ena_state AND seq_addr_wire(i);
-	END GENERATE loop11;
-	loop12 : FOR i IN 0 TO 5 GENERATE 
-		wire_reconfig_seq_ena_state_w_lg_q1857w(i) <= reconfig_seq_ena_state AND seq_sload_value(i);
-	END GENERATE loop12;
+	loop14 : FOR i IN 0 TO 7 GENERATE 
+		wire_reconfig_seq_ena_state_w_lg_q1903w(i) <= reconfig_seq_ena_state AND seq_addr_wire(i);
+	END GENERATE loop14;
+	loop15 : FOR i IN 0 TO 5 GENERATE 
+		wire_reconfig_seq_ena_state_w_lg_q1904w(i) <= reconfig_seq_ena_state AND seq_sload_value(i);
+	END GENERATE loop15;
 	wire_reconfig_seq_ena_state_w_lg_q1702w(0) <= NOT reconfig_seq_ena_state;
 	PROCESS (clock, reset)
 	BEGIN
 		IF (reset = '1') THEN reconfig_wait_state <= '0';
-		ELSIF (clock = '1' AND clock'event) THEN reconfig_wait_state <= ((reconfig_post_state AND reconfig_post_done) OR wire_reconfig_wait_state_w_lg_q1833w(0));
+		ELSIF (clock = '1' AND clock'event) THEN reconfig_wait_state <= ((reconfig_post_state AND reconfig_post_done) OR wire_reconfig_wait_state_w_lg_q1853w(0));
 		END IF;
 	END PROCESS;
-	wire_reconfig_wait_state_w_lg_q1833w(0) <= reconfig_wait_state AND wire_w_lg_reconfig_done1832w(0);
+	wire_reconfig_wait_state_w_lg_q1853w(0) <= reconfig_wait_state AND wire_w_lg_reconfig_done1852w(0);
 	wire_reconfig_wait_state_w_lg_q1708w(0) <= NOT reconfig_wait_state;
 	PROCESS (clock, reset)
 	BEGIN
@@ -1659,6 +1790,63 @@
 	wire_reset_state_w_lg_q1671w(0) <= NOT reset_state;
 	PROCESS (clock, reset)
 	BEGIN
+		IF (reset = '1') THEN rom_data_state <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN rom_data_state <= (rom_second_state OR (wire_rom_data_state_w_lg_q1868w(0) AND wire_w_lg_reset_rom_address1752w(0)));
+		END IF;
+	END PROCESS;
+	wire_rom_data_state_w_lg_q1868w(0) <= rom_data_state AND wire_w_lg_read_addr_counter_done1867w(0);
+	wire_rom_data_state_w_lg_q1889w(0) <= rom_data_state AND wire_w_lg_rom_width_counter_done1888w(0);
+	wire_rom_data_state_w_lg_w_lg_q1897w1933w(0) <= NOT wire_rom_data_state_w_lg_q1897w(0);
+	wire_rom_data_state_w_lg_q1716w(0) <= NOT rom_data_state;
+	wire_rom_data_state_w_lg_w_lg_q1897w1898w(0) <= wire_rom_data_state_w_lg_q1897w(0) OR rom_second_state;
+	wire_rom_data_state_w_lg_w_lg_q1929w1930w(0) <= wire_rom_data_state_w_lg_q1929w(0) OR rom_last_state;
+	wire_rom_data_state_w_lg_q1897w(0) <= rom_data_state OR rom_first_state;
+	wire_rom_data_state_w_lg_q1929w(0) <= rom_data_state OR rom_second_last_state;
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN rom_first_state <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN rom_first_state <= rom_init_state;
+		END IF;
+	END PROCESS;
+	wire_rom_first_state_w_lg_w_lg_w_lg_w_lg_q1943w1944w1945w1947w(0) <= NOT wire_rom_first_state_w_lg_w_lg_w_lg_q1943w1944w1945w(0);
+	wire_rom_first_state_w_lg_q1712w(0) <= NOT rom_first_state;
+	wire_rom_first_state_w_lg_w_lg_w_lg_q1943w1944w1945w(0) <= wire_rom_first_state_w_lg_w_lg_q1943w1944w(0) OR rom_last_state;
+	wire_rom_first_state_w_lg_w_lg_q1943w1944w(0) <= wire_rom_first_state_w_lg_q1943w(0) OR rom_second_last_state;
+	wire_rom_first_state_w_lg_w_lg_q1885w1886w(0) <= wire_rom_first_state_w_lg_q1885w(0) OR rom_data_state;
+	wire_rom_first_state_w_lg_q1943w(0) <= rom_first_state OR rom_data_state;
+	wire_rom_first_state_w_lg_q1885w(0) <= rom_first_state OR rom_second_state;
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN rom_init_state <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN rom_init_state <= (((((idle_state AND write_from_rom) OR (rom_first_state AND reset_rom_address)) OR (rom_second_state AND reset_rom_address)) OR (rom_data_state AND reset_rom_address)) OR (rom_second_last_state AND reset_rom_address));
+		END IF;
+	END PROCESS;
+	wire_rom_init_state_w_lg_q1710w(0) <= NOT rom_init_state;
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN rom_last_state <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN rom_last_state <= wire_rom_second_last_state_w_lg_q1754w(0);
+		END IF;
+	END PROCESS;
+	wire_rom_last_state_w_lg_q1753w(0) <= rom_last_state AND wire_w_lg_reset_rom_address1752w(0);
+	wire_rom_last_state_w_lg_q1720w(0) <= NOT rom_last_state;
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN rom_second_last_state <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN rom_second_last_state <= ((rom_data_state AND read_addr_counter_done) AND wire_w_lg_reset_rom_address1752w(0));
+		END IF;
+	END PROCESS;
+	wire_rom_second_last_state_w_lg_q1754w(0) <= rom_second_last_state AND wire_w_lg_reset_rom_address1752w(0);
+	wire_rom_second_last_state_w_lg_q1718w(0) <= NOT rom_second_last_state;
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN rom_second_state <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN rom_second_state <= (rom_first_state AND wire_w_lg_reset_rom_address1752w(0));
+		END IF;
+	END PROCESS;
+	wire_rom_second_state_w_lg_q1714w(0) <= NOT rom_second_state;
+	PROCESS (clock, reset)
+	BEGIN
 		IF (reset = '1') THEN shift_reg0 <= '0';
 		ELSIF (clock = '1' AND clock'event) THEN 
 			IF (wire_shift_reg_ena(0) = '1') THEN 
@@ -1881,12 +2069,12 @@
 	wire_shift_reg_w_lg_q276w(0) <= shift_reg17 AND wire_w_shift_reg_width_select_range275w(0);
 	wire_shift_reg_w_lg_q279w(0) <= shift_reg17 AND wire_w_shift_reg_width_select_range278w(0);
 	wire_shift_reg_w_lg_q282w(0) <= shift_reg17 AND wire_w_shift_reg_width_select_range281w(0);
-	loop13 : FOR i IN 0 TO 17 GENERATE
+	loop16 : FOR i IN 0 TO 17 GENERATE
 		wire_shift_reg_ena(i) <= wire_w63w(0);
-	END GENERATE loop13;
+	END GENERATE loop16;
 	PROCESS (clock)
 	BEGIN
-		IF (clock = '1' AND clock'event) THEN tmp_nominal_data_out_state <= (wire_read_last_nominal_state_w_lg_q1865w(0) OR (tmp_nominal_data_out_state AND idle_state));
+		IF (clock = '1' AND clock'event) THEN tmp_nominal_data_out_state <= (wire_read_last_nominal_state_w_lg_q1917w(0) OR (tmp_nominal_data_out_state AND idle_state));
 		END IF;
 	END PROCESS;
 	PROCESS (clock)
@@ -1897,10 +2085,10 @@
 	PROCESS (clock, reset)
 	BEGIN
 		IF (reset = '1') THEN write_data_state <= '0';
-		ELSIF (clock = '1' AND clock'event) THEN write_data_state <= (write_init_state OR (write_data_state AND wire_w_lg_width_counter_done1744w(0)));
+		ELSIF (clock = '1' AND clock'event) THEN write_data_state <= (write_init_state OR (write_data_state AND wire_w_lg_width_counter_done1764w(0)));
 		END IF;
 	END PROCESS;
-	wire_write_data_state_w_lg_q1726w(0) <= write_data_state AND width_counter_done;
+	wire_write_data_state_w_lg_q1738w(0) <= write_data_state AND width_counter_done;
 	wire_write_data_state_w_lg_q1692w(0) <= NOT write_data_state;
 	PROCESS (clock, reset)
 	BEGIN
@@ -1916,14 +2104,14 @@
 		END IF;
 	END PROCESS;
 	wire_write_init_state_w_lg_q1690w(0) <= NOT write_init_state;
-	wire_write_init_state_w_lg_q1853w(0) <= write_init_state OR write_init_nominal_state;
+	wire_write_init_state_w_lg_q1900w(0) <= write_init_state OR write_init_nominal_state;
 	PROCESS (clock, reset)
 	BEGIN
 		IF (reset = '1') THEN write_nominal_state <= '0';
-		ELSIF (clock = '1' AND clock'event) THEN write_nominal_state <= (write_init_nominal_state OR (write_nominal_state AND wire_w_lg_width_counter_done1744w(0)));
+		ELSIF (clock = '1' AND clock'event) THEN write_nominal_state <= (write_init_nominal_state OR (write_nominal_state AND wire_w_lg_width_counter_done1764w(0)));
 		END IF;
 	END PROCESS;
-	wire_write_nominal_state_w_lg_q1725w(0) <= write_nominal_state AND width_counter_done;
+	wire_write_nominal_state_w_lg_q1737w(0) <= write_nominal_state AND width_counter_done;
 	wire_write_nominal_state_w_lg_q1696w(0) <= NOT write_nominal_state;
 	wire_add_sub5_w_lg_w_result_range214w215w(0) <= wire_add_sub5_w_result_range214w(0) AND read_nominal_out;
 	wire_add_sub5_w_lg_w_result_range221w222w(0) <= wire_add_sub5_w_result_range221w(0) AND read_nominal_out;
@@ -2021,6 +2209,19 @@
 	  GENERIC MAP (
 		lpm_direction => "DOWN",
 		lpm_port_updown => "PORT_UNUSED",
+		lpm_width => 8
+	  )
+	  PORT MAP ( 
+		clock => clock,
+		cnt_en => rom_width_counter_enable,
+		data => rom_width_counter_sload_value,
+		q => wire_cntr14_q,
+		sload => rom_width_counter_sload
+	  );
+	cntr15 :  lpm_counter
+	  GENERIC MAP (
+		lpm_direction => "DOWN",
+		lpm_port_updown => "PORT_UNUSED",
 		lpm_width => 5
 	  )
 	  PORT MAP ( 
@@ -2027,10 +2228,10 @@
 		clock => clock,
 		cnt_en => rotate_width_counter_enable,
 		data => rotate_width_counter_sload_value,
-		q => wire_cntr14_q,
+		q => wire_cntr15_q,
 		sload => rotate_width_counter_sload
 	  );
-	cntr15 :  lpm_counter
+	cntr16 :  lpm_counter
 	  GENERIC MAP (
 		lpm_direction => "DOWN",
 		lpm_modulus => 144,
@@ -2041,7 +2242,7 @@
 		clock => clock,
 		cnt_en => rotate_addr_counter_enable,
 		data => rotate_addr_counter_sload_value,
-		q => wire_cntr15_q,
+		q => wire_cntr16_q,
 		sload => rotate_addr_counter_sload
 	  );
 	cntr2 :  lpm_counter
@@ -2080,7 +2281,7 @@
 		eq => wire_decode11_eq
 	  );
 
- END RTL; --video_pll_reconfig_pllrcfg_6bu
+ END RTL; --video_pll_reconfig_pllrcfg_op51
 --VALID FILE
 
 
@@ -2100,6 +2301,9 @@
 		read_param		: IN STD_LOGIC ;
 		reconfig		: IN STD_LOGIC ;
 		reset		: IN STD_LOGIC ;
+		reset_rom_address		: IN STD_LOGIC  := '0';
+		rom_data_in		: IN STD_LOGIC  := '0';
+		write_from_rom		: IN STD_LOGIC  := '0';
 		write_param		: IN STD_LOGIC ;
 		busy		: OUT STD_LOGIC ;
 		data_out		: OUT STD_LOGIC_VECTOR (8 DOWNTO 0);
@@ -2107,7 +2311,9 @@
 		pll_configupdate		: OUT STD_LOGIC ;
 		pll_scanclk		: OUT STD_LOGIC ;
 		pll_scanclkena		: OUT STD_LOGIC ;
-		pll_scandata		: OUT STD_LOGIC 
+		pll_scandata		: OUT STD_LOGIC ;
+		rom_address_out		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+		write_rom_ena		: OUT STD_LOGIC 
 	);
 END video_pll_reconfig;
 
@@ -2125,12 +2331,14 @@
 	SIGNAL sub_wire2	: STD_LOGIC ;
 	SIGNAL sub_wire3	: STD_LOGIC ;
 	SIGNAL sub_wire4	: STD_LOGIC ;
-	SIGNAL sub_wire5	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (7 DOWNTO 0);
 	SIGNAL sub_wire6	: STD_LOGIC ;
+	SIGNAL sub_wire7	: STD_LOGIC ;
+	SIGNAL sub_wire8	: STD_LOGIC ;
 
 
 
-	COMPONENT video_pll_reconfig_pllrcfg_6bu
+	COMPONENT video_pll_reconfig_pllrcfg_op51
 	PORT (
 			counter_param	: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
 			data_in	: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
@@ -2138,18 +2346,23 @@
 			counter_type	: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
 			data_out	: OUT STD_LOGIC_VECTOR (8 DOWNTO 0);
 			pll_areset_in	: IN STD_LOGIC ;
-			reconfig	: IN STD_LOGIC ;
 			pll_scanclk	: OUT STD_LOGIC ;
 			pll_scanclkena	: OUT STD_LOGIC ;
 			pll_scandata	: OUT STD_LOGIC ;
 			pll_scandataout	: IN STD_LOGIC ;
 			pll_scandone	: IN STD_LOGIC ;
+			rom_address_out	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
 			busy	: OUT STD_LOGIC ;
 			pll_areset	: OUT STD_LOGIC ;
 			reset	: IN STD_LOGIC ;
+			write_from_rom	: IN STD_LOGIC ;
 			write_param	: IN STD_LOGIC ;
+			write_rom_ena	: OUT STD_LOGIC ;
 			clock	: IN STD_LOGIC ;
-			read_param	: IN STD_LOGIC 
+			read_param	: IN STD_LOGIC ;
+			reconfig	: IN STD_LOGIC ;
+			reset_rom_address	: IN STD_LOGIC ;
+			rom_data_in	: IN STD_LOGIC 
 	);
 	END COMPONENT;
 
@@ -2159,29 +2372,36 @@
 	pll_scanclk    <= sub_wire2;
 	pll_scanclkena    <= sub_wire3;
 	pll_scandata    <= sub_wire4;
-	busy    <= sub_wire5;
-	pll_areset    <= sub_wire6;
+	rom_address_out    <= sub_wire5(7 DOWNTO 0);
+	busy    <= sub_wire6;
+	pll_areset    <= sub_wire7;
+	write_rom_ena    <= sub_wire8;
 
-	video_pll_reconfig_pllrcfg_6bu_component : video_pll_reconfig_pllrcfg_6bu
+	video_pll_reconfig_pllrcfg_op51_component : video_pll_reconfig_pllrcfg_op51
 	PORT MAP (
 		counter_param => counter_param,
 		data_in => data_in,
 		counter_type => counter_type,
 		pll_areset_in => pll_areset_in,
-		reconfig => reconfig,
 		pll_scandataout => pll_scandataout,
 		pll_scandone => pll_scandone,
 		reset => reset,
+		write_from_rom => write_from_rom,
 		write_param => write_param,
 		clock => clock,
 		read_param => read_param,
+		reconfig => reconfig,
+		reset_rom_address => reset_rom_address,
+		rom_data_in => rom_data_in,
 		pll_configupdate => sub_wire0,
 		data_out => sub_wire1,
 		pll_scanclk => sub_wire2,
 		pll_scanclkena => sub_wire3,
 		pll_scandata => sub_wire4,
-		busy => sub_wire5,
-		pll_areset => sub_wire6
+		rom_address_out => sub_wire5,
+		busy => sub_wire6,
+		pll_areset => sub_wire7,
+		write_rom_ena => sub_wire8
 	);
 
 
@@ -2216,7 +2436,12 @@
 -- Retrieval info: USED_PORT: read_param 0 0 0 0 INPUT NODEFVAL "read_param"
 -- Retrieval info: USED_PORT: reconfig 0 0 0 0 INPUT NODEFVAL "reconfig"
 -- Retrieval info: USED_PORT: reset 0 0 0 0 INPUT NODEFVAL "reset"
+-- Retrieval info: USED_PORT: reset_rom_address 0 0 0 0 INPUT GND "reset_rom_address"
+-- Retrieval info: USED_PORT: rom_address_out 0 0 8 0 OUTPUT NODEFVAL "rom_address_out[7..0]"
+-- Retrieval info: USED_PORT: rom_data_in 0 0 0 0 INPUT GND "rom_data_in"
+-- Retrieval info: USED_PORT: write_from_rom 0 0 0 0 INPUT GND "write_from_rom"
 -- Retrieval info: USED_PORT: write_param 0 0 0 0 INPUT NODEFVAL "write_param"
+-- Retrieval info: USED_PORT: write_rom_ena 0 0 0 0 OUTPUT NODEFVAL "write_rom_ena"
 -- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
 -- Retrieval info: CONNECT: @counter_param 0 0 3 0 counter_param 0 0 3 0
 -- Retrieval info: CONNECT: @counter_type 0 0 4 0 counter_type 0 0 4 0
@@ -2227,6 +2452,9 @@
 -- Retrieval info: CONNECT: @read_param 0 0 0 0 read_param 0 0 0 0
 -- Retrieval info: CONNECT: @reconfig 0 0 0 0 reconfig 0 0 0 0
 -- Retrieval info: CONNECT: @reset 0 0 0 0 reset 0 0 0 0
+-- Retrieval info: CONNECT: @reset_rom_address 0 0 0 0 reset_rom_address 0 0 0 0
+-- Retrieval info: CONNECT: @rom_data_in 0 0 0 0 rom_data_in 0 0 0 0
+-- Retrieval info: CONNECT: @write_from_rom 0 0 0 0 write_from_rom 0 0 0 0
 -- Retrieval info: CONNECT: @write_param 0 0 0 0 write_param 0 0 0 0
 -- Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0
 -- Retrieval info: CONNECT: data_out 0 0 9 0 @data_out 0 0 9 0
@@ -2235,6 +2463,8 @@
 -- Retrieval info: CONNECT: pll_scanclk 0 0 0 0 @pll_scanclk 0 0 0 0
 -- Retrieval info: CONNECT: pll_scanclkena 0 0 0 0 @pll_scanclkena 0 0 0 0
 -- Retrieval info: CONNECT: pll_scandata 0 0 0 0 @pll_scandata 0 0 0 0
+-- Retrieval info: CONNECT: rom_address_out 0 0 8 0 @rom_address_out 0 0 8 0
+-- Retrieval info: CONNECT: write_rom_ena 0 0 0 0 @write_rom_ena 0 0 0 0
 -- Retrieval info: GEN_FILE: TYPE_NORMAL video_pll_reconfig.vhd TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL video_pll_reconfig.inc FALSE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL video_pll_reconfig.cmp TRUE
Index: mist/zpu_rom.cmp
===================================================================
--- mist/zpu_rom.cmp	(revision 1315)
+++ mist/zpu_rom.cmp	(revision 1316)
@@ -1,4 +1,4 @@
---Copyright (C) 1991-2013 Altera Corporation
+--Copyright (C) 1991-2014 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 
@@ -16,7 +16,7 @@
 component zpu_rom
 	PORT
 	(
-		address		: IN STD_LOGIC_VECTOR (12 DOWNTO 0);
+		address		: IN STD_LOGIC_VECTOR (11 DOWNTO 0);
 		clock		: IN STD_LOGIC  := '1';
 		q		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
 	);
Index: mist/zpu_rom.mif
===================================================================
--- mist/zpu_rom.mif	(revision 1315)
+++ mist/zpu_rom.mif	(revision 1316)
@@ -9,7 +9,7 @@
 CONTENT 
 BEGIN 
 0000 : 0b0b0b89;
-0001 : ad040b0b;
+0001 : ab040b0b;
 0002 : 0b0b0b0b;
 0003 : 0b0b0b0b;
 0004 : 0b0b0b0b;
@@ -169,8 +169,8 @@
 009e : 00000000;
 009f : 00000000;
 00a0 : 71fc0608;
-00a1 : 0b0b81a1;
-00a2 : fc738306;
+00a1 : 0b0b80d4;
+00a2 : dc738306;
 00a3 : 10100508;
 00a4 : 060b0b0b;
 00a5 : 88a20400;
@@ -177,7 +177,7 @@
 00a6 : 00000000;
 00a7 : 00000000;
 00a8 : 0b0b0b88;
-00a9 : ff040000;
+00a9 : fe040000;
 00aa : 00000000;
 00ab : 00000000;
 00ac : 00000000;
@@ -216,8 +216,8 @@
 00cd : 00000000;
 00ce : 00000000;
 00cf : 00000000;
-00d0 : 810b81ad;
-00d1 : 840c5104;
+00d0 : 810b80d6;
+00d1 : a00c5104;
 00d2 : 00000000;
 00d3 : 00000000;
 00d4 : 00000000;
@@ -289,5399 +289,2567 @@
 0116 : 83c08008;
 0117 : 83c08408;
 0118 : 83c08808;
-0119 : 7575819c;
-011a : 822d5050;
-011b : 83c08008;
-011c : 5683c088;
-011d : 0c83c084;
-011e : 0c83c080;
-011f : 0c510483;
-0120 : c0800883;
-0121 : c0840883;
-0122 : c0880875;
-0123 : 75819bc1;
-0124 : 2d505083;
-0125 : c0800856;
-0126 : 83c0880c;
-0127 : 83c0840c;
-0128 : 83c0800c;
-0129 : 51040000;
-012a : 800489aa;
-012b : 0489aa0b;
-012c : 80e4b404;
-012d : fd3d0d75;
-012e : 705254ae;
-012f : c63f83c0;
-0130 : 80081453;
-0131 : 72742e92;
-0132 : 38ff1370;
-0133 : 33535371;
-0134 : af2e0981;
-0135 : 06ee3881;
-0136 : 13537283;
-0137 : c0800c85;
-0138 : 3d0d04fd;
-0139 : 3d0d7577;
-013a : 70535454;
-013b : c73f83c0;
-013c : 8008732e;
-013d : a13883c0;
-013e : 80087331;
-013f : 52ff1252;
-0140 : 71ff2e8f;
-0141 : 38727081;
-0142 : 05543374;
-0143 : 70810556;
-0144 : 34eb39ff;
-0145 : 14548074;
-0146 : 34853d0d;
-0147 : 04803d0d;
-0148 : 7251ff90;
-0149 : 3f823d0d;
-014a : 047183c0;
-014b : 800c0480;
-014c : 3d0d7251;
-014d : 80713481;
-014e : 0bbc120c;
-014f : 800b80c0;
-0150 : 120c823d;
-0151 : 0d04800b;
-0152 : 83c2c808;
-0153 : 248a38b5;
-0154 : 9b3fff0b;
-0155 : 83c2c80c;
-0156 : 800b83c0;
-0157 : 800c04ff;
-0158 : 3d0d7352;
-0159 : 83c0a408;
-015a : 722e9b38;
-015b : d93f8183;
-015c : 0b9088a0;
-015d : 0c715196;
-015e : c93f8193;
-015f : 0b9088a0;
-0160 : 0c7183c0;
-0161 : a40c833d;
-0162 : 0d04f43d;
-0163 : 0d7e6062;
-0164 : 5c5a5580;
-0165 : 568154bc;
-0166 : 1508762e;
-0167 : 09810681;
-0168 : 92387451;
-0169 : ffb93f79;
-016a : 58757a25;
-016b : 80f73883;
-016c : c2f80870;
-016d : 892a5783;
-016e : ff067884;
-016f : 80723156;
-0170 : 56577378;
-0171 : 25833873;
-0172 : 557583c2;
-0173 : c8082e84;
-0174 : 38fef33f;
-0175 : 83c2c808;
-0176 : 8025a638;
-0177 : 75892b51;
-0178 : 98fd3f83;
-0179 : c2f8088f;
-017a : 3dfc1155;
-017b : 5c548152;
-017c : f81b5196;
-017d : e73f7614;
-017e : 83c2f80c;
-017f : 7583c2c8;
-0180 : 0c745376;
-0181 : 527851b3;
-0182 : b63f83c0;
-0183 : 800883c2;
-0184 : f8081683;
-0185 : c2f80c78;
-0186 : 7631761b;
-0187 : 5b595677;
-0188 : 8024ff8b;
-0189 : 38617a71;
-018a : 0c547554;
-018b : 75802e83;
-018c : 38815473;
-018d : 83c0800c;
-018e : 8e3d0d04;
-018f : fc3d0dfe;
-0190 : 853f7651;
-0191 : fe993f86;
-0192 : 3dfc0553;
-0193 : 78527751;
-0194 : 968a3f79;
-0195 : 75710c54;
-0196 : 83c08008;
-0197 : 5483c080;
-0198 : 08802e83;
-0199 : 38815473;
-019a : 83c0800c;
-019b : 863d0d04;
-019c : fe3d0d75;
-019d : 83c2c808;
-019e : 53538072;
-019f : 24953871;
-01a0 : 732e9038;
-01a1 : 80c30b90;
-01a2 : 88a00c71;
-01a3 : 9088a40c;
-01a4 : fdb43f80;
-01a5 : d30b9088;
-01a6 : a00c7451;
-01a7 : fdc13f80;
-01a8 : e30b9088;
-01a9 : a00c7251;
-01aa : 97b53f80;
-01ab : f30b9088;
-01ac : a00c83c0;
-01ad : 80085283;
-01ae : c0800880;
-01af : 2e833881;
-01b0 : 527183c0;
-01b1 : 800c843d;
-01b2 : 0d04803d;
-01b3 : 0d7280c0;
-01b4 : 110883c0;
-01b5 : 800c5182;
-01b6 : 3d0d0480;
-01b7 : 3d0d72bc;
-01b8 : 110883c0;
-01b9 : 800c5182;
-01ba : 3d0d0480;
-01bb : c40b83c0;
-01bc : 800c04fd;
-01bd : 3d0d7577;
-01be : 71547053;
-01bf : 5553a9e7;
-01c0 : 3f82c813;
-01c1 : 08bc150c;
-01c2 : 82c01308;
-01c3 : 80c0150c;
-01c4 : fcb43f73;
-01c5 : 5193ab3f;
-01c6 : 7383c0a4;
-01c7 : 0c83c080;
-01c8 : 085383c0;
-01c9 : 8008802e;
-01ca : 83388153;
-01cb : 7283c080;
-01cc : 0c853d0d;
-01cd : 04fd3d0d;
-01ce : 75775553;
-01cf : fc883f72;
-01d0 : 802ea538;
-01d1 : bc130852;
-01d2 : 7351a8f1;
-01d3 : 3f83c080;
-01d4 : 088f3877;
-01d5 : 527251ff;
-01d6 : 9a3f83c0;
-01d7 : 8008538a;
-01d8 : 3982cc13;
-01d9 : 0853d839;
-01da : 81537283;
-01db : c0800c85;
-01dc : 3d0d04fe;
-01dd : 3d0dff0b;
-01de : 83c2c80c;
-01df : 7483c0a8;
-01e0 : 0c7583c2;
-01e1 : c40cafc9;
-01e2 : 3f83c080;
-01e3 : 0881ff06;
-01e4 : 52815371;
-01e5 : 993883c2;
-01e6 : e0518e94;
-01e7 : 3f83c080;
-01e8 : 085283c0;
-01e9 : 8008802e;
-01ea : 83387252;
-01eb : 71537283;
-01ec : c0800c84;
-01ed : 3d0d04fa;
-01ee : 3d0d787a;
-01ef : 82c41208;
-01f0 : 82c41208;
-01f1 : 70722459;
-01f2 : 56565757;
-01f3 : 73732e09;
-01f4 : 81069138;
-01f5 : 80c01652;
-01f6 : 80c01751;
-01f7 : a6e23f83;
-01f8 : c0800855;
-01f9 : 7483c080;
-01fa : 0c883d0d;
-01fb : 04f63d0d;
-01fc : 7c5b807b;
-01fd : 715c5457;
-01fe : 7a772e8c;
-01ff : 38811a82;
-0200 : cc140854;
-0201 : 5a72f638;
-0202 : 805980d9;
-0203 : 397a5481;
-0204 : 5780707b;
-0205 : 7b315a57;
-0206 : 55ff1853;
-0207 : 74732580;
-0208 : c13882cc;
-0209 : 14085273;
-020a : 51ff8c3f;
-020b : 800b83c0;
-020c : 800825a1;
-020d : 3882cc14;
-020e : 0882cc11;
-020f : 0882cc16;
-0210 : 0c7482cc;
-0211 : 120c5375;
-0212 : 802e8638;
-0213 : 7282cc17;
-0214 : 0c725480;
-0215 : 577382cc;
-0216 : 15088117;
-0217 : 575556ff;
-0218 : b8398119;
-0219 : 59800bff;
-021a : 1b545478;
-021b : 73258338;
-021c : 81547681;
-021d : 32707506;
-021e : 515372ff;
-021f : 90388c3d;
-0220 : 0d04f73d;
-0221 : 0d7b7d5a;
-0222 : 5a82d052;
-0223 : 83c2c408;
-0224 : 51818a8d;
-0225 : 3f83c080;
-0226 : 0857f9aa;
-0227 : 3f795283;
-0228 : c2cc5195;
-0229 : b73f83c0;
-022a : 80085480;
-022b : 5383c080;
-022c : 08732e09;
-022d : 81068283;
-022e : 3883c0a8;
-022f : 080b0b81;
-0230 : a6ec5370;
-0231 : 5256a69f;
-0232 : 3f0b0b81;
-0233 : a6ec5280;
-0234 : c01651a6;
-0235 : 923f75bc;
-0236 : 170c7382;
-0237 : c0170c81;
-0238 : 0b82c417;
-0239 : 0c810b82;
-023a : c8170c73;
-023b : 82cc170c;
-023c : ff1782d0;
-023d : 17555781;
-023e : 913983c0;
-023f : b4337082;
-0240 : 2a708106;
-0241 : 51545572;
-0242 : 81803874;
-0243 : 812a8106;
-0244 : 587780f6;
-0245 : 3874842a;
-0246 : 810682c4;
-0247 : 150c83c0;
-0248 : b4338106;
-0249 : 82c8150c;
-024a : 79527351;
-024b : a5b93f73;
-024c : 51a5d03f;
-024d : 83c08008;
-024e : 1453af73;
-024f : 70810555;
-0250 : 3472bc15;
-0251 : 0c83c0b5;
-0252 : 527251a5;
-0253 : 9a3f83c0;
-0254 : ac0882c0;
-0255 : 150c83c0;
-0256 : c25280c0;
-0257 : 1451a587;
-0258 : 3f78802e;
-0259 : 8d387351;
-025a : 782d83c0;
-025b : 8008802e;
-025c : 99387782;
-025d : cc150c75;
-025e : 802e8638;
-025f : 7382cc17;
-0260 : 0c7382d0;
-0261 : 15ff1959;
-0262 : 55567680;
-0263 : 2e9b3883;
-0264 : c0ac5283;
-0265 : c2cc5194;
-0266 : ad3f83c0;
-0267 : 80088a38;
-0268 : 83c0b533;
-0269 : 5372fed2;
-026a : 3878802e;
-026b : 893883c0;
-026c : a80851fc;
-026d : b83f83c0;
-026e : a8085372;
-026f : 83c0800c;
-0270 : 8b3d0d04;
-0271 : ff3d0d80;
-0272 : 527351fd;
-0273 : b53f833d;
-0274 : 0d04f03d;
-0275 : 0d627052;
-0276 : 54f5d93f;
-0277 : 83c08008;
-0278 : 7453873d;
-0279 : 70535555;
-027a : f5f93ff6;
-027b : d93f7351;
-027c : d33f6353;
-027d : 745283c0;
-027e : 800851fa;
-027f : b83f923d;
-0280 : 0d047183;
-0281 : c0800c04;
-0282 : 80c01283;
-0283 : c0800c04;
-0284 : 803d0d72;
-0285 : 82c01108;
-0286 : 83c0800c;
-0287 : 51823d0d;
-0288 : 04803d0d;
-0289 : 7282cc11;
-028a : 0883c080;
-028b : 0c51823d;
-028c : 0d04803d;
-028d : 0d7282c4;
-028e : 110883c0;
-028f : 800c5182;
-0290 : 3d0d04f9;
-0291 : 3d0d7983;
-0292 : c0900857;
-0293 : 57817727;
-0294 : 81963876;
-0295 : 88170827;
-0296 : 818e3875;
-0297 : 33557482;
-0298 : 2e893874;
-0299 : 832eb338;
-029a : 80fe3974;
-029b : 54761083;
-029c : fe065376;
-029d : 882a8c17;
-029e : 08055289;
-029f : 3dfc0551;
-02a0 : a9f73f83;
-02a1 : c0800880;
-02a2 : df38029d;
-02a3 : 0533893d;
-02a4 : 3371882b;
-02a5 : 07565680;
-02a6 : d1398454;
-02a7 : 76822b83;
-02a8 : fc065376;
-02a9 : 872a8c17;
-02aa : 08055289;
-02ab : 3dfc0551;
-02ac : a9c73f83;
-02ad : c08008b0;
-02ae : 38029f05;
-02af : 33028405;
-02b0 : 9e053371;
-02b1 : 982b7190;
-02b2 : 2b07028c;
-02b3 : 059d0533;
-02b4 : 70882b72;
-02b5 : 078d3d33;
-02b6 : 7180ffff;
-02b7 : fe800607;
-02b8 : 51525357;
-02b9 : 58568339;
-02ba : 81557483;
-02bb : c0800c89;
-02bc : 3d0d04fb;
-02bd : 3d0d83c0;
-02be : 9008fe19;
-02bf : 881208fe;
-02c0 : 05555654;
-02c1 : 80567473;
-02c2 : 278d3882;
-02c3 : 14337571;
-02c4 : 29941608;
-02c5 : 05575375;
-02c6 : 83c0800c;
-02c7 : 873d0d04;
-02c8 : fc3d0d76;
-02c9 : 52800b83;
-02ca : c0900870;
-02cb : 33515253;
-02cc : 70832e09;
-02cd : 81069138;
-02ce : 95123394;
-02cf : 13337198;
-02d0 : 2b71902b;
-02d1 : 07555551;
-02d2 : 9b12339a;
-02d3 : 13337188;
-02d4 : 2b077407;
-02d5 : 83c0800c;
-02d6 : 55863d0d;
-02d7 : 04fc3d0d;
-02d8 : 7683c090;
-02d9 : 08555580;
-02da : 75238815;
-02db : 08537281;
-02dc : 2e883888;
-02dd : 14087326;
-02de : 85388152;
-02df : b2397290;
-02e0 : 38733352;
-02e1 : 71832e09;
-02e2 : 81068538;
-02e3 : 90140853;
-02e4 : 728c160c;
-02e5 : 72802e8d;
-02e6 : 387251fe;
-02e7 : d63f83c0;
-02e8 : 80085285;
-02e9 : 39901408;
-02ea : 52719016;
-02eb : 0c805271;
-02ec : 83c0800c;
-02ed : 863d0d04;
-02ee : fa3d0d78;
-02ef : 83c09008;
-02f0 : 71228105;
-02f1 : 7083ffff;
-02f2 : 06575457;
-02f3 : 5573802e;
-02f4 : 88389015;
-02f5 : 08537286;
-02f6 : 38835280;
-02f7 : e739738f;
-02f8 : 06527180;
-02f9 : da388113;
-02fa : 90160c8c;
-02fb : 15085372;
-02fc : 9038830b;
-02fd : 84172257;
-02fe : 52737627;
-02ff : 80c638bf;
-0300 : 39821633;
-0301 : ff057484;
-0302 : 2a065271;
-0303 : b2387251;
-0304 : fcb13f81;
-0305 : 527183c0;
-0306 : 800827a8;
-0307 : 38835283;
-0308 : c0800888;
-0309 : 1708279c;
-030a : 3883c080;
-030b : 088c160c;
-030c : 83c08008;
-030d : 51fdbc3f;
-030e : 83c08008;
-030f : 90160c73;
-0310 : 75238052;
-0311 : 7183c080;
-0312 : 0c883d0d;
-0313 : 04f23d0d;
-0314 : 60626458;
-0315 : 5e5b7533;
-0316 : 5574a02e;
-0317 : 09810688;
-0318 : 38811670;
-0319 : 4456ef39;
-031a : 62703356;
-031b : 5674af2e;
-031c : 09810684;
-031d : 38811643;
-031e : 800b881c;
-031f : 0c627033;
-0320 : 5155749f;
-0321 : 2691387a;
-0322 : 51fdd23f;
-0323 : 83c08008;
-0324 : 56807d34;
-0325 : 83813993;
-0326 : 3d841c08;
-0327 : 7058595f;
-0328 : 8a55a076;
-0329 : 70810558;
-032a : 34ff1555;
-032b : 74ff2e09;
-032c : 8106ef38;
-032d : 80705a5c;
-032e : 887f085f;
-032f : 5a7b811d;
-0330 : 7081ff06;
-0331 : 60137033;
-0332 : 70af3270;
-0333 : 30a07327;
-0334 : 71802507;
-0335 : 5151525b;
-0336 : 535e5755;
-0337 : 7480e738;
-0338 : 76ae2e09;
-0339 : 81068338;
-033a : 8155787a;
-033b : 27750755;
-033c : 74802e9f;
-033d : 38798832;
-033e : 703078ae;
-033f : 32703070;
-0340 : 73079f2a;
-0341 : 53515751;
-0342 : 5675bb38;
-0343 : 88598b5a;
-0344 : ffab3976;
-0345 : 982b5574;
-0346 : 80258738;
-0347 : 81a18c17;
-0348 : 3357ff9f;
-0349 : 17557499;
-034a : 268938e0;
-034b : 177081ff;
-034c : 06585578;
-034d : 811a7081;
-034e : ff06721b;
-034f : 535b5755;
-0350 : 767534fe;
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-1590 : 46617374;
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-15a0 : 62696e00;
-15a1 : 00000000;
-15a2 : 00000000;
-15a3 : 01010008;
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-15bf : 00000000;
-15c0 : 70704740;
-15c1 : 0c704268;
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+0a98 : ff00ffff;
+0a99 : ffff00ff;
+0a9a : ffffff00;
+0a9b : 25303278;
+0a9c : 00000000;
+0a9d : 58464400;
+0a9e : 41545800;
+0a9f : 5374616e;
+0aa0 : 64617264;
+0aa1 : 00000000;
+0aa2 : 46617374;
+0aa3 : 28362900;
+0aa4 : 46617374;
+0aa5 : 28352900;
+0aa6 : 46617374;
+0aa7 : 28342900;
+0aa8 : 46617374;
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+0aac : 46617374;
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+0aae : 46617374;
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+0ab0 : 52474200;
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+0ab2 : 444f5542;
+0ab3 : 4c450000;
+0ab4 : 53564944;
+0ab5 : 454f0000;
+0ab6 : 48444d49;
+0ab7 : 00000000;
+0ab8 : 44564900;
+0ab9 : 56474100;
+0aba : 434f4d50;
+0abb : 4f534954;
+0abc : 45000000;
+0abd : 4e545343;
+0abe : 00000000;
+0abf : 50414c00;
+0ac0 : 73657474;
+0ac1 : 696e6773;
+0ac2 : 00000000;
+0ac3 : 524f4d00;
+0ac4 : 42494e00;
+0ac5 : 43415200;
+0ac6 : 4d454d00;
+0ac7 : 52504400;
+0ac8 : 00000000;
+0ac9 : 00000000;
+0aca : 70704740;
+0acb : 0c704268;
+0acc : 0c020202;
+0acd : 02020202;
+0ace : 02020202;
+0acf : 02020202;
+0ad0 : 02020202;
+0ad1 : 02020241;
+0ad2 : 00060000;
+0ad3 : 72025f07;
+0ad4 : f807a900;
+0ad5 : 8d04038d;
+0ad6 : 4402a907;
+0ad7 : 8d0503a9;
+0ad8 : 708d0a03;
+0ad9 : a9018d0b;
+0ada : 03850960;
+0adb : 7d8a4820;
+0adc : 53e488d0;
+0add : fa68aa8c;
+0ade : 8e07ad7d;
+0adf : 07ee8e07;
+0ae0 : 60a9938d;
+0ae1 : e202a907;
+0ae2 : 8de302a2;
+0ae3 : 0220da07;
+0ae4 : 954320da;
+0ae5 : 07954435;
+0ae6 : 43c9fff0;
+0ae7 : f0caca10;
+0ae8 : ec3006e6;
+0ae9 : 45d002e6;
+0aea : 4620da07;
+0aeb : a2018144;
+0aec : b545d543;
+0aed : d0edca10;
+0aee : f720d207;
+0aef : 4c9407a9;
+0af0 : 038d0fd2;
+0af1 : 6ce202ad;
+0af2 : 8e07cd7f;
+0af3 : 07d0abee;
+0af4 : 0a03d003;
+0af5 : ee0b03ad;
+0af6 : 7d070d7e;
+0af7 : 07d08e20;
+0af8 : d2076ce0;
+0af9 : 0220da07;
+0afa : 8de00220;
+0afb : da078de1;
+0afc : 022de002;
+0afd : c9fff0ed;
+0afe : a9008d8e;
+0aff : 07f08200;
+0b00 : 28060504;
+0b01 : 03020100;
+0b02 : 00002a7c;
+0b03 : 00002a88;
+0b04 : 00002a90;
+0b05 : 00002a98;
+0b06 : 00002aa0;
+0b07 : 00002aa8;
+0b08 : 00002ab0;
+0b09 : 00002ab8;
+0b0a : 2f617461;
+0b0b : 72693830;
+0b0c : 302f726f;
+0b0d : 6d000000;
+0b0e : 2f617461;
+0b0f : 72693830;
+0b10 : 302f7573;
+0b11 : 65720000;
+0b12 : 00002ac0;
+0b13 : 00002ac4;
+0b14 : 00002ad0;
+0b15 : 00002ad8;
+0b16 : 00002ae0;
+0b17 : 00002ae4;
+0b18 : 00002ae8;
+0b19 : 00002af4;
+0b1a : 00002afc;
+0b1b : 00002af8;
 END; 
Index: mist/zpu_rom.qip
===================================================================
--- mist/zpu_rom.qip	(revision 1315)
+++ mist/zpu_rom.qip	(revision 1316)
@@ -1,4 +1,4 @@
 set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
-set_global_assignment -name IP_TOOL_VERSION "13.0"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
 set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "zpu_rom.vhd"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "zpu_rom.cmp"]
Index: mist/zpu_rom.vhd
===================================================================
--- mist/zpu_rom.vhd	(revision 1315)
+++ mist/zpu_rom.vhd	(revision 1316)
@@ -14,11 +14,11 @@
 -- ************************************************************
 -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 --
--- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
+-- 13.1.4 Build 182 03/12/2014 Patches 4.26 SJ Web Edition
 -- ************************************************************
 
 
---Copyright (C) 1991-2013 Altera Corporation
+--Copyright (C) 1991-2014 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 
@@ -37,12 +37,12 @@
 USE ieee.std_logic_1164.all;
 
 LIBRARY altera_mf;
-USE altera_mf.all;
+USE altera_mf.altera_mf_components.all;
 
 ENTITY zpu_rom IS
 	PORT
 	(
-		address		: IN STD_LOGIC_VECTOR (12 DOWNTO 0);
+		address		: IN STD_LOGIC_VECTOR (11 DOWNTO 0);
 		clock		: IN STD_LOGIC  := '1';
 		q		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
 	);
@@ -53,32 +53,6 @@
 
 	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (31 DOWNTO 0);
 
-
-
-	COMPONENT altsyncram
-	GENERIC (
-		address_aclr_a		: STRING;
-		clock_enable_input_a		: STRING;
-		clock_enable_output_a		: STRING;
-		init_file		: STRING;
-		intended_device_family		: STRING;
-		lpm_hint		: STRING;
-		lpm_type		: STRING;
-		numwords_a		: NATURAL;
-		operation_mode		: STRING;
-		outdata_aclr_a		: STRING;
-		outdata_reg_a		: STRING;
-		widthad_a		: NATURAL;
-		width_a		: NATURAL;
-		width_byteena_a		: NATURAL
-	);
-	PORT (
-			address_a	: IN STD_LOGIC_VECTOR (12 DOWNTO 0);
-			clock0	: IN STD_LOGIC ;
-			q_a	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
-	);
-	END COMPONENT;
-
 BEGIN
 	q    <= sub_wire0(31 DOWNTO 0);
 
@@ -91,11 +65,11 @@
 		intended_device_family => "Cyclone III",
 		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
 		lpm_type => "altsyncram",
-		numwords_a => 8192,
+		numwords_a => 4096,
 		operation_mode => "ROM",
 		outdata_aclr_a => "NONE",
 		outdata_reg_a => "UNREGISTERED",
-		widthad_a => 13,
+		widthad_a => 12,
 		width_a => 32,
 		width_byteena_a => 1
 	)
@@ -130,7 +104,7 @@
 -- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
 -- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
 -- Retrieval info: PRIVATE: MIFfilename STRING "zpu_rom.mif"
--- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8192"
+-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
 -- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
 -- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
 -- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
@@ -137,7 +111,7 @@
 -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
 -- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
 -- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
--- Retrieval info: PRIVATE: WidthAddr NUMERIC "13"
+-- Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
 -- Retrieval info: PRIVATE: WidthData NUMERIC "32"
 -- Retrieval info: PRIVATE: rden NUMERIC "0"
 -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
@@ -148,17 +122,17 @@
 -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
 -- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
 -- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
--- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
 -- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
 -- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
 -- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
--- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
 -- Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
 -- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
--- Retrieval info: USED_PORT: address 0 0 13 0 INPUT NODEFVAL "address[12..0]"
+-- Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
 -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
 -- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
--- Retrieval info: CONNECT: @address_a 0 0 13 0 address 0 0 13 0
+-- Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
 -- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
 -- Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
 -- Retrieval info: GEN_FILE: TYPE_NORMAL zpu_rom.vhd TRUE
