Revision 1406
Added by markw over 1 year ago
| sallymax.vhd | ||
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signal CPU_NMI_N : std_logic;
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signal CPU_IRQ_N : std_logic;
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signal CPU_RDY : std_logic;
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signal BUS_ADDR : std_logic_vector(15 downto 0);
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signal BUS_ADDR_OE : std_logic;
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signal BUS_DATA : std_logic_vector(7 downto 0);
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| ... | ... | |
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CPU_REQUEST_COMPLETE => CPU_REQUEST_COMPLETE,
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CPU_NMI_N => CPU_NMI_N,
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CPU_IRQ_N => CPU_IRQ_N,
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CPU_RDY => CPU_RDY,
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-- bus side
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BUS_DATA_IN => D,
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| ... | ... | |
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BUS_DATA_OUT => BUS_DATA,
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BUS_DATA_OE => BUS_DATA_OE,
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BUS_WRITE_N => BUS_WRITE_N,
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BUS_WRITE_OE => BUS_WRITE_OE
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BUS_WRITE_OE => BUS_WRITE_OE,
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BUS_RDY => RDY
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);
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cpu6502 : entity work.cpu
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| ... | ... | |
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NMI_n => CPU_NMI_N,
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MEMORY_READY => CPU_REQUEST_COMPLETE,
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THROTTLE => CPU_REQUEST,
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RDY => RDY,
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RDY => CPU_RDY,
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DI => CPU_READ_DATA,
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R_W_n => CPU_WRITE_N,
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CPU_FETCH => open,
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Improve phi timing. Try to improve RDY timing.