Revision 147
Added by markw over 11 years ago
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signal b_reg : std_logic_vector(7 downto 0);
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signal linea_address : std_logic_vector(10 downto 0);
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signal linea_address_integer : integer;
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signal linea_write_enable : std_logic;
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signal linea_out : std_logic_vector(7 downto 0);
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signal lineb_address : std_logic_vector(10 downto 0);
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signal lineb_address_integer : integer;
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signal lineb_write_enable : std_logic;
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signal lineb_out : std_logic_vector(7 downto 0);
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| ... | ... | |
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--lineb : reg_file
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-- generic map (BYTES=>456,WIDTH=>9)
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-- port map (clk=>clk,addr=>lineb_address,wr_en=>lineb_write_enable,data_in=>colour_in,data_out=>lineb_out);
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linea_address_integer <= to_integer(unsigned(linea_address));
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linea : scandouble_ram_infer
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port map (clock=>clk,address=>to_integer(unsigned(linea_address)),we=>linea_write_enable,data=>colour_in,q=>linea_out);
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port map (clock=>clk,address=>linea_address_integer,we=>linea_write_enable,data=>colour_in,q=>linea_out);
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lineb_address_integer <= to_integer(unsigned(lineb_address));
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lineb : scandouble_ram_infer
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port map (clock=>clk,address=>to_integer(unsigned(lineb_address)),we=>lineb_write_enable,data=>colour_in,q=>lineb_out);
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port map (clock=>clk,address=>lineb_address_integer,we=>lineb_write_enable,data=>colour_in,q=>lineb_out);
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-- capture
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process(input_address_reg,colour_enable,hsync_in,hsync_in_reg,buffer_select_reg)
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Changes for Aeon lite - notably 1MB ram support and ise build warnings fixed