Revision 147
Added by markw over 11 years ago
| zpu_config_regs.vhdl | ||
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signal spi_dma_addr_reg : std_logic_vector(15 downto 0);
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signal spi_dma_addrend_reg : std_logic_vector(15 downto 0);
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signal spi_dma_reg : std_logic;
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signal spi_clk_div_integer : integer;
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signal spi_addr_integer : integer;
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begin
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-- register
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process(clk,reset_n)
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| ... | ... | |
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-- spi - for sd card access without bit banging...
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-- 200KHz to start with - probably fine for 8-bit, can up it later after init
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spi_clk_div_integer <= to_integer(unsigned(spi_speed_reg));
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spi_addr_integer <= to_integer(unsigned(vectorize(spi_addr_reg)));
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spi_master1 : entity work.spi_master
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generic map(slaves=>1,d_width=>8)
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port map (clock=>clk,reset_n=>reset_n,enable=>spi_enable,cpol=>'0',cpha=>'0',cont=>'0',clk_div=>to_integer(unsigned(spi_speed_reg)),addr=>to_integer(unsigned(vectorize(spi_addr_reg))),
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port map (clock=>clk,reset_n=>reset_n,enable=>spi_enable,cpol=>'0',cpha=>'0',cont=>'0',clk_div=>spi_clk_div_integer,addr=>spi_addr_integer,
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tx_data=>spi_tx_data, miso=>spi_miso,sclk=>spi_clk_out,ss_n=>spi_chip_select,mosi=>spi_mosi,
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rx_data=>spi_rx_data,busy=>spi_busy);
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| ... | ... | |
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if (spi_busy = '0') then
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spi_dma_wr <= '1';
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spi_dma_addr_next <= std_logic_vector(unsigned(spi_dma_addr_reg)+1);
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spi_dma_addr_next <= std_logic_vector(unsigned(spi_dma_addr_reg)+to_unsigned(1,16));
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spi_dma_next <= '0';
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if (not(spi_dma_addr_next = spi_dma_addrend_reg)) then
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Changes for Aeon lite - notably 1MB ram support and ise build warnings fixed