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Revision 1494

Added by markw 3 days ago

Switch on synchronous reset. Switch to dithering 2nd order sigma delta.

View differences:

pokeymax.vhd
signal CLK116 : std_logic;
signal CLK106 : std_logic;
signal RESET_N : std_logic;
signal PLL_LOCKED : std_logic;
signal ENABLE_CYCLE : std_logic;
signal ENABLE_DOUBLE_CYCLE : std_logic;
......
c0 => CLK, --56 ish
c1 => CLK116, --113ish
c2 => CLK106, --106ish
locked => RESET_N);
locked => PLL_LOCKED);
CLK49152 <= '0';
end generate;
......
c1 => CLK116, --56ish
c2 => CLK106, --106ish
c3 => CLK6144, --6.44MHz
locked => RESET_N);
locked => PLL_LOCKED);
CLK49152 <= CLK0;
end generate;
pll_sync : entity work.pll_reset_sync
PORT MAP(CLK => CLK116,
PLL_LOCKED => PLL_LOCKED,
RESET_N => RESET_N);
AIN(3 downto 0) <= A;
AIN(7) <= EXT_INT(a7_bit);
......
dac_0 : entity work.filtered_sigmadelta --pin37
GENERIC MAP
(
IMPLEMENTATION => 2,
LOWPASS => lowpass
IMPLEMENTATION => 4,
LOWPASS => lowpass,
LFSR_SEED => x"ACE2"
)
port map
(
......
dac_1 : entity work.filtered_sigmadelta
GENERIC MAP
(
IMPLEMENTATION => 2,
LOWPASS => lowpass
IMPLEMENTATION => 4,
LOWPASS => lowpass,
LFSR_SEED => x"1D2B"
)
port map
(
......
dac_2 : entity work.filtered_sigmadelta
GENERIC MAP
(
IMPLEMENTATION => 2,
LOWPASS => lowpass
IMPLEMENTATION => 4,
LOWPASS => lowpass,
LFSR_SEED => x"BEEF"
)
port map
(
......
dac_3 : entity work.filtered_sigmadelta
GENERIC MAP
(
IMPLEMENTATION => 2,
LOWPASS => lowpass
IMPLEMENTATION => 4,
LOWPASS => lowpass,
LFSR_SEED => x"5A3C"
)
port map
(

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