Index: mist/zpu_config_regs.vhdl
===================================================================
--- mist/zpu_config_regs.vhdl	(revision 15)
+++ mist/zpu_config_regs.vhdl	(nonexistent)
@@ -1,538 +0,0 @@
----------------------------------------------------------------------------
--- (c) 2013 mark watson
--- I am happy for anyone to use this for non-commercial use.
--- If my vhdl files are used commercially or otherwise sold,
--- please contact me for explicit permission at scrameta (gmail).
--- This applies for source and binary form and derived works.
----------------------------------------------------------------------------
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-ENTITY zpu_config_regs IS
-PORT 
-( 
-	CLK : IN STD_LOGIC;
-	
-	ENABLE_179 : in std_logic;
-	
-	ADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
-	CPU_DATA_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-	WR_EN : IN STD_LOGIC;
-	
-	-- SWITCHES
-	SWITCH : in std_logic_vector(9 downto 0); -- already synchronized
-	KEY : in std_logic_vector(3 downto 0); -- already synchronized
-	
-	-- LEDS
-	LEDG : out std_logic_vector(7 downto 0);
-	LEDR : out std_logic_vector(9 downto 0);
-	
-	-- SDCARD
-	SDCARD_CLK : out std_logic;
-	SDCARD_CMD : out std_logic;
-	SDCARD_DAT : in std_logic;
-	SDCARD_DAT3 : out std_logic;
-	
-	-- ATARI interface (in future we can also turbo load by directly hitting memory...)
-	SIO_DATA_IN  : out std_logic;
-	SIO_COMMAND_OUT : in std_logic;
-	SIO_DATA_OUT : in std_logic;
-	
-	-- CPU interface
-	DATA_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
-	PAUSE_ZPU : out std_logic;
-	
-	-- SYSTEM CONFIG SETTINGS (legacy from switches - hardcoded to start with, then much fancier)
-	PAL : OUT STD_LOGIC;
-	USE_SDRAM : OUT STD_LOGIC;
-	RAM_SELECT : OUT STD_LOGIC_VECTOR(3 downto 0);
-	VGA : OUT STD_LOGIC;
-	COMPOSITE_ON_HSYNC : OUT STD_LOGIC;
-	GPIO_ENABLE : OUT STD_LOGIC;
-	ROM_SELECT : out stD_logic_vector(3 downto 0);
-	
-	-- sector buffer
-	sector : out std_logic_vector(31 downto 0);
-	sector_request : out std_logic;
-	sector_ready : in std_logic;
-
-	-- system reset/halt
-	PLL_LOCKED : IN STD_LOGIC; -- pll locked
-	REQUEST_RESET_ZPU : in std_logic; -- from keyboard (f12 to start with)
-	
-	RESET_6502 : OUT STD_LOGIC; -- i.e. cpu reset - 6502
-	RESET_ZPU : OUT STD_LOGIC; -- i.e. cpu reset - zpu
-	RESET_N : OUT STD_LOGIC; -- i.e. reset line on flip flops
-	
-	PAUSE_6502 : out std_logic;
-	
-	THROTTLE_COUNT_6502 : out std_logic_vector(5 downto 0);
-	
-	ZPU_HEX : out std_logic_vector(15 downto 0)
-
---	-- synchronize async inputs
---	locked_synchronizer : synchronizer
---		port map (clk=>clk, raw=>LOCKED, sync=>LOCKED_REG);
-	
-);
-END zpu_config_regs;
-
-ARCHITECTURE vhdl OF zpu_config_regs IS
-	COMPONENT complete_address_decoder IS
-	generic (width : natural := 4);
-	PORT 
-	( 
-		addr_in : in std_logic_vector(width-1 downto 0);			
-		addr_decoded : out std_logic_vector((2**width)-1 downto 0)
-	);
-	END component;
-	
-	COMPONENT spi_master IS
-	  GENERIC(
-		 slaves  : INTEGER := 4;  --number of spi slaves
-		 d_width : INTEGER := 2); --data bus width
-	  PORT(
-		 clock   : IN     STD_LOGIC;                             --system clock
-		 reset_n : IN     STD_LOGIC;                             --asynchronous reset
-		 enable  : IN     STD_LOGIC;                             --initiate transaction
-		 cpol    : IN     STD_LOGIC;                             --spi clock polarity
-		 cpha    : IN     STD_LOGIC;                             --spi clock phase
-		 cont    : IN     STD_LOGIC;                             --continuous mode command
-		 clk_div : IN     INTEGER;                               --system clock cycles per 1/2 period of sclk
-		 addr    : IN     INTEGER;                               --address of slave
-		 tx_data : IN     STD_LOGIC_VECTOR(d_width-1 DOWNTO 0);  --data to transmit
-		 miso    : IN     STD_LOGIC;                             --master in, slave out
-		 sclk    : BUFFER STD_LOGIC;                             --spi clock
-		 ss_n    : BUFFER STD_LOGIC_VECTOR(slaves-1 DOWNTO 0);   --slave select
-		 mosi    : OUT    STD_LOGIC;                             --master out, slave in
-		 busy    : OUT    STD_LOGIC;                             --busy / data ready signal
-		 rx_data : OUT    STD_LOGIC_VECTOR(d_width-1 DOWNTO 0)); --data received
-	END component;	
-	
-
-	component pokey IS
-	PORT 
-	( 
-		CLK : IN STD_LOGIC;
-		--ENABLE_179 :in std_logic;
-		CPU_MEMORY_READY :in std_logic;
-		ANTIC_MEMORY_READY :in std_logic;
-		ADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
-		DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-		WR_EN : IN STD_LOGIC;
-		
-		RESET_N : IN STD_LOGIC;
-		
-		-- keyboard interface
-		keyboard_scan : out std_logic_vector(5 downto 0);
-		keyboard_response : in std_logic_vector(1 downto 0);
-		
-		-- pots - go high as capacitor charges
-		POT_IN : in std_logic_vector(7 downto 0);
-		
-		-- sio interface
-		SIO_IN1 : IN std_logic;
-		SIO_IN2 : IN std_logic;
-		SIO_IN3 : IN std_logic;
-		
-		DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
-		
-		CHANNEL_0_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
-		CHANNEL_1_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
-		CHANNEL_2_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
-		CHANNEL_3_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
-		
-		IRQ_N_OUT : OUT std_logic;
-		
-		SIO_OUT1 : OUT std_logic;
-		SIO_OUT2 : OUT std_logic;
-		SIO_OUT3 : OUT std_logic;
-		
-		SIO_CLOCK : INOUT std_logic; -- TODO, should not use internally
-		
-		POT_RESET : out std_logic
-	);
-	END component;	
-	
-	function vectorize(s: std_logic) return std_logic_vector is
-	variable v: std_logic_vector(0 downto 0);
-	begin
-		v(0) := s;
-		return v;
-	end;
-	
-	signal addr_decoded : std_logic_vector(15 downto 0);	
-	
-	signal config_6502_next : std_logic_vector(7 downto 0);
-	signal config_6502_reg : std_logic_vector(7 downto 0);
-	signal ram_select_next : std_logic_vector(3 downto 0);
-	signal ram_select_reg : std_logic_vector(3 downto 0);
-	signal rom_select_next : std_logic_vector(3 downto 0);
-	signal rom_select_reg : std_logic_vector(3 downto 0);
-	signal gpio_enable_next : std_logic;
-	signal gpio_enable_reg : std_logic;
-	
-	signal pause_next : std_logic_vector(31 downto 0);
-	signal pause_reg : std_logic_vector(31 downto 0);
-	signal paused_next : std_logic;
-	signal paused_reg : std_logic;
-	
-	signal ledg_next : std_logic_vector(7 downto 0);
-	signal ledg_reg : std_logic_vector(7 downto 0);
-
-	signal ledr_next : std_logic_vector(9 downto 0);
-	signal ledr_reg : std_logic_vector(9 downto 0);
-	
-	signal reset_n_next : std_logic;
-	signal reset_n_reg : std_logic;
-	
-	signal reset_6502_cpu_next : std_logic;
-	signal reset_6502_cpu_reg : std_logic;
-	
-	signal reset_zpu_next : std_logic;
-	signal reset_zpu_reg : std_logic;	
-	
-	signal spi_miso : std_logic;
-	signal spi_mosi : std_logic;
-	signal spi_busy : std_logic;	
-	signal spi_enable : std_logic;
-	signal spi_chip_select : std_logic_vector(0 downto 0);
-	signal spi_clk_out : std_logic;
-	
-	signal spi_tx_data : std_logic_vector(7 downto 0);
-	signal spi_rx_data : std_logic_vector(7 downto 0);
-	
-	signal spi_addr_next : std_logic;
-	signal spi_addr_reg : std_logic;
-	signal spi_speed_next : std_logic_vector(7 downto 0);
-	signal spi_speed_reg : std_logic_vector(7 downto 0);
-
-	signal zpu_hex_next : std_logic_vector(15 downto 0);
-	signal zpu_hex_reg : std_logic_vector(15 downto 0);
-	
-	signal pokey_data_out : std_logic_vector(7 downto 0);
-	
-	signal sector_next : std_logic_vector(31 downto 0);
-	signal sector_reg : std_logic_vector(31 downto 0);
-	signal sector_request_next : std_logic;
-	signal sector_request_reg : std_logic; -- cleared when ready asserted
-	
-begin
-	-- register
-	process(clk,pll_locked)
-	begin
-		if (clk'event and clk='1') then	
-			if (pll_locked = '0') then
-				config_6502_reg <= "1"&"0"&"011111"; -- reset_6502, halt_6502, run_every 32 cycles
-				rom_select_reg <= "0010";
-				ram_select_reg <= "0010";
-				gpio_enable_reg <= '0';
-				pause_reg <= (others=>'0');
-				paused_reg <= '0';
-				ledg_reg <= (others=>'0');
-				ledr_reg <= (others=>'0');
-				
-				spi_addr_reg <= '1';
-				spi_speed_reg <= X"80";
-				
-				zpu_hex_reg <= X"b007";
-				
-				reset_n_reg <= '0';			
-				reset_zpu_reg <= '1';
-				reset_6502_cpu_reg <= '1';											
-				
-				sector_reg <= (others=>'0');
-				sector_request_reg <= '0';
-			else
-				config_6502_reg <= config_6502_next;
-				rom_select_reg <= rom_select_next;
-				ram_select_reg <= ram_select_next;
-				gpio_enable_reg <= gpio_enable_next;			
-				pause_reg <= pause_next;
-				paused_reg <= paused_next;
-				ledg_reg <= ledg_next;
-				ledr_reg <= ledr_next;
-				
-				spi_addr_reg <= spi_addr_next;
-				spi_speed_reg <= spi_speed_next;
-	
-				zpu_hex_reg <= zpu_hex_next;
-	
-				reset_n_reg <= reset_n_next;			
-				reset_zpu_reg <= reset_zpu_next;
-				reset_6502_cpu_reg <= reset_6502_cpu_next;							
-				
-				sector_reg <= sector_next;
-				sector_request_reg <= sector_request_next;				
-			end if;
-		end if;
-	end process;
-
-	-- decode address
-	decode_addr1 : complete_address_decoder
-		generic map(width=>4)
-		port map (addr_in=>addr(3 downto 0), addr_decoded=>addr_decoded);
-
-	-- spi - for sd card access without bit banging...
-	-- 200KHz to start with - probably fine for 8-bit, can up it later after init
-	spi_master1 : spi_master
-		generic map(slaves=>1,d_width=>8)
-		port map (clock=>clk,reset_n=>pll_locked,enable=>spi_enable,cpol=>'0',cpha=>'0',cont=>'0',clk_div=>to_integer(unsigned(spi_speed_reg)),addr=>to_integer(unsigned(vectorize(spi_addr_reg))),
-		          tx_data=>spi_tx_data, miso=>spi_miso,sclk=>spi_clk_out,ss_n=>spi_chip_select,mosi=>spi_mosi,
-					 rx_data=>spi_rx_data,busy=>spi_busy);
-					 
-	-- spi-programming model:
-	-- reg for write/read
-	-- data (send/receive)
-	-- busy
-	-- speed - 0=400KHz, 1=10MHz? Start with 400KHz then atari800core...
-	-- chip select
-	
-	-- uart - another Pokey! Running at atari frequency.
-	uart1 : pokey
-		port map (clk=>clk,CPU_MEMORY_READY=>enable_179,ANTIC_MEMORY_READY=>enable_179,addr=>addr(3 downto 0),data_in=>cpu_data_in(7 downto 0),wr_en=>addr(4) and wr_en, 
-		reset_n=>pll_locked,keyboard_response=>"11",pot_in=>X"00",
-		sio_in1=>sio_data_out,sio_in2=>'1',sio_in3=>'1', -- TODO, pokey dir...
-		data_out=>pokey_data_out, 
-		sio_out1=>sio_data_in);
-
-	-- hardware regs for ZPU
-	--
-	-- KEYS -> all for ZPU. SWITCHES -> all for ZPU
-	-- i.e. zpu must control: rom/ram select, turbo, 6502 reset, scandoubler, rom wait states, pal/ntsc, gpio enable, sdram vs sram
-	-- these need storing somewhere...
-	-- TODO - volume output from here
-	-- TODO - hex digits register
-	-- TODO - if we take over antic we need to point antic to alternative RAM!
-	-- TODO - if we take over antic we need to point it back at the original display list... e.g. freeze, store state, restore state...
-	-- TODO - reset pokey and pia interrupts too?
-	--
-	-- virtual joystick button -> keyboard (windows key?)
-	-- reset -> keyboard -> f12 -> zpu reset. Then zpu controls 6502 reset.
-	--
-	-- important todo -> speed up clearing ram. e.g. 32-bit sram write. Only clear bit we need to.
-	--
-	-- STEP 1 -> joystick -> keyboard (DONE)
-	-- STEP 2 -> hardcode switch inputs to 65XE, PAL, non scandoubled  (DONE)
-	-- STEP 3 -> 6502 reset (DONE))/turbo under zpu control (DONE)
-	-- STEP 4 -> zpu starts 6502 on key1 (DONE)
-	-- STEP 5 -> simple OSD! ok, just make antic display mode 2 on reset with hello world, joystick to select... (CLOSE)
-	--
-	-- CONFIG_ATARI: 
-	-- 	R/W: 0-5: run every n cycles (0-63), 6: pause, 7: reset 
-	--    R/W(8-11 bits) - XX 00=64k,01=128K,10=320K Compy,11=320K Rambo
-	--    R/W(12-15 bits) - XX 00=XL, 01=XL turbo, 10=OS B/debugger, 11=OS B turbo
-	--	   R/W(16-20 bits) - XXXG= G:0=GPIO_OFF,1=GPIO_ON(ISH!)
-	-- PAUSE (DONE) -- W: 0-31:wait for n cycles
-	-- SWITCH (DONE)
-	--		R: 0-9 - switches
-	-- KEY (DONE)
-	--    R: 0-3 - keys
-	-- LEDG (DONE) 
-	--    R/W: 0-9
-	-- LEDR (DONE) 
-	--    R/W: 0-9
-	-- SPI_DATA (DONE) 
-	--		W - write data (starts transmission)
-	--		R - read data (wait for complete first)
-	-- SPI_STATE/SPI_CTRL (DONE) 
-	--    R: 0=busy
-	--    W: 0=select_n, speed
-	-- SIO
-	--    R: 0=CMD
-	-- FPGA board (DONE) 
-	--    R(32 bits) 0=DE1
-	-- HEX digits
-	--    W(16 bits)
-	-- SECTOR
-	--   W(32 bits) - write here initiates a request_reset_zpu
-	--   R: 0=request_active
-	
-	-- TODO, ROM select, RAM select etc etc
-	-- TODO firmware with OSD!
-				
-	-- Writes to registers
-	process(cpu_data_in,wr_en,addr,addr_decoded, ledg_reg, ledr_reg, pause_reg, config_6502_reg, rom_select_reg, ram_select_reg, gpio_enable_reg, spi_speed_reg, spi_addr_reg, zpu_hex_reg, sector_request_reg, sector_ready, sector_reg)
-	begin
-		config_6502_next <= config_6502_reg;
-		rom_select_next <= rom_select_reg;
-		ram_select_next <= ram_select_reg;
-		gpio_enable_next <= gpio_enable_reg;
-		pause_next <= pause_reg;
-		ledg_next <= ledg_reg;
-		ledr_next <= ledr_reg;
-		
-		spi_speed_next <= spi_speed_reg;
-		spi_addr_next <= spi_addr_reg;
-		spi_tx_data <= (others=>'0');
-		spi_enable <= '0';
-		
-		zpu_hex_next <= zpu_hex_reg;
-		
-		sector_next <= sector_reg;
-		sector_request_next <= sector_request_reg and not(sector_ready);
-		
-		paused_next <= '0';
-		if (not(pause_reg = X"00000000")) then
-			pause_next <= std_LOGIC_VECTOR(unsigned(pause_reg)-to_unsigned(1,32));
-			paused_next <= '1';
-		end if;
-	
-		if (wr_en = '1' and addr(4) = '0') then
-			if(addr_decoded(0) = '1') then
-				config_6502_next <= cpu_data_in(7 downto 0);
-				ram_select_next <= cpu_DATA_IN(11 downto 8);
-				rom_select_next <= cpu_DATA_IN(15 downto 12);
-				gpio_enable_next <= cpu_DATA_IN(16);
-			end if;	
-			
-			if(addr_decoded(1) = '1') then
-				pause_next <= cpu_data_in;
-				paused_next <= '1';
-			end if;				
-
-			if(addr_decoded(4) = '1') then
-				ledg_next <= cpu_data_in(7 downto 0);
-			end if;	
-			
-			if(addr_decoded(5) = '1') then
-				ledr_next <= cpu_data_in(9 downto 0);
-			end if;	
-
-			if(addr_decoded(6) = '1') then
-				-- TODO, check overrun?
-				spi_tx_data <= cpu_data_in(7 downto 0);
-				spi_enable <= '1';
-			end if;	
-
-			if(addr_decoded(7) = '1') then
-				spi_addr_next <= cpu_data_in(0);
-				if (cpu_data_in(1) = '1') then
-					spi_speed_next <= X"80"; -- slow, for init
-				else
-					spi_speed_next <= X"04"; -- turbo!
-				end if;
-			end if;	
-
-			if(addr_decoded(10) = '1') then
-				zpu_hex_next <= cpu_data_in(15 downto 0);
-			end if;	
-			
-			if(addr_decoded(11) = '1') then
-				sector_next <= cpu_data_in;
-				sector_request_next <= '1';
-			end if;
-			
-		end if;
-	end process;
-	
-	-- Read from registers
-	process(addr,addr_decoded, ledg_reg, ledr_reg, SWITCH, KEY, SIO_COMMAND_OUT, spi_rx_data, spi_busy, pokey_data_out, zpu_hex_reg, config_6502_reg, ram_select_reg, rom_select_reg, gpio_enable_reg, sector_request_reg)
-	begin
-		data_out <= (others=>'0');
-
-		if (addr(4) = '0') then
-			if (addr_decoded(0) = '1') then
-				data_out(7 downto 0) <= config_6502_reg;
-				data_out(11 downto 8) <= ram_select_reg;
-				data_out(15 downto 12) <= rom_select_reg;
-				data_out(16) <= gpio_enable_reg;
-			end if;
-			
-			if (addr_decoded(2) = '1') then
-				data_out(9 downto 0) <= (others=>'0'); -- TODO - enable SD.
-			end if;		
-			
-			if (addr_decoded(3) = '1') then
-				data_out(3 downto 0) <= key;
-			end if;		
-			
-			if (addr_decoded(4) = '1') then
-				data_out(7 downto 0) <= ledg_reg;
-			end if;
-
-			if (addr_decoded(5) = '1') then
-				data_out(9 downto 0) <= ledr_reg;
-			end if;
-
-			if (addr_decoded(6) = '1') then
-				data_out(7 downto 0) <= spi_rx_data;
-			end if;
-
-			if (addr_decoded(7) = '1') then
-				data_out(0) <= spi_busy;
-			end if;		
-
-			if(addr_decoded(8) = '1') then
-				data_out(0) <= sio_command_OUT;
-			end if;	
-			
-			if (addr_decoded(9) = '1') then
-				--data_out <= X"00000000"; -- DE1!
-				--data_out <= X"00000001"; -- DE2!
-				--data_out <= X"00000002"; -- SOCKIT!
-				--data_out <= X"00000003"; -- REPLAY!
-				data_out <= X"00000004"; -- MMC!		
-			end if;
-			
-			if (addr_decoded(10) = '1') then
-				data_out(15 downto 0) <= zpu_hex_reg;
-			end if;			
-			
-			if (addr_decoded(11) = '1') then
-				data_out(0) <= sector_request_reg;
-			end if;			
-			
-		else
-			data_out(7 downto 0) <= pokey_data_out;
-		end if;
-	end process;	
-	
-	process(request_reset_zpu, config_6502_next, config_6502_reg)
-	begin
-		reset_n_next <= '1';
-		reset_zpu_next <= '0';
-		reset_6502_cpu_next <= config_6502_reg(7);
-		
-		if (request_reset_zpu = '1') then
-			reset_n_next <= '0';
-			reset_zpu_next <= '1';
-			reset_6502_cpu_next <= '1';
-		end if;
-	end process;
-	
-	-- outputs
-	PAUSE_ZPU <= paused_reg;
-	LEDG <= ledg_reg;
-	LEDR <= ledr_reg;
-	
-	SDCARD_CLK <= spi_clk_out;
-	SDCARD_CMD <= spi_mosi;
-	spi_miso <= SDCARD_DAT; -- INPUT!! XXX
-	SDCARD_DAT3 <= spi_chip_select(0);
-	
-	PAL <= '1'; -- TODO
-	--USE_SDRAM <= '1'; -- should not be all or nothing. can mix for higher ram settings...
-	USE_SDRAM <= '1'; -- should not be all or nothing. can mix for higher ram settings...
-	RAM_SELECT <= ram_select_reg;
-	VGA <= '1';
-	COMPOSITE_ON_HSYNC <= '0';
-	GPIO_ENABLE <= '0'; -- enable gpio - FIXME - esp carts!
-	ROM_SELECT <= rom_select_reg;
-	
-	reset_n <= reset_n_reg; -- system reset or pll not locked
-	reset_zpu <= reset_zpu_reg; -- system_reset or pll not locked
-	reset_6502 <= reset_6502_cpu_reg; -- zpu software controlled
-	
-	pause_6502 <= config_6502_reg(6); -- zpu software controlled
-	
-	throttle_count_6502 <= config_6502_reg(5 downto 0); -- zpu software controlled	
-	
-	zpu_hex <= zpu_hex_reg;
-	
-	sector <= sector_reg;
-	sector_request <= sector_request_reg;
-end vhdl;
-
-
Index: mist/atari800core.vhd
===================================================================
--- mist/atari800core.vhd	(revision 15)
+++ mist/atari800core.vhd	(nonexistent)
@@ -1,1846 +0,0 @@
--- Copyright (C) 1991-2012 Altera Corporation
--- Your use of Altera Corporation's design tools, logic functions 
--- and other software and tools, and its AMPP partner logic 
--- functions, and any output files from any of the foregoing 
--- (including device programming or simulation files), and any 
--- associated documentation or information are expressly subject 
--- to the terms and conditions of the Altera Program License 
--- Subscription Agreement, Altera MegaCore Function License 
--- Agreement, or other applicable license agreement, including, 
--- without limitation, that your use is for the sole purpose of 
--- programming logic devices manufactured by Altera and sold by 
--- Altera or its authorized distributors.  Please refer to the 
--- applicable agreement for further details.
-
--- PROGRAM		"Quartus II 64-Bit"
--- VERSION		"Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Web Edition"
--- CREATED		"Tue Dec 31 22:21:48 2013"
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all; 
-use ieee.numeric_std.all;
-
-LIBRARY work;
-
-ENTITY atari800core IS 
-	PORT
-	(
-		CLOCK_27 :  IN  STD_LOGIC_VECTOR(1 downto 0);
---		PS2K_CLK :  IN  STD_LOGIC;
---		PS2K_DAT :  IN  STD_LOGIC;
---		PS2M_CLK :  IN  STD_LOGIC;
---		PS2M_DAT :  IN  STD_LOGIC;		
-
-		VGA_VS :  OUT  STD_LOGIC;
-		VGA_HS :  OUT  STD_LOGIC;
-		VGA_B :  OUT  STD_LOGIC_VECTOR(5 DOWNTO 0);
-		VGA_G :  OUT  STD_LOGIC_VECTOR(5 DOWNTO 0);
-		VGA_R :  OUT  STD_LOGIC_VECTOR(5 DOWNTO 0);
-		
---		JOY1_n :  IN  STD_LOGIC_VECTOR(5 DOWNTO 0);
---		JOY2_n :  IN  STD_LOGIC_VECTOR(5 DOWNTO 0);
-		
-		AUDIO_L : OUT std_logic;
-		AUDIO_R : OUT std_logic;
-
-		SDRAM_BA :  OUT  STD_LOGIC_VECTOR(1 downto 0);
-		SDRAM_nCS :  OUT  STD_LOGIC;
-		SDRAM_nRAS :  OUT  STD_LOGIC;
-		SDRAM_nCAS :  OUT  STD_LOGIC;
-		SDRAM_nWE :  OUT  STD_LOGIC;
-		SDRAM_DQMH :  OUT  STD_LOGIC;
-		SDRAM_DQML :  OUT  STD_LOGIC;
-		SDRAM_CLK :  OUT  STD_LOGIC;
-		SDRAM_CKE :  OUT  STD_LOGIC;
-		SDRAM_A :  OUT  STD_LOGIC_VECTOR(12 DOWNTO 0);
-		SDRAM_DQ :  INOUT  STD_LOGIC_VECTOR(15 DOWNTO 0);
-
---		SD_DAT0 :  IN  STD_LOGIC;
---		SD_CLK :  OUT  STD_LOGIC;
---		SD_CMD :  OUT  STD_LOGIC;
---		SD_DAT3 :  OUT  STD_LOGIC
-
-		LED : OUT std_logic;
-		
-		UART_TX :  OUT  STD_LOGIC;
-		UART_RX :  IN  STD_LOGIC;
-		
-		SPI_DO :  INOUT  STD_LOGIC;
-		SPI_DI :  IN  STD_LOGIC;
-		SPI_SCK :  IN  STD_LOGIC;
-		SPI_SS2 :  IN  STD_LOGIC;		
-		SPI_SS3 :  IN  STD_LOGIC;		
-		SPI_SS4 :  IN  STD_LOGIC;
-		CONF_DATA0 :  IN  STD_LOGIC -- AKA SPI_SS5
-	);
-END atari800core;
-
-ARCHITECTURE bdf_type OF atari800core IS 
---
---component generic_ram_infer IS
---	generic
---	(
---		ADDRESS_WIDTH : natural := 9;
---		SPACE : natural := 512;
---		DATA_WIDTH : natural := 8
---	);
---   PORT
---   (
---      clock: IN   std_logic;
---      data:  IN   std_logic_vector (data_width-1 DOWNTO 0);
---      address:  IN   std_logic_vector(address_width-1 downto 0);
---      we:    IN   std_logic;
---      q:     OUT  std_logic_vector (data_width-1 DOWNTO 0)
---   );
---END component;
-
-component mist_sector_buffer IS
-	PORT
-	(
-		address_a		: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
-		address_b		: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
-		clock_a		: IN STD_LOGIC  := '1';
-		clock_b		: IN STD_LOGIC ;
-		data_a		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-		data_b		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
-		wren_a		: IN STD_LOGIC  := '0';
-		wren_b		: IN STD_LOGIC  := '0';
-		q_a		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
-		q_b		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
-	);
-END component;
-
-component synchronizer IS
-PORT 
-( 
-	CLK : IN STD_LOGIC;
-	RAW : IN STD_LOGIC;
-	SYNC : OUT STD_LOGIC
-);
-END component;
-
-component data_io IS 
-	PORT
-	(
-		CLK : in std_logic;
-		RESET_n : in std_logic;
-		
-		-- SPI connection - up to upstream to make miso 'Z' on ss_io going high
-	   SPI_CLK : in std_logic;
-	   SPI_SS_IO : in std_logic;
-	   SPI_MISO: out std_logic;
-	   SPI_MOSI : in std_logic;
-		
-		-- Sector access request
-		request : in std_logic;
-		sector : in std_logic_vector(23 downto 0);
-		ready : out std_logic;
-		
-		-- DMA to RAM
-		ADDR: out std_logic_vector(8 downto 0);
-		DATA_OUT : out std_logic_vector(7 downto 0);
-		DATA_IN : in std_logic_vector(7 downto 0);
-		WR_EN : out std_logic
-	 );
-end component;
-
-component user_io
-	PORT(
-	   SPI_CLK : in std_logic;
-	   SPI_SS_IO : in std_logic;
-	   SPI_MISO : out std_logic;
-	   SPI_MOSI : in std_logic;
-	   CORE_TYPE : in std_logic_vector(7 downto 0);
-		JOY0 : out std_logic_vector(5 downto 0);
-		JOY1 : out std_logic_vector(5 downto 0);
-		KEYBOARD : out std_logic_vector(127 downto 0);
-		BUTTONS : out std_logic_vector(1 downto 0);
-		SWITCHES : out std_logic_vector(1 downto 0)
-	  );
-end component;
-
-COMPONENT complete_address_decoder IS
-generic (width : natural := 1);
-PORT 
-( 
-	addr_in : in std_logic_vector(width-1 downto 0);			
-	addr_decoded : out std_logic_vector((2**width)-1 downto 0)
-);
-END component;
-
-COMPONENT cpu
-	PORT(CLK : IN STD_LOGIC;
-		 RESET : IN STD_LOGIC;
-		 ENABLE : IN STD_LOGIC;
-		 IRQ_n : IN STD_LOGIC;
-		 NMI_n : IN STD_LOGIC;
-		 MEMORY_READY : IN STD_LOGIC;
-		 THROTTLE : IN STD_LOGIC;
-		 RDY : IN STD_LOGIC;
-		 DI : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-		 R_W_n : OUT STD_LOGIC;
-		 CPU_FETCH : OUT STD_LOGIC;
-		 A : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
-		 DO : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
-	);
-END COMPONENT;
-
-component hq_dac
-port (
-  reset :in std_logic;
-  clk :in std_logic;
-  clk_ena : in std_logic;
-  pcm_in : in std_logic_vector(19 downto 0);
-  dac_out : out std_logic
-);
-end component;
-
-component internalromram IS
-  PORT(
-    clock   : IN     STD_LOGIC;                             --system clock
-    reset_n : IN     STD_LOGIC;                             --asynchronous reset
-
-	ROM_ADDR : in STD_LOGIC_VECTOR(21 downto 0);
-	ROM_REQUEST_COMPLETE : out STD_LOGIC;
-	ROM_REQUEST : in std_logic;
-	ROM_DATA : out std_logic_vector(7 downto 0);
-	
-	RAM_ADDR : in STD_LOGIC_VECTOR(18 downto 0);
-	RAM_WR_ENABLE : in std_logic;
-	RAM_DATA_IN : in STD_LOGIC_VECTOR(7 downto 0);
-	RAM_REQUEST_COMPLETE : out STD_LOGIC;
-	RAM_REQUEST : in std_logic;
-	RAM_DATA : out std_logic_vector(7 downto 0)
-	);
-	
-END component;
-
-COMPONENT antic
-	PORT(CLK : IN STD_LOGIC;
-		 WR_EN : IN STD_LOGIC;
-		 RESET_N : IN STD_LOGIC;
-		 MEMORY_READY_ANTIC : IN STD_LOGIC;
-		 MEMORY_READY_CPU : IN STD_LOGIC;
-		 ANTIC_ENABLE_179 : IN STD_LOGIC;
-		 PAL : IN STD_LOGIC;
-		 lightpen : IN STD_LOGIC;
-		 ADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
-		 CPU_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-		 MEMORY_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-		 NMI_N_OUT : OUT STD_LOGIC;
-		 ANTIC_READY : OUT STD_LOGIC;
-		 COLOUR_CLOCK_ORIGINAL_OUT : OUT STD_LOGIC;
-		 COLOUR_CLOCK_OUT : OUT STD_LOGIC;
-		 HIGHRES_COLOUR_CLOCK_OUT : OUT STD_LOGIC;
-		 dma_fetch_out : OUT STD_LOGIC;
-		 refresh_out : OUT STD_LOGIC;
-		 dma_clock_out : OUT STD_LOGIC;
-		 AN : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
-		 DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
-		 dma_address_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
-	);
-END COMPONENT;
-
-COMPONENT ledsw
-	PORT(CLK : IN STD_LOGIC;
-		 KEY : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
-		 SW : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
-		 SYNC_KEYS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
-		 SYNC_SWITCHES : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
-	);
-END COMPONENT;
-
-COMPONENT pokey_mixer
-	PORT(CLK : IN STD_LOGIC;
-		 GTIA_SOUND : IN STD_LOGIC;
-		 CHANNEL_0 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
-		 CHANNEL_1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
-		 CHANNEL_2 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
-		 CHANNEL_3 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
-		 COVOX_CHANNEL_0 : IN STD_LOGIC_VECTOR(7 downto 0);
-		 COVOX_CHANNEL_1 : IN STD_LOGIC_VECTOR(7 downto 0);
-		 CHANNEL_ENABLE : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
-		 VOLUME_OUT : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
-	);
-END COMPONENT;
-
-COMPONENT ps2_keyboard
-	PORT(CLK : IN STD_LOGIC;
-		 RESET_N : IN STD_LOGIC;
-		 PS2_CLK : IN STD_LOGIC;
-		 PS2_DAT : IN STD_LOGIC;
-		 KEY_EVENT : OUT STD_LOGIC;
-		 KEY_EXTENDED : OUT STD_LOGIC;
-		 KEY_UP : OUT STD_LOGIC;
-		 KEY_VALUE : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
-	);
-END COMPONENT;
-
-COMPONENT zpu_glue
-	PORT(CLK : IN STD_LOGIC;
-		 RESET : IN STD_LOGIC;
-		 PAUSE : IN STD_LOGIC;
-		 MEMORY_READY : IN STD_LOGIC;
-		 ZPU_CONFIG_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-		 ZPU_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-		 ZPU_RAM_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-		 ZPU_ROM_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-		 ZPU_SECTOR_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-		 MEMORY_FETCH : OUT STD_LOGIC;
-		 ZPU_READ_ENABLE : OUT STD_LOGIC;
-		 ZPU_32BIT_WRITE_ENABLE : OUT STD_LOGIC;
-		 ZPU_16BIT_WRITE_ENABLE : OUT STD_LOGIC;
-		 ZPU_8BIT_WRITE_ENABLE : OUT STD_LOGIC;
-		 ZPU_CONFIG_WRITE : OUT STD_LOGIC;
-		 ZPU_ADDR_FETCH : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
-		 ZPU_ADDR_ROM_RAM : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
-		 ZPU_DO : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
-		 ZPU_STACK_WRITE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
-	);
-END COMPONENT;
-
-COMPONENT pokey
-	PORT(CLK : IN STD_LOGIC;
-		 CPU_MEMORY_READY : IN STD_LOGIC;
-		 ANTIC_MEMORY_READY : IN STD_LOGIC;
-		 WR_EN : IN STD_LOGIC;
-		 RESET_N : IN STD_LOGIC;
-		 SIO_IN1 : IN STD_LOGIC;
-		 SIO_IN2 : IN STD_LOGIC;
-		 SIO_IN3 : IN STD_LOGIC;
-		 SIO_CLOCK : INOUT STD_LOGIC;
-		 ADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
-		 DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-		 keyboard_response : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
-		 POT_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-		 IRQ_N_OUT : OUT STD_LOGIC;
-		 SIO_OUT1 : OUT STD_LOGIC;
-		 SIO_OUT2 : OUT STD_LOGIC;
-		 SIO_OUT3 : OUT STD_LOGIC;
-		 POT_RESET : OUT STD_LOGIC;
-		 CHANNEL_0_OUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
-		 CHANNEL_1_OUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
-		 CHANNEL_2_OUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
-		 CHANNEL_3_OUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
-		 DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
-		 keyboard_scan : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
-	);
-END COMPONENT;
-
-COMPONENT pia
-	PORT(	CLK : IN STD_LOGIC;
-	ADDR : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
-	CPU_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-	EN : IN STD_LOGIC;
-	WR_EN : IN STD_LOGIC;
-	
-	RESET_N : IN STD_LOGIC;
-	
-	CA1 : IN STD_LOGIC;
-	CB1 : IN STD_LOGIC;		
-	
-	CA2_DIR_OUT : OUT std_logic;
-	CA2_OUT : OUT std_logic;
-	CA2_IN : IN STD_LOGIC;
-
-	CB2_DIR_OUT : OUT std_logic;
-	CB2_OUT : OUT std_logic;
-	CB2_IN : IN STD_LOGIC;
-	
-	-- remember these two are different if connecting to gpio (push pull vs pull up - check 6520 data sheet...)
-	-- pull up - i.e. 0 driven only
-	PORTA_DIR_OUT : OUT STD_LOGIC_VECTOR(7 downto 0); -- set bit to 1 to enable output mode
-	PORTA_OUT : OUT STD_LOGIC_VECTOR(7 downto 0); 
-	PORTA_IN : IN STD_LOGIC_VECTOR(7 downto 0);
-	
-	PORTB_DIR_OUT : OUT STD_LOGIC_VECTOR(7 downto 0);
-	PORTB_OUT : OUT STD_LOGIC_VECTOR(7 downto 0); -- push pull
-	PORTB_IN : IN STD_LOGIC_VECTOR(7 downto 0); -- push pull
-	
-	-- CPU interface
-	DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
-		
-	IRQA_N : OUT STD_LOGIC;
-	IRQB_N : OUT STD_LOGIC	);
-END COMPONENT;
-
-COMPONENT shared_enable
-	PORT(CLK : IN STD_LOGIC;
-		 RESET_N : IN STD_LOGIC;
-		 MEMORY_READY_CPU : IN STD_LOGIC;
-		 MEMORY_READY_ANTIC : IN STD_LOGIC;
-		 PAUSE_6502 : IN STD_LOGIC;
-		 THROTTLE_COUNT_6502 : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
-		 POKEY_ENABLE_179 : OUT STD_LOGIC;
-		 ANTIC_ENABLE_179 : OUT STD_LOGIC;
-		 oldcpu_enable : OUT STD_LOGIC;
-		 CPU_ENABLE_OUT : OUT STD_LOGIC;
-		 SCANDOUBLER_ENABLE_LOW : OUT STD_LOGIC;
-		 SCANDOUBLER_ENABLE_HIGH : OUT STD_LOGIC
-	);
-END COMPONENT;
-
-COMPONENT pokey_ps2_decoder
-	PORT(CLK : IN STD_LOGIC;
-		 RESET_N : IN STD_LOGIC;
-		 KEY_EVENT : IN STD_LOGIC;
-		 KEY_EXTENDED : IN STD_LOGIC;
-		 KEY_UP : IN STD_LOGIC;
-		 KEY_CODE : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-		 KEY_HELD : OUT STD_LOGIC;
-		 SHIFT_PRESSED : OUT STD_LOGIC;
-		 BREAK_PRESSED : OUT STD_LOGIC;
-		 KEY_INTERRUPT : OUT STD_LOGIC;
-		 CONSOL_START : OUT STD_LOGIC;
-		 CONSOL_SELECT : OUT STD_LOGIC;
-		 CONSOL_OPTION : OUT STD_LOGIC;
-		 SYSTEM_RESET : OUT STD_LOGIC;
-		 KBCODE : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
-		 VIRTUAL_STICKS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
-		 VIRTUAL_TRIGGER : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
-		 VIRTUAL_KEYS : out std_logic_vector(3 downto 0)
-	);
-END COMPONENT;
-
-
-COMPONENT address_decoder
-	PORT(CLK : IN STD_LOGIC;
-		 CPU_FETCH : IN STD_LOGIC;
-		 CPU_WRITE_N : IN STD_LOGIC;
-		 ANTIC_FETCH : IN STD_LOGIC;
-		 antic_refresh : IN STD_LOGIC;
-		 ZPU_FETCH : IN STD_LOGIC;
-		 ZPU_READ_ENABLE : IN STD_LOGIC;
-		 ZPU_32BIT_WRITE_ENABLE : IN STD_LOGIC;
-		 ZPU_16BIT_WRITE_ENABLE : IN STD_LOGIC;
-		 ZPU_8BIT_WRITE_ENABLE : IN STD_LOGIC;
-		 RAM_REQUEST_COMPLETE : IN STD_LOGIC;
-		 ROM_REQUEST_COMPLETE : IN STD_LOGIC;
-		 CART_REQUEST_COMPLETE : IN STD_LOGIC;
-		 reset_n : IN STD_LOGIC;
-		 CART_RD4 : IN STD_LOGIC;
-		 CART_RD5 : IN STD_LOGIC;
-		 use_sdram : IN STD_LOGIC;
-		 SDRAM_REQUEST_COMPLETE : IN STD_LOGIC;
-		 ANTIC_ADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
-		 ANTIC_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-		 CACHE_ANTIC_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-		 CART_ROM_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-		 CPU_ADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
-		 CPU_WRITE_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-		 GTIA_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-		 CACHE_GTIA_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-		 PIA_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-		 POKEY2_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-		 CACHE_POKEY2_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-		 POKEY_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-		 CACHE_POKEY_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-		 PORTB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-		 RAM_DATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
-		 ram_select : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
-		 ROM_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-		 rom_select : in std_logic_vector(5 downto 0);
-		 cart_select : in std_logic_vector(6 downto 0);
-		 cart_activate : in std_logic;
-		 SDRAM_DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-		 ZPU_ADDR : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
-		 ZPU_WRITE_DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-		 MEMORY_READY_ANTIC : OUT STD_LOGIC;
-		 MEMORY_READY_ZPU : OUT STD_LOGIC;
-		 MEMORY_READY_CPU : OUT STD_LOGIC;
-		 GTIA_WR_ENABLE : OUT STD_LOGIC;
-		 POKEY_WR_ENABLE : OUT STD_LOGIC;
-		 POKEY2_WR_ENABLE : OUT STD_LOGIC;
-		 ANTIC_WR_ENABLE : OUT STD_LOGIC;
-		 PIA_WR_ENABLE : OUT STD_LOGIC;
-		 PIA_RD_ENABLE : OUT STD_LOGIC;
-		 RAM_WR_ENABLE : OUT STD_LOGIC;
-		 PBI_WR_ENABLE : OUT STD_LOGIC;
-		 RAM_REQUEST : OUT STD_LOGIC;
-		 ROM_REQUEST : OUT STD_LOGIC;
-		 CART_REQUEST : OUT STD_LOGIC;
-		 CART_S4_n : OUT STD_LOGIC;
-		 CART_S5_n : OUT STD_LOGIC;
-		 CART_CCTL_n : OUT STD_LOGIC;
-		 WIDTH_8bit_ACCESS : OUT STD_LOGIC;
-		 WIDTH_16bit_ACCESS : OUT STD_LOGIC;
-		 WIDTH_32bit_ACCESS : OUT STD_LOGIC;
-		 SDRAM_READ_EN : OUT STD_LOGIC;
-		 SDRAM_WRITE_EN : OUT STD_LOGIC;
-		 SDRAM_REQUEST : OUT STD_LOGIC;
-		 SDRAM_REFRESH : OUT STD_LOGIC;
-		 MEMORY_DATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
-		 PBI_ADDR : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
-		 RAM_ADDR : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
-		 ROM_ADDR : OUT STD_LOGIC_VECTOR(21 DOWNTO 0);
-		 SDRAM_ADDR : OUT STD_LOGIC_VECTOR(22 DOWNTO 0);
-		 WRITE_DATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
-		 D6_WR_ENABLE : out std_logic
-	);
-END COMPONENT;
-
-COMPONENT sdram_statemachine
-GENERIC (ADDRESS_WIDTH : INTEGER;
-			AP_BIT : INTEGER;
-			COLUMN_WIDTH : INTEGER;
-			ROW_WIDTH : INTEGER
-			);
-	PORT(CLK_SYSTEM : IN STD_LOGIC;
-		 CLK_SDRAM : IN STD_LOGIC;
-		 RESET_N : IN STD_LOGIC;
-		 READ_EN : IN STD_LOGIC;
-		 WRITE_EN : IN STD_LOGIC;
-		 REQUEST : IN STD_LOGIC;
-		 BYTE_ACCESS : IN STD_LOGIC;
-		 WORD_ACCESS : IN STD_LOGIC;
-		 LONGWORD_ACCESS : IN STD_LOGIC;
-		 REFRESH : IN STD_LOGIC;
-		 ADDRESS_IN : IN STD_LOGIC_VECTOR(22 DOWNTO 0);
-		 DATA_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-		 SDRAM_DQ : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);
-		 COMPLETE : OUT STD_LOGIC;
-		 SDRAM_BA0 : OUT STD_LOGIC;
-		 SDRAM_BA1 : OUT STD_LOGIC;
-		 SDRAM_CKE : OUT STD_LOGIC;
-		 SDRAM_CS_N : OUT STD_LOGIC;
-		 SDRAM_RAS_N : OUT STD_LOGIC;
-		 SDRAM_CAS_N : OUT STD_LOGIC;
-		 SDRAM_WE_N : OUT STD_LOGIC;
-		 SDRAM_ldqm : OUT STD_LOGIC;
-		 SDRAM_udqm : OUT STD_LOGIC;
-		 DATA_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
-		 SDRAM_ADDR : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
-	);
-END COMPONENT;
-
-component sdram_statemachine_mcc IS
-generic
-(
-	ADDRESS_WIDTH : natural := 22;
-	ROW_WIDTH : natural := 12;
-	AP_BIT : natural := 10;
-	COLUMN_WIDTH : natural := 8
-);
-PORT 
-( 
-	CLK_SYSTEM : IN STD_LOGIC;
-	CLK_SDRAM : IN STD_LOGIC; -- this is a exact multiple of system clock
-	RESET_N : in STD_LOGIC;
-	
-	-- interface as though SRAM - this module can take care of caching/write combining etc etc. For first cut... nothing. TODO: What extra info would help me here?
-	DATA_IN : in std_logic_vector(31 downto 0);
-	ADDRESS_IN : in std_logic_vector(ADDRESS_WIDTH downto 0); -- 1 extra bit for byte alignment
-	READ_EN : in std_logic; -- if no reads pending may be a good time to do a refresh
-	WRITE_EN : in std_logic;
-	REQUEST : in std_logic; -- Toggle this to issue a new request
-	BYTE_ACCESS : in std_logic; -- ldqm/udqm set based on a(0) - if 0=0111, if 1=1011. Data fields valid:7 downto 0.
-	WORD_ACCESS : in std_logic; -- ldqm/udqm set based on a(0) - if 0=0011, if 1=1001. Data fields valid:15 downto 0.
-	LONGWORD_ACCESS : in std_logic; -- a(0) ignored. lqdm/udqm mask is 0000
-	REFRESH : in std_logic;
-
-	REPLY : out std_logic; -- This matches the request once complete
-	DATA_OUT : out std_logic_vector(31 downto 0);
-
-	-- sdram itself
-	SDRAM_ADDR : out std_logic_vector(ROW_WIDTH downto 0);
-	SDRAM_DQ : inout std_logic_vector(15 downto 0);
-	SDRAM_BA0 : out std_logic;
-	SDRAM_BA1 : out std_logic;
-	
-	SDRAM_CS_N : out std_logic;
-	SDRAM_RAS_N : out std_logic;
-	SDRAM_CAS_N : out std_logic;
-	SDRAM_WE_N : out std_logic;
-	
-	SDRAM_ldqm : out std_logic; -- low enable, high disable - for byte addressing - NB, cas latency applies to reads
-	SDRAM_udqm : out std_logic
-);
-END component;
-
-COMPONENT zpu_rom
-	PORT(clock : IN STD_LOGIC;
-		 address : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
-		 q : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
-	);
-END COMPONENT;
-
-COMPONENT scandoubler
-	PORT(CLK : IN STD_LOGIC;
-		 RESET_N : IN STD_LOGIC;
-		 VGA : IN STD_LOGIC;
-		 COMPOSITE_ON_HSYNC : IN STD_LOGIC;
-		 colour_enable : IN STD_LOGIC;
-		 doubled_enable : IN STD_LOGIC;
-		 vsync_in : IN STD_LOGIC;
-		 hsync_in : IN STD_LOGIC;
-		 colour_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-		 VSYNC : OUT STD_LOGIC;
-		 HSYNC : OUT STD_LOGIC;
-		 B : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
-		 G : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
-		 R : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
-	);
-END COMPONENT;
-
-COMPONENT zpu_ram
-	PORT(wren : IN STD_LOGIC;
-		 clock : IN STD_LOGIC;
-		 address : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
-		 data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-		 q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
-	);
-END COMPONENT;
-
-COMPONENT zpu_config_regs
-	PORT(CLK : IN STD_LOGIC;
-		 ENABLE_179 : IN STD_LOGIC;
-		 WR_EN : IN STD_LOGIC;
-		 SDCARD_DAT : IN STD_LOGIC;
-		 SIO_COMMAND_OUT : IN STD_LOGIC;
-		 SIO_DATA_OUT : IN STD_LOGIC;
-		 PLL_LOCKED : IN STD_LOGIC;
-		 REQUEST_RESET_ZPU : IN STD_LOGIC;
-		 ADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
-		 CPU_DATA_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-		 KEY : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
-		 SWITCH : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
-		 SDCARD_CLK : OUT STD_LOGIC;
-		 SDCARD_CMD : OUT STD_LOGIC;
-		 SDCARD_DAT3 : OUT STD_LOGIC;
-		 SIO_DATA_IN : OUT STD_LOGIC;
-		 PAUSE_ZPU : OUT STD_LOGIC;
-		 PAL : OUT STD_LOGIC;
-		 USE_SDRAM : OUT STD_LOGIC;
-		 VGA : OUT STD_LOGIC;
-		 COMPOSITE_ON_HSYNC : OUT STD_LOGIC;
-		 GPIO_ENABLE : OUT STD_LOGIC;
-		 RESET_6502 : OUT STD_LOGIC;
-		 RESET_ZPU : OUT STD_LOGIC;
-		 RESET_N : OUT STD_LOGIC;
-		 PAUSE_6502 : OUT STD_LOGIC;
-		 DATA_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
-		 LEDG : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
-		 LEDR : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
-		 RAM_SELECT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
-		 ROM_SELECT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
-		 THROTTLE_COUNT_6502 : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
-		 ZPU_HEX : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
-		 sector : out std_logic_vector(31 downto 0);
-		 sector_request : out std_logic;
-		 sector_ready : in std_logic
-	);
-END COMPONENT;
-
-COMPONENT pll
-	PORT(inclk0 : IN STD_LOGIC;
-		 c0 : OUT STD_LOGIC;
-		 c1 : OUT STD_LOGIC;
-		 c2 : OUT STD_LOGIC;
-		 locked : OUT STD_LOGIC
-	);
-END COMPONENT;
-
-COMPONENT gtia
-	PORT(CLK : IN STD_LOGIC;
-		 WR_EN : IN STD_LOGIC;
-		 CPU_MEMORY_READY : IN STD_LOGIC;
-		 ANTIC_MEMORY_READY : IN STD_LOGIC;
-		 ANTIC_FETCH : IN STD_LOGIC;
-		 CPU_ENABLE_ORIGINAL : IN STD_LOGIC;
-		 RESET_N : IN STD_LOGIC;
-		 PAL : IN STD_LOGIC;
-		 COLOUR_CLOCK_ORIGINAL : IN STD_LOGIC;
-		 COLOUR_CLOCK : IN STD_LOGIC;
-		 COLOUR_CLOCK_HIGHRES : IN STD_LOGIC;
-		 CONSOL_START : IN STD_LOGIC;
-		 CONSOL_SELECT : IN STD_LOGIC;
-		 CONSOL_OPTION : IN STD_LOGIC;
-		 TRIG0 : IN STD_LOGIC;
-		 TRIG1 : IN STD_LOGIC;
-		 TRIG2 : IN STD_LOGIC;
-		 TRIG3 : IN STD_LOGIC;
-		 ADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
-		 AN : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
-		 CPU_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-		 MEMORY_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-		 VSYNC : OUT STD_LOGIC;
-		 HSYNC : OUT STD_LOGIC;
-		 sound : OUT STD_LOGIC;
-		 COLOUR_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
-		 DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
-	);
-END COMPONENT;
-
-COMPONENT irq_glue
-	PORT(pokey_irq : IN STD_LOGIC;
-		 pia_irqa : IN STD_LOGIC;
-		 pia_irqb : IN STD_LOGIC;
-		 combined_irq : OUT STD_LOGIC
-	);
-END COMPONENT;
-
-component reg_file IS
-generic
-(
-	BYTES : natural := 1;
-	WIDTH : natural := 1
-);
-PORT 
-( 
-	CLK : IN STD_LOGIC;
-	ADDR : IN STD_LOGIC_VECTOR(width-1 DOWNTO 0);
-	DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-	WR_EN : IN STD_LOGIC;
-	
-	DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
-);
-END component;
-
-component covox IS
-PORT 
-( 
-	CLK : IN STD_LOGIC;
-	ADDR : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
-	DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-	WR_EN : IN STD_LOGIC;
-	
-	covox_channel0 : out std_logic_vector(7 downto 0);
-	covox_channel1 : out std_logic_vector(7 downto 0);
-	covox_channel2 : out std_logic_vector(7 downto 0);
-	covox_channel3 : out std_logic_vector(7 downto 0)
-);
-END component;
-
-SIGNAL	ANTIC_ADDR :  STD_LOGIC_VECTOR(15 DOWNTO 0);
-SIGNAL	ANTIC_AN :  STD_LOGIC_VECTOR(2 DOWNTO 0);
-SIGNAL	ANTIC_COLOUR_CLOCK_OUT :  STD_LOGIC;
-SIGNAL	ANTIC_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
-SIGNAL	CACHE_ANTIC_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
-SIGNAL	ANTIC_ENABLE_179 :  STD_LOGIC;
-SIGNAL	ANTIC_FETCH :  STD_LOGIC;
-SIGNAL	ANTIC_HIGHRES_COLOUR_CLOCK_OUT :  STD_LOGIC;
-SIGNAL	ANTIC_ORIGINAL_COLOUR_CLOCK_OUT :  STD_LOGIC;
-SIGNAL	ANTIC_RDY :  STD_LOGIC;
-SIGNAL	ANTIC_REFRESH :  STD_LOGIC;
-SIGNAL	ANTIC_WRITE_ENABLE :  STD_LOGIC;
-SIGNAL	AUDIO_LEFT :  STD_LOGIC_VECTOR(15 DOWNTO 0);
-SIGNAL	AUDIO_RIGHT :  STD_LOGIC_VECTOR(15 DOWNTO 0);
-SIGNAL	BREAK_PRESSED :  STD_LOGIC;
-
-SIGNAL	CART_RD4 :  STD_LOGIC;
-SIGNAL	CART_RD5 :  STD_LOGIC;
-SIGNAL	CART_REQUEST :  STD_LOGIC;
-SIGNAL	CART_REQUEST_COMPLETE :  STD_LOGIC;
-SIGNAL	CART_ROM_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
-SIGNAL	CART_S4_n :  STD_LOGIC;
-SIGNAL	CART_S5_N :  STD_LOGIC;
-signal CART_CCTL_N : std_logic;
-SIGNAL	CA2_OUT :  STD_LOGIC;
-SIGNAL	CA2_DIR_OUT:  STD_LOGIC;
-SIGNAL	CB2_OUT :  STD_LOGIC;
-SIGNAL	CB2_DIR_OUT:  STD_LOGIC;
-SIGNAL	CLK :  STD_LOGIC;
-SIGNAL	CLK_SDRAM :  STD_LOGIC;
-SIGNAL	COMPOSITE_ON_HSYNC :  STD_LOGIC;
-SIGNAL	CONSOL_OPTION :  STD_LOGIC;
-SIGNAL	CONSOL_SELECT :  STD_LOGIC;
-SIGNAL	CONSOL_START :  STD_LOGIC;
-SIGNAL	CPU_6502_RESET :  STD_LOGIC;
-SIGNAL	CPU_ADDR :  STD_LOGIC_VECTOR(15 DOWNTO 0);
-SIGNAL	CPU_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
-SIGNAL	CPU_FETCH :  STD_LOGIC;
-SIGNAL	CPU_SHARED_ENABLE :  STD_LOGIC;
-SIGNAL	ENABLE_179_MEMWAIT :  STD_LOGIC;
-SIGNAL   GPIO_0_IN : STD_LOGIC_VECTOR(35 downto 0);
-SIGNAL   GPIO_0_OUT : STD_LOGIC_VECTOR(35 downto 0);
-SIGNAL   GPIO_0_DIR_OUT : STD_LOGIC_VECTOR(35 downto 0);
-SIGNAL   GPIO_1_IN : STD_LOGIC_VECTOR(35 downto 0);
-SIGNAL   GPIO_1_OUT : STD_LOGIC_VECTOR(35 downto 0);
-SIGNAL   GPIO_1_DIR_OUT : STD_LOGIC_VECTOR(35 downto 0);
-SIGNAL	GPIO_CA2_IN:  STD_LOGIC;
-SIGNAL	GPIO_CB2_IN:  STD_LOGIC;
-SIGNAL	GPIO_ENABLE :  STD_LOGIC;
-SIGNAL	GPIO_PORTA_IN :  STD_LOGIC_VECTOR(7 DOWNTO 0);
-SIGNAL	GPIO_PORTB_IN :  STD_LOGIC_VECTOR(7 DOWNTO 0);
-SIGNAL   GPIO_SIO_IN : STD_LOGIC;
-SIGNAL   GPIO_SIO_OUT : STD_LOGIC;
-SIGNAL	GREEN_LEDS :  STD_LOGIC_VECTOR(1 TO 1);
-SIGNAL	GREREN_LEDS :  STD_LOGIC_VECTOR(0 TO 0);
-SIGNAL	GTIA_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
-SIGNAL	CACHE_GTIA_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
-SIGNAL	GTIA_SOUND :  STD_LOGIC;
-SIGNAL	GTIA_WRITE_ENABLE :  STD_LOGIC;
-SIGNAL	IRQ_n :  STD_LOGIC;
-SIGNAL	KBCODE_DUMMY :  STD_LOGIC_VECTOR(7 DOWNTO 0);
-SIGNAL	KEY_HELD :  STD_LOGIC;
-SIGNAL	KEY_INTERRUPT :  STD_LOGIC;
-SIGNAL	KEYBOARD_RESPONSE :  STD_LOGIC_VECTOR(1 DOWNTO 0);
-SIGNAL	KEYBOARD_SCAN :  STD_LOGIC_VECTOR(5 DOWNTO 0);
-SIGNAL	LIGHTPEN :  STD_LOGIC;
-SIGNAL	MEMORY_DATA :  STD_LOGIC_VECTOR(31 DOWNTO 0);
-SIGNAL	MEMORY_READY_ANTIC :  STD_LOGIC;
-SIGNAL	MEMORY_READY_CPU :  STD_LOGIC;
-SIGNAL	MEMORY_READY_ZPU :  STD_LOGIC;
-SIGNAL	NMI_n :  STD_LOGIC;
-SIGNAL	PAL :  STD_LOGIC;
-SIGNAL	PAUSE_6502 :  STD_LOGIC;
-SIGNAL	PBI_ADDR :  STD_LOGIC_VECTOR(15 DOWNTO 0);
-SIGNAL	PBI_WRITE_ENABLE :  STD_LOGIC;
-SIGNAL	PIA_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
-SIGNAL	PIA_IRQA :  STD_LOGIC;
-SIGNAL	PIA_IRQB :  STD_LOGIC;
-SIGNAL	PIA_READ_ENABLE :  STD_LOGIC;
-SIGNAL	PIA_WRITE_ENABLE :  STD_LOGIC;
-SIGNAL	PLL_LOCKED :  STD_LOGIC;
-SIGNAL	POKEY2_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
-SIGNAL	CACHE_POKEY2_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
-SIGNAL	POKEY2_WRITE_ENABLE :  STD_LOGIC;
-SIGNAL	POKEY_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
-SIGNAL	CACHE_POKEY_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
-SIGNAL	POKEY_ENABLE_179 :  STD_LOGIC;
-SIGNAL	POKEY_IRQ :  STD_LOGIC;
-SIGNAL	POKEY_WRITE_ENABLE :  STD_LOGIC;
-SIGNAL	PORTA_OUT :  STD_LOGIC_VECTOR(7 DOWNTO 0);
-SIGNAL	PORTA_DIR_OUT :  STD_LOGIC_VECTOR(7 DOWNTO 0);
-SIGNAL	PORTB_OUT :  STD_LOGIC_VECTOR(7 DOWNTO 0);
-SIGNAL	PORTB_DIR_OUT :  STD_LOGIC_VECTOR(7 DOWNTO 0);
-SIGNAL	POT_IN :  STD_LOGIC_VECTOR(7 DOWNTO 0);
-SIGNAL	POT_RESET :  STD_LOGIC;
-SIGNAL	R_W_N :  STD_LOGIC;
-SIGNAL	RAM_ADDR :  STD_LOGIC_VECTOR(18 DOWNTO 0);
-SIGNAL	RAM_DO :  STD_LOGIC_VECTOR(15 DOWNTO 0);
-SIGNAL	RAM_REQUEST :  STD_LOGIC;
-SIGNAL	RAM_REQUEST_COMPLETE :  STD_LOGIC;
-SIGNAL	RAM_SELECT :  STD_LOGIC_VECTOR(3 DOWNTO 0);
-SIGNAL	RAM_WRITE_ENABLE :  STD_LOGIC;
-SIGNAL	RESET_N :  STD_LOGIC;
-SIGNAL	ROM_ADDR :  STD_LOGIC_VECTOR(21 DOWNTO 0);
-SIGNAL	ROM_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
-SIGNAL	ROM_REQUEST :  STD_LOGIC;
-SIGNAL	ROM_REQUEST_COMPLETE :  STD_LOGIC;
-SIGNAL	ROM_SELECT :  STD_LOGIC_VECTOR(3 DOWNTO 0);
-SIGNAL	SCANDOUBLER_SHARED_ENABLE_HIGH :  STD_LOGIC;
-SIGNAL	SCANDOUBLER_SHARED_ENABLE_LOW :  STD_LOGIC;
-SIGNAL	SDRAM_ADDR :  STD_LOGIC_VECTOR(22 DOWNTO 0);
-SIGNAL	SDRAM_DO :  STD_LOGIC_VECTOR(31 DOWNTO 0);
-SIGNAL	SDRAM_READ_ENABLE :  STD_LOGIC;
-SIGNAL	SDRAM_REFRESH :  STD_LOGIC;
---SIGNAL	SDRAM_REPLY :  STD_LOGIC;
-SIGNAL	SDRAM_REQUEST_COMPLETE :  STD_LOGIC;
-SIGNAL	SDRAM_REQUEST :  STD_LOGIC;
-SIGNAL	SDRAM_WRITE_ENABLE :  STD_LOGIC;
-SIGNAL	SHIFT_PRESSED :  STD_LOGIC;
-SIGNAL	SIO_COMMAND_OUT :  STD_LOGIC;
-SIGNAL	SIO_DATA_IN :  STD_LOGIC;
-SIGNAL	SIO_DATA_OUT :  STD_LOGIC;
-SIGNAL	SYNC_KEYS :  STD_LOGIC_VECTOR(3 DOWNTO 0);
-SIGNAL	SYNC_SWITCHES :  STD_LOGIC_VECTOR(9 DOWNTO 0);
-SIGNAL	SYSTEM_RESET_REQUEST :  STD_LOGIC;
-SIGNAL	THROTTLE_COUNT_6502 :  STD_LOGIC_VECTOR(5 DOWNTO 0);
-SIGNAL	TRIGGERS :  STD_LOGIC_VECTOR(3 DOWNTO 0);
-SIGNAL	USE_SDRAM :  STD_LOGIC;
-SIGNAL	VGA :  STD_LOGIC;
-SIGNAL	VIRTUAL_STICKS :  STD_LOGIC_VECTOR(7 DOWNTO 0);
-SIGNAL	VIRTUAL_TRIGGERS :  STD_LOGIC_VECTOR(3 DOWNTO 0);
-SIGNAL	VIRTUAL_KEYS :  STD_LOGIC_VECTOR(3 DOWNTO 0);
-SIGNAL	WIDTH_16BIT_ACCESS :  STD_LOGIC;
-SIGNAL	WIDTH_32BIT_ACCESS :  STD_LOGIC;
-SIGNAL	WIDTH_8BIT_ACCESS :  STD_LOGIC;
-SIGNAL	WRITE_DATA :  STD_LOGIC_VECTOR(31 DOWNTO 0);
-SIGNAL	ZPU_16BIT_WRITE_ENABLE :  STD_LOGIC;
-SIGNAL	ZPU_32BIT_WRITE_ENABLE :  STD_LOGIC;
-SIGNAL	ZPU_8BIT_WRITE_ENABLE :  STD_LOGIC;
-SIGNAL	ZPU_ADDR_FETCH :  STD_LOGIC_VECTOR(23 DOWNTO 0);
-SIGNAL	ZPU_ADDR_ROM_RAM :  STD_LOGIC_VECTOR(23 DOWNTO 0);
-SIGNAL	ZPU_CONFIG_DO :  STD_LOGIC_VECTOR(31 DOWNTO 0);
-SIGNAL	ZPU_CONFIG_WRITE_ENABLE :  STD_LOGIC;
-SIGNAL	ZPU_DO :  STD_LOGIC_VECTOR(31 DOWNTO 0);
-SIGNAL	ZPU_FETCH :  STD_LOGIC;
-SIGNAL	ZPU_HEX :  STD_LOGIC_VECTOR(15 DOWNTO 0);
-SIGNAL	ZPU_PAUSE :  STD_LOGIC;
-SIGNAL	ZPU_RAM_DATA :  STD_LOGIC_VECTOR(31 DOWNTO 0);
-SIGNAL	ZPU_READ_ENABLE :  STD_LOGIC;
-SIGNAL	ZPU_RESET :  STD_LOGIC;
-SIGNAL	ZPU_ROM_DATA :  STD_LOGIC_VECTOR(31 DOWNTO 0);
-SIGNAL	ZPU_SECTOR_DATA :  STD_LOGIC_VECTOR(31 DOWNTO 0);
-SIGNAL	ZPU_STACK_WRITE :  STD_LOGIC_VECTOR(3 DOWNTO 0);
-SIGNAL	SYNTHESIZED_WIRE_0 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
-SIGNAL	SYNTHESIZED_WIRE_1 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
-SIGNAL	SYNTHESIZED_WIRE_2 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
-SIGNAL	SYNTHESIZED_WIRE_3 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
-SIGNAL	SYNTHESIZED_WIRE_4 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
-SIGNAL	SYNTHESIZED_WIRE_5 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
-SIGNAL	SYNTHESIZED_WIRE_6 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
-SIGNAL	SYNTHESIZED_WIRE_7 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
-SIGNAL	SYNTHESIZED_WIRE_8 :  STD_LOGIC;
-SIGNAL	SYNTHESIZED_WIRE_9 :  STD_LOGIC;
-SIGNAL	SYNTHESIZED_WIRE_10 :  STD_LOGIC;
-SIGNAL	SYNTHESIZED_WIRE_11 :  STD_LOGIC_VECTOR(7 DOWNTO 0);
-SIGNAL	SYNTHESIZED_WIRE_12 :  STD_LOGIC;
-SIGNAL	SYNTHESIZED_WIRE_13 :  STD_LOGIC;
-SIGNAL	SYNTHESIZED_WIRE_14 :  STD_LOGIC_VECTOR(7 DOWNTO 0);
-
-SIGNAL	LEDR_dummy :  STD_LOGIC_VECTOR(9 DOWNTO 0);
-SIGNAL	LEDG_dummy :  STD_LOGIC_VECTOR(7 DOWNTO 0);
-signal UART_TXD_dummy : std_logic;
-
--- STUB OUT FOR NOW
-SIGNAL		PS2K_CLK :  STD_LOGIC;
-SIGNAL		PS2K_DAT :  STD_LOGIC;
-signal		JOY1_n :  STD_LOGIC_VECTOR(5 DOWNTO 0);
-signal		JOY2_n :  STD_LOGIC_VECTOR(5 DOWNTO 0);
-signal		JOY1 :  STD_LOGIC_VECTOR(5 DOWNTO 0);
-signal		JOY2 :  STD_LOGIC_VECTOR(5 DOWNTO 0);
-
-
-SIGNAL		SD_DAT0 :  STD_LOGIC;
-SIGNAL		SD_CLK :  STD_LOGIC;
-SIGNAL		SD_CMD :  STD_LOGIC;
-SIGNAL		SD_DAT3 :  STD_LOGIC;
-
-signal mist_buttons : std_logic_vector(1 downto 0);
-signal mist_switches : std_logic_vector(1 downto 0);
-
-signal keyboard : std_logic_vector(127 downto 0);
-signal atari_keyboard : std_logic_vector(63 downto 0);
-
-SIGNAL	SHIFT_PRESSED_DUMMY :  STD_LOGIC;
-SIGNAL	BREAK_PRESSED_DUMMY :  STD_LOGIC;
-SIGNAL	CONTROL_PRESSED :  STD_LOGIC;
-
-SIGNAL	CONSOL_OPTION_DUMMY :  STD_LOGIC;
-SIGNAL	CONSOL_SELECT_DUMMY :  STD_LOGIC;
-SIGNAL	CONSOL_START_DUMMY :  STD_LOGIC;
-
-signal capslock_pressed : std_logic;
-signal capsheld_next : std_logic;
-signal capsheld_reg : std_logic;
-
-signal mist_sector_ready : std_logic;
-signal mist_sector_ready_sync : std_logic;
-signal mist_sector_request : std_logic;
-signal mist_sector_request_sync : std_logic;
-signal mist_sector : std_logic_vector(31 downto 0);
-signal mist_sector_sync : std_logic_vector(31 downto 0);
-
-		
-signal mist_addr : std_logic_vector(8 downto 0);
-signal mist_do : std_logic_vector(7 downto 0);
-signal mist_di : std_logic_vector(7 downto 0);
-signal mist_wren : std_logic;
-
-signal spi_miso_data : std_logic;
-signal spi_miso_io : std_logic;
-
-signal covox_write_enable : std_logic;
-signal covox_channel0 : std_logic_vector(7 downto 0);
-signal covox_channel1 : std_logic_vector(7 downto 0);
-signal covox_channel2 : std_logic_vector(7 downto 0);
-signal covox_channel3 : std_logic_vector(7 downto 0);
-
-BEGIN 
-
-	
--- mist spi io
-mist_spi_interface : data_io 
-	PORT map
-	(
-		CLK =>spi_sck,
-		RESET_n =>reset_n,
-		
-		-- SPI connection - up to upstream to make miso 'Z' on ss_io going high
-		SPI_CLK =>spi_sck,
-		SPI_SS_IO => spi_ss2,
-		SPI_MISO => spi_miso_data,
-		SPI_MOSI => spi_di,
-		
-		-- Sector access request
-		request => mist_sector_request_sync,
-		sector => mist_sector_sync(23 downto 0),
-		ready => mist_sector_ready,
-		
-		-- DMA to RAM
-		ADDR => mist_addr,
-		DATA_OUT => mist_do,
-		DATA_IN => mist_di,
-		WR_EN => mist_wren
-	 );
- 
-	select_sync : synchronizer
-	PORT MAP ( CLK => clk, raw => mist_sector_ready, sync=>mist_sector_ready_sync);
-
-	select_sync2 : synchronizer
-	PORT MAP ( CLK => spi_sck, raw => mist_sector_request, sync=>mist_sector_request_sync);
-
-	sector_sync0 : synchronizer
-	PORT MAP ( CLK => spi_sck, raw => mist_sector(0), sync=>mist_sector_sync(0));
-
-	sector_sync1 : synchronizer
-	PORT MAP ( CLK => spi_sck, raw => mist_sector(1), sync=>mist_sector_sync(1));
-
-	sector_sync2 : synchronizer
-	PORT MAP ( CLK => spi_sck, raw => mist_sector(2), sync=>mist_sector_sync(2));
-
-	sector_sync3 : synchronizer
-	PORT MAP ( CLK => spi_sck, raw => mist_sector(3), sync=>mist_sector_sync(3));
-
-	sector_sync4 : synchronizer
-	PORT MAP ( CLK => spi_sck, raw => mist_sector(4), sync=>mist_sector_sync(4));
-
-	sector_sync5 : synchronizer
-	PORT MAP ( CLK => spi_sck, raw => mist_sector(5), sync=>mist_sector_sync(5));
-
-	sector_sync6 : synchronizer
-	PORT MAP ( CLK => spi_sck, raw => mist_sector(6), sync=>mist_sector_sync(6));
-
-	sector_sync7 : synchronizer
-	PORT MAP ( CLK => spi_sck, raw => mist_sector(7), sync=>mist_sector_sync(7));
-
-	sector_sync8 : synchronizer
-	PORT MAP ( CLK => spi_sck, raw => mist_sector(8), sync=>mist_sector_sync(8));
-
-	sector_sync9 : synchronizer
-	PORT MAP ( CLK => spi_sck, raw => mist_sector(9), sync=>mist_sector_sync(9));
-
-	sector_sync10 : synchronizer
-	PORT MAP ( CLK => spi_sck, raw => mist_sector(10), sync=>mist_sector_sync(10));
-
-	sector_sync11 : synchronizer
-	PORT MAP ( CLK => spi_sck, raw => mist_sector(11), sync=>mist_sector_sync(11));
-
-	sector_sync12 : synchronizer
-	PORT MAP ( CLK => spi_sck, raw => mist_sector(12), sync=>mist_sector_sync(12));
-
-	sector_sync13 : synchronizer
-	PORT MAP ( CLK => spi_sck, raw => mist_sector(13), sync=>mist_sector_sync(13));
-
-	sector_sync14 : synchronizer
-	PORT MAP ( CLK => spi_sck, raw => mist_sector(14), sync=>mist_sector_sync(14));
-
-	sector_sync15 : synchronizer
-	PORT MAP ( CLK => spi_sck, raw => mist_sector(15), sync=>mist_sector_sync(15));
-
-	sector_sync16 : synchronizer
-	PORT MAP ( CLK => spi_sck, raw => mist_sector(16), sync=>mist_sector_sync(16));
-
-	sector_sync17 : synchronizer
-	PORT MAP ( CLK => spi_sck, raw => mist_sector(17), sync=>mist_sector_sync(17));
-
-	sector_sync18 : synchronizer
-	PORT MAP ( CLK => spi_sck, raw => mist_sector(18), sync=>mist_sector_sync(18));
-
-	sector_sync19 : synchronizer
-	PORT MAP ( CLK => spi_sck, raw => mist_sector(19), sync=>mist_sector_sync(19));
-
-	sector_sync20 : synchronizer
-	PORT MAP ( CLK => spi_sck, raw => mist_sector(20), sync=>mist_sector_sync(20));
-
-	sector_sync21 : synchronizer
-	PORT MAP ( CLK => spi_sck, raw => mist_sector(21), sync=>mist_sector_sync(21));
-
-	sector_sync22 : synchronizer
-	PORT MAP ( CLK => spi_sck, raw => mist_sector(22), sync=>mist_sector_sync(22));
-
-	sector_sync23 : synchronizer
-	PORT MAP ( CLK => spi_sck, raw => mist_sector(23), sync=>mist_sector_sync(23));
-	
-	
-	spi_do <= spi_miso_io when CONF_DATA0 ='0' else spi_miso_data when spi_SS2='0' else 'Z';
-
-	-- TODO, dual port, dual clock! 
---	mist_sector_buffer : generic_ram_infer
---	generic map
---	(
---		ADDRESS_WIDTH => 9,
---		SPACE => 512,
---		DATA_WIDTH => 8
---	)
---   PORT map
---   (
---      clock => spi_sck,
---      data => mist_do,
---      address => mist_addr,
---      we => mist_wren,
---      q => mist_di
---   );
-
-mist_sector_buffer1 : mist_sector_buffer
-	PORT map
-	(
-		address_a		=> mist_addr,
-		address_b		=> ZPU_ADDR_ROM_RAM(8 DOWNTO 2),
-		clock_a		=> spi_sck,
-		clock_b		=> clk,
-		data_a		=> mist_do,
-		data_b		=> zpu_do,
-		wren_a		=> mist_wren,
-		wren_b		=> '0',
-		q_a		=> mist_di,
-		q_b		=> zpu_sector_data
-	);
-	
-my_user_io : user_io
-	PORT map(
-	   SPI_CLK => SPI_SCK,
-	   SPI_SS_IO => CONF_DATA0,
-	   SPI_MISO => SPI_miso_io,
-	   SPI_MOSI => SPI_DI,
-	   CORE_TYPE => x"A4",
-		JOY0 => joy1,
-		JOY1 => joy2,
-		KEYBOARD => keyboard,
-		BUTTONS => mist_buttons,
-		SWITCHES => mist_switches
-	  );
-	  
-	 joy1_n <= not(joy1);
-	 joy2_n <= not(joy2);
-	 
-	process(clk,reset_n)
-	begin
-		if (reset_n='0') then
-			capsheld_reg <= '0';
-		elsif (clk'event and clk='1') then
-			capsheld_reg <= capsheld_next;
-		end if;
-	end process;
-
-	process(keyboard,capsheld_reg)
-	begin
-		capsheld_next <= capsheld_reg;
-		capslock_pressed <= '0';
-		
-		if ((keyboard(58) xor capsheld_reg)='1') then
-			capsheld_next <= keyboard(58);
-			
-			-- assert something for 10 frames
-			capslock_pressed <= '1';
-		end if;
-	end process;
-	
-atari_keyboard(63) <= keyboard(30);
-atari_keyboard(62) <= keyboard(31);
-atari_keyboard(61) <= keyboard(34);
-atari_keyboard(60) <= '0';
-atari_keyboard(58) <= keyboard(32);
-atari_keyboard(57) <= keyboard(35);
-atari_keyboard(56) <= keyboard(33);
-atari_keyboard(55) <= keyboard(13);
-atari_keyboard(54) <= keyboard(12);
-atari_keyboard(53) <= keyboard(9);
-atari_keyboard(52) <= keyboard(14);
-atari_keyboard(51) <= keyboard(8);
-atari_keyboard(50) <= keyboard(11);
-atari_keyboard(48) <= keyboard(10);
-atari_keyboard(47) <= keyboard(16);
-atari_keyboard(46) <= keyboard(17);
-atari_keyboard(45) <= keyboard(20);
-atari_keyboard(44) <= keyboard(15);
-atari_keyboard(43) <= keyboard(21);
-atari_keyboard(42) <= keyboard(18);
-atari_keyboard(40) <= keyboard(19);
-atari_keyboard(39) <= keyboard(56);
-atari_keyboard(38) <= keyboard(53);
-atari_keyboard(37) <= keyboard(50);
-atari_keyboard(35) <= keyboard(49);
-atari_keyboard(34) <= keyboard(52);
-atari_keyboard(33) <= keyboard(57);
-atari_keyboard(32) <= keyboard(51);
-atari_keyboard(31) <= keyboard(2);
-atari_keyboard(30) <= keyboard(3);
-atari_keyboard(29) <= keyboard(6);
-atari_keyboard(28) <= keyboard(1);
-atari_keyboard(27) <= keyboard(7);
-atari_keyboard(26) <= keyboard(4);
-atari_keyboard(24) <= keyboard(5);
-atari_keyboard(23) <= keyboard(44);
-atari_keyboard(22) <= keyboard(45);
-atari_keyboard(21) <= keyboard(48);
-atari_keyboard(18) <= keyboard(46);
-atari_keyboard(17) <= keyboard(59);
-atari_keyboard(16) <= keyboard(47);
-atari_keyboard(15) <= keyboard(27);
-atari_keyboard(14) <= keyboard(26);
-atari_keyboard(13) <= keyboard(23);
-atari_keyboard(12) <= keyboard(28);
-atari_keyboard(11) <= keyboard(22);
-atari_keyboard(10) <= keyboard(25);
-atari_keyboard(8) <= keyboard(24);
-atari_keyboard(7) <= keyboard(41);
-atari_keyboard(6) <= keyboard(40);
-atari_keyboard(5) <= keyboard(37);
-atari_keyboard(2) <= keyboard(39);
-atari_keyboard(1) <= keyboard(36);
-atari_keyboard(0) <= keyboard(38);
-
-	  
-shift_pressed <= keyboard(54) or keyboard(42);
-control_pressed <= keyboard(29);
-break_pressed <= keyboard(96); -- TODO - not on st keyboard
-
-consol_start <= keyboard(60); --F2
-consol_select <= keyboard(61); --F3
-consol_option <= keyboard(62); -- F4
-		
---f5 <= keyboard(63);
---f6 <= keyboard(64);
---f7 <= keyboard(65);
---f8 <= keyboard(66);
---f9 <= keyboard(67);
---f10 <= keyboard(68);
-
-virtual_keys <= keyboard(65)&keyboard(66)&keyboard(67)&keyboard(68);
-SYSTEM_RESET_REQUEST <= keyboard(63);
-
-process(keyboard_scan, atari_keyboard, control_pressed, shift_pressed, break_pressed)
-	begin	
-		keyboard_response <= (others=>'1');		
-		
-		if (atari_keyboard(to_integer(unsigned(not(keyboard_scan)))) = '1') then
-			keyboard_response(0) <= '0';
-		end if;
-		
---		if (key_held='1' and kbcode(5 downto 0) = not(keyboard_scan)) then
---			keyboard_response(0) <= '0';
---		end if;
-		
-		if (keyboard_scan(5 downto 4)="00" and break_pressed = '1') then
-			keyboard_response(1) <= '0';
-		end if;
-		
-		if (keyboard_scan(5 downto 4)="10" and shift_pressed = '1') then
-			keyboard_response(1) <= '0';
-		end if;
-
-		if (keyboard_scan(5 downto 4)="11" and control_pressed = '1') then
-			keyboard_response(1) <= '0';
-		end if;
-end process;		 
-		  
-	-- decode address
---decode_addr1 : complete_address_decoder
---	generic map(width=>6)
---	port map (addr_in=>keyboard_scan, addr_decoded=>keyboard_scan_decoded);
-	  
-b2v_a_6502 : cpu
-PORT MAP(CLK => CLK,
-		 RESET => CPU_6502_RESET,
-		 ENABLE => RESET_N,
-		 IRQ_n => IRQ_n,
-		 NMI_n => NMI_n,
-		 MEMORY_READY => MEMORY_READY_CPU,
-		 THROTTLE => CPU_SHARED_ENABLE,
-		 RDY => ANTIC_RDY,
-		 DI => MEMORY_DATA(7 DOWNTO 0),
-		 R_W_n => R_W_N,
-		 CPU_FETCH => CPU_FETCH,
-		 A => CPU_ADDR,
-		 DO => CPU_DO);
-
-LIGHTPEN <= '1';
-b2v_inst1 : antic
-PORT MAP(CLK => CLK,
-		 WR_EN => ANTIC_WRITE_ENABLE,
-		 RESET_N => RESET_N,
-		 MEMORY_READY_ANTIC => MEMORY_READY_ANTIC,
-		 MEMORY_READY_CPU => MEMORY_READY_CPU,
-		 ANTIC_ENABLE_179 => ANTIC_ENABLE_179,
-		 PAL => PAL,
-		 lightpen => LIGHTPEN,
-		 ADDR => PBI_ADDR(3 DOWNTO 0),
-		 CPU_DATA_IN => WRITE_DATA(7 DOWNTO 0),
-		 MEMORY_DATA_IN => MEMORY_DATA(7 DOWNTO 0),
-		 NMI_N_OUT => NMI_n,
-		 ANTIC_READY => ANTIC_RDY,
-		 COLOUR_CLOCK_ORIGINAL_OUT => ANTIC_ORIGINAL_COLOUR_CLOCK_OUT,
-		 COLOUR_CLOCK_OUT => ANTIC_COLOUR_CLOCK_OUT,
-		 HIGHRES_COLOUR_CLOCK_OUT => ANTIC_HIGHRES_COLOUR_CLOCK_OUT,
-		 dma_fetch_out => ANTIC_FETCH,
-		 refresh_out => ANTIC_REFRESH,
-		 AN => ANTIC_AN,
-		 DATA_OUT => ANTIC_DO,
-		 dma_address_out => ANTIC_ADDR);
-
-b2v_inst11 : pokey_mixer
-PORT MAP(CLK => CLK,
-		 GTIA_SOUND => GTIA_SOUND,
-		 CHANNEL_0 => SYNTHESIZED_WIRE_0,
-		 CHANNEL_1 => SYNTHESIZED_WIRE_1,
-		 CHANNEL_2 => SYNTHESIZED_WIRE_2,
-		 CHANNEL_3 => SYNTHESIZED_WIRE_3,
-		 COVOX_CHANNEL_0 => covox_channel0,
-		 COVOX_CHANNEL_1 => covox_channel1,
-		 CHANNEL_ENABLE => "1111",
-		 VOLUME_OUT => AUDIO_LEFT);
-		 
-dac_left : hq_dac
-port map
-(
-  reset => not(reset_n),
-  clk => clk,
-  clk_ena => '1',
-  pcm_in => audio_left&"0000",
-  dac_out => audio_l
-);
-
-dac_right : hq_dac
-port map
-(
-  reset => not(reset_n),
-  clk => clk,
-  clk_ena => '1',
-  pcm_in => audio_right&"0000",
-  dac_out => audio_r
-);
-
-
-b2v_inst12 : ps2_keyboard
-PORT MAP(CLK => CLK,
-		 RESET_N => RESET_N,
-		 PS2_CLK => PS2K_CLK,
-		 PS2_DAT => PS2K_DAT,
-		 KEY_EVENT => SYNTHESIZED_WIRE_8,
-		 KEY_EXTENDED => SYNTHESIZED_WIRE_9,
-		 KEY_UP => SYNTHESIZED_WIRE_10,
-		 KEY_VALUE => SYNTHESIZED_WIRE_11);
-
-
-b2v_inst13 : zpu_glue
-PORT MAP(CLK => CLK,
-		 RESET => ZPU_RESET,
-		 PAUSE => ZPU_PAUSE,
-		 MEMORY_READY => MEMORY_READY_ZPU,
-		 ZPU_CONFIG_DI => ZPU_CONFIG_DO,
-		 ZPU_DI => MEMORY_DATA,
-		 ZPU_RAM_DI => ZPU_RAM_DATA,
-		 ZPU_ROM_DI => ZPU_ROM_DATA,
-		 ZPU_SECTOR_DI => zpu_sector_data,
-		 MEMORY_FETCH => ZPU_FETCH,
-		 ZPU_READ_ENABLE => ZPU_READ_ENABLE,
-		 ZPU_32BIT_WRITE_ENABLE => ZPU_32BIT_WRITE_ENABLE,
-		 ZPU_16BIT_WRITE_ENABLE => ZPU_16BIT_WRITE_ENABLE,
-		 ZPU_8BIT_WRITE_ENABLE => ZPU_8BIT_WRITE_ENABLE,
-		 ZPU_CONFIG_WRITE => ZPU_CONFIG_WRITE_ENABLE,
-		 ZPU_ADDR_FETCH => ZPU_ADDR_FETCH,
-		 ZPU_ADDR_ROM_RAM => ZPU_ADDR_ROM_RAM,
-		 ZPU_DO => ZPU_DO,
-		 ZPU_STACK_WRITE => ZPU_STACK_WRITE);
-
-
-b2v_inst14 : pokey_mixer
-PORT MAP(CLK => CLK,
-		 GTIA_SOUND => GTIA_SOUND,
-		 CHANNEL_0 => SYNTHESIZED_WIRE_4,
-		 CHANNEL_1 => SYNTHESIZED_WIRE_5,
-		 CHANNEL_2 => SYNTHESIZED_WIRE_6,
-		 CHANNEL_3 => SYNTHESIZED_WIRE_7,
-		 COVOX_CHANNEL_0 => covox_channel2,
-		 COVOX_CHANNEL_1 => covox_channel3, 
-		 CHANNEL_ENABLE => "1111",
-		 VOLUME_OUT => AUDIO_RIGHT);
-
-
-b2v_inst15 : pokey
-PORT MAP(CLK => CLK,
-		 CPU_MEMORY_READY => MEMORY_READY_CPU,
-		 ANTIC_MEMORY_READY => MEMORY_READY_ANTIC,
-		 WR_EN => POKEY2_WRITE_ENABLE,
-		 RESET_N => RESET_N,
-		 ADDR => PBI_ADDR(3 DOWNTO 0),
-		 DATA_IN => WRITE_DATA(7 DOWNTO 0),
-		 CHANNEL_0_OUT => SYNTHESIZED_WIRE_4,
-		 CHANNEL_1_OUT => SYNTHESIZED_WIRE_5,
-		 CHANNEL_2_OUT => SYNTHESIZED_WIRE_6,
-		 CHANNEL_3_OUT => SYNTHESIZED_WIRE_7,
-		 DATA_OUT => POKEY2_DO,
-		 SIO_IN1 => '1',
-		 SIO_IN2 => '1',
-		 SIO_IN3 => '1',
-		 keyboard_response => "00",
-		 pot_in=>"00000000");
-
-
--- PIA
---GPIO_0[0] <= CA2_OUT when CA2_DIR_OUT='1' else 'Z';
---CA2_IN <= GPIO_0[0];
-
---GPIO_O[1] <= CB2_OUT when CB2_DIR_OUT='1' else 'Z';
---CB2_IN <= GPIO_O[1];
-SIO_COMMAND_OUT <= CB2_OUT; -- we generate command frame, use internal rather than from pin
--- TODO - sioto gpio!
-GPIO_PORTB_IN <= PORTB_OUT;
-GPIO_CA2_IN <= CA2_OUT;
-GPIO_CB2_IN <= CB2_OUT;
-GPIO_PORTA_IN <= VIRTUAL_STICKS and (JOY1_n(0)&JOY1_n(1)&JOY1_n(2)&JOY1_n(3)&JOY2_n(0)&JOY2_n(1)&JOY2_n(2)&JOY2_n(3));
-
-b2v_inst16 : pia
-PORT MAP(CLK => CLK,
-		 EN => PIA_READ_ENABLE,
-		 WR_EN => PIA_WRITE_ENABLE,
-		 RESET_N => RESET_N,
-		 CA1 => '1', --todo - high/low?
-		 CB1 => '1',
-		 CA2_DIR_OUT => CA2_DIR_OUT,
-		 CA2_IN => GPIO_CA2_IN,
-		 CA2_OUT => CA2_OUT,
-		 CB2_DIR_OUT => CB2_DIR_OUT,
-		 CB2_IN => GPIO_CB2_IN,
-		 CB2_OUT => CB2_OUT,
-		 ADDR => PBI_ADDR(1 DOWNTO 0),
-		 CPU_DATA_IN => WRITE_DATA(7 DOWNTO 0),
-		 IRQA_N => PIA_IRQA,
-		 IRQB_N => PIA_IRQB,
-		 DATA_OUT => PIA_DO,
-		 PORTA_IN => GPIO_PORTA_IN,
-		 PORTA_DIR_OUT => PORTA_DIR_OUT,
-		 PORTA_OUT => PORTA_OUT,
-		 PORTB_IN => GPIO_PORTB_IN,
-		 PORTB_DIR_OUT => PORTB_DIR_OUT,
-		 PORTB_OUT => PORTB_OUT);
-
-b2v_inst17 : shared_enable
-PORT MAP(CLK => CLK,
-		 RESET_N => RESET_N,
-		 MEMORY_READY_CPU => MEMORY_READY_CPU,
-		 MEMORY_READY_ANTIC => MEMORY_READY_ANTIC,
-		 PAUSE_6502 => PAUSE_6502,
-		 THROTTLE_COUNT_6502 => THROTTLE_COUNT_6502,
-		 POKEY_ENABLE_179 => POKEY_ENABLE_179,
-		 ANTIC_ENABLE_179 => ANTIC_ENABLE_179,
-		 oldcpu_enable => ENABLE_179_MEMWAIT,
-		 CPU_ENABLE_OUT => CPU_SHARED_ENABLE,
-		 SCANDOUBLER_ENABLE_LOW => SCANDOUBLER_SHARED_ENABLE_LOW,
-		 SCANDOUBLER_ENABLE_HIGH => SCANDOUBLER_SHARED_ENABLE_HIGH);
-
-
-virtual_sticks <= (others=>'1');
-virtual_triggers <= "0011";
---b2v_inst18 : pokey_ps2_decoder
---PORT MAP(CLK => CLK,
---		 RESET_N => RESET_N,
---		 KEY_EVENT => SYNTHESIZED_WIRE_8,
---		 KEY_EXTENDED => SYNTHESIZED_WIRE_9,
---		 KEY_UP => SYNTHESIZED_WIRE_10,
---		 KEY_CODE => SYNTHESIZED_WIRE_11,
---		 KEY_HELD => KEY_HELD,
---		 SHIFT_PRESSED => SHIFT_PRESSED_DUMMY,
---		 BREAK_PRESSED => BREAK_PRESSED_DUMMY,
---		 CONSOL_START => CONSOL_START_DUMMY,
---		 CONSOL_SELECT => CONSOL_SELECT_DUMMY,
---		 CONSOL_OPTION => CONSOL_OPTION_DUMMY,
---		 SYSTEM_RESET => SYSTEM_RESET_REQUEST,
---		 KBCODE => KBCODE_dummy,
---		 VIRTUAL_STICKS => VIRTUAL_STICKS,
---		 VIRTUAL_TRIGGER => VIRTUAL_TRIGGERS,
---		 VIRTUAL_KEYS => VIRTUAL_KEYS);
-
--- no cart!
-CART_RD4 <= '0';
-CART_RD5 <= '0';
-CART_REQUEST_COMPLETE <= '0';
-CART_ROM_DO <= (others=>'0');
-
-b2v_inst2 : address_decoder
-PORT MAP(CLK => CLK,
-		 CPU_FETCH => CPU_FETCH,
-		 CPU_WRITE_N => R_W_N,
-		 ANTIC_FETCH => ANTIC_FETCH,
-		 antic_refresh => ANTIC_REFRESH,
-		 ZPU_FETCH => ZPU_FETCH,
-		 ZPU_READ_ENABLE => ZPU_READ_ENABLE,
-		 ZPU_32BIT_WRITE_ENABLE => ZPU_32BIT_WRITE_ENABLE,
-		 ZPU_16BIT_WRITE_ENABLE => ZPU_16BIT_WRITE_ENABLE,
-		 ZPU_8BIT_WRITE_ENABLE => ZPU_8BIT_WRITE_ENABLE,
-		 RAM_REQUEST_COMPLETE => RAM_REQUEST_COMPLETE,
-		 ROM_REQUEST_COMPLETE => ROM_REQUEST_COMPLETE,
-		 CART_REQUEST_COMPLETE => CART_REQUEST_COMPLETE,
-		 reset_n => RESET_N,
-		 CART_RD4 => CART_RD4,
-		 CART_RD5 => CART_RD5,
-		 use_sdram => USE_SDRAM,
-		 SDRAM_REQUEST_COMPLETE => SDRAM_REQUEST_COMPLETE,
-		 ANTIC_ADDR => ANTIC_ADDR,
-		 ANTIC_DATA => ANTIC_DO,
-		 CACHE_ANTIC_DATA => CACHE_ANTIC_DO,
-		 CART_ROM_DATA => CART_ROM_DO,
-		 CPU_ADDR => CPU_ADDR,
-		 CPU_WRITE_DATA => CPU_DO,
-		 GTIA_DATA => GTIA_DO,
-		 CACHE_GTIA_DATA => CACHE_GTIA_DO,
-		 PIA_DATA => PIA_DO,
-		 POKEY2_DATA => POKEY2_DO,
-		 CACHE_POKEY2_DATA => CACHE_POKEY2_DO,
-		 POKEY_DATA => POKEY_DO,
-		 CACHE_POKEY_DATA => CACHE_POKEY_DO,
-		 PORTB => PORTB_OUT,
-		 RAM_DATA => RAM_DO,
-		 ram_select => RAM_SELECT(2 downto 0),
-		 ROM_DATA => ROM_DO,
-		 rom_select => "00"&ROM_SELECT, -- TODO
-		 SDRAM_DATA => SDRAM_DO,
-		 ZPU_ADDR => ZPU_ADDR_FETCH,
-		 ZPU_WRITE_DATA => ZPU_DO,
-		 MEMORY_READY_ANTIC => MEMORY_READY_ANTIC,
-		 MEMORY_READY_ZPU => MEMORY_READY_ZPU,
-		 MEMORY_READY_CPU => MEMORY_READY_CPU,
-		 GTIA_WR_ENABLE => GTIA_WRITE_ENABLE,
-		 POKEY_WR_ENABLE => POKEY_WRITE_ENABLE,
-		 POKEY2_WR_ENABLE => POKEY2_WRITE_ENABLE,
-		 ANTIC_WR_ENABLE => ANTIC_WRITE_ENABLE,
-		 PIA_WR_ENABLE => PIA_WRITE_ENABLE,
-		 PIA_RD_ENABLE => PIA_READ_ENABLE,
-		 RAM_WR_ENABLE => RAM_WRITE_ENABLE,
-		 PBI_WR_ENABLE => PBI_WRITE_ENABLE,
-		 RAM_REQUEST => RAM_REQUEST,
-		 ROM_REQUEST => ROM_REQUEST,
-		 CART_REQUEST => CART_REQUEST,
-		 CART_S4_n => CART_S4_n,
-		 CART_S5_n => CART_S5_N,
-		 CART_CCTL_n => CART_CCTL_N,
-		 WIDTH_8bit_ACCESS => WIDTH_8BIT_ACCESS,
-		 WIDTH_16bit_ACCESS => WIDTH_16BIT_ACCESS,
-		 WIDTH_32bit_ACCESS => WIDTH_32BIT_ACCESS,
-		 SDRAM_READ_EN => SDRAM_READ_ENABLE,
-		 SDRAM_WRITE_EN => SDRAM_WRITE_ENABLE,
-		 SDRAM_REQUEST => SDRAM_REQUEST,
-		 SDRAM_REFRESH => SDRAM_REFRESH,
-		 MEMORY_DATA => MEMORY_DATA,
-		 PBI_ADDR => PBI_ADDR,
-		 RAM_ADDR => RAM_ADDR,
-		 ROM_ADDR => ROM_ADDR,
-		 SDRAM_ADDR => SDRAM_ADDR,
-		 WRITE_DATA => WRITE_DATA,
-		 d6_wr_enable => covox_write_enable,
-		 cart_select => "0000000",
-		 cart_activate => '0');
-
-b2v_inst21 : zpu_rom
-PORT MAP(clock => CLK,
-		 address => ZPU_ADDR_ROM_RAM(13 DOWNTO 2),
-		 q => ZPU_ROM_DATA);
-
-
-b2v_inst22 : scandoubler
-PORT MAP(CLK => CLK,
-		 RESET_N => RESET_N,
-		 VGA => VGA,
-		 COMPOSITE_ON_HSYNC => COMPOSITE_ON_HSYNC,
-		 colour_enable => SCANDOUBLER_SHARED_ENABLE_LOW,
-		 doubled_enable => SCANDOUBLER_SHARED_ENABLE_HIGH,
-		 vsync_in => SYNTHESIZED_WIRE_12,
-		 hsync_in => SYNTHESIZED_WIRE_13,
-		 colour_in => SYNTHESIZED_WIRE_14,
-		 VSYNC => VGA_VS,
-		 HSYNC => VGA_HS,
-		 B => VGA_B(5 downto 2),
-		 G => VGA_G(5 downto 2),
-		 R => VGA_R(5 downto 2));
-
-b2v_inst23 : zpu_ram
-PORT MAP(wren => ZPU_STACK_WRITE(2),
-		 clock => CLK,
-		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
-		 data => ZPU_DO(23 DOWNTO 16),
-		 q => ZPU_RAM_DATA(23 DOWNTO 16));
-
-SYNC_KEYS <= (others=> '0');
-SYNC_SWITCHES <= (others=> '1');
-b2v_inst24 : zpu_config_regs
-PORT MAP(CLK => CLK,
-		 ENABLE_179 => POKEY_ENABLE_179,
-		 WR_EN => ZPU_CONFIG_WRITE_ENABLE,
-		 SDCARD_DAT => SD_DAT0,
-		 SIO_COMMAND_OUT => SIO_COMMAND_OUT,
-		 SIO_DATA_OUT => SIO_DATA_OUT,
-		 PLL_LOCKED => PLL_LOCKED,
-		 REQUEST_RESET_ZPU => SYSTEM_RESET_REQUEST,
-		 ADDR => ZPU_ADDR_ROM_RAM(6 DOWNTO 2),
-		 CPU_DATA_IN => ZPU_DO,
-		 KEY => VIRTUAL_KEYS, --SYNC_KEYS,
-		 SWITCH => SYNC_SWITCHES,
-		 SDCARD_CLK => SD_CLK,
-		 SDCARD_CMD => SD_CMD,
-		 SDCARD_DAT3 => SD_DAT3,
-		 SIO_DATA_IN => SIO_DATA_IN,
-		 PAUSE_ZPU => ZPU_PAUSE,
-		 PAL => PAL,
-		 USE_SDRAM => USE_SDRAM,
-		 VGA => VGA,
-		 COMPOSITE_ON_HSYNC => COMPOSITE_ON_HSYNC,
-		 GPIO_ENABLE => GPIO_ENABLE,
-		 RESET_6502 => CPU_6502_RESET,
-		 RESET_ZPU => ZPU_RESET,
-		 RESET_N => RESET_N,
-		 PAUSE_6502 => PAUSE_6502,
-		 DATA_OUT => ZPU_CONFIG_DO,
-		 LEDG => LEDG_dummy,
-		 LEDR => LEDR_dummy,
-		 RAM_SELECT => RAM_SELECT,
-		 ROM_SELECT => ROM_SELECT,
-		 THROTTLE_COUNT_6502 => THROTTLE_COUNT_6502,
-		 ZPU_HEX => ZPU_HEX,
-		 sector_request => mist_sector_request,
-		 sector => mist_sector,
-		 sector_ready => mist_sector_ready_sync
-		 );
-
-
-b2v_inst25 : zpu_ram
-PORT MAP(wren => ZPU_STACK_WRITE(3),
-		 clock => CLK,
-		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
-		 data => ZPU_DO(31 DOWNTO 24),
-		 q => ZPU_RAM_DATA(31 DOWNTO 24));
-
-
-b2v_inst26 : zpu_ram
-PORT MAP(wren => ZPU_STACK_WRITE(0),
-		 clock => CLK,
-		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
-		 data => ZPU_DO(7 DOWNTO 0),
-		 q => ZPU_RAM_DATA(7 DOWNTO 0));
-
-
-b2v_inst27 : zpu_ram
-PORT MAP(wren => ZPU_STACK_WRITE(1),
-		 clock => CLK,
-		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
-		 data => ZPU_DO(15 DOWNTO 8),
-		 q => ZPU_RAM_DATA(15 DOWNTO 8));
-
-
-b2v_inst5 : pll
-PORT MAP(inclk0 => CLOCK_27(0),
-		 c0 => CLK_SDRAM,
-		 c1 => CLK,
-		 c2 => SDRAM_CLK,
-		 locked => PLL_LOCKED);
-
-b2v_inst7 : pokey
-PORT MAP(CLK => CLK,
-		 CPU_MEMORY_READY => MEMORY_READY_CPU,
-		 ANTIC_MEMORY_READY => MEMORY_READY_ANTIC,
-		 WR_EN => POKEY_WRITE_ENABLE,
-		 RESET_N => RESET_N,
-		 SIO_IN1 => '1',
-		 SIO_IN2 => '1',
-		 SIO_IN3 => SIO_DATA_IN,
-		 ADDR => PBI_ADDR(3 DOWNTO 0),
-		 DATA_IN => WRITE_DATA(7 DOWNTO 0),
-		 keyboard_response => KEYBOARD_RESPONSE,
-		 POT_IN => POT_IN,
-		 IRQ_N_OUT => POKEY_IRQ,
-		 SIO_OUT1 => UART_TXD_dummy,
-		 SIO_OUT2 => GPIO_SIO_OUT,
-		 SIO_OUT3 => SIO_DATA_OUT,
-		 POT_RESET => POT_RESET,
-		 CHANNEL_0_OUT => SYNTHESIZED_WIRE_0,
-		 CHANNEL_1_OUT => SYNTHESIZED_WIRE_1,
-		 CHANNEL_2_OUT => SYNTHESIZED_WIRE_2,
-		 CHANNEL_3_OUT => SYNTHESIZED_WIRE_3,
-		 DATA_OUT => POKEY_DO,
-		 keyboard_scan => KEYBOARD_SCAN);
-
---	process(keyboard_scan, kbcode, key_held, shift_pressed, break_pressed)
---	begin	
---		keyboard_response <= (others=>'1');
---		
---		if (key_held='1' and kbcode(5 downto 0) = not(keyboard_scan)) then
---			keyboard_response(0) <= '0';
---		end if;
---		
---		if (keyboard_scan(5 downto 4)="00" and break_pressed = '1') then
---			keyboard_response(1) <= '0';
---		end if;
---		
---		if (keyboard_scan(5 downto 4)="10" and shift_pressed = '1') then
---			keyboard_response(1) <= '0';
---		end if;
---
---		if (keyboard_scan(5 downto 4)="11" and kbcode(7) = '1') then
---			keyboard_response(1) <= '0';
---		end if;
---	end process;		 
---		 	 
-b2v_inst8 : gtia
-PORT MAP(CLK => CLK,
-		 WR_EN => GTIA_WRITE_ENABLE,
-		 CPU_MEMORY_READY => MEMORY_READY_CPU,
-		 ANTIC_MEMORY_READY => MEMORY_READY_ANTIC,
-		 ANTIC_FETCH => ANTIC_FETCH,
-		 CPU_ENABLE_ORIGINAL => ENABLE_179_MEMWAIT,
-		 RESET_N => RESET_N,
-		 PAL => PAL,
-		 COLOUR_CLOCK_ORIGINAL => ANTIC_ORIGINAL_COLOUR_CLOCK_OUT,
-		 COLOUR_CLOCK => ANTIC_COLOUR_CLOCK_OUT,
-		 COLOUR_CLOCK_HIGHRES => ANTIC_HIGHRES_COLOUR_CLOCK_OUT,
-		 CONSOL_START => CONSOL_START,
-		 CONSOL_SELECT => CONSOL_SELECT,
-		 CONSOL_OPTION => CONSOL_OPTION,
-		 TRIG0 => VIRTUAL_TRIGGERS(0) and joy2_n(4), -- TODO - joystick trigger too
-		 TRIG1 => VIRTUAL_TRIGGERS(1) and joy1_n(4),
-		 --TRIG0 => VIRTUAL_TRIGGERS(0),
-		 --TRIG1 => VIRTUAL_TRIGGERS(1),
-		 TRIG2 => VIRTUAL_TRIGGERS(2),
-		 TRIG3 => VIRTUAL_TRIGGERS(3),
-		 ADDR => PBI_ADDR(4 DOWNTO 0),
-		 AN => ANTIC_AN,
-		 CPU_DATA_IN => WRITE_DATA(7 DOWNTO 0),
-		 MEMORY_DATA_IN => MEMORY_DATA(7 DOWNTO 0),
-		 VSYNC => SYNTHESIZED_WIRE_12,
-		 HSYNC => SYNTHESIZED_WIRE_13,
-		 sound => GTIA_SOUND,
-		 COLOUR_out => SYNTHESIZED_WIRE_14,
-		 DATA_OUT => GTIA_DO);
-
-
-b2v_inst9 : irq_glue
-PORT MAP(pokey_irq => POKEY_IRQ,
-		 pia_irqa => PIA_IRQA,
-		 pia_irqb => PIA_IRQB,
-		 combined_irq => IRQ_n);
-		 
-pokey1_mirror : reg_file
-generic map(BYTES=>16,WIDTH=>4)
-port map(
-	CLK => CLK,
-	ADDR => PBI_ADDR(3 downto 0),
-	DATA_IN => WRITE_DATA(7 downto 0),
-	WR_EN => POKEY_WRITE_ENABLE,
-	DATA_OUT => CACHE_POKEY_DO
-);	 
-
-pokey2_mirror : reg_file
-generic map(BYTES=>16,WIDTH=>4)
-port map(
-	CLK => CLK,
-	ADDR => PBI_ADDR(3 downto 0),
-	DATA_IN => WRITE_DATA(7 downto 0),
-	WR_EN => POKEY2_WRITE_ENABLE,
-	DATA_OUT => CACHE_POKEY2_DO
-);	 		 
-
-gtia_mirror : reg_file
-generic map(BYTES=>32,WIDTH=>5)
-port map(
-	CLK => CLK,
-	ADDR => PBI_ADDR(4 downto 0),
-	DATA_IN => WRITE_DATA(7 downto 0),
-	WR_EN => GTIA_WRITE_ENABLE,
-	DATA_OUT => CACHE_GTIA_DO
-);	
-
-antic_mirror : reg_file
-generic map(BYTES=>16,WIDTH=>4)
-port map(
-	CLK => CLK,
-	ADDR => PBI_ADDR(3 downto 0),
-	DATA_IN => WRITE_DATA(7 downto 0),
-	WR_EN => ANTIC_WRITE_ENABLE,
-	DATA_OUT => CACHE_ANTIC_DO
-);	
-
-irr : internalromram
-  PORT map(
-    clock => clk,
-    reset_n => reset_n,
-
-	ROM_ADDR =>rom_addr,
-	ROM_REQUEST_COMPLETE => rom_REQUEST_COMPLETE,
-	ROM_REQUEST => rom_REQUEST,
-	ROM_DATA => rom_DO,
-	
-	RAM_ADDR => ram_addr,
-	RAM_WR_ENABLE => ram_WRITE_ENABLE,
-	RAM_DATA_IN => wriTE_DATA(7 downto 0),
-	RAM_REQUEST_COMPLETE => ram_REQUEST_COMPLETE,
-	RAM_REQUEST => ram_REQUEST,
-	RAM_DATA => ram_do(7 downto 0)
-	);
-
-b2v_inst20 : sdram_statemachine
-GENERIC MAP(ADDRESS_WIDTH => 22,
-			AP_BIT => 10,
-			COLUMN_WIDTH => 8,
-			ROW_WIDTH => 12
-			)
-PORT MAP(CLK_SYSTEM => CLK,
-		 CLK_SDRAM => CLK_SDRAM,
-		 RESET_N => RESET_N,
-		 READ_EN => SDRAM_READ_ENABLE,
-		 WRITE_EN => SDRAM_WRITE_ENABLE,
-		 REQUEST => SDRAM_REQUEST,
-		 BYTE_ACCESS => WIDTH_8BIT_ACCESS,
-		 WORD_ACCESS => WIDTH_16BIT_ACCESS,
-		 LONGWORD_ACCESS => WIDTH_32BIT_ACCESS,
-		 REFRESH => SDRAM_REFRESH,
-		 ADDRESS_IN => SDRAM_ADDR,
-		 DATA_IN => WRITE_DATA,
-		 SDRAM_DQ => SDRAM_DQ,
-		 COMPLETE => SDRAM_REQUEST_COMPLETE,
-		 SDRAM_BA0 => SDRAM_BA(0),
-		 SDRAM_BA1 => SDRAM_BA(1),
-		 SDRAM_CKE => SDRAM_CKE,
-		 SDRAM_CS_N => SDRAM_nCS,
-		 SDRAM_RAS_N => SDRAM_nRAS,
-		 SDRAM_CAS_N => SDRAM_nCAS,
-		 SDRAM_WE_N => SDRAM_nWE,
-		 SDRAM_ldqm => SDRAM_DQML,
-		 SDRAM_udqm => SDRAM_DQMH,
-		 DATA_OUT => SDRAM_DO,
-		 SDRAM_ADDR => SDRAM_A(11 downto 0));
-		 
-SDRAM_A(12) <= '0';
-
---b2v_inst20 : sdram_statemachine_mcc
---GENERIC MAP(ADDRESS_WIDTH => 22,
---			AP_BIT => 10,
---			COLUMN_WIDTH => 8,
---			ROW_WIDTH => 12
---			)
---PORT MAP(CLK_SYSTEM => CLK,
---		 CLK_SDRAM => CLK_SDRAM,
---		 RESET_N => RESET_N,
---		 READ_EN => SDRAM_READ_ENABLE,
---		 WRITE_EN => SDRAM_WRITE_ENABLE,
---		 REQUEST => SDRAM_REQUEST,
---		 BYTE_ACCESS => WIDTH_8BIT_ACCESS,
---		 WORD_ACCESS => WIDTH_16BIT_ACCESS,
---		 LONGWORD_ACCESS => WIDTH_32BIT_ACCESS,
---		 REFRESH => SDRAM_REFRESH,
---		 ADDRESS_IN => SDRAM_ADDR,
---		 DATA_IN => WRITE_DATA,
---		 SDRAM_DQ => SDRAM_DQ,
---		 REPLY => SDRAM_REQUEST_COMPLETE,
---		 SDRAM_BA0 => SDRAM_BA(0),
---		 SDRAM_BA1 => SDRAM_BA(1),
---		 --SDRAM_CKE => SDRAM_A(12), -- TODO?
---		 SDRAM_CS_N => SDRAM_nCS,
---		 SDRAM_RAS_N => SDRAM_nRAS,
---		 SDRAM_CAS_N => SDRAM_nCAS,
---		 SDRAM_WE_N => SDRAM_nWE,
---		 SDRAM_ldqm => SDRAM_DQML,
---		 SDRAM_udqm => SDRAM_DQMH,
---		 DATA_OUT => SDRAM_DO,
---		 SDRAM_ADDR => SDRAM_A(12 downto 0)); -- TODO?
-
---SDRAM_CKE <= '1';		 
-LED <= '0';
-VGA_R(1 downto 0) <= "00";
-VGA_G(1 downto 0) <= "00";
-VGA_B(1 downto 0) <= "00";
-
-covox1 : covox
-	PORT map
-	( 
-		clk => clk,
-		addr => pbi_addr(1 downto 0),
-		data_in => WRITE_DATA(7 DOWNTO 0),
-		wr_en => covox_write_enable,
-		covox_channel0 => covox_channel0,
-		covox_channel1 => covox_channel1,
-		covox_channel2 => covox_channel2,
-		covox_channel3 => covox_channel3
-	);
-		
-END bdf_type;
\ No newline at end of file
Index: mist/atari800core_assignment_defaults.qdf
===================================================================
--- mist/atari800core_assignment_defaults.qdf	(revision 15)
+++ mist/atari800core_assignment_defaults.qdf	(nonexistent)
@@ -1,796 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2012 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 64-Bit
-# Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Web Edition
-# Date created = 09:08:15  February 16, 2014
-#
-# -------------------------------------------------------------------------- #
-#
-# Note:
-#
-# 1) Do not modify this file. This file was generated
-#    automatically by the Quartus II software and is used
-#    to preserve global assignments across Quartus II versions.
-#
-# -------------------------------------------------------------------------- #
-
-set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
-set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off
-set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off
-set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
-set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
-set_global_assignment -name SMART_RECOMPILE Off
-set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
-set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off
-set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off
-set_global_assignment -name HC_OUTPUT_DIR hc_output
-set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
-set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
-set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
-set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off
-set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings"
-set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On
-set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On
-set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off
-set_global_assignment -name REVISION_TYPE Base
-set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
-set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
-set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
-set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
-set_global_assignment -name DO_COMBINED_ANALYSIS Off
-set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On
-set_global_assignment -name TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000B
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy II"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV E"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix IV"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000AE
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX V"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family Cyclone
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix II GX"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix V"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V GZ"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX II"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GX"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GZ"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "Stratix GX"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy III"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000S
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone II"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV GX"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy IV"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III LS"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix III"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria GX"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX3000A
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix II"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone V"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family Stratix
-set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING Off
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX7000B
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "HardCopy II"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone III"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX7000AE
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix II GX"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family Cyclone
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix GX"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "HardCopy III"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX7000S
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone II"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "HardCopy IV"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone III LS"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix III"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria GX"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX3000A
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix II"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family Stratix
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V"
-set_global_assignment -name TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS 100
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000B
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "HardCopy II"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV E"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix IV"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000AE
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX V"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family Cyclone
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix II GX"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix V"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V GZ"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX II"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GX"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix GX"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GZ"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000S
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "HardCopy III"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Cyclone II"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV GX"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "HardCopy IV"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III LS"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix III"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Arria GX"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX3000A
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix II"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone V"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family Stratix
-set_global_assignment -name MUX_RESTRUCTURE Auto
-set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off
-set_global_assignment -name ENABLE_IP_DEBUG Off
-set_global_assignment -name SAVE_DISK_SPACE On
-set_global_assignment -name DISABLE_OCP_HW_EVAL Off
-set_global_assignment -name DEVICE_FILTER_PACKAGE Any
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
-set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
-set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
-set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
-set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993
-set_global_assignment -name FAMILY -value "Cyclone IV GX"
-set_global_assignment -name TRUE_WYSIWYG_FLOW Off
-set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
-set_global_assignment -name STATE_MACHINE_PROCESSING Auto
-set_global_assignment -name SAFE_STATE_MACHINE Off
-set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
-set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
-set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
-set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
-set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
-set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On
-set_global_assignment -name PARALLEL_SYNTHESIS On
-set_global_assignment -name DSP_BLOCK_BALANCING Auto
-set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
-set_global_assignment -name NOT_GATE_PUSH_BACK On
-set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
-set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
-set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
-set_global_assignment -name IGNORE_CARRY_BUFFERS Off
-set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
-set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
-set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
-set_global_assignment -name IGNORE_LCELL_BUFFERS Off
-set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
-set_global_assignment -name IGNORE_SOFT_BUFFERS On
-set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
-set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
-set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
-set_global_assignment -name AUTO_GLOBAL_OE_MAX On
-set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
-set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
-set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
-set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced
-set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
-set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
-set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
-set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
-set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
-set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
-set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
-set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
-set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
-set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
-set_global_assignment -name ALLOW_XOR_GATE_USAGE On
-set_global_assignment -name AUTO_LCELL_INSERTION On
-set_global_assignment -name CARRY_CHAIN_LENGTH 48
-set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
-set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
-set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
-set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
-set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
-set_global_assignment -name CASCADE_CHAIN_LENGTH 2
-set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
-set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
-set_global_assignment -name AUTO_CARRY_CHAINS On
-set_global_assignment -name AUTO_CASCADE_CHAINS On
-set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
-set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
-set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
-set_global_assignment -name AUTO_ROM_RECOGNITION On
-set_global_assignment -name AUTO_RAM_RECOGNITION On
-set_global_assignment -name AUTO_DSP_RECOGNITION On
-set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto
-set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
-set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
-set_global_assignment -name STRICT_RAM_RECOGNITION Off
-set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
-set_global_assignment -name FORCE_SYNCH_CLEAR Off
-set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
-set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
-set_global_assignment -name AUTO_RESOURCE_SHARING Off
-set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off
-set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off
-set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
-set_global_assignment -name MAX7000_FANIN_PER_CELL 100
-set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On
-set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
-set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
-set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
-set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
-set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "HardCopy III"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Cyclone II"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "HardCopy II"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "HardCopy IV"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone III"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone III LS"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix III"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Night Fury"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Arria GX"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Stratix II GX"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Stratix II"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX"
-set_global_assignment -name REPORT_PARAMETER_SETTINGS On
-set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On
-set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On
-set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V"
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "HardCopy II"
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E"
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV"
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone III"
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Night Fury"
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family Cyclone
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V"
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Stratix II GX"
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V"
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II"
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ"
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX"
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ"
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Stratix GX"
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "HardCopy III"
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone II"
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX"
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "HardCopy IV"
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone III LS"
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Stratix III"
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Arria GX"
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Stratix II"
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family Stratix
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V"
-set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
-set_global_assignment -name HDL_MESSAGE_LEVEL Level2
-set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
-set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000
-set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000
-set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100
-set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
-set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off
-set_global_assignment -name BLOCK_DESIGN_NAMING Auto
-set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off
-set_global_assignment -name SYNTHESIS_EFFORT Auto
-set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On
-set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off
-set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium
-set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ"
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy III"
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V"
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone II"
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy II"
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX"
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV"
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E"
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy IV"
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone III LS"
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone III"
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix III"
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Night Fury"
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family Cyclone
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix II"
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V"
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ"
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V"
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family Stratix
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX"
-set_global_assignment -name MAX_LABS "-1 (Unlimited)"
-set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On
-set_global_assignment -name SYNTHESIS_SEED 1
-set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)"
-set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
-set_global_assignment -name AUTO_MERGE_PLLS On
-set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
-set_global_assignment -name TXPMA_SLEW_RATE Low
-set_global_assignment -name ADCE_ENABLED Auto
-set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
-set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off
-set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
-set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
-set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
-set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
-set_global_assignment -name DEVICE AUTO
-set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
-set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
-set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
-set_global_assignment -name ENABLE_NCEO_OUTPUT Off
-set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
-set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
-set_global_assignment -name STRATIX_UPDATE_MODE Standard
-set_global_assignment -name CVP_MODE Off
-set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
-set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
-set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
-set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name USER_START_UP_CLOCK Off
-set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC
-set_global_assignment -name ENABLE_VREFA_PIN Off
-set_global_assignment -name ENABLE_VREFB_PIN Off
-set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
-set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
-set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
-set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
-set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
-set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
-set_global_assignment -name INIT_DONE_OPEN_DRAIN On
-set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
-set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Cyclone II"
-set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family Cyclone
-set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Stratix II GX"
-set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "HardCopy II"
-set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Arria GX"
-set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Stratix II"
-set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
-set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
-set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
-set_global_assignment -name CRC_ERROR_CHECKING Off
-set_global_assignment -name INTERNAL_SCRUBBING Off
-set_global_assignment -name PR_ERROR_OPEN_DRAIN On
-set_global_assignment -name PR_READY_OPEN_DRAIN On
-set_global_assignment -name ENABLE_CVP_CONFDONE Off
-set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix GX"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "HardCopy III"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Cyclone II"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "HardCopy II"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "HardCopy IV"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone III LS"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone III"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix III"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Night Fury"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria GX"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family Cyclone
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix II GX"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix II"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family Stratix
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family MAX7000B
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "HardCopy II"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone III"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "Night Fury"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family MAX7000AE
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family Cyclone
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix II GX"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "Stratix GX"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family MAX7000S
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "HardCopy III"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone II"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "HardCopy IV"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone III LS"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix III"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria GX"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family MAX3000A
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix II"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family Stratix
-set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
-set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
-set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
-set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING "Force All Tiles with Failing Timing Paths to High Speed"
-set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
-set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
-set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
-set_global_assignment -name OPTIMIZE_SSN Off
-set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
-set_global_assignment -name ECO_OPTIMIZE_TIMING Off
-set_global_assignment -name ECO_REGENERATE_REPORT Off
-set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal
-set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
-set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
-set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
-set_global_assignment -name SEED 1
-set_global_assignment -name SLOW_SLEW_RATE Off
-set_global_assignment -name PCI_IO Off
-set_global_assignment -name TURBO_BIT On
-set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
-set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
-set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
-set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
-set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII AUTO
-set_global_assignment -name AUTO_PACKED_REGISTERS_MAXII AUTO
-set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE Auto
-set_global_assignment -name AUTO_PACKED_REGISTERS Off
-set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIX AUTO
-set_global_assignment -name NORMAL_LCELL_INSERT On
-set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
-set_global_assignment -name AUTO_DELAY_CHAINS On
-set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF
-set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
-set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
-set_global_assignment -name AUTO_TURBO_BIT ON
-set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
-set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
-set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
-set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
-set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
-set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
-set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
-set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
-set_global_assignment -name FITTER_EFFORT "Auto Fit"
-set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
-set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
-set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION AUTO
-set_global_assignment -name ROUTER_REGISTER_DUPLICATION AUTO
-set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
-set_global_assignment -name AUTO_GLOBAL_CLOCK On
-set_global_assignment -name AUTO_GLOBAL_OE On
-set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
-set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
-set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
-set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
-set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
-set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
-set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
-set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
-set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
-set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
-set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
-set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
-set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
-set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
-set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
-set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
-set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
-set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
-set_global_assignment -name ENABLE_HOLD_BACK_OFF On
-set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
-set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
-set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Off
-set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On
-set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone III"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Night Fury"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "HardCopy III"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone III LS"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Stratix III"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V"
-set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
-set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
-set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
-set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
-set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Night Fury"
-set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX"
-set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V"
-set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V"
-set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ"
-set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V"
-set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX"
-set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off
-set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
-set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
-set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off
-set_global_assignment -name PR_DONE_OPEN_DRAIN On
-set_global_assignment -name NCEO_OPEN_DRAIN On
-set_global_assignment -name ENABLE_CRC_ERROR_PIN Off
-set_global_assignment -name ENABLE_PR_PINS Off
-set_global_assignment -name PR_PINS_OPEN_DRAIN Off
-set_global_assignment -name CLAMPING_DIODE Off
-set_global_assignment -name TRI_STATE_SPI_PINS Off
-set_global_assignment -name UNUSED_TSD_PINS_GND Off
-set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off
-set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off
-set_global_assignment -name ALM_REGISTER_PACKING_EFFORT LOW
-set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
-set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
-set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>"
-set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>"
-set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>"
-set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "<None>"
-set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
-set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
-set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
-set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
-set_global_assignment -name COMPRESSION_MODE Off
-set_global_assignment -name CLOCK_SOURCE Internal
-set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
-set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
-set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
-set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
-set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
-set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
-set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
-set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
-set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
-set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
-set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
-set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
-set_global_assignment -name USE_CHECKSUM_AS_USERCODE Off
-set_global_assignment -name SECURITY_BIT Off
-set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000B
-set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "HardCopy II"
-set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"
-set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E"
-set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III"
-set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000AE
-set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V"
-set_global_assignment -name USE_CONFIGURATION_DEVICE On -family Cyclone
-set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix II GX"
-set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"
-set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"
-set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix GX"
-set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ"
-set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000S
-set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "HardCopy III"
-set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Cyclone II"
-set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX"
-set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "HardCopy IV"
-set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III LS"
-set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix III"
-set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Arria GX"
-set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX3000A
-set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix II"
-set_global_assignment -name USE_CONFIGURATION_DEVICE On -family Stratix
-set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
-set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
-set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
-set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
-set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
-set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
-set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
-set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
-set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
-set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
-set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
-set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
-set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
-set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
-set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
-set_global_assignment -name GENERATE_TTF_FILE Off
-set_global_assignment -name GENERATE_RBF_FILE Off
-set_global_assignment -name GENERATE_HEX_FILE Off
-set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
-set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
-set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
-set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
-set_global_assignment -name AUTO_RESTART_CONFIGURATION On
-set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
-set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
-set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
-set_global_assignment -name ENABLE_OCT_DONE Off
-set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF
-set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off
-set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off
-set_global_assignment -name START_TIME 0ns
-set_global_assignment -name SIMULATION_MODE TIMING
-set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
-set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
-set_global_assignment -name SETUP_HOLD_DETECTION Off
-set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
-set_global_assignment -name CHECK_OUTPUTS Off
-set_global_assignment -name SIMULATION_COVERAGE On
-set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
-set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
-set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
-set_global_assignment -name GLITCH_DETECTION Off
-set_global_assignment -name GLITCH_INTERVAL 1ns
-set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
-set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On
-set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
-set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
-set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
-set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
-set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT
-set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT
-set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off
-set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO
-set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO
-set_global_assignment -name DRC_TOP_FANOUT 50
-set_global_assignment -name DRC_FANOUT_EXCEEDING 30
-set_global_assignment -name DRC_GATED_CLOCK_FEED 30
-set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
-set_global_assignment -name ENABLE_DRC_SETTINGS Off
-set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
-set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
-set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
-set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2
-set_global_assignment -name MERGE_HEX_FILE Off
-set_global_assignment -name GENERATE_SVF_FILE Off
-set_global_assignment -name GENERATE_ISC_FILE Off
-set_global_assignment -name GENERATE_JAM_FILE Off
-set_global_assignment -name GENERATE_JBC_FILE Off
-set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
-set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
-set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
-set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
-set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
-set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
-set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
-set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
-set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
-set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
-set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
-set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
-set_global_assignment -name POWER_USE_PVA On
-set_global_assignment -name POWER_USE_INPUT_FILE "No File"
-set_global_assignment -name POWER_USE_INPUT_FILES Off
-set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
-set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off
-set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off
-set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
-set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
-set_global_assignment -name POWER_TJ_VALUE 25
-set_global_assignment -name POWER_USE_TA_VALUE 25
-set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
-set_global_assignment -name POWER_BOARD_TEMPERATURE 25
-set_global_assignment -name POWER_HPS_ENABLE Off
-set_global_assignment -name POWER_HPS_PROC_FREQ 0.0
-set_global_assignment -name IGNORE_PARTITIONS Off
-set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
-set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End"
-set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
-set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
-set_global_assignment -name RTLV_GROUP_RELATED_NODES On
-set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off
-set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off
-set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On
-set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On
-set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On
-set_global_assignment -name EQC_BBOX_MERGE On
-set_global_assignment -name EQC_LVDS_MERGE On
-set_global_assignment -name EQC_RAM_UNMERGING On
-set_global_assignment -name EQC_DFF_SS_EMULATION On
-set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
-set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
-set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
-set_global_assignment -name EQC_STRUCTURE_MATCHING On
-set_global_assignment -name EQC_AUTO_BREAK_CONE On
-set_global_assignment -name EQC_POWER_UP_COMPARE Off
-set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
-set_global_assignment -name EQC_AUTO_INVERSION On
-set_global_assignment -name EQC_AUTO_TERMINATE On
-set_global_assignment -name EQC_SUB_CONE_REPORT Off
-set_global_assignment -name EQC_RENAMING_RULES On
-set_global_assignment -name EQC_PARAMETER_CHECK On
-set_global_assignment -name EQC_AUTO_PORTSWAP On
-set_global_assignment -name EQC_DETECT_DONT_CARES On
-set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
-set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
-set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
-set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
-set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
-set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
-set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
-set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
-set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
-set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
-set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
-set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "<None>" -section_id ?
-set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
-set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ?
-set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ?
-set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ?
-set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ?
-set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
-set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
-set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
-set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
-set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
-set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
-set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
-set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ?
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ?
-set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
-set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ?
-set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ?
-set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
-set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
-set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
-set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
-set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
-set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?
-set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ?
-set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ?
-set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ?
-set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
-set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
-set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p1 -section_id ?
-set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
-set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
-set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
-set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
-set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
-set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
-set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
-set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ?
-set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ?
-set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ?
-set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
-set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
-set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS REPLACE_CONFLICTING -section_id ? -entity ?
-set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?
-set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ?
-set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ?
-set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ?
-set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ?
-set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ?
-set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ?
-set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ?
-set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ?
-set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ?
Index: mist/PLLJ_PLLSPE_INFO.txt
===================================================================
--- mist/PLLJ_PLLSPE_INFO.txt	(revision 15)
+++ mist/PLLJ_PLLSPE_INFO.txt	(nonexistent)
@@ -1,5 +0,0 @@
-PLL_Name	pll:b2v_inst5|altpll:altpll_component|pll_altpll:auto_generated|pll1
-PLLJITTER	26
-PLLSPEmax	84
-PLLSPEmin	-53
-
Index: mist/atari800core.qsf
===================================================================
--- mist/atari800core.qsf	(revision 15)
+++ mist/atari800core.qsf	(revision 16)
@@ -1,634 +1,317 @@
-# Copyright (C) 1991-2007 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-
-
-# The default values for assignments are stored in the file
-#		minimig_de1_assignment_defaults.qdf
-# If this file doesn't exist, and for assignments not listed, see file
-#		assignment_defaults.qdf
-
-# Altera recommends that you do not modify this file. This
-# file is updated automatically by the Quartus II software
-# and any changes you make may be lost or overwritten.
-
-
-set_global_assignment -name FAMILY "Cyclone III"
-set_global_assignment -name DEVICE EP3C25E144C8
-set_global_assignment -name TOP_LEVEL_ENTITY atari800core
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.2
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:27:29  OCTOBER 30, 2007"
-set_global_assignment -name LAST_QUARTUS_VERSION "12.1 SP1.33"
-set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
-set_global_assignment -name FITTER_EFFORT "AUTO FIT"
-set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4
-set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
-set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
-set_global_assignment -name GENERATE_RBF_FILE ON
-set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
-
-set_location_assignment PIN_7 -to LED
-set_location_assignment PIN_22 -to CLOCK_50[0]
-set_location_assignment PIN_23 -to CLOCK_50[1]
-set_location_assignment PIN_128 -to CLOCK_32[0]
-set_location_assignment PIN_129 -to CLOCK_32[1]
-set_location_assignment PIN_54 -to CLOCK_27[0]
-set_location_assignment PIN_55 -to CLOCK_27[1]
-set_location_assignment PIN_144 -to VGA_R[5]
-set_location_assignment PIN_143 -to VGA_R[4]
-set_location_assignment PIN_142 -to VGA_R[3]
-set_location_assignment PIN_141 -to VGA_R[2]
-set_location_assignment PIN_137 -to VGA_R[1]
-set_location_assignment PIN_135 -to VGA_R[0]
-set_location_assignment PIN_133 -to VGA_B[5]
-set_location_assignment PIN_132 -to VGA_B[4]
-set_location_assignment PIN_125 -to VGA_B[3]
-set_location_assignment PIN_121 -to VGA_B[2]
-set_location_assignment PIN_120 -to VGA_B[1]
-set_location_assignment PIN_115 -to VGA_B[0]
-set_location_assignment PIN_114 -to VGA_G[5]
-set_location_assignment PIN_113 -to VGA_G[4]
-set_location_assignment PIN_112 -to VGA_G[3]
-set_location_assignment PIN_111 -to VGA_G[2]
-set_location_assignment PIN_110 -to VGA_G[1]
-set_location_assignment PIN_106 -to VGA_G[0]
-set_location_assignment PIN_136 -to VGA_VS
-set_location_assignment PIN_119 -to VGA_HS
-set_location_assignment PIN_65 -to AUDIO_L
-set_location_assignment PIN_80 -to AUDIO_R
-set_location_assignment PIN_46 -to UART_TX
-set_location_assignment PIN_31 -to UART_RX
-set_location_assignment PIN_105 -to SPI_DO
-set_location_assignment PIN_88 -to SPI_DI
-set_location_assignment PIN_126 -to SPI_SCK
-set_location_assignment PIN_127 -to SPI_SS2
-set_location_assignment PIN_91 -to SPI_SS3
-set_location_assignment PIN_90 -to SPI_SS4
-set_location_assignment PIN_13 -to CONF_DATA0
-
-set_location_assignment PIN_49 -to SDRAM_A[0]
-set_location_assignment PIN_44 -to SDRAM_A[1]
-set_location_assignment PIN_42 -to SDRAM_A[2]
-set_location_assignment PIN_39 -to SDRAM_A[3]
-set_location_assignment PIN_4 -to SDRAM_A[4]
-set_location_assignment PIN_6 -to SDRAM_A[5]
-set_location_assignment PIN_8 -to SDRAM_A[6]
-set_location_assignment PIN_10 -to SDRAM_A[7]
-set_location_assignment PIN_11 -to SDRAM_A[8]
-set_location_assignment PIN_28 -to SDRAM_A[9]
-set_location_assignment PIN_50 -to SDRAM_A[10]
-set_location_assignment PIN_30 -to SDRAM_A[11]
-set_location_assignment PIN_32 -to SDRAM_A[12]
-set_location_assignment PIN_83 -to SDRAM_DQ[0]
-set_location_assignment PIN_79 -to SDRAM_DQ[1]
-set_location_assignment PIN_77 -to SDRAM_DQ[2]
-set_location_assignment PIN_76 -to SDRAM_DQ[3]
-set_location_assignment PIN_72 -to SDRAM_DQ[4]
-set_location_assignment PIN_71 -to SDRAM_DQ[5]
-set_location_assignment PIN_69 -to SDRAM_DQ[6]
-set_location_assignment PIN_68 -to SDRAM_DQ[7]
-set_location_assignment PIN_86 -to SDRAM_DQ[8]
-set_location_assignment PIN_87 -to SDRAM_DQ[9]
-set_location_assignment PIN_98 -to SDRAM_DQ[10]
-set_location_assignment PIN_99 -to SDRAM_DQ[11]
-set_location_assignment PIN_100 -to SDRAM_DQ[12]
-set_location_assignment PIN_101 -to SDRAM_DQ[13]
-set_location_assignment PIN_103 -to SDRAM_DQ[14]
-set_location_assignment PIN_104 -to SDRAM_DQ[15]
-set_location_assignment PIN_58 -to SDRAM_BA[0]
-set_location_assignment PIN_51 -to SDRAM_BA[1]
-set_location_assignment PIN_85 -to SDRAM_DQMH
-set_location_assignment PIN_67 -to SDRAM_DQML
-set_location_assignment PIN_60 -to SDRAM_nRAS
-set_location_assignment PIN_64 -to SDRAM_nCAS
-set_location_assignment PIN_66 -to SDRAM_nWE
-set_location_assignment PIN_59 -to SDRAM_nCS
-set_location_assignment PIN_33 -to SDRAM_CKE
-set_location_assignment PIN_43 -to SDRAM_CLK
-
-set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE BALANCED
-set_global_assignment -name SMART_RECOMPILE ON
-set_global_assignment -name ENABLE_SIGNALTAP ON
-set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
-set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
-set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
-set_global_assignment -name FMAX_REQUIREMENT "114 MHz"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name USE_CONFIGURATION_DEVICE ON
-set_global_assignment -name TPD_REQUIREMENT "2 ns"
-set_global_assignment -name TSU_REQUIREMENT "2 ns"
-set_global_assignment -name TCO_REQUIREMENT "2 ns"
-set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
-set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION OFF
-set_global_assignment -name AUTO_RAM_RECOGNITION ON
-set_global_assignment -name AUTO_ROM_RECOGNITION ON
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
-set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
-set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top
-set_global_assignment -name MISC_FILE atari800core.dpf
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-
-set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
-set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA OFF
-set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA OFF
-
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY out
-set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 4.0
-set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 4.0
-set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY OFF
-
-#set_parameter -name ENABLE_RUNTIME_MOD YES -to "Minimig1:minimig|amiga_boot:BOOTROM1|altsyncram:Ram0_rtl_10"
-#set_parameter -name INSTANCE_NAME mig -to "Minimig1:minimig|amiga_boot:BOOTROM1|altsyncram:Ram0_rtl_10"
-
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
-set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
-
-
-
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[0]
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[1]
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[2]
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[3]
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[4]
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[5]
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[6]
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[7]
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[8]
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[9]
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[10]
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[11]
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[12]
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[13]
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[14]
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[15]
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[0]
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[1]
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[2]
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[3]
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[4]
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[5]
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[6]
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[7]
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[8]
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[9]
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[10]
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[11]
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[12]
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
-
-set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[0]
-set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[1]
-set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[2]
-set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[3]
-set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[4]
-set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[5]
-set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[6]
-set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[7]
-set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[8]
-set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[9]
-set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[10]
-set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[11]
-set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[12]
-set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[13]
-set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[14]
-set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[15]
-
-set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[0]
-set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[1]
-set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[2]
-set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[3]
-set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[4]
-set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[5]
-set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[6]
-set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[7]
-set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[8]
-set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[9]
-set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[10]
-set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[11]
-set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[12]
-set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[13]
-set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[14]
-set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[15]
-
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[0]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[1]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[2]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[3]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[4]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[5]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[6]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[7]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[8]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[9]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[10]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[11]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[12]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[0]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[1]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[2]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[3]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[4]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[5]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[6]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[7]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[8]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[9]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[10]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[11]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[12]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[13]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[14]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[15]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_BA[0]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_BA[1]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQML
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQMH
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nRAS
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nCAS
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nWE
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nCS
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_CKE
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_CLK
-
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[5]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[4]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[3]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[2]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[1]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[0]
-
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[5]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[4]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[3]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[2]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[1]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[0]
-
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[5]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[4]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[3]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[2]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[1]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[0]
-
-
-set_global_assignment -name VHDL_FILE data_io.vhdl
-set_global_assignment -name QIP_FILE basic.qip
-set_global_assignment -name VERILOG_FILE user_io.v
-set_global_assignment -name VERILOG_FILE hq_dac.v
-set_global_assignment -name VERILOG_FILE sdram_ctrl_4_ports.v
-set_global_assignment -name VHDL_FILE ramint.vhd
-set_global_assignment -name VHDL_FILE atari800core.vhd
-set_global_assignment -name VHDL_FILE spi_master.vhd
-set_global_assignment -name VHDL_FILE zpu_config_regs.vhdl
-set_global_assignment -name VHDL_FILE zpu_rom.vhd
-set_global_assignment -name SOURCE_FILE zpu_rom.cmp
-set_global_assignment -name VHDL_FILE zpu_core.vhd
-set_global_assignment -name VHDL_FILE zpupkg.vhd
-set_global_assignment -name VHDL_FILE sdram_statemachine.vhdl
-set_global_assignment -name VHDL_FILE cpu_65xx_e.vhd
-set_global_assignment -name VHDL_FILE cpu_65xx_a.vhd
-set_global_assignment -name VHDL_FILE cpu.vhd
-set_global_assignment -name QIP_FILE pll.qip
-set_global_assignment -name VHDL_FILE reg_file.vhdl
-set_global_assignment -name VHDL_FILE address_decoder.vhdl
-set_global_assignment -name VHDL_FILE pokey.vhdl
-set_global_assignment -name VHDL_FILE enable_divider.vhdl
-set_global_assignment -name VHDL_FILE poly_17_9.vhdl
-set_global_assignment -name VHDL_FILE poly_5.vhdl
-set_global_assignment -name VHDL_FILE poly_4.vhdl
-set_global_assignment -name VHDL_FILE delay_line.vhdl
-set_global_assignment -name VHDL_FILE countdown_timer.vhdl
-set_global_assignment -name VHDL_FILE pokey_mixer.vhdl
-set_global_assignment -name VHDL_FILE pokey_noise_filter.vhdl
-set_global_assignment -name VHDL_FILE complete_address_decoder.vhdl
-set_global_assignment -name VHDL_FILE ps2_keyboard.vhdl
-set_global_assignment -name VHDL_FILE pokey_ps2_decoder.vhdl
-set_global_assignment -name VHDL_FILE antic.vhdl
-set_global_assignment -name VHDL_FILE antic_dma_clock.vhdl
-set_global_assignment -name VHDL_FILE antic_counter.vhdl
-set_global_assignment -name VHDL_FILE simple_counter.vhdl
-set_global_assignment -name VHDL_FILE gtia.vhdl
-set_global_assignment -name VHDL_FILE gtia_palette.vhdl
-set_global_assignment -name VHDL_FILE pia.vhdl
-set_global_assignment -name VHDL_FILE shared_enable.vhdl
-set_global_assignment -name VHDL_FILE gtia_player.vhdl
-set_global_assignment -name VHDL_FILE gtia_priority.vhdl
-set_global_assignment -name VHDL_FILE synchronizer.vhdl
-set_global_assignment -name VHDL_FILE scandoubler.vhdl
-set_global_assignment -name VHDL_FILE scandouble_ram_infer.vhdl
-set_global_assignment -name VHDL_FILE syncreset_enable_divider.vhd
-set_global_assignment -name VHDL_FILE wide_delay_line.vhdl
-set_global_assignment -name VHDL_FILE irq_glue.vhdl
-set_global_assignment -name VHDL_FILE pokey_keyboard_scanner.vhdl
-set_global_assignment -name VHDL_FILE zpu_glue.vhdl
-set_global_assignment -name QIP_FILE zpu_ram.qip
-set_global_assignment -name QIP_FILE zpu_rom.qip
-set_global_assignment -name SIGNALTAP_FILE output_files/stp1.stp
-set_global_assignment -name VHDL_FILE internalromram.vhd
-set_global_assignment -name VHDL_FILE sdram_statemachine_mcc.vhdl
-set_global_assignment -name SIGNALTAP_FILE stp1.stp
-set_global_assignment -name SDC_FILE atari800core.sdc
-set_global_assignment -name QIP_FILE rom16.qip
-set_global_assignment -name VHDL_FILE generic_ram_infer.vhdl
-set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to CONF_DATA0 -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[1] -to SPI_DI -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[2] -to SPI_DO -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[3] -to SPI_SS2 -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=805334528" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_POWER_UP_TRIGGER=0" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=0" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ATTRIBUTE_MEM_MODE=OFF" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_USE_GENERATED=0" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_BITS=11" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_BUFFER_FULL_STOP=1" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_CURRENT_RESOURCE_WIDTH=1" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=0" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to "data_io:mist_spi_interface|SPI_CLK" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[4] -to "data_io:mist_spi_interface|ADDR[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[5] -to "data_io:mist_spi_interface|ADDR[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[6] -to "data_io:mist_spi_interface|ADDR[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[7] -to "data_io:mist_spi_interface|ADDR[3]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[8] -to "data_io:mist_spi_interface|ADDR[4]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[9] -to "data_io:mist_spi_interface|ADDR[5]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[10] -to "data_io:mist_spi_interface|ADDR[6]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[11] -to "data_io:mist_spi_interface|ADDR[7]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[12] -to "data_io:mist_spi_interface|ADDR[8]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[13] -to "data_io:mist_spi_interface|DATA_OUT[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[14] -to "data_io:mist_spi_interface|DATA_OUT[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[15] -to "data_io:mist_spi_interface|DATA_OUT[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[16] -to "data_io:mist_spi_interface|DATA_OUT[3]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[17] -to "data_io:mist_spi_interface|DATA_OUT[4]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[18] -to "data_io:mist_spi_interface|DATA_OUT[5]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[19] -to "data_io:mist_spi_interface|DATA_OUT[6]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[20] -to "data_io:mist_spi_interface|DATA_OUT[7]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[21] -to "data_io:mist_spi_interface|WR_EN" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[22] -to "data_io:mist_spi_interface|cmd_reg[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[23] -to "data_io:mist_spi_interface|cmd_reg[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[24] -to "data_io:mist_spi_interface|cmd_reg[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[25] -to "data_io:mist_spi_interface|cmd_reg[3]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[26] -to "data_io:mist_spi_interface|cmd_reg[4]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[27] -to "data_io:mist_spi_interface|cmd_reg[5]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[28] -to "data_io:mist_spi_interface|cmd_reg[6]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[29] -to "data_io:mist_spi_interface|cmd_reg[7]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[30] -to "data_io:mist_spi_interface|cnt_reg[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[31] -to "data_io:mist_spi_interface|cnt_reg[10]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[32] -to "data_io:mist_spi_interface|cnt_reg[11]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[33] -to "data_io:mist_spi_interface|cnt_reg[12]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[34] -to "data_io:mist_spi_interface|cnt_reg[13]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[35] -to "data_io:mist_spi_interface|cnt_reg[14]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[36] -to "data_io:mist_spi_interface|cnt_reg[15]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[37] -to "data_io:mist_spi_interface|cnt_reg[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[38] -to "data_io:mist_spi_interface|cnt_reg[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[39] -to "data_io:mist_spi_interface|cnt_reg[3]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[40] -to "data_io:mist_spi_interface|cnt_reg[4]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[41] -to "data_io:mist_spi_interface|cnt_reg[5]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[42] -to "data_io:mist_spi_interface|cnt_reg[6]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[43] -to "data_io:mist_spi_interface|cnt_reg[7]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[44] -to "data_io:mist_spi_interface|cnt_reg[8]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[45] -to "data_io:mist_spi_interface|cnt_reg[9]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[46] -to "data_io:mist_spi_interface|ready" -section_id auto_signaltap_0
-set_global_assignment -name QIP_FILE mist_sector_buffer.qip
-set_global_assignment -name VHDL_FILE covox.vhd
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to CONF_DATA0 -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[1] -to SPI_DI -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[2] -to SPI_DO -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[3] -to SPI_SS2 -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[4] -to "data_io:mist_spi_interface|ADDR[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[5] -to "data_io:mist_spi_interface|ADDR[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[6] -to "data_io:mist_spi_interface|ADDR[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[7] -to "data_io:mist_spi_interface|ADDR[3]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[8] -to "data_io:mist_spi_interface|ADDR[4]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[9] -to "data_io:mist_spi_interface|ADDR[5]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[10] -to "data_io:mist_spi_interface|ADDR[6]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[11] -to "data_io:mist_spi_interface|ADDR[7]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[12] -to "data_io:mist_spi_interface|ADDR[8]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[13] -to "data_io:mist_spi_interface|DATA_OUT[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[14] -to "data_io:mist_spi_interface|DATA_OUT[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[15] -to "data_io:mist_spi_interface|DATA_OUT[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[16] -to "data_io:mist_spi_interface|DATA_OUT[3]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[17] -to "data_io:mist_spi_interface|DATA_OUT[4]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[18] -to "data_io:mist_spi_interface|DATA_OUT[5]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[19] -to "data_io:mist_spi_interface|DATA_OUT[6]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[20] -to "data_io:mist_spi_interface|DATA_OUT[7]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[21] -to "data_io:mist_spi_interface|WR_EN" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[22] -to "data_io:mist_spi_interface|cmd_reg[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[23] -to "data_io:mist_spi_interface|cmd_reg[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[24] -to "data_io:mist_spi_interface|cmd_reg[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[25] -to "data_io:mist_spi_interface|cmd_reg[3]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[26] -to "data_io:mist_spi_interface|cmd_reg[4]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[27] -to "data_io:mist_spi_interface|cmd_reg[5]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[28] -to "data_io:mist_spi_interface|cmd_reg[6]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[29] -to "data_io:mist_spi_interface|cmd_reg[7]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[30] -to "data_io:mist_spi_interface|cnt_reg[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[31] -to "data_io:mist_spi_interface|cnt_reg[10]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[32] -to "data_io:mist_spi_interface|cnt_reg[11]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[33] -to "data_io:mist_spi_interface|cnt_reg[12]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[34] -to "data_io:mist_spi_interface|cnt_reg[13]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[35] -to "data_io:mist_spi_interface|cnt_reg[14]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[36] -to "data_io:mist_spi_interface|cnt_reg[15]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[37] -to "data_io:mist_spi_interface|cnt_reg[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[38] -to "data_io:mist_spi_interface|cnt_reg[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[39] -to "data_io:mist_spi_interface|cnt_reg[3]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[40] -to "data_io:mist_spi_interface|cnt_reg[4]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[41] -to "data_io:mist_spi_interface|cnt_reg[5]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[42] -to "data_io:mist_spi_interface|cnt_reg[6]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[43] -to "data_io:mist_spi_interface|cnt_reg[7]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[44] -to "data_io:mist_spi_interface|cnt_reg[8]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[45] -to "data_io:mist_spi_interface|cnt_reg[9]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[46] -to "data_io:mist_spi_interface|ready" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=2048" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=2048" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[47] -to "data_io:mist_spi_interface|request" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[48] -to "data_io:mist_spi_interface|sbuf_reg[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[49] -to "data_io:mist_spi_interface|sbuf_reg[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[50] -to "data_io:mist_spi_interface|sbuf_reg[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[51] -to "data_io:mist_spi_interface|sbuf_reg[3]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[52] -to "data_io:mist_spi_interface|sbuf_reg[4]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[53] -to "data_io:mist_spi_interface|sbuf_reg[5]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[54] -to "data_io:mist_spi_interface|sbuf_reg[6]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[55] -to "data_io:mist_spi_interface|sector[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[56] -to "data_io:mist_spi_interface|sector[10]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[57] -to "data_io:mist_spi_interface|sector[11]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[58] -to "data_io:mist_spi_interface|sector[12]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[59] -to "data_io:mist_spi_interface|sector[13]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[60] -to "data_io:mist_spi_interface|sector[14]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[61] -to "data_io:mist_spi_interface|sector[15]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[62] -to "data_io:mist_spi_interface|sector[16]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[63] -to "data_io:mist_spi_interface|sector[17]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[64] -to "data_io:mist_spi_interface|sector[18]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[65] -to "data_io:mist_spi_interface|sector[19]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[66] -to "data_io:mist_spi_interface|sector[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[67] -to "data_io:mist_spi_interface|sector[20]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[68] -to "data_io:mist_spi_interface|sector[21]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[69] -to "data_io:mist_spi_interface|sector[22]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[70] -to "data_io:mist_spi_interface|sector[23]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[71] -to "data_io:mist_spi_interface|sector[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[72] -to "data_io:mist_spi_interface|sector[3]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[73] -to "data_io:mist_spi_interface|sector[4]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[74] -to "data_io:mist_spi_interface|sector[5]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[75] -to "data_io:mist_spi_interface|sector[6]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[76] -to "data_io:mist_spi_interface|sector[7]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[77] -to "data_io:mist_spi_interface|sector[8]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[78] -to "data_io:mist_spi_interface|sector[9]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[79] -to "pia:b2v_inst16|portb_output_reg[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[80] -to "pia:b2v_inst16|portb_output_reg[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[81] -to "pia:b2v_inst16|portb_output_reg[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[82] -to "pia:b2v_inst16|portb_output_reg[3]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[83] -to "pia:b2v_inst16|portb_output_reg[4]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[84] -to "pia:b2v_inst16|portb_output_reg[5]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[85] -to "pia:b2v_inst16|portb_output_reg[6]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[86] -to "pia:b2v_inst16|portb_output_reg[7]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[87] -to "zpu_config_regs:b2v_inst24|sector[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[88] -to "zpu_config_regs:b2v_inst24|sector[10]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[89] -to "zpu_config_regs:b2v_inst24|sector[11]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[90] -to "zpu_config_regs:b2v_inst24|sector[12]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[91] -to "zpu_config_regs:b2v_inst24|sector[13]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[92] -to "zpu_config_regs:b2v_inst24|sector[14]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[93] -to "zpu_config_regs:b2v_inst24|sector[15]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[94] -to "zpu_config_regs:b2v_inst24|sector[16]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[95] -to "zpu_config_regs:b2v_inst24|sector[17]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[96] -to "zpu_config_regs:b2v_inst24|sector[18]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[97] -to "zpu_config_regs:b2v_inst24|sector[19]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[98] -to "zpu_config_regs:b2v_inst24|sector[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[99] -to "zpu_config_regs:b2v_inst24|sector[20]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[100] -to "zpu_config_regs:b2v_inst24|sector[21]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[101] -to "zpu_config_regs:b2v_inst24|sector[22]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[102] -to "zpu_config_regs:b2v_inst24|sector[23]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[103] -to "zpu_config_regs:b2v_inst24|sector[24]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[104] -to "zpu_config_regs:b2v_inst24|sector[25]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[105] -to "zpu_config_regs:b2v_inst24|sector[26]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[106] -to "zpu_config_regs:b2v_inst24|sector[27]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[107] -to "zpu_config_regs:b2v_inst24|sector[28]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[108] -to "zpu_config_regs:b2v_inst24|sector[29]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[109] -to "zpu_config_regs:b2v_inst24|sector[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[110] -to "zpu_config_regs:b2v_inst24|sector[30]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[111] -to "zpu_config_regs:b2v_inst24|sector[31]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[112] -to "zpu_config_regs:b2v_inst24|sector[3]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[113] -to "zpu_config_regs:b2v_inst24|sector[4]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[114] -to "zpu_config_regs:b2v_inst24|sector[5]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[115] -to "zpu_config_regs:b2v_inst24|sector[6]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[116] -to "zpu_config_regs:b2v_inst24|sector[7]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[117] -to "zpu_config_regs:b2v_inst24|sector[8]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[118] -to "zpu_config_regs:b2v_inst24|sector[9]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[47] -to "data_io:mist_spi_interface|request" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[48] -to "data_io:mist_spi_interface|sbuf_reg[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[49] -to "data_io:mist_spi_interface|sbuf_reg[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[50] -to "data_io:mist_spi_interface|sbuf_reg[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[51] -to "data_io:mist_spi_interface|sbuf_reg[3]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[52] -to "data_io:mist_spi_interface|sbuf_reg[4]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[53] -to "data_io:mist_spi_interface|sbuf_reg[5]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[54] -to "data_io:mist_spi_interface|sbuf_reg[6]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[55] -to "data_io:mist_spi_interface|sector[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[56] -to "data_io:mist_spi_interface|sector[10]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[57] -to "data_io:mist_spi_interface|sector[11]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[58] -to "data_io:mist_spi_interface|sector[12]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[59] -to "data_io:mist_spi_interface|sector[13]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[60] -to "data_io:mist_spi_interface|sector[14]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[61] -to "data_io:mist_spi_interface|sector[15]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[62] -to "data_io:mist_spi_interface|sector[16]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[63] -to "data_io:mist_spi_interface|sector[17]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[64] -to "data_io:mist_spi_interface|sector[18]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[65] -to "data_io:mist_spi_interface|sector[19]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[66] -to "data_io:mist_spi_interface|sector[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[67] -to "data_io:mist_spi_interface|sector[20]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[68] -to "data_io:mist_spi_interface|sector[21]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[69] -to "data_io:mist_spi_interface|sector[22]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[70] -to "data_io:mist_spi_interface|sector[23]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[71] -to "data_io:mist_spi_interface|sector[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[72] -to "data_io:mist_spi_interface|sector[3]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[73] -to "data_io:mist_spi_interface|sector[4]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[74] -to "data_io:mist_spi_interface|sector[5]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[75] -to "data_io:mist_spi_interface|sector[6]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[76] -to "data_io:mist_spi_interface|sector[7]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[77] -to "data_io:mist_spi_interface|sector[8]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[78] -to "data_io:mist_spi_interface|sector[9]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[79] -to "pia:b2v_inst16|portb_output_reg[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[80] -to "pia:b2v_inst16|portb_output_reg[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[81] -to "pia:b2v_inst16|portb_output_reg[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[82] -to "pia:b2v_inst16|portb_output_reg[3]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[83] -to "pia:b2v_inst16|portb_output_reg[4]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[84] -to "pia:b2v_inst16|portb_output_reg[5]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[85] -to "pia:b2v_inst16|portb_output_reg[6]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[86] -to "pia:b2v_inst16|portb_output_reg[7]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[87] -to "zpu_config_regs:b2v_inst24|sector[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[88] -to "zpu_config_regs:b2v_inst24|sector[10]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[89] -to "zpu_config_regs:b2v_inst24|sector[11]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[90] -to "zpu_config_regs:b2v_inst24|sector[12]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[91] -to "zpu_config_regs:b2v_inst24|sector[13]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[92] -to "zpu_config_regs:b2v_inst24|sector[14]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[93] -to "zpu_config_regs:b2v_inst24|sector[15]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[94] -to "zpu_config_regs:b2v_inst24|sector[16]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[95] -to "zpu_config_regs:b2v_inst24|sector[17]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[96] -to "zpu_config_regs:b2v_inst24|sector[18]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[97] -to "zpu_config_regs:b2v_inst24|sector[19]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[98] -to "zpu_config_regs:b2v_inst24|sector[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[99] -to "zpu_config_regs:b2v_inst24|sector[20]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[100] -to "zpu_config_regs:b2v_inst24|sector[21]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[101] -to "zpu_config_regs:b2v_inst24|sector[22]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[102] -to "zpu_config_regs:b2v_inst24|sector[23]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[103] -to "zpu_config_regs:b2v_inst24|sector[24]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[104] -to "zpu_config_regs:b2v_inst24|sector[25]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[105] -to "zpu_config_regs:b2v_inst24|sector[26]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[106] -to "zpu_config_regs:b2v_inst24|sector[27]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[107] -to "zpu_config_regs:b2v_inst24|sector[28]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[108] -to "zpu_config_regs:b2v_inst24|sector[29]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[109] -to "zpu_config_regs:b2v_inst24|sector[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[110] -to "zpu_config_regs:b2v_inst24|sector[30]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[111] -to "zpu_config_regs:b2v_inst24|sector[31]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[112] -to "zpu_config_regs:b2v_inst24|sector[3]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[113] -to "zpu_config_regs:b2v_inst24|sector[4]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[114] -to "zpu_config_regs:b2v_inst24|sector[5]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[115] -to "zpu_config_regs:b2v_inst24|sector[6]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[116] -to "zpu_config_regs:b2v_inst24|sector[7]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[117] -to "zpu_config_regs:b2v_inst24|sector[8]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[118] -to "zpu_config_regs:b2v_inst24|sector[9]" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=119" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=119" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=382" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_LOWORD=25945" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_HIWORD=37736" -section_id auto_signaltap_0
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
+# Copyright (C) 1991-2007 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+
+
+# The default values for assignments are stored in the file
+#		minimig_de1_assignment_defaults.qdf
+# If this file doesn't exist, and for assignments not listed, see file
+#		assignment_defaults.qdf
+
+# Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+
+
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE EP3C25E144C8
+set_global_assignment -name TOP_LEVEL_ENTITY atari800core_mist
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.2
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:27:29  OCTOBER 30, 2007"
+set_global_assignment -name LAST_QUARTUS_VERSION "12.1 SP1.33"
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
+set_global_assignment -name FITTER_EFFORT "AUTO FIT"
+set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name GENERATE_RBF_FILE ON
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+
+set_location_assignment PIN_7 -to LED
+set_location_assignment PIN_22 -to CLOCK_50[0]
+set_location_assignment PIN_23 -to CLOCK_50[1]
+set_location_assignment PIN_128 -to CLOCK_32[0]
+set_location_assignment PIN_129 -to CLOCK_32[1]
+set_location_assignment PIN_54 -to CLOCK_27[0]
+set_location_assignment PIN_55 -to CLOCK_27[1]
+set_location_assignment PIN_144 -to VGA_R[5]
+set_location_assignment PIN_143 -to VGA_R[4]
+set_location_assignment PIN_142 -to VGA_R[3]
+set_location_assignment PIN_141 -to VGA_R[2]
+set_location_assignment PIN_137 -to VGA_R[1]
+set_location_assignment PIN_135 -to VGA_R[0]
+set_location_assignment PIN_133 -to VGA_B[5]
+set_location_assignment PIN_132 -to VGA_B[4]
+set_location_assignment PIN_125 -to VGA_B[3]
+set_location_assignment PIN_121 -to VGA_B[2]
+set_location_assignment PIN_120 -to VGA_B[1]
+set_location_assignment PIN_115 -to VGA_B[0]
+set_location_assignment PIN_114 -to VGA_G[5]
+set_location_assignment PIN_113 -to VGA_G[4]
+set_location_assignment PIN_112 -to VGA_G[3]
+set_location_assignment PIN_111 -to VGA_G[2]
+set_location_assignment PIN_110 -to VGA_G[1]
+set_location_assignment PIN_106 -to VGA_G[0]
+set_location_assignment PIN_136 -to VGA_VS
+set_location_assignment PIN_119 -to VGA_HS
+set_location_assignment PIN_65 -to AUDIO_L
+set_location_assignment PIN_80 -to AUDIO_R
+set_location_assignment PIN_46 -to UART_TX
+set_location_assignment PIN_31 -to UART_RX
+set_location_assignment PIN_105 -to SPI_DO
+set_location_assignment PIN_88 -to SPI_DI
+set_location_assignment PIN_126 -to SPI_SCK
+set_location_assignment PIN_127 -to SPI_SS2
+set_location_assignment PIN_91 -to SPI_SS3
+set_location_assignment PIN_90 -to SPI_SS4
+set_location_assignment PIN_13 -to CONF_DATA0
+
+set_location_assignment PIN_49 -to SDRAM_A[0]
+set_location_assignment PIN_44 -to SDRAM_A[1]
+set_location_assignment PIN_42 -to SDRAM_A[2]
+set_location_assignment PIN_39 -to SDRAM_A[3]
+set_location_assignment PIN_4 -to SDRAM_A[4]
+set_location_assignment PIN_6 -to SDRAM_A[5]
+set_location_assignment PIN_8 -to SDRAM_A[6]
+set_location_assignment PIN_10 -to SDRAM_A[7]
+set_location_assignment PIN_11 -to SDRAM_A[8]
+set_location_assignment PIN_28 -to SDRAM_A[9]
+set_location_assignment PIN_50 -to SDRAM_A[10]
+set_location_assignment PIN_30 -to SDRAM_A[11]
+set_location_assignment PIN_32 -to SDRAM_A[12]
+set_location_assignment PIN_83 -to SDRAM_DQ[0]
+set_location_assignment PIN_79 -to SDRAM_DQ[1]
+set_location_assignment PIN_77 -to SDRAM_DQ[2]
+set_location_assignment PIN_76 -to SDRAM_DQ[3]
+set_location_assignment PIN_72 -to SDRAM_DQ[4]
+set_location_assignment PIN_71 -to SDRAM_DQ[5]
+set_location_assignment PIN_69 -to SDRAM_DQ[6]
+set_location_assignment PIN_68 -to SDRAM_DQ[7]
+set_location_assignment PIN_86 -to SDRAM_DQ[8]
+set_location_assignment PIN_87 -to SDRAM_DQ[9]
+set_location_assignment PIN_98 -to SDRAM_DQ[10]
+set_location_assignment PIN_99 -to SDRAM_DQ[11]
+set_location_assignment PIN_100 -to SDRAM_DQ[12]
+set_location_assignment PIN_101 -to SDRAM_DQ[13]
+set_location_assignment PIN_103 -to SDRAM_DQ[14]
+set_location_assignment PIN_104 -to SDRAM_DQ[15]
+set_location_assignment PIN_58 -to SDRAM_BA[0]
+set_location_assignment PIN_51 -to SDRAM_BA[1]
+set_location_assignment PIN_85 -to SDRAM_DQMH
+set_location_assignment PIN_67 -to SDRAM_DQML
+set_location_assignment PIN_60 -to SDRAM_nRAS
+set_location_assignment PIN_64 -to SDRAM_nCAS
+set_location_assignment PIN_66 -to SDRAM_nWE
+set_location_assignment PIN_59 -to SDRAM_nCS
+set_location_assignment PIN_33 -to SDRAM_CKE
+set_location_assignment PIN_43 -to SDRAM_CLK
+
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE BALANCED
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name ENABLE_SIGNALTAP ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
+set_global_assignment -name FMAX_REQUIREMENT "114 MHz"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name TPD_REQUIREMENT "2 ns"
+set_global_assignment -name TSU_REQUIREMENT "2 ns"
+set_global_assignment -name TCO_REQUIREMENT "2 ns"
+set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
+set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION OFF
+set_global_assignment -name AUTO_RAM_RECOGNITION ON
+set_global_assignment -name AUTO_ROM_RECOGNITION ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top
+set_global_assignment -name MISC_FILE atari800core.dpf
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA OFF
+
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY out
+set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 4.0
+set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 4.0
+set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY OFF
+
+#set_parameter -name ENABLE_RUNTIME_MOD YES -to "Minimig1:minimig|amiga_boot:BOOTROM1|altsyncram:Ram0_rtl_10"
+#set_parameter -name INSTANCE_NAME mig -to "Minimig1:minimig|amiga_boot:BOOTROM1|altsyncram:Ram0_rtl_10"
+
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+
+
+
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[0]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[1]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[2]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[3]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[4]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[5]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[6]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[7]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[8]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[9]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[10]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[11]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[12]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[13]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[14]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[15]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[0]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[1]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[2]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[3]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[4]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[5]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[6]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[7]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[8]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[9]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[10]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[11]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[12]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
+
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[0]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[1]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[2]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[3]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[4]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[5]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[6]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[7]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[8]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[9]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[10]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[11]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[12]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[13]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[14]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[15]
+
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[0]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[1]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[2]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[3]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[4]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[5]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[6]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[7]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[8]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[9]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[10]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[11]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[12]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[13]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[14]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[15]
+
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[0]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[1]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[2]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[3]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[4]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[5]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[6]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[7]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[8]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[9]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[10]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[11]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[12]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[0]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[1]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[2]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[3]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[4]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[5]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[6]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[7]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[8]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[9]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[10]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[11]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[12]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[13]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[14]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[15]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_BA[0]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_BA[1]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQML
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQMH
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nRAS
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nCAS
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nWE
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nCS
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_CKE
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_CLK
+
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[5]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[4]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[3]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[2]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[1]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[0]
+
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[5]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[4]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[3]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[2]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[1]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[0]
+
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[5]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[4]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[3]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[2]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[1]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[0]
+
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+
+set_global_assignment -name VHDL_FILE data_io.vhdl
+set_global_assignment -name SDC_FILE atari800core.sdc
+set_global_assignment -name QIP_FILE mist_sector_buffer.qip
+set_global_assignment -name VHDL_FILE atari800core_mist.vhd
+set_global_assignment -name VERILOG_FILE user_io.v
+set_global_assignment -name QIP_FILE pll.qip
+
Index: mist/atari800core_mist.vhd
===================================================================
--- mist/atari800core_mist.vhd	(nonexistent)
+++ mist/atari800core_mist.vhd	(revision 16)
@@ -0,0 +1,548 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all; 
+use ieee.numeric_std.all;
+
+LIBRARY work;
+
+ENTITY atari800core_mist IS 
+	PORT
+	(
+		CLOCK_27 :  IN  STD_LOGIC_VECTOR(1 downto 0);
+
+		VGA_VS :  OUT  STD_LOGIC;
+		VGA_HS :  OUT  STD_LOGIC;
+		VGA_B :  OUT  STD_LOGIC_VECTOR(5 DOWNTO 0);
+		VGA_G :  OUT  STD_LOGIC_VECTOR(5 DOWNTO 0);
+		VGA_R :  OUT  STD_LOGIC_VECTOR(5 DOWNTO 0);
+		
+		AUDIO_L : OUT std_logic;
+		AUDIO_R : OUT std_logic;
+
+		SDRAM_BA :  OUT  STD_LOGIC_VECTOR(1 downto 0);
+		SDRAM_nCS :  OUT  STD_LOGIC;
+		SDRAM_nRAS :  OUT  STD_LOGIC;
+		SDRAM_nCAS :  OUT  STD_LOGIC;
+		SDRAM_nWE :  OUT  STD_LOGIC;
+		SDRAM_DQMH :  OUT  STD_LOGIC;
+		SDRAM_DQML :  OUT  STD_LOGIC;
+		SDRAM_CLK :  OUT  STD_LOGIC;
+		SDRAM_CKE :  OUT  STD_LOGIC;
+		SDRAM_A :  OUT  STD_LOGIC_VECTOR(12 DOWNTO 0);
+		SDRAM_DQ :  INOUT  STD_LOGIC_VECTOR(15 DOWNTO 0);
+
+		LED : OUT std_logic;
+		
+		UART_TX :  OUT  STD_LOGIC;
+		UART_RX :  IN  STD_LOGIC;
+		
+		SPI_DO :  INOUT  STD_LOGIC;
+		SPI_DI :  IN  STD_LOGIC;
+		SPI_SCK :  IN  STD_LOGIC;
+		SPI_SS2 :  IN  STD_LOGIC;		
+		SPI_SS3 :  IN  STD_LOGIC;		
+		SPI_SS4 :  IN  STD_LOGIC;
+		CONF_DATA0 :  IN  STD_LOGIC -- AKA SPI_SS5
+	);
+END atari800core_mist;
+
+ARCHITECTURE vhdl OF atari800core_mist IS 
+
+component hq_dac
+port (
+  reset :in std_logic;
+  clk :in std_logic;
+  clk_ena : in std_logic;
+  pcm_in : in std_logic_vector(19 downto 0);
+  dac_out : out std_logic
+);
+end component;
+
+component user_io
+	PORT(
+	   SPI_CLK : in std_logic;
+	   SPI_SS_IO : in std_logic;
+	   SPI_MISO : out std_logic;
+	   SPI_MOSI : in std_logic;
+	   CORE_TYPE : in std_logic_vector(7 downto 0);
+		JOY0 : out std_logic_vector(5 downto 0);
+		JOY1 : out std_logic_vector(5 downto 0);
+		KEYBOARD : out std_logic_vector(127 downto 0);
+		BUTTONS : out std_logic_vector(1 downto 0);
+		SWITCHES : out std_logic_vector(1 downto 0)
+	  );
+end component;
+
+
+
+  signal AUDIO_L_PCM : std_logic_vector(15 downto 0);
+  signal AUDIO_R_PCM : std_logic_vector(15 downto 0);
+
+  signal VGA_R_WIDE : std_logic_vector(7 downto 0);
+  signal VGA_G_WIDE : std_logic_vector(7 downto 0);
+  signal VGA_B_WIDE : std_logic_vector(7 downto 0);
+  signal VGA_VS_RAW : std_logic;
+  signal VGA_HS_RAW : std_logic;
+
+  signal RESET_n : std_logic;
+  signal PLL_LOCKED : std_logic;
+  signal CLK : std_logic;
+  signal CLK_SDRAM : std_logic;
+
+  signal keyboard : std_logic_vector(127 downto 0);
+  signal atari_keyboard : std_logic_vector(63 downto 0);
+  
+  SIGNAL	SHIFT_PRESSED :  STD_LOGIC;
+  SIGNAL	BREAK_PRESSED :  STD_LOGIC;
+  SIGNAL	CONTROL_PRESSED :  STD_LOGIC;
+
+  SIGNAL	CONSOL_OPTION :  STD_LOGIC;
+  SIGNAL	CONSOL_SELECT :  STD_LOGIC;
+  SIGNAL	CONSOL_START :  STD_LOGIC;
+
+  signal capslock_pressed : std_logic;
+  signal capsheld_next : std_logic;
+  signal capsheld_reg : std_logic;
+  
+  signal mist_sector_ready : std_logic;
+  signal mist_sector_ready_sync : std_logic;
+  signal mist_sector_request : std_logic;
+  signal mist_sector_request_sync : std_logic;
+  signal mist_sector : std_logic_vector(31 downto 0);
+  signal mist_sector_sync : std_logic_vector(31 downto 0);
+  
+  		
+  signal mist_addr : std_logic_vector(8 downto 0);
+  signal mist_do : std_logic_vector(7 downto 0);
+  signal mist_di : std_logic_vector(7 downto 0);
+  signal mist_wren : std_logic;
+  
+  signal spi_miso_data : std_logic;
+  signal spi_miso_io : std_logic;
+
+  signal mist_buttons : std_logic_vector(1 downto 0);
+  signal mist_switches : std_logic_vector(1 downto 0);
+
+  signal		JOY1 :  STD_LOGIC_VECTOR(5 DOWNTO 0);
+  signal		JOY2 :  STD_LOGIC_VECTOR(5 DOWNTO 0);
+  signal		JOY1_n :  STD_LOGIC_VECTOR(4 DOWNTO 0);
+  signal		JOY2_n :  STD_LOGIC_VECTOR(4 DOWNTO 0);
+
+  SIGNAL	KEYBOARD_RESPONSE :  STD_LOGIC_VECTOR(1 DOWNTO 0);
+  SIGNAL	KEYBOARD_SCAN :  STD_LOGIC_VECTOR(5 DOWNTO 0);
+
+  SIGNAL	THROTTLE_COUNT_6502 :  STD_LOGIC_VECTOR(5 DOWNTO 0);
+
+  SIGNAL PAL : std_logic;
+BEGIN 
+pal <= '1'; -- TODO, two builds, with appropriate pll settings
+
+-- mist spi io
+mist_spi_interface : entity work.data_io 
+	PORT map
+	(
+		CLK =>spi_sck,
+		RESET_n =>reset_n,
+		
+		-- SPI connection - up to upstream to make miso 'Z' on ss_io going high
+		SPI_CLK =>spi_sck,
+		SPI_SS_IO => spi_ss2,
+		SPI_MISO => spi_miso_data,
+		SPI_MOSI => spi_di,
+		
+		-- Sector access request
+		request => mist_sector_request_sync,
+		sector => mist_sector_sync(23 downto 0),
+		ready => mist_sector_ready,
+		
+		-- DMA to RAM
+		ADDR => mist_addr,
+		DATA_OUT => mist_do,
+		DATA_IN => mist_di,
+		WR_EN => mist_wren
+	 );
+ 
+	-- TODO, review if these are all needed when ZPU connected again...
+	select_sync : entity work.synchronizer
+	PORT MAP ( CLK => clk, raw => mist_sector_ready, sync=>mist_sector_ready_sync);
+
+	select_sync2 : entity work.synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector_request, sync=>mist_sector_request_sync);
+
+	sector_sync0 : entity work.synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(0), sync=>mist_sector_sync(0));
+
+	sector_sync1 : entity work.synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(1), sync=>mist_sector_sync(1));
+
+	sector_sync2 : entity work.synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(2), sync=>mist_sector_sync(2));
+
+	sector_sync3 : entity work.synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(3), sync=>mist_sector_sync(3));
+
+	sector_sync4 : entity work.synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(4), sync=>mist_sector_sync(4));
+
+	sector_sync5 : entity work.synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(5), sync=>mist_sector_sync(5));
+
+	sector_sync6 : entity work.synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(6), sync=>mist_sector_sync(6));
+
+	sector_sync7 : entity work.synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(7), sync=>mist_sector_sync(7));
+
+	sector_sync8 : entity work.synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(8), sync=>mist_sector_sync(8));
+
+	sector_sync9 : entity work.synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(9), sync=>mist_sector_sync(9));
+
+	sector_sync10 : entity work.synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(10), sync=>mist_sector_sync(10));
+
+	sector_sync11 : entity work.synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(11), sync=>mist_sector_sync(11));
+
+	sector_sync12 : entity work.synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(12), sync=>mist_sector_sync(12));
+
+	sector_sync13 : entity work.synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(13), sync=>mist_sector_sync(13));
+
+	sector_sync14 : entity work.synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(14), sync=>mist_sector_sync(14));
+
+	sector_sync15 : entity work.synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(15), sync=>mist_sector_sync(15));
+
+	sector_sync16 : entity work.synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(16), sync=>mist_sector_sync(16));
+
+	sector_sync17 : entity work.synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(17), sync=>mist_sector_sync(17));
+
+	sector_sync18 : entity work.synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(18), sync=>mist_sector_sync(18));
+
+	sector_sync19 : entity work.synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(19), sync=>mist_sector_sync(19));
+
+	sector_sync20 : entity work.synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(20), sync=>mist_sector_sync(20));
+
+	sector_sync21 : entity work.synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(21), sync=>mist_sector_sync(21));
+
+	sector_sync22 : entity work.synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(22), sync=>mist_sector_sync(22));
+
+	sector_sync23 : entity work.synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(23), sync=>mist_sector_sync(23));
+	
+	
+	spi_do <= spi_miso_io when CONF_DATA0 ='0' else spi_miso_data when spi_SS2='0' else 'Z';
+
+mist_sector_buffer1 : entity work.mist_sector_buffer
+	PORT map
+	(
+		address_a		=> mist_addr,
+		address_b		=> "0000000", -- TODO - need to expose a 2nd dma channel of some kind, so we don't have to halt 6502 to access sector buffer! ZPU_ADDR_ROM_RAM(8 DOWNTO 2),
+		clock_a		=> spi_sck,
+		clock_b		=> clk,
+		data_a		=> mist_do,
+		data_b		=> X"00000000", -- TODO zpu_do,
+		wren_a		=> mist_wren,
+		wren_b		=> '0',
+		q_a		=> mist_di,
+		q_b		=> open -- TODO zpu_sector_data
+	);
+	
+my_user_io : user_io
+	PORT map(
+	   SPI_CLK => SPI_SCK,
+	   SPI_SS_IO => CONF_DATA0,
+	   SPI_MISO => SPI_miso_io,
+	   SPI_MOSI => SPI_DI,
+	   CORE_TYPE => x"A4",
+		JOY0 => joy1,
+		JOY1 => joy2,
+		KEYBOARD => keyboard,
+		BUTTONS => mist_buttons,
+		SWITCHES => mist_switches
+	  );
+	  
+	 joy1_n <= not(joy1(4 downto 0));
+	 joy2_n <= not(joy2(4 downto 0));
+	 
+	process(clk,reset_n)
+	begin
+		if (reset_n='0') then
+			capsheld_reg <= '0';
+		elsif (clk'event and clk='1') then
+			capsheld_reg <= capsheld_next;
+		end if;
+	end process;
+
+-- TODO, this doesn't work yet
+	process(keyboard,capsheld_reg)
+	begin
+		capsheld_next <= capsheld_reg;
+		capslock_pressed <= '0';
+		
+		if ((keyboard(58) xor capsheld_reg)='1') then
+			capsheld_next <= keyboard(58);
+			
+			-- assert something for 10 frames
+			capslock_pressed <= '1';
+		end if;
+	end process;
+	
+-- TODO, this is mapping from ST keycode, make mist firmware send PS2 keycodes or USB keycodes if possible
+atari_keyboard(63) <= keyboard(30);
+atari_keyboard(62) <= keyboard(31);
+atari_keyboard(61) <= keyboard(34);
+atari_keyboard(60) <= '0';
+atari_keyboard(58) <= keyboard(32);
+atari_keyboard(57) <= keyboard(35);
+atari_keyboard(56) <= keyboard(33);
+atari_keyboard(55) <= keyboard(13);
+atari_keyboard(54) <= keyboard(12);
+atari_keyboard(53) <= keyboard(9);
+atari_keyboard(52) <= keyboard(14);
+atari_keyboard(51) <= keyboard(8);
+atari_keyboard(50) <= keyboard(11);
+atari_keyboard(48) <= keyboard(10);
+atari_keyboard(47) <= keyboard(16);
+atari_keyboard(46) <= keyboard(17);
+atari_keyboard(45) <= keyboard(20);
+atari_keyboard(44) <= keyboard(15);
+atari_keyboard(43) <= keyboard(21);
+atari_keyboard(42) <= keyboard(18);
+atari_keyboard(40) <= keyboard(19);
+atari_keyboard(39) <= keyboard(56);
+atari_keyboard(38) <= keyboard(53);
+atari_keyboard(37) <= keyboard(50);
+atari_keyboard(35) <= keyboard(49);
+atari_keyboard(34) <= keyboard(52);
+atari_keyboard(33) <= keyboard(57);
+atari_keyboard(32) <= keyboard(51);
+atari_keyboard(31) <= keyboard(2);
+atari_keyboard(30) <= keyboard(3);
+atari_keyboard(29) <= keyboard(6);
+atari_keyboard(28) <= keyboard(1);
+atari_keyboard(27) <= keyboard(7);
+atari_keyboard(26) <= keyboard(4);
+atari_keyboard(24) <= keyboard(5);
+atari_keyboard(23) <= keyboard(44);
+atari_keyboard(22) <= keyboard(45);
+atari_keyboard(21) <= keyboard(48);
+atari_keyboard(18) <= keyboard(46);
+atari_keyboard(17) <= keyboard(59);
+atari_keyboard(16) <= keyboard(47);
+atari_keyboard(15) <= keyboard(27);
+atari_keyboard(14) <= keyboard(26);
+atari_keyboard(13) <= keyboard(23);
+atari_keyboard(12) <= keyboard(28);
+atari_keyboard(11) <= keyboard(22);
+atari_keyboard(10) <= keyboard(25);
+atari_keyboard(8) <= keyboard(24);
+atari_keyboard(7) <= keyboard(41);
+atari_keyboard(6) <= keyboard(40);
+atari_keyboard(5) <= keyboard(37);
+atari_keyboard(2) <= keyboard(39);
+atari_keyboard(1) <= keyboard(36);
+atari_keyboard(0) <= keyboard(38);
+
+	  
+shift_pressed <= keyboard(54) or keyboard(42);
+control_pressed <= keyboard(29);
+break_pressed <= keyboard(96); -- TODO - not on st keyboard
+
+consol_start <= keyboard(60); --F2
+consol_select <= keyboard(61); --F3
+consol_option <= keyboard(62); -- F4
+		
+--f5 <= keyboard(63);
+--f6 <= keyboard(64);
+--f7 <= keyboard(65);
+--f8 <= keyboard(66);
+--f9 <= keyboard(67);
+--f10 <= keyboard(68);
+
+--HOT KEYS! Connect to ZPU when present...
+--virtual_keys <= keyboard(65)&keyboard(66)&keyboard(67)&keyboard(68);
+--SYSTEM_RESET_REQUEST <= keyboard(63);
+
+-- TODO this should be common, same for PS2 after mapping...
+process(keyboard_scan, atari_keyboard, control_pressed, shift_pressed, break_pressed)
+	begin	
+		keyboard_response <= (others=>'1');		
+		
+		if (atari_keyboard(to_integer(unsigned(not(keyboard_scan)))) = '1') then
+			keyboard_response(0) <= '0';
+		end if;
+		
+		if (keyboard_scan(5 downto 4)="00" and break_pressed = '1') then
+			keyboard_response(1) <= '0';
+		end if;
+		
+		if (keyboard_scan(5 downto 4)="10" and shift_pressed = '1') then
+			keyboard_response(1) <= '0';
+		end if;
+
+		if (keyboard_scan(5 downto 4)="11" and control_pressed = '1') then
+			keyboard_response(1) <= '0';
+		end if;
+end process;		 
+		  
+dac_left : hq_dac
+port map
+(
+  reset => not(reset_n),
+  clk => clk,
+  clk_ena => '1',
+  pcm_in => AUDIO_L_PCM&"0000",
+  dac_out => audio_l
+);
+
+dac_right : hq_dac
+port map
+(
+  reset => not(reset_n),
+  clk => clk,
+  clk_ena => '1',
+  pcm_in => AUDIO_R_PCM&"0000",
+  dac_out => audio_r
+);
+
+-- TODO - mist joystick mapping!
+--GPIO_PORTA_IN <= VIRTUAL_STICKS and (JOY1_n(0)&JOY1_n(1)&JOY1_n(2)&JOY1_n(3)&JOY2_n(0)&JOY2_n(1)&JOY2_n(2)&JOY2_n(3));
+--fire is bit 4...
+
+mist_pll : entity work.pll
+PORT MAP(inclk0 => CLOCK_27(0),
+		 c0 => CLK_SDRAM,
+		 c1 => CLK,
+		 c2 => SDRAM_CLK,
+		 locked => PLL_LOCKED);
+
+reset_n <= PLL_LOCKED;
+
+-- THROTTLE
+THROTTLE_COUNT_6502 <= std_logic_vector(to_unsigned(32-1,6));
+
+atarixl_simple_sdram1 : entity work.atari800core_simple_sdram
+	GENERIC MAP
+	(
+		cycle_length => 32,
+		internal_rom => 1,
+		internal_ram => 16384
+	)
+	PORT MAP
+	(
+		CLK => CLK,
+		RESET_N => RESET_N,
+
+		VGA_VS => VGA_VS_RAW,
+		VGA_HS => VGA_HS_RAW,
+		VGA_B => VGA_B_WIDE,
+		VGA_G => VGA_G_WIDE,
+		VGA_R => VGA_R_WIDE,
+
+		AUDIO_L => AUDIO_L_PCM,
+		AUDIO_R => AUDIO_R_PCM,
+
+		JOY1_n => JOY1_n,
+		JOY2_n => JOY2_n,
+
+		KEYBOARD_RESPONSE => KEYBOARD_RESPONSE,
+		KEYBOARD_SCAN => KEYBOARD_SCAN,
+
+		SIO_COMMAND => open,
+		SIO_RXD => '1',
+		SIO_TXD => open,
+
+		CONSOL_OPTION => CONSOL_OPTION,
+		CONSOL_SELECT => CONSOL_SELECT,
+		CONSOL_START => CONSOL_START,
+
+		SDRAM_REQUEST => open,
+		SDRAM_REQUEST_COMPLETE => '1',
+		SDRAM_READ_ENABLE => open,
+		SDRAM_WRITE_ENABLE => open,
+		SDRAM_ADDR => open,
+		SDRAM_DO => (others=>'1'),
+
+		DMA_FETCH => '0',
+		DMA_READ_ENABLE => '0',
+		DMA_32BIT_WRITE_ENABLE => '0',
+		DMA_16BIT_WRITE_ENABLE => '0',
+		DMA_8BIT_WRITE_ENABLE => '0',
+		DMA_ADDR => (others=>'1'),
+		DMA_WRITE_DATA => (others=>'1'),
+		MEMORY_READY_DMA => open,
+
+   		RAM_SELECT => (others=>'0'),
+    		ROM_SELECT => "000001",
+		PAL => PAL,
+		HALT => '0',
+		THROTTLE_COUNT_6502 => THROTTLE_COUNT_6502
+	);
+
+--b2v_inst20 : sdram_statemachine
+--GENERIC MAP(ADDRESS_WIDTH => 22,
+--			AP_BIT => 10,
+--			COLUMN_WIDTH => 8,
+--			ROW_WIDTH => 12
+--			)
+--PORT MAP(CLK_SYSTEM => CLK,
+--		 CLK_SDRAM => CLK_SDRAM,
+--		 RESET_N => RESET_N,
+--		 READ_EN => SDRAM_READ_ENABLE,
+--		 WRITE_EN => SDRAM_WRITE_ENABLE,
+--		 REQUEST => SDRAM_REQUEST,
+--		 BYTE_ACCESS => WIDTH_8BIT_ACCESS,
+--		 WORD_ACCESS => WIDTH_16BIT_ACCESS,
+--		 LONGWORD_ACCESS => WIDTH_32BIT_ACCESS,
+--		 REFRESH => SDRAM_REFRESH,
+--		 ADDRESS_IN => SDRAM_ADDR,
+--		 DATA_IN => WRITE_DATA,
+--		 SDRAM_DQ => SDRAM_DQ,
+--		 COMPLETE => SDRAM_REQUEST_COMPLETE,
+--		 SDRAM_BA0 => SDRAM_BA(0),
+--		 SDRAM_BA1 => SDRAM_BA(1),
+--		 SDRAM_CKE => SDRAM_CKE,
+--		 SDRAM_CS_N => SDRAM_nCS,
+--		 SDRAM_RAS_N => SDRAM_nRAS,
+--		 SDRAM_CAS_N => SDRAM_nCAS,
+--		 SDRAM_WE_N => SDRAM_nWE,
+--		 SDRAM_ldqm => SDRAM_DQML,
+--		 SDRAM_udqm => SDRAM_DQMH,
+--		 DATA_OUT => SDRAM_DO,
+--		 SDRAM_ADDR => SDRAM_A(11 downto 0));
+--		 
+--SDRAM_A(12) <= '0';
+
+-- Until SDRAM enabled... TODO
+SDRAM_nCS <= '1';
+SDRAM_DQ <= (others=>'Z');
+
+--SDRAM_CKE <= '1';		 
+LED <= '0';
+
+VGA_HS <= not(VGA_HS_RAW xor VGA_VS_RAW);
+VGA_VS <= not(VGA_VS_RAW);
+VGA_R <= VGA_R_WIDE(7 downto 2);
+VGA_G <= VGA_G_WIDE(7 downto 2);
+VGA_B <= VGA_B_WIDE(7 downto 2);
+
+END vhdl;
Index: mist/build.sh
===================================================================
--- mist/build.sh	(nonexistent)
+++ mist/build.sh	(revision 16)
@@ -0,0 +1,13 @@
+rm -rf build
+mkdir build
+cp atari800core_mist.vhd build
+cp pll.* build
+cp atari800core.sdc build
+cp data_io.vhdl build
+cp user_io.v build
+cp mist_sector_buffer.* build
+
+cd build
+../makeqsf ../atari800core.qsf ../../common/a8core ../../common/components
+
+quartus_sh --flow compile atari800core

Property changes on: mist/build.sh
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: mist/makeqsf
===================================================================
--- mist/makeqsf	(nonexistent)
+++ mist/makeqsf	(revision 16)
@@ -0,0 +1,33 @@
+#!/usr/bin/perl -w
+use strict;
+
+my $qsf_in = shift @ARGV;
+my $qsf_out = $qsf_in;
+$qsf_out =~ s/.*\///;
+
+open (QSF_IN,$qsf_in) or die "Failed to open $qsf_in";
+my @qsf_base = <QSF_IN>;
+close (QSF_IN);
+
+open (QSF_OUT,">$qsf_out") or die "Failed to open $qsf_out";
+print QSF_OUT @qsf_base;
+
+foreach (@ARGV)
+{
+	my @vhdl = glob ("$_/*.vhd");
+	push @vhdl, glob ("$_/*.vhdl");
+	my @verilog = glob ("$_/*.v");
+
+	foreach (@verilog)
+	{
+		print QSF_OUT "set_global_assignment -name VERILOG_FILE $_\n";
+	}
+
+	foreach (@vhdl)
+	{
+		print QSF_OUT "set_global_assignment -name VHDL_FILE $_\n";
+	}
+}
+
+close (QSF_OUT);
+

Property changes on: mist/makeqsf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
