Index: de1_5200/COPYRIGHT_NOTICE
===================================================================
--- de1_5200/COPYRIGHT_NOTICE	(nonexistent)
+++ de1_5200/COPYRIGHT_NOTICE	(revision 176)
@@ -0,0 +1,128 @@
+(c) 2013 Mark Watson
+I am happy for anyone to use these for non-commercial use.
+If my vhdl files are used commercially or sold please contact me for explicit permission at scrameta@gmail.com.
+This applies for source and binary form and derived works.
+
+pokey.vhdl
+pokey_noise_filter.vhdl
+pokey_keyboard_scanner.vhdl
+pokey_ps2_decoder.vhdl
+pokey_mixer.vhdl
+poly_4.vhdl
+poly_5.vhdl
+poly_17_9.vhdl
+
+gtia.vhdl
+gtia_priority.vhdl
+gtia_palette.vhdl // Palette data itself from laoo and Altirra
+gtia_player.vhdl
+
+antic.vhdl
+antic_dma_clock.vhdl
+antic_counter.vhdl
+
+pia.vhdl
+
+cpu.vhd
+shared_enable.vhdl
+irq_glue.vhdl
+
+ps2_keyboard.vhdl
+
+scandoubler.vhdl
+scandouble_ram_infer.vhdl
+
+zpu_glue.vhdl
+zpu_config_regs.vhdl
+
+// utils
+synchronizer.vhdl
+delay_line.vhdl
+wide_delay_line.vhdl
+reg_file.vhdl
+enable_divider.vhdl
+syncreset_enable_divider.vhd
+complete_address_decoder.vhdl
+countdown_timer.vhdl
+simple_counter.vhdl
+
+// semi de1 specific
+sram.vhdl
+flashrom.vhdl
+sdram_statemachine.vhdl
+address_decoder.vhdl
+
+// de1 specific
+atari800core.vhd // top level for DE1
+i2sslave.vhdl
+hexdecoder.vhd
+gpio.vhd
+ledsw.vhd
+
+// altera megafunctions
+pll.vhd 
+zpu_ram.vhd
+zpu_rom.vhd
+
+-----------------------------------------------------------------------------------
+(c) Mike Stirling (from Spectrum core)
+See header for Mike's copyright note
+Parameters modified for my use case
+
+i2c_loader.vhd
+
+-----------------------------------------------------------------------------------
+(c) Peter Wendrich
+Please contact Peter if you wish to use them. I have permission for use as part of the Atari800 core.
+
+cpu_6510.vhd
+cpu_65xx_e.vhd
+cpu_65xx_a.vhd
+
+-----------------------------------------------------------------------------------
+---- Copyright (c) 2008 Ãvind Harboe <oyvind.harboe zylin.com>           ----
+---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar>         ----
+---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial       ----
+ZPU implementation. See headers for more details
+I made a few fixes to make it work for my use case.
+
+zpu_core.vhd
+zpupkg.vhd
+
+-----------------------------------------------------------------------------------
+(c) Scott Larson
+See file header
+
+spi_master.vhd
+
+-----------------------------------------------------------------------------------
+-----------------------------------------------------------------------------------
+zpu/*.[ch]
+SD card/OSD
+-----------------------------------------------------------------------------------
+(c) Mark Watson
+Also some portions taken from SDrive, so (c) Bob and Raster
+
+I am happy for these to be used freely for commercial and non-commercial use.
+
+debug.h  led.h   pause.h  regs.h  types.h  uart.h
+bootdump.c  debug.c  led.c  main.c  regs.c  test.c  uart.c
+
+zpuromgen.c
+
+----------------------------------------------------------------------------------
+(c) Pascal Stang + Bob and Raster
+spi.c
+spi.h
+mmc.c  
+mmc.h
+mmcconf.h 
+
+-----------------------------------------------------------------------------------
+(c) ChaN
+Petit File System
+
+integer.h  
+diskio.h  
+pff.h
+pff.c  
Index: de1_5200/atari800core.qsf
===================================================================
--- de1_5200/atari800core.qsf	(nonexistent)
+++ de1_5200/atari800core.qsf	(revision 176)
@@ -0,0 +1,580 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2012 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Web Edition
+# Date created = 13:58:39  April 11, 2013
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		atari800core_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone II"
+set_global_assignment -name DEVICE EP2C20F484C7
+set_global_assignment -name TOP_LEVEL_ENTITY atari800core_de1
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "12.1 SP1"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:58:39  APRIL 11, 2013"
+set_global_assignment -name LAST_QUARTUS_VERSION "12.1 SP1.33"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_location_assignment PIN_A15 -to GPIO_0[4]
+set_location_assignment PIN_B15 -to GPIO_0[5]
+set_location_assignment PIN_A16 -to GPIO_0[6]
+set_location_assignment PIN_B16 -to GPIO_0[7]
+set_location_assignment PIN_A17 -to GPIO_0[8]
+set_location_assignment PIN_B17 -to GPIO_0[9]
+set_location_assignment PIN_A18 -to GPIO_0[10]
+set_location_assignment PIN_B18 -to GPIO_0[11]
+set_location_assignment PIN_A19 -to GPIO_0[12]
+set_location_assignment PIN_B19 -to GPIO_0[13]
+set_location_assignment PIN_A20 -to GPIO_0[14]
+set_location_assignment PIN_B20 -to GPIO_0[15]
+set_location_assignment PIN_C21 -to GPIO_0[16]
+set_location_assignment PIN_C22 -to GPIO_0[17]
+set_location_assignment PIN_D21 -to GPIO_0[18]
+set_location_assignment PIN_D22 -to GPIO_0[19]
+set_location_assignment PIN_E21 -to GPIO_0[20]
+set_location_assignment PIN_E22 -to GPIO_0[21]
+set_location_assignment PIN_F21 -to GPIO_0[22]
+set_location_assignment PIN_F22 -to GPIO_0[23]
+set_location_assignment PIN_G21 -to GPIO_0[24]
+set_location_assignment PIN_G22 -to GPIO_0[25]
+set_location_assignment PIN_J21 -to GPIO_0[26]
+set_location_assignment PIN_J22 -to GPIO_0[27]
+set_location_assignment PIN_K21 -to GPIO_0[28]
+set_location_assignment PIN_K22 -to GPIO_0[29]
+set_location_assignment PIN_J19 -to GPIO_0[30]
+set_location_assignment PIN_J20 -to GPIO_0[31]
+set_location_assignment PIN_J18 -to GPIO_0[32]
+set_location_assignment PIN_K20 -to GPIO_0[33]
+set_location_assignment PIN_L19 -to GPIO_0[34]
+set_location_assignment PIN_L18 -to GPIO_0[35]
+set_location_assignment PIN_H12 -to GPIO_1[0]
+set_location_assignment PIN_H13 -to GPIO_1[1]
+set_location_assignment PIN_H14 -to GPIO_1[2]
+set_location_assignment PIN_G15 -to GPIO_1[3]
+set_location_assignment PIN_E14 -to GPIO_1[4]
+set_location_assignment PIN_E15 -to GPIO_1[5]
+set_location_assignment PIN_F15 -to GPIO_1[6]
+set_location_assignment PIN_G16 -to GPIO_1[7]
+set_location_assignment PIN_F12 -to GPIO_1[8]
+set_location_assignment PIN_F13 -to GPIO_1[9]
+set_location_assignment PIN_C14 -to GPIO_1[10]
+set_location_assignment PIN_D14 -to GPIO_1[11]
+set_location_assignment PIN_D15 -to GPIO_1[12]
+set_location_assignment PIN_D16 -to GPIO_1[13]
+set_location_assignment PIN_C17 -to GPIO_1[14]
+set_location_assignment PIN_C18 -to GPIO_1[15]
+set_location_assignment PIN_C19 -to GPIO_1[16]
+set_location_assignment PIN_C20 -to GPIO_1[17]
+set_location_assignment PIN_D19 -to GPIO_1[18]
+set_location_assignment PIN_D20 -to GPIO_1[19]
+set_location_assignment PIN_E20 -to GPIO_1[20]
+set_location_assignment PIN_F20 -to GPIO_1[21]
+set_location_assignment PIN_E19 -to GPIO_1[22]
+set_location_assignment PIN_E18 -to GPIO_1[23]
+set_location_assignment PIN_G20 -to GPIO_1[24]
+set_location_assignment PIN_G18 -to GPIO_1[25]
+set_location_assignment PIN_G17 -to GPIO_1[26]
+set_location_assignment PIN_H17 -to GPIO_1[27]
+set_location_assignment PIN_J15 -to GPIO_1[28]
+set_location_assignment PIN_H18 -to GPIO_1[29]
+set_location_assignment PIN_N22 -to GPIO_1[30]
+set_location_assignment PIN_N21 -to GPIO_1[31]
+set_location_assignment PIN_P15 -to GPIO_1[32]
+set_location_assignment PIN_N15 -to GPIO_1[33]
+set_location_assignment PIN_P17 -to GPIO_1[34]
+set_location_assignment PIN_P18 -to GPIO_1[35]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[7]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[8]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[9]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[10]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[11]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[12]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[13]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[14]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[15]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[16]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[17]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[18]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[19]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[20]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[21]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[22]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[23]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[24]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[25]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to GPIO_0[26]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[27]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[28]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[29]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[30]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[31]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[32]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[33]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[34]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[35]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[7]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[8]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[9]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[10]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[11]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[12]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[13]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[14]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[15]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[16]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[17]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[18]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[19]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[20]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[21]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[22]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[23]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[24]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[25]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[26]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[27]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[28]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[29]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[30]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[31]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[32]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[33]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[34]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[35]
+set_location_assignment PIN_L22 -to SW[0]
+set_location_assignment PIN_L21 -to SW[1]
+set_location_assignment PIN_M22 -to SW[2]
+set_location_assignment PIN_V12 -to SW[3]
+set_location_assignment PIN_W12 -to SW[4]
+set_location_assignment PIN_U12 -to SW[5]
+set_location_assignment PIN_U11 -to SW[6]
+set_location_assignment PIN_M2 -to SW[7]
+set_location_assignment PIN_M1 -to SW[8]
+set_location_assignment PIN_L2 -to SW[9]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[7]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[8]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[9]
+set_location_assignment PIN_J2 -to HEX0[0]
+set_location_assignment PIN_J1 -to HEX0[1]
+set_location_assignment PIN_H2 -to HEX0[2]
+set_location_assignment PIN_H1 -to HEX0[3]
+set_location_assignment PIN_F2 -to HEX0[4]
+set_location_assignment PIN_F1 -to HEX0[5]
+set_location_assignment PIN_E2 -to HEX0[6]
+set_location_assignment PIN_E1 -to HEX1[0]
+set_location_assignment PIN_H6 -to HEX1[1]
+set_location_assignment PIN_H5 -to HEX1[2]
+set_location_assignment PIN_H4 -to HEX1[3]
+set_location_assignment PIN_G3 -to HEX1[4]
+set_location_assignment PIN_D2 -to HEX1[5]
+set_location_assignment PIN_D1 -to HEX1[6]
+set_location_assignment PIN_G5 -to HEX2[0]
+set_location_assignment PIN_G6 -to HEX2[1]
+set_location_assignment PIN_C2 -to HEX2[2]
+set_location_assignment PIN_C1 -to HEX2[3]
+set_location_assignment PIN_E3 -to HEX2[4]
+set_location_assignment PIN_E4 -to HEX2[5]
+set_location_assignment PIN_D3 -to HEX2[6]
+set_location_assignment PIN_F4 -to HEX3[0]
+set_location_assignment PIN_D5 -to HEX3[1]
+set_location_assignment PIN_D6 -to HEX3[2]
+set_location_assignment PIN_J4 -to HEX3[3]
+set_location_assignment PIN_L8 -to HEX3[4]
+set_location_assignment PIN_F3 -to HEX3[5]
+set_location_assignment PIN_D4 -to HEX3[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[6]
+set_location_assignment PIN_R22 -to KEY[0]
+set_location_assignment PIN_R21 -to KEY[1]
+set_location_assignment PIN_T22 -to KEY[2]
+set_location_assignment PIN_T21 -to KEY[3]
+set_location_assignment PIN_R20 -to LEDR[0]
+set_location_assignment PIN_R19 -to LEDR[1]
+set_location_assignment PIN_U19 -to LEDR[2]
+set_location_assignment PIN_Y19 -to LEDR[3]
+set_location_assignment PIN_T18 -to LEDR[4]
+set_location_assignment PIN_V19 -to LEDR[5]
+set_location_assignment PIN_Y18 -to LEDR[6]
+set_location_assignment PIN_U18 -to LEDR[7]
+set_location_assignment PIN_R18 -to LEDR[8]
+set_location_assignment PIN_R17 -to LEDR[9]
+set_location_assignment PIN_U22 -to LEDG[0]
+set_location_assignment PIN_U21 -to LEDG[1]
+set_location_assignment PIN_V22 -to LEDG[2]
+set_location_assignment PIN_V21 -to LEDG[3]
+set_location_assignment PIN_W22 -to LEDG[4]
+set_location_assignment PIN_W21 -to LEDG[5]
+set_location_assignment PIN_Y22 -to LEDG[6]
+set_location_assignment PIN_Y21 -to LEDG[7]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[7]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[8]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[9]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[7]
+set_location_assignment PIN_D12 -to CLOCK_27[0]
+set_location_assignment PIN_E12 -to CLOCK_27[1]
+set_location_assignment PIN_B12 -to CLOCK_24[0]
+set_location_assignment PIN_A12 -to CLOCK_24[1]
+set_location_assignment PIN_L1 -to CLOCK_50
+set_location_assignment PIN_M21 -to EXT_CLOCK
+set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_27[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_24[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_24[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_50
+set_instance_assignment -name IO_STANDARD LVTTL -to EXT_CLOCK
+set_location_assignment PIN_H15 -to PS2_CLK
+set_location_assignment PIN_J14 -to PS2_DAT
+set_location_assignment PIN_F14 -to UART_RXD
+set_location_assignment PIN_G12 -to UART_TXD
+set_instance_assignment -name IO_STANDARD LVTTL -to PS2_CLK
+set_instance_assignment -name IO_STANDARD LVTTL -to PS2_DAT
+set_instance_assignment -name IO_STANDARD LVTTL -to UART_RXD
+set_instance_assignment -name IO_STANDARD LVTTL -to UART_TXD
+set_location_assignment PIN_E8 -to TDI
+set_location_assignment PIN_D8 -to TCS
+set_location_assignment PIN_C7 -to TCK
+set_location_assignment PIN_D7 -to TDO
+set_instance_assignment -name IO_STANDARD LVTTL -to TDI
+set_instance_assignment -name IO_STANDARD LVTTL -to TCS
+set_instance_assignment -name IO_STANDARD LVTTL -to TCK
+set_instance_assignment -name IO_STANDARD LVTTL -to TDO
+set_location_assignment PIN_D9 -to VGA_R[0]
+set_location_assignment PIN_C9 -to VGA_R[1]
+set_location_assignment PIN_A7 -to VGA_R[2]
+set_location_assignment PIN_B7 -to VGA_R[3]
+set_location_assignment PIN_B8 -to VGA_G[0]
+set_location_assignment PIN_C10 -to VGA_G[1]
+set_location_assignment PIN_B9 -to VGA_G[2]
+set_location_assignment PIN_A8 -to VGA_G[3]
+set_location_assignment PIN_A9 -to VGA_B[0]
+set_location_assignment PIN_D11 -to VGA_B[1]
+set_location_assignment PIN_A10 -to VGA_B[2]
+set_location_assignment PIN_B10 -to VGA_B[3]
+set_location_assignment PIN_A11 -to VGA_HS
+set_location_assignment PIN_B11 -to VGA_VS
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_HS
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_VS
+set_location_assignment PIN_A3 -to I2C_SCLK
+set_location_assignment PIN_B3 -to I2C_SDAT
+set_location_assignment PIN_A6 -to AUD_ADCLRCK
+set_location_assignment PIN_B6 -to AUD_ADCDAT
+set_location_assignment PIN_A5 -to AUD_DACLRCK
+set_location_assignment PIN_B5 -to AUD_DACDAT
+set_location_assignment PIN_B4 -to AUD_XCK
+set_location_assignment PIN_A4 -to AUD_BCLK
+set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SCLK
+set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCLRCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACLRCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_XCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_BCLK
+set_location_assignment PIN_W4 -to DRAM_ADDR[0]
+set_location_assignment PIN_W5 -to DRAM_ADDR[1]
+set_location_assignment PIN_Y3 -to DRAM_ADDR[2]
+set_location_assignment PIN_Y4 -to DRAM_ADDR[3]
+set_location_assignment PIN_R6 -to DRAM_ADDR[4]
+set_location_assignment PIN_R5 -to DRAM_ADDR[5]
+set_location_assignment PIN_P6 -to DRAM_ADDR[6]
+set_location_assignment PIN_P5 -to DRAM_ADDR[7]
+set_location_assignment PIN_P3 -to DRAM_ADDR[8]
+set_location_assignment PIN_N4 -to DRAM_ADDR[9]
+set_location_assignment PIN_W3 -to DRAM_ADDR[10]
+set_location_assignment PIN_N6 -to DRAM_ADDR[11]
+set_location_assignment PIN_U3 -to DRAM_BA_0
+set_location_assignment PIN_V4 -to DRAM_BA_1
+set_location_assignment PIN_T3 -to DRAM_CAS_N
+set_location_assignment PIN_N3 -to DRAM_CKE
+set_location_assignment PIN_U4 -to DRAM_CLK
+set_location_assignment PIN_T6 -to DRAM_CS_N
+set_location_assignment PIN_U1 -to DRAM_DQ[0]
+set_location_assignment PIN_U2 -to DRAM_DQ[1]
+set_location_assignment PIN_V1 -to DRAM_DQ[2]
+set_location_assignment PIN_V2 -to DRAM_DQ[3]
+set_location_assignment PIN_W1 -to DRAM_DQ[4]
+set_location_assignment PIN_W2 -to DRAM_DQ[5]
+set_location_assignment PIN_Y1 -to DRAM_DQ[6]
+set_location_assignment PIN_Y2 -to DRAM_DQ[7]
+set_location_assignment PIN_N1 -to DRAM_DQ[8]
+set_location_assignment PIN_N2 -to DRAM_DQ[9]
+set_location_assignment PIN_P1 -to DRAM_DQ[10]
+set_location_assignment PIN_P2 -to DRAM_DQ[11]
+set_location_assignment PIN_R1 -to DRAM_DQ[12]
+set_location_assignment PIN_R2 -to DRAM_DQ[13]
+set_location_assignment PIN_T1 -to DRAM_DQ[14]
+set_location_assignment PIN_T2 -to DRAM_DQ[15]
+set_location_assignment PIN_R7 -to DRAM_LDQM
+set_location_assignment PIN_T5 -to DRAM_RAS_N
+set_location_assignment PIN_M5 -to DRAM_UDQM
+set_location_assignment PIN_R8 -to DRAM_WE_N
+set_location_assignment PIN_AB20 -to FL_ADDR[0]
+set_location_assignment PIN_AA14 -to FL_ADDR[1]
+set_location_assignment PIN_Y16 -to FL_ADDR[2]
+set_location_assignment PIN_R15 -to FL_ADDR[3]
+set_location_assignment PIN_T15 -to FL_ADDR[4]
+set_location_assignment PIN_U15 -to FL_ADDR[5]
+set_location_assignment PIN_V15 -to FL_ADDR[6]
+set_location_assignment PIN_W15 -to FL_ADDR[7]
+set_location_assignment PIN_R14 -to FL_ADDR[8]
+set_location_assignment PIN_Y13 -to FL_ADDR[9]
+set_location_assignment PIN_R12 -to FL_ADDR[10]
+set_location_assignment PIN_T12 -to FL_ADDR[11]
+set_location_assignment PIN_AB14 -to FL_ADDR[12]
+set_location_assignment PIN_AA13 -to FL_ADDR[13]
+set_location_assignment PIN_AB13 -to FL_ADDR[14]
+set_location_assignment PIN_AA12 -to FL_ADDR[15]
+set_location_assignment PIN_AB12 -to FL_ADDR[16]
+set_location_assignment PIN_AA20 -to FL_ADDR[17]
+set_location_assignment PIN_U14 -to FL_ADDR[18]
+set_location_assignment PIN_V14 -to FL_ADDR[19]
+set_location_assignment PIN_U13 -to FL_ADDR[20]
+set_location_assignment PIN_R13 -to FL_ADDR[21]
+set_location_assignment PIN_AB16 -to FL_DQ[0]
+set_location_assignment PIN_AA16 -to FL_DQ[1]
+set_location_assignment PIN_AB17 -to FL_DQ[2]
+set_location_assignment PIN_AA17 -to FL_DQ[3]
+set_location_assignment PIN_AB18 -to FL_DQ[4]
+set_location_assignment PIN_AA18 -to FL_DQ[5]
+set_location_assignment PIN_AB19 -to FL_DQ[6]
+set_location_assignment PIN_AA19 -to FL_DQ[7]
+set_location_assignment PIN_AA15 -to FL_OE_N
+set_location_assignment PIN_W14 -to FL_RST_N
+set_location_assignment PIN_Y14 -to FL_WE_N
+set_location_assignment PIN_AA3 -to SRAM_ADDR[0]
+set_location_assignment PIN_AB3 -to SRAM_ADDR[1]
+set_location_assignment PIN_AA4 -to SRAM_ADDR[2]
+set_location_assignment PIN_AB4 -to SRAM_ADDR[3]
+set_location_assignment PIN_AA5 -to SRAM_ADDR[4]
+set_location_assignment PIN_AB10 -to SRAM_ADDR[5]
+set_location_assignment PIN_AA11 -to SRAM_ADDR[6]
+set_location_assignment PIN_AB11 -to SRAM_ADDR[7]
+set_location_assignment PIN_V11 -to SRAM_ADDR[8]
+set_location_assignment PIN_W11 -to SRAM_ADDR[9]
+set_location_assignment PIN_R11 -to SRAM_ADDR[10]
+set_location_assignment PIN_T11 -to SRAM_ADDR[11]
+set_location_assignment PIN_Y10 -to SRAM_ADDR[12]
+set_location_assignment PIN_U10 -to SRAM_ADDR[13]
+set_location_assignment PIN_R10 -to SRAM_ADDR[14]
+set_location_assignment PIN_T7 -to SRAM_ADDR[15]
+set_location_assignment PIN_Y6 -to SRAM_ADDR[16]
+set_location_assignment PIN_Y5 -to SRAM_ADDR[17]
+set_location_assignment PIN_AB5 -to SRAM_CE_N
+set_location_assignment PIN_AA6 -to SRAM_DQ[0]
+set_location_assignment PIN_AB6 -to SRAM_DQ[1]
+set_location_assignment PIN_AA7 -to SRAM_DQ[2]
+set_location_assignment PIN_AB7 -to SRAM_DQ[3]
+set_location_assignment PIN_AA8 -to SRAM_DQ[4]
+set_location_assignment PIN_AB8 -to SRAM_DQ[5]
+set_location_assignment PIN_AA9 -to SRAM_DQ[6]
+set_location_assignment PIN_AB9 -to SRAM_DQ[7]
+set_location_assignment PIN_Y9 -to SRAM_DQ[8]
+set_location_assignment PIN_W9 -to SRAM_DQ[9]
+set_location_assignment PIN_V9 -to SRAM_DQ[10]
+set_location_assignment PIN_U9 -to SRAM_DQ[11]
+set_location_assignment PIN_R9 -to SRAM_DQ[12]
+set_location_assignment PIN_W8 -to SRAM_DQ[13]
+set_location_assignment PIN_V8 -to SRAM_DQ[14]
+set_location_assignment PIN_U8 -to SRAM_DQ[15]
+set_location_assignment PIN_Y7 -to SRAM_LB_N
+set_location_assignment PIN_T8 -to SRAM_OE_N
+set_location_assignment PIN_W7 -to SRAM_UB_N
+set_location_assignment PIN_AA10 -to SRAM_WE_N
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_CE_N
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_LB_N
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_OE_N
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_UB_N
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_WE_N
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[0]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[1]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[2]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[3]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[4]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[5]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[6]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[7]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[8]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[9]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[10]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[11]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[12]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[13]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[14]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[15]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[16]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[17]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[0]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[1]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[2]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[3]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[4]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[5]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[6]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[7]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[8]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[9]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[10]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[11]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[12]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[13]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[14]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[15]
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name ENABLE_SIGNALTAP ON
+set_location_assignment PIN_V20 -to SD_CLK
+set_location_assignment PIN_Y20 -to SD_CMD
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
+set_global_assignment -name BLOCK_DESIGN_NAMING AUTO
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_location_assignment PIN_W20 -to SD_DATA
+set_location_assignment PIN_U20 -to SD_THREE
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name ENABLE_DRC_SETTINGS ON
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
+set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
+set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII NORMAL
+set_global_assignment -name FITTER_EFFORT "AUTO FIT"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
+set_location_assignment PIN_A13 -to GPIO_0[0]
+set_location_assignment PIN_B13 -to GPIO_0[1]
+set_location_assignment PIN_A14 -to GPIO_0[2]
+set_location_assignment PIN_B14 -to GPIO_0[3]
+
+set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp1.stp
+set_global_assignment -name SIGNALTAP_FILE output_files/stp1.stp
+
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+
+set_global_assignment -name VHDL_FILE gpio.vhd
+set_global_assignment -name VHDL_FILE atari800core_de1.vhd
+set_global_assignment -name VHDL_FILE hexdecoder.vhd
+set_global_assignment -name VHDL_FILE i2c_loader.vhd
+set_global_assignment -name VHDL_FILE i2s_intf.vhd
+set_global_assignment -name VHDL_FILE i2sslave.vhdl
+set_global_assignment -name QIP_FILE pll_pal.qip
+set_global_assignment -name QIP_FILE pll_ntsc.qip
+set_global_assignment -name QIP_FILE pll.qip
+set_global_assignment -name VHDL_FILE sram.vhdl
+set_global_assignment -name VHDL_FILE sync_switches.vhd
+set_global_assignment -name VHDL_FILE zpu_rom.vhdl
+
Index: de1_5200/atari800core.sdc
===================================================================
--- de1_5200/atari800core.sdc	(nonexistent)
+++ de1_5200/atari800core.sdc	(revision 176)
@@ -0,0 +1,6 @@
+create_clock -period 50MHz [get_ports CLOCK_50]
+derive_pll_clocks
+
+set_input_delay -max -clock CLOCK_50 -1.5 [get_ports SRAM_DQ*]
+set_input_delay -min -clock CLOCK_50 -1.5 [get_ports SRAM_DQ*]
+
Index: de1_5200/atari800core_de1.vhd
===================================================================
--- de1_5200/atari800core_de1.vhd	(nonexistent)
+++ de1_5200/atari800core_de1.vhd	(revision 176)
@@ -0,0 +1,630 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all; 
+use ieee.numeric_std.all;
+
+LIBRARY work;
+
+ENTITY atari800core_de1 IS 
+	GENERIC
+	(
+		TV : integer  -- 1 = PAL, 0=NTSC
+	);
+	PORT
+	(
+		CLOCK_50 :  IN  STD_LOGIC;
+
+		AUD_BCLK :  IN  STD_LOGIC;
+		AUD_DACLRCK :  IN  STD_LOGIC;
+		I2C_SCLK :  INOUT  STD_LOGIC;
+		I2C_SDAT :  INOUT  STD_LOGIC;
+
+		PS2_CLK :  IN  STD_LOGIC;
+		PS2_DAT :  IN  STD_LOGIC;
+
+		UART_RXD :  IN  STD_LOGIC;
+		UART_TXD :  OUT  STD_LOGIC;
+
+		GPIO_0 :  INOUT  STD_LOGIC_VECTOR(35 DOWNTO 0);
+		GPIO_1 :  INOUT  STD_LOGIC_VECTOR(35 DOWNTO 0);
+
+		KEY :  IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
+		SW :  IN  STD_LOGIC_VECTOR(9 DOWNTO 0);
+
+		AUD_XCK :  OUT  STD_LOGIC;
+		AUD_DACDAT :  OUT  STD_LOGIC;
+
+		FL_OE_N :  OUT  STD_LOGIC;
+		FL_WE_N :  OUT  STD_LOGIC;
+		FL_RST_N :  OUT  STD_LOGIC;
+		FL_ADDR :  OUT  STD_LOGIC_VECTOR(21 DOWNTO 0);
+		FL_DQ :  IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
+
+		SRAM_CE_N :  OUT  STD_LOGIC;
+		SRAM_OE_N :  OUT  STD_LOGIC;
+		SRAM_WE_N :  OUT  STD_LOGIC;
+		SRAM_LB_N :  OUT  STD_LOGIC;
+		SRAM_UB_N :  OUT  STD_LOGIC;
+		SRAM_ADDR :  OUT  STD_LOGIC_VECTOR(17 DOWNTO 0);
+		SRAM_DQ :  INOUT  STD_LOGIC_VECTOR(15 DOWNTO 0);
+
+		DRAM_BA_0 :  OUT  STD_LOGIC;
+		DRAM_BA_1 :  OUT  STD_LOGIC;
+		DRAM_CS_N :  OUT  STD_LOGIC;
+		DRAM_RAS_N :  OUT  STD_LOGIC;
+		DRAM_CAS_N :  OUT  STD_LOGIC;
+		DRAM_WE_N :  OUT  STD_LOGIC;
+		DRAM_LDQM :  OUT  STD_LOGIC;
+		DRAM_UDQM :  OUT  STD_LOGIC;
+		DRAM_CLK :  OUT  STD_LOGIC;
+		DRAM_CKE :  OUT  STD_LOGIC;
+		DRAM_ADDR :  OUT  STD_LOGIC_VECTOR(11 DOWNTO 0);
+		DRAM_DQ :  INOUT  STD_LOGIC_VECTOR(15 DOWNTO 0);
+
+		SD_CLK :  OUT  STD_LOGIC;
+		SD_CMD :  OUT  STD_LOGIC;
+		SD_THREE :  OUT  STD_LOGIC;
+		SD_DATA :  IN  STD_LOGIC;
+
+		HEX0 :  OUT  STD_LOGIC_VECTOR(6 DOWNTO 0);
+		HEX1 :  OUT  STD_LOGIC_VECTOR(6 DOWNTO 0);
+		HEX2 :  OUT  STD_LOGIC_VECTOR(6 DOWNTO 0);
+		HEX3 :  OUT  STD_LOGIC_VECTOR(6 DOWNTO 0);
+
+		LEDG :  OUT  STD_LOGIC_VECTOR(7 DOWNTO 0);
+		LEDR :  OUT  STD_LOGIC_VECTOR(9 DOWNTO 0);
+
+		VGA_VS :  OUT  STD_LOGIC;
+		VGA_HS :  OUT  STD_LOGIC;
+		VGA_B :  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0);
+		VGA_G :  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0);
+		VGA_R :  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0)
+	);
+END atari800core_de1;
+
+ARCHITECTURE vhdl OF atari800core_de1 IS 
+	-- SYSTEM
+	SIGNAL CLK : STD_LOGIC;
+	SIGNAL CLK_SDRAM : STD_LOGIC;
+	SIGNAL RESET_N : STD_LOGIC;
+	signal SDRAM_RESET_N : std_logic;
+	SIGNAL PLL_LOCKED : STD_LOGIC;
+
+	-- GTIA
+	signal CONSOL_OUT : std_logic_vector(3 downto 0);
+	signal CONSOL_IN : std_logic_vector(3 downto 0);
+	signal GTIA_TRIG : std_logic_vector(3 downto 0);
+	
+	-- CARTRIDGE ACCESS
+	--SIGNAL	CART_RD4 :  STD_LOGIC;
+	--SIGNAL	CART_RD5 :  STD_LOGIC;
+	--SIGNAL	CART_S4_n :  STD_LOGIC;
+	--SIGNAL	CART_S5_n :  STD_LOGIC;
+	--SIGNAL	CART_CCTL_n :  STD_LOGIC;
+	
+	-- PBI
+	SIGNAL PBI_WRITE_DATA : std_logic_vector(31 downto 0);
+	SIGNAL PBI_WIDTH_32BIT_ACCESS : std_logic;
+	SIGNAL PBI_WIDTH_16BIT_ACCESS : std_logic;
+	SIGNAL PBI_WIDTH_8BIT_ACCESS : std_logic;
+	
+	-- INTERNAL ROM/RAM
+	SIGNAL	RAM_ADDR :  STD_LOGIC_VECTOR(18 DOWNTO 0);
+	SIGNAL	RAM_DO :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+	SIGNAL	RAM_REQUEST :  STD_LOGIC;
+	SIGNAL	RAM_REQUEST_COMPLETE :  STD_LOGIC;
+	SIGNAL	RAM_WRITE_ENABLE :  STD_LOGIC;
+	
+	SIGNAL	ROM_ADDR :  STD_LOGIC_VECTOR(21 DOWNTO 0);
+	SIGNAL	ROM_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+	SIGNAL	ROM_REQUEST :  STD_LOGIC;
+	SIGNAL	ROM_REQUEST_COMPLETE :  STD_LOGIC;
+
+	-- SDRAM
+	signal SDRAM_REQUEST : std_logic;
+	signal SDRAM_REQUEST_COMPLETE : std_logic;
+	signal SDRAM_READ_ENABLE :  STD_LOGIC;
+	signal SDRAM_WRITE_ENABLE : std_logic;
+	signal SDRAM_ADDR : STD_LOGIC_VECTOR(22 DOWNTO 0);
+	signal SDRAM_DO : STD_LOGIC_VECTOR(31 DOWNTO 0);
+	
+	signal SDRAM_REFRESH : std_logic;
+	
+	-- pokey keyboard
+	SIGNAL KEYBOARD_SCAN : std_logic_vector(5 downto 0);
+	SIGNAL KEYBOARD_RESPONSE : std_logic_vector(1 downto 0);
+	
+	-- SIO
+	SIGNAL SIO_RXD : std_logic;
+	SIGNAL SIO_COMMAND : std_logic;
+	SIGNAL SIO_TXD : std_logic;
+
+	SIGNAL GPIO_SIO_RXD : std_logic;
+
+	-- VIDEO
+	signal VGA_VS_RAW : std_logic;
+	signal VGA_HS_RAW : std_logic;
+
+	-- AUDIO
+	signal AUDIO_LEFT : std_logic_vector(15 downto 0);
+	signal AUDIO_RIGHT : std_logic_vector(15 downto 0);
+
+	-- dma/virtual drive
+	signal DMA_ADDR_FETCH : std_logic_vector(23 downto 0);
+	signal DMA_WRITE_DATA : std_logic_vector(31 downto 0);
+	signal DMA_FETCH : std_logic;
+	signal DMA_32BIT_WRITE_ENABLE : std_logic;
+	signal DMA_16BIT_WRITE_ENABLE : std_logic;
+	signal DMA_8BIT_WRITE_ENABLE : std_logic;
+	signal DMA_READ_ENABLE : std_logic;
+	signal DMA_MEMORY_READY : std_logic;
+	signal DMA_MEMORY_DATA : std_logic_vector(31 downto 0);
+
+	signal ZPU_ADDR_ROM : std_logic_vector(15 downto 0);
+	signal ZPU_ROM_DATA :  std_logic_vector(31 downto 0);
+
+	signal ZPU_OUT1 : std_logic_vector(31 downto 0);
+	signal ZPU_OUT2 : std_logic_vector(31 downto 0);
+	signal ZPU_OUT3 : std_logic_vector(31 downto 0);
+	signal ZPU_OUT4 : std_logic_vector(31 downto 0);
+
+	signal zpu_pokey_enable : std_logic;
+	signal zpu_sio_txd : std_logic;
+	signal zpu_sio_rxd : std_logic;
+	signal zpu_sio_command : std_logic;
+
+	SIGNAL FKEYS : std_logic_vector(11 downto 0);
+
+	-- system control from zpu
+	signal reset_atari : std_logic;
+	signal pause_atari : std_logic;
+	SIGNAL speed_6502 : std_logic_vector(5 downto 0);
+
+	-- GPIO
+	signal GPIO_0_DIR_OUT : std_logic_vector(35 downto 0);
+	signal GPIO_0_OUT : std_logic_vector(35 downto 0);
+	signal GPIO_1_DIR_OUT : std_logic_vector(35 downto 0);
+	signal GPIO_1_OUT : std_logic_vector(35 downto 0);
+	signal TRIGGERS : std_logic_vector(3 downto 0);
+
+	-- POT
+	signal POT_RESET : std_logic;
+	signal POT_IN : std_logic_vector(7 downto 0);
+
+BEGIN 
+
+-- ANYTHING NOT CONNECTED...
+--GPIO_0(0) <= 'Z';
+--GPIO_0(35 downto 2) <= (others=>'Z');
+--GPIO_1(35 downto 0) <= (others=>'Z');
+
+FL_OE_N <= '1';
+FL_WE_N <= '1';
+FL_RST_N <= '1';
+FL_ADDR <= (others=>'0');
+
+LEDG <= (others=>'1');
+LEDR <= (others=>'1');
+
+-- TODO FUJI? Or Program counter or...
+hexdecoder0 : entity work.hexdecoder
+PORT MAP(CLK => CLK,
+		 NUMBER => X"5",
+		 DIGIT => HEX0);
+
+
+hexdecoder1 : entity work.hexdecoder
+PORT MAP(CLK => CLK,
+		 NUMBER => X"2",
+		 DIGIT => HEX1);
+
+
+hexdecoder2 : entity work.hexdecoder
+PORT MAP(CLK => CLK,
+		 NUMBER => X"0",
+		 DIGIT => HEX2);
+
+
+hexdecoder3 : entity work.hexdecoder
+PORT MAP(CLK => CLK,
+		 NUMBER => X"0",
+		 DIGIT => HEX3);
+
+sram1 : entity work.sram
+PORT MAP(WREN => RAM_WRITE_ENABLE,
+		 clk => CLK,
+		 reset_n => RESET_N,
+		 request => RAM_REQUEST,
+		 width_16bit => PBI_WIDTH_16BIT_ACCESS,
+		 ADDRESS => RAM_ADDR,
+		 DIN => PBI_WRITE_DATA(15 DOWNTO 0),
+		 SRAM_DQ => SRAM_DQ,
+		 SRAM_CE_N => SRAM_CE_N,
+		 SRAM_OE_N => SRAM_OE_N,
+		 SRAM_WE_N => SRAM_WE_N,
+		 SRAM_LB_N => SRAM_LB_N,
+		 SRAM_UB_N => SRAM_UB_N,
+		 complete => RAM_REQUEST_COMPLETE,
+		 DOUT => RAM_DO,
+		 SRAM_ADDR => SRAM_ADDR);
+
+sdram_adaptor : entity work.sdram_statemachine
+GENERIC MAP(ADDRESS_WIDTH => 22,
+			AP_BIT => 10,
+			COLUMN_WIDTH => 8,
+			ROW_WIDTH => 12
+			)
+PORT MAP(CLK_SYSTEM => CLK,
+		 CLK_SDRAM => CLK_SDRAM,
+		 RESET_N =>  RESET_N,
+		 READ_EN => SDRAM_READ_ENABLE,
+		 WRITE_EN => SDRAM_WRITE_ENABLE,
+		 REQUEST => SDRAM_REQUEST,
+		 BYTE_ACCESS => PBI_WIDTH_8BIT_ACCESS,
+		 WORD_ACCESS => PBI_WIDTH_16BIT_ACCESS,
+		 LONGWORD_ACCESS => PBI_WIDTH_32BIT_ACCESS,
+		 REFRESH => SDRAM_REFRESH,
+		 ADDRESS_IN => SDRAM_ADDR,
+		 DATA_IN => PBI_WRITE_DATA(31 downto 0),
+		 SDRAM_DQ => DRAM_DQ,
+		 COMPLETE => SDRAM_REQUEST_COMPLETE,
+		 SDRAM_BA0 => DRAM_BA_0,
+		 SDRAM_BA1 => DRAM_BA_1,
+		 SDRAM_CKE => DRAM_CKE,
+		 SDRAM_CS_N => DRAM_CS_N,
+		 SDRAM_RAS_N => DRAM_RAS_N,
+		 SDRAM_CAS_N => DRAM_CAS_N,
+		 SDRAM_WE_N => DRAM_WE_N,
+		 SDRAM_ldqm => DRAM_LDQM,
+		 SDRAM_udqm => DRAM_UDQM,
+		 DATA_OUT => SDRAM_DO,
+		 SDRAM_ADDR => DRAM_ADDR(11 downto 0),
+		 reset_client_n => SDRAM_RESET_N
+		 );
+
+-- GTIA triggers
+--GTIA_TRIG <= CART_RD5&"1"&JOY2_n(4)&JOY1_n(4);
+GTIA_TRIG <= TRIGGERS(3 downto 0);
+
+-- Internal rom/ram
+internalromram1 : entity work.internalromram
+	GENERIC MAP
+	(
+		internal_rom => 0,
+		internal_ram => 0
+	)
+	PORT MAP (
+ 		clock   => CLK,
+		reset_n => RESET_N,
+
+		ROM_ADDR => ROM_ADDR,
+		ROM_REQUEST_COMPLETE => ROM_REQUEST_COMPLETE,
+		ROM_REQUEST => ROM_REQUEST,
+		ROM_DATA => ROM_DO,
+		
+		RAM_ADDR => RAM_ADDR,
+		RAM_WR_ENABLE => RAM_WRITE_ENABLE,
+		RAM_DATA_IN => PBI_WRITE_DATA(7 downto 0),
+		RAM_REQUEST_COMPLETE => open,
+		RAM_REQUEST => RAM_REQUEST,
+		RAM_DATA => open
+	);
+
+--sync_switches1 : entity work.sync_switches
+--PORT MAP(CLK => CLK,
+--		 KEY => KEY,
+--		 SW => SW,
+--		 SYNC_KEYS => SYNC_KEYS,
+--		 SYNC_SWITCHES => SYNC_SWITCHES);
+
+gpio0_gen:
+   for I in 0 to 35 generate
+		gpio_0(I) <= gpio_0_out(I) when gpio_0_dir_out(I)='1' else 'Z';
+   end generate gpio0_gen;
+
+gpio1_gen:
+   for I in 0 to 35 generate
+		gpio_1(I) <= gpio_1_out(I) when gpio_1_dir_out(I)='1' else 'Z';
+   end generate gpio1_gen;
+
+gpio1 : entity work.gpio
+PORT MAP(clk => CLK,
+		 gpio_enable => '1',
+		 pot_reset => pot_reset,
+		 pbi_write_enable => '0',
+		 cart_request => '0',
+		 cart_complete => open,
+		 cart_data_read => open,
+		 s4_n => '0',
+		 s5_n => '0',
+		 cctl_n => '0',
+		 cart_data_write => x"00",
+		 GPIO_0_IN => GPIO_0,
+		 GPIO_0_OUT => GPIO_0_OUT,
+		 GPIO_0_DIR_OUT => GPIO_0_DIR_OUT,
+		 GPIO_1_IN => GPIO_1,
+		 GPIO_1_OUT => GPIO_1_OUT,
+		 GPIO_1_DIR_OUT => GPIO_1_DIR_OUT,		 
+		 keyboard_scan => KEYBOARD_SCAN, --5200
+		 pbi_addr_out => X"0000",
+		 porta_out => (others=>'0'),
+		 porta_output => (others=>'0'),
+		 lightpen => open,
+		 rd4 => open,
+		 rd5 => open,
+		 keyboard_response => KEYBOARD_RESPONSE, -- 5200
+		 porta_in => open,
+		 pot_in => pot_in,
+		 trig_in => TRIGGERS, -- 5200
+		 CA2_DIR_OUT => '0',
+		 CA2_OUT => '0',
+		 CA2_IN => open,
+		 CB2_DIR_OUT => '0',
+		 CB2_OUT => '0',
+		 CB2_IN => open,
+		 SIO_IN => GPIO_SIO_RXD,
+		 SIO_OUT => SIO_TXD,
+		CONSOL => CONSOL_OUT
+		 );
+
+--b2v_inst22 : entity work.scandoubler
+--PORT MAP(CLK => CLK,
+--		 RESET_N => RESET_N,
+--		 VGA => VGA,
+--		 COMPOSITE_ON_HSYNC => COMPOSITE_ON_HSYNC,
+--		 colour_enable => SCANDOUBLER_SHARED_ENABLE_LOW,
+--		 doubled_enable => SCANDOUBLER_SHARED_ENABLE_HIGH,
+--		 vsync_in => SYNTHESIZED_WIRE_12,
+--		 hsync_in => SYNTHESIZED_WIRE_13,
+--		 colour_in => SYNTHESIZED_WIRE_14,
+--		 VSYNC => VGA_VS,
+--		 HSYNC => VGA_HS,
+--		 B => VGA_B,
+--		 G => VGA_G,
+--		 R => VGA_R);
+
+
+audio_codec_config_over_i2c : entity work.i2c_loader
+GENERIC MAP(device_address => 26,
+			log2_divider => 6,
+			num_retries => 0
+			)
+PORT MAP(CLK => CLK,
+		 nRESET => RESET_N,
+		 I2C_SCL => I2C_SCLK,
+		 I2C_SDA => I2C_SDAT);
+
+audio_codec_data : entity work.i2sslave
+PORT MAP(CLK => CLK,
+		 BCLK => AUD_BCLK,
+		 DACLRC => AUD_DACLRCK,
+		 LEFT_IN => AUDIO_LEFT,
+		 RIGHT_IN => AUDIO_RIGHT,
+		 MCLK_2 => AUD_XCK,
+		 DACDAT => AUD_DACDAT);
+
+
+pll : entity work.pll
+PORT MAP(inclk0 => CLOCK_50,
+		 c0 => CLK_SDRAM,
+		 c1 => CLK,
+		 c2 => DRAM_CLK,
+		 locked => PLL_LOCKED);
+
+--gen_ntsc_pll : if tv=0 generate
+--pll : entity work.pll_ntsc
+--PORT MAP(inclk0 => CLOCK_27(0),
+--		 c0 => CLK_SDRAM,
+--		 c1 => CLK,
+--		 c2 => DRAM_CLK,
+--		 locked => PLL_LOCKED);
+--end generate;
+--
+--gen_pal_pll : if tv=1 generate
+--pll : entity work.pll_pal
+--PORT MAP(inclk0 => CLOCK_27(0),
+--		 c0 => CLK_SDRAM,
+--		 c1 => CLK,
+--		 c2 => DRAM_CLK,
+--		 locked => PLL_LOCKED);
+--end generate;
+
+RESET_N <= PLL_LOCKED;
+
+-- PS2 to pokey (just for fkeys!)
+keyboard_map1 : entity work.ps2_to_atari800
+	PORT MAP
+	( 
+		CLK => clk,
+		RESET_N => reset_n,
+		PS2_CLK => ps2_clk,
+		PS2_DAT => ps2_dat,
+		
+		KEYBOARD_SCAN => KEYBOARD_SCAN,
+		KEYBOARD_RESPONSE => open,
+
+		CONSOL_START => open,
+		CONSOL_SELECT => open,
+		CONSOL_OPTION => open,
+		
+		FKEYS => FKEYS
+	);
+
+-- SIO
+-- TODO combine
+--SIO_RXD <= UART_RXD;
+UART_TXD <= SIO_TXD;
+--GPIO_0(1) <= SIO_COMMAND;
+
+SIO_COMMAND <= 'Z'; -- no PIA...
+zpu_sio_command <= SIO_COMMAND;
+zpu_sio_rxd <= SIO_TXD;
+SIO_RXD <= zpu_sio_txd and UART_RXD;
+
+-- VIDEO
+VGA_HS <= not(VGA_HS_RAW xor VGA_VS_RAW);
+VGA_VS <= not(VGA_VS_RAW);
+
+CONSOL_IN <= "1000";
+
+atari800 : entity work.atari5200core
+	GENERIC MAP
+	(
+		cycle_length => 32,
+		video_bits => 4
+	)
+	PORT MAP
+	(
+		CLK => CLK,
+		RESET_N => RESET_N and SDRAM_RESET_N and not(reset_atari),
+
+		VIDEO_VS => VGA_VS_RAW,
+		VIDEO_HS => VGA_HS_RAW,
+		VIDEO_B => VGA_B,
+		VIDEO_G => VGA_G,
+		VIDEO_R => VGA_R,
+
+		AUDIO_L => AUDIO_LEFT,
+		AUDIO_R => AUDIO_RIGHT,
+
+		KEYBOARD_RESPONSE => KEYBOARD_RESPONSE,
+		KEYBOARD_SCAN => KEYBOARD_SCAN,
+
+		POT_IN => POT_IN,
+		POT_RESET => POT_RESET,
+		
+		PBI_ADDR => open,
+		PBI_WRITE_ENABLE => open,
+		PBI_SNOOP_DATA => open,
+		PBI_WRITE_DATA => PBI_WRITE_DATA,
+		PBI_WIDTH_8bit_ACCESS => PBI_WIDTH_8bit_ACCESS,
+		PBI_WIDTH_16bit_ACCESS => PBI_WIDTH_16bit_ACCESS,
+		PBI_WIDTH_32bit_ACCESS => PBI_WIDTH_32bit_ACCESS,
+
+		PBI_ROM_DO => "11111111",
+		PBI_REQUEST => open,
+		PBI_REQUEST_COMPLETE => '1',
+
+		SIO_RXD => SIO_RXD,
+		SIO_TXD => SIO_TXD,
+
+		CONSOL_OUT => CONSOL_OUT,
+		CONSOL_IN => CONSOL_IN,
+		GTIA_TRIG => GTIA_TRIG,
+		
+		SDRAM_REQUEST => SDRAM_REQUEST,
+		SDRAM_REQUEST_COMPLETE => SDRAM_REQUEST_COMPLETE,
+		SDRAM_READ_ENABLE => SDRAM_READ_ENABLE,
+		SDRAM_WRITE_ENABLE => SDRAM_WRITE_ENABLE,
+		SDRAM_ADDR => SDRAM_ADDR,
+		SDRAM_DO => SDRAM_DO,
+
+		ANTIC_REFRESH => SDRAM_REFRESH,
+
+		RAM_ADDR => RAM_ADDR,
+		RAM_DO => RAM_DO,
+		RAM_REQUEST => RAM_REQUEST,
+		RAM_REQUEST_COMPLETE => RAM_REQUEST_COMPLETE,
+		RAM_WRITE_ENABLE => RAM_WRITE_ENABLE,
+		
+		ROM_ADDR => ROM_ADDR,
+		ROM_DO => ROM_DO,
+		ROM_REQUEST => ROM_REQUEST,
+		ROM_REQUEST_COMPLETE => ROM_REQUEST_COMPLETE,
+
+		DMA_FETCH => dma_fetch,
+		DMA_READ_ENABLE => dma_read_enable,
+		DMA_32BIT_WRITE_ENABLE => dma_32bit_write_enable,
+		DMA_16BIT_WRITE_ENABLE => dma_16bit_write_enable,
+		DMA_8BIT_WRITE_ENABLE => dma_8bit_write_enable,
+		DMA_ADDR => dma_addr_fetch,
+		DMA_WRITE_DATA => dma_write_data,
+		MEMORY_READY_DMA => dma_memory_ready,
+		--DMA_MEMORY_DATA => dma_memory_data,  
+		PBI_SNOOP_DATA => DMA_MEMORY_DATA,
+
+		USE_SDRAM => '1', --SW(9), -- TODO
+		ROM_IN_RAM => '1',
+		HALT => pause_atari,
+		THROTTLE_COUNT_6502 => speed_6502
+	);
+
+zpu: entity work.zpucore
+	GENERIC MAP
+	(
+		platform => 1,
+		spi_clock_div => 1 -- 28MHz/2. Max for SD cards is 25MHz...
+	)
+	PORT MAP
+	(
+		-- standard...
+		CLK => CLK,
+		RESET_N => RESET_N and sdram_reset_n,
+
+		-- dma bus master (with many waitstates...)
+		ZPU_ADDR_FETCH => dma_addr_fetch,
+		ZPU_DATA_OUT => dma_write_data,
+		ZPU_FETCH => dma_fetch,
+		ZPU_32BIT_WRITE_ENABLE => dma_32bit_write_enable,
+		ZPU_16BIT_WRITE_ENABLE => dma_16bit_write_enable,
+		ZPU_8BIT_WRITE_ENABLE => dma_8bit_write_enable,
+		ZPU_READ_ENABLE => dma_read_enable,
+		ZPU_MEMORY_READY => dma_memory_ready,
+		ZPU_MEMORY_DATA => dma_memory_data, 
+
+		-- rom bus master
+		-- data on next cycle after addr
+		ZPU_ADDR_ROM => zpu_addr_rom,
+		ZPU_ROM_DATA => zpu_rom_data,
+
+		-- spi master
+		-- Too painful to bit bang spi from zpu, so we have a hardware master in here
+		ZPU_SD_DAT0 => sd_data,
+		ZPU_SD_CLK => sd_clk,
+		ZPU_SD_CMD => sd_cmd,
+		ZPU_SD_DAT3 => sd_three,
+
+		-- SIO
+		-- Ditto for speaking to Atari, we have a built in Pokey
+		ZPU_POKEY_ENABLE => zpu_pokey_enable,
+		ZPU_SIO_TXD => zpu_sio_txd,
+		ZPU_SIO_RXD => zpu_sio_rxd,
+		ZPU_SIO_COMMAND => zpu_sio_command,
+
+		-- external control
+		-- switches etc. sector DMA blah blah.
+		ZPU_IN1 => X"00000"&FKEYS,
+		ZPU_IN2 => X"00000000",
+		ZPU_IN3 => X"00000000",
+		ZPU_IN4 => X"00000000",
+
+		-- ouputs - e.g. Atari system control, halt, throttle, rom select
+		ZPU_OUT1 => zpu_out1,
+		ZPU_OUT2 => zpu_out2,
+		ZPU_OUT3 => zpu_out3,
+		ZPU_OUT4 => zpu_out4
+	);
+
+	pause_atari <= zpu_out1(0);
+	reset_atari <= zpu_out1(1);
+	speed_6502 <= zpu_out1(7 downto 2);
+
+zpu_rom1: entity work.zpu_rom
+	port map(
+	        clock => clk,
+	        address => zpu_addr_rom(13 downto 2),
+	        q => zpu_rom_data
+	);
+
+enable_179_clock_div_zpu_pokey : entity work.enable_divider
+	generic map (COUNT=>32) -- cycle_length
+	port map(clk=>clk,reset_n=>reset_n,enable_in=>'1',enable_out=>zpu_pokey_enable);
+
+END vhdl;
Index: de1_5200/build.sh
===================================================================
--- de1_5200/build.sh	(nonexistent)
+++ de1_5200/build.sh	(revision 176)
@@ -0,0 +1,69 @@
+#!/usr/bin/perl -w
+use strict;
+
+my $wanted_variant = shift @ARGV;
+
+#variants...
+my $PAL = 1;
+my $NTSC = 0;
+
+my $RGB = 1; # i.e. not scandoubled
+my $VGA = 2;
+
+#Added like this to the generated qsf
+#set_parameter -name TV 1
+
+my %variants = 
+(
+	"PAL" => 
+	{
+		"TV" => $PAL
+	},
+	"NTSC" =>
+	{
+		"TV" => $NTSC
+	}
+);
+
+if (not defined $wanted_variant or (not exists $variants{$wanted_variant} and $wanted_variant ne "ALL"))
+{
+	die "Provide variant of ALL or ".join ",",sort keys %variants;
+}
+
+foreach my $variant (sort keys %variants)
+{
+	next if ($wanted_variant ne $variant and $wanted_variant ne "ALL");
+	print "Building $variant\n";
+
+	my $dir = "build_$variant";
+	`rm -rf $dir`;
+	mkdir $dir;
+	`cp atari800core_de1.vhd $dir`;
+	`cp *pll*.* $dir`;
+	`cp *.v $dir`;
+	`cp *.vhd* $dir`;
+	`cp atari800core.sdc $dir`;
+	`mkdir $dir/common`;
+	`mkdir $dir/common/a8core`;
+	`mkdir $dir/common/components`;
+	`mkdir $dir/common/zpu`;
+	`cp ../common/a8core/* ./$dir/common/a8core`;
+	`cp ../common/components/* ./$dir/common/components`;
+	`cp ../common/zpu/* ./$dir/common/zpu`;
+
+	chdir $dir;
+	`../makeqsf ../atari800core.qsf ./common/a8core ./common/components ./common/zpu`;
+
+	foreach my $key (sort keys %{$variants{$variant}})
+	{
+		my $val = $variants{$variant}->{$key};
+		`echo set_parameter -name $key $val >> atari800core.qsf`;
+	}
+
+	`quartus_sh --flow compile atari800core > build.log 2> build.err`;
+
+	`quartus_cpf --convert ../output_file.cof`;
+	
+	chdir "..";
+}
+

Property changes on: de1_5200/build.sh
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: de1_5200/gpio.vhd
===================================================================
--- de1_5200/gpio.vhd	(nonexistent)
+++ de1_5200/gpio.vhd	(revision 176)
@@ -0,0 +1,408 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use IEEE.STD_LOGIC_MISC.all;
+
+entity gpio is
+port
+(
+	clk : in std_logic;
+	
+	gpio_enable : in std_logic;
+
+	-- pia
+	porta_in : out std_logic_vector(7 downto 0);
+	porta_out : in std_logic_vector(7 downto 0);
+	porta_output : in std_logic_vector(7 downto 0);
+	CA2_DIR_OUT : IN std_logic;
+	CA2_OUT : IN std_logic;
+	CA2_IN : OUT STD_LOGIC;
+	CB2_DIR_OUT : IN std_logic;
+	CB2_OUT : IN std_logic;
+	CB2_IN : OUT STD_LOGIC;
+	
+	-- gtia
+	trig_in : out std_logic_vector(3 downto 0);
+	
+	-- antic
+	lightpen : out std_logic;
+
+	consol : in std_logic_vector(3 downto 0);
+	
+	-- pokey
+	pot_reset : in std_logic;
+	pot_in : out std_logic_vector(7 downto 0);
+	keyboard_scan : in std_logic_vector(5 downto 0);
+	keyboard_response : out std_logic_vector(1 downto 0);
+	SIO_IN : OUT STD_LOGIC;
+	SIO_OUT : IN STD_LOGIC;
+	
+	-- cartridge
+	pbi_addr_out : in std_logic_vector(15 downto 0);
+	pbi_write_enable : in std_logic;
+	cart_data_read : out std_logic_vector(7 downto 0);
+	cart_request : in std_logic;
+	cart_complete : out std_logic;
+	cart_data_write : in std_logic_vector(7 downto 0);
+	rd4 : out std_logic;
+	rd5 : out std_logic;
+	s4_n : in std_logic;
+	s5_n : in std_logic;
+	cctl_n : in std_logic;
+	
+	-- gpio connections
+	GPIO_0_IN : in std_logic_vector(35 downto 0);
+	GPIO_0_OUT : out std_logic_vector(35 downto 0);
+	GPIO_0_DIR_OUT : out std_logic_vector(35 downto 0);
+	GPIO_1_IN : in std_logic_vector(35 downto 0);
+	GPIO_1_OUT : out std_logic_vector(35 downto 0);
+	GPIO_1_DIR_OUT : out std_logic_vector(35 downto 0)
+);
+end gpio;
+
+architecture vhdl of gpio is
+	component synchronizer IS
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RAW : IN STD_LOGIC;
+		SYNC : OUT STD_LOGIC
+	);
+	END component;
+	
+	signal pot_in_async : std_logic_vector(7 downto 0);
+	signal porta_in_async : std_logic_vector(7 downto 0);
+	signal trig_in_async : std_logic_vector(3 downto 0);
+	signal trig_in_sync : std_logic_vector(3 downto 0);
+	
+	signal read_write_n : std_logic;	
+	signal cart_data_read_async : std_logic_vector(7 downto 0);
+	signal rd4_async : std_logic;
+	signal rd5_async : std_logic;	
+	
+	signal keyboard_response_async : std_logic_vector(3 downto 0);
+	signal keyboard_response_gpio : std_logic_vector(3 downto 0);
+	signal keyboard_col : std_logic_vector(3 downto 0);
+	signal keyboard_row : std_logic_vector(3 downto 0);
+	
+	signal porta_in_gpio : std_logic_vector(7 downto 0);
+begin	
+-- OUTPUTS TO GPIO
+	-- unused
+	GPIO_1_DIR_OUT(18 downto 8) <= (others=>'0');
+	GPIO_1_OUT(18 downto 8) <= (others=>'0');
+	
+	GPIO_0_DIR_OUT(7 downto 5) <= (others=>'0');
+	GPIO_0_OUT(7 downto 5) <= (others=>'0');
+	
+	-- sio
+	GPIO_0_DIR_OUT(0) <= CA2_dir_out;
+	GPIO_0_OUT(0) <= CA2_out;
+	GPIO_0_DIR_OUT(1) <= CB2_dir_out;
+	GPIO_0_OUT(1) <= CB2_out;
+	GPIO_0_DIR_OUT(2) <= '1';
+	GPIO_0_OUT(2) <= SIO_OUT;
+	GPIO_0_DIR_OUT(3) <= '0';
+	GPIO_0_OUT(3) <= '0';
+	
+	GPIO_0_DIR_OUT(4) <= 'Z';
+	GPIO_0_OUT(4) <= '0'; -- zpu output for logic analyzer
+	
+	CA2_in <= GPIO_0_IN(0);
+	CB2_in <= GPIO_0_IN(1);
+	SIO_IN <= GPIO_0_IN(3);
+	
+	-- sticks
+	GPIO_1_OUT(35 downto 19) <= (others=>'0');
+	GPIO_1_DIR_OUT(35) <= '0'; -- trig 0
+	GPIO_1_DIR_OUT(34) <= gpio_enable and porta_output(0) and not(porta_out(0)); -- stick 0
+	GPIO_1_DIR_OUT(33) <= '0';
+	GPIO_1_DIR_OUT(32) <= gpio_enable and porta_output(1) and not(porta_out(1)); -- stick 0
+	GPIO_1_DIR_OUT(31) <= '0';
+	GPIO_1_DIR_OUT(30) <= gpio_enable and porta_output(2) and not(porta_out(2)); -- stick 0
+	GPIO_1_DIR_OUT(29) <= gpio_enable and pot_reset;
+	GPIO_1_DIR_OUT(28) <= gpio_enable and porta_output(3) and not(porta_out(3)); -- stick 0
+	GPIO_1_DIR_OUT(27) <= gpio_enable and pot_reset;
+	GPIO_1_DIR_OUT(26) <= gpio_enable and pot_reset;
+	GPIO_1_DIR_OUT(25) <= '0'; -- trig 1
+	GPIO_1_DIR_OUT(24) <= gpio_enable and porta_output(4) and not(porta_out(4)); -- stick 1
+	GPIO_1_DIR_OUT(23) <= gpio_enable and porta_output(7) and not(porta_out(7)); -- stick 1
+	GPIO_1_DIR_OUT(22) <= gpio_enable and porta_output(5) and not(porta_out(5)); -- stick 1
+	GPIO_1_DIR_OUT(21) <= gpio_enable and pot_reset;
+	GPIO_1_DIR_OUT(20) <= gpio_enable and porta_output(6) and not(porta_out(6)); -- stick 1
+	GPIO_1_DIR_OUT(19 downto 8) <= (others=>'0');
+	
+	-- keyboard
+--	GPIO_1_OUT(7 downto 0) <= (others=>'0');
+--	GPIO_1_DIR_OUT(7) <= '0'; -- keyboard response 2
+--	GPIO_1_DIR_OUT(6) <= '0'; -- keyboard response 1
+--	GPIO_1_DIR_OUT(5) <= gpio_enable and not(keyboard_scan(5)); -- keyboard scan 5
+--	GPIO_1_DIR_OUT(4) <= gpio_enable and not(keyboard_scan(4)); -- keyboard scan 4
+--	GPIO_1_DIR_OUT(3) <= gpio_enable and not(keyboard_scan(3)); -- keyboard scan 3
+--	GPIO_1_DIR_OUT(2) <= gpio_enable and not(keyboard_scan(2)); -- keyboard scan 2
+--	GPIO_1_DIR_OUT(1) <= gpio_enable and not(keyboard_scan(1)); -- keyboard scan 1
+--	GPIO_1_DIR_OUT(0) <= gpio_enable and not(keyboard_scan(0)); -- keyboard scan 0
+
+	-- lets use GPIO 0-7 for 5200 1-8
+	-- we drive 1-4 and listen to 5-8
+	GPIO_1_DIR_OUT(3 downto 0) <= (others=>'1');
+	GPIO_1_DIR_OUT(7 downto 4) <= (others=>'0');
+
+	decode_kb_col : entity work.complete_address_decoder
+		generic map(width=>2)
+		port map (addr_in=>not(keyboard_scan(2 downto 1)), addr_decoded=>keyboard_col);
+--	GPIO_1_OUT(3 downto 0) <= keyboard_col(0)&keyboard_col(3)&keyboard_col(2)&keyboard_col(1) and not(keyboard_scan(0)&keyboard_scan(0)&keyboard_scan(0)&keyboard_scan(0)) and not(keyboard_scan(5)&keyboard_scan(5)&keyboard_scan(5)&keyboard_scan(5));
+	GPIO_1_OUT(3 downto 0) <= keyboard_col(0)&keyboard_col(3)&keyboard_col(2)&keyboard_col(1);
+
+	-- cart
+	GPIO_0_DIR_OUT(35) <= '0'; -- clock - TODO
+	GPIO_0_OUT(35) <= '0'; -- clock - TODO
+	GPIO_0_DIR_OUT(34) <= gpio_enable; 
+	GPIO_0_OUT(34) <= read_write_n; 
+	GPIO_0_DIR_OUT(33) <= gpio_enable;
+	GPIO_0_OUT(33) <= pbi_addr_out(10);
+	GPIO_0_DIR_OUT(32) <= gpio_enable;
+	GPIO_0_OUT(32) <= pbi_addr_out(11);
+	GPIO_0_DIR_OUT(31) <= gpio_enable and pbi_write_enable; -- d7
+	GPIO_0_OUT(31) <= cart_data_write(7); -- d7
+	GPIO_0_DIR_OUT(30) <= gpio_enable and pbi_write_enable; -- d3
+	GPIO_0_OUT(30) <= cart_data_write(3); -- d3
+	GPIO_0_DIR_OUT(29) <= gpio_enable;
+	GPIO_0_OUT(29) <= pbi_addr_out(12);
+	GPIO_0_DIR_OUT(28) <= gpio_enable;
+	GPIO_0_OUT(28) <= pbi_addr_out(9);
+	GPIO_0_DIR_OUT(27) <= gpio_enable;
+	GPIO_0_OUT(27) <= pbi_addr_out(8);
+	GPIO_0_DIR_OUT(26) <= gpio_enable;
+	GPIO_0_OUT(26) <= pbi_addr_out(7);
+	GPIO_0_DIR_OUT(25) <= gpio_enable;
+	GPIO_0_OUT(25) <= pbi_addr_out(6);
+	GPIO_0_DIR_OUT(24) <= gpio_enable;
+	GPIO_0_OUT(24) <= pbi_addr_out(5);
+	GPIO_0_DIR_OUT(23) <= gpio_enable;
+	GPIO_0_OUT(23) <= pbi_addr_out(4);
+	GPIO_0_DIR_OUT(22) <= '0'; -- RD4 rom present
+	GPIO_0_OUT(22) <= '0'; -- RD4 rom present
+	GPIO_0_DIR_OUT(21) <= gpio_enable;
+	GPIO_0_OUT(21) <= S4_n;
+	GPIO_0_DIR_OUT(20) <= gpio_enable;
+	GPIO_0_OUT(20) <= pbi_addr_out(3);
+	GPIO_0_DIR_OUT(19) <= gpio_enable;
+	GPIO_0_OUT(19) <= pbi_addr_out(2);
+	GPIO_0_DIR_OUT(18) <= gpio_enable;
+	GPIO_0_OUT(18) <= pbi_addr_out(1);
+	GPIO_0_DIR_OUT(17) <= gpio_enable;
+	GPIO_0_OUT(17) <= pbi_addr_out(0);
+	GPIO_0_DIR_OUT(16) <= gpio_enable and pbi_write_enable; -- d4
+	GPIO_0_OUT(16) <= cart_data_write(4); -- d4
+	GPIO_0_DIR_OUT(15) <= gpio_enable and pbi_write_enable; -- d5
+	GPIO_0_OUT(15) <= cart_data_write(5); -- d5
+	GPIO_0_DIR_OUT(14) <= gpio_enable and pbi_write_enable; -- d2
+	GPIO_0_OUT(14) <= cart_data_write(2); -- d2
+	GPIO_0_DIR_OUT(13) <= gpio_enable and pbi_write_enable; -- d1
+	GPIO_0_OUT(13) <= cart_data_write(1); -- d1
+	GPIO_0_DIR_OUT(12) <= gpio_enable and pbi_write_enable; -- d0
+	GPIO_0_OUT(12) <= cart_data_write(0); -- d0
+	GPIO_0_DIR_OUT(11) <= gpio_enable and pbi_write_enable; -- d6
+	GPIO_0_OUT(11) <= cart_data_write(6); -- d6
+	GPIO_0_DIR_OUT(10) <= gpio_enable;
+	GPIO_0_OUT(10) <= S5_n;
+	GPIO_0_DIR_OUT(9) <= '0'; -- RD5 rom present
+	GPIO_0_OUT(9) <= '0'; -- RD5 rom present
+	GPIO_0_DIR_OUT(8) <= gpio_enable; -- cart control
+	GPIO_0_OUT(8) <= CCTL_n; -- cart control
+	GPIO_0_DIR_OUT(7 downto 5) <= (others=>'0'); -- unused
+	GPIO_0_OUT(7 downto 5) <= (others=>'0'); -- unused	
+	
+-- INPUTS FROM GPIO	
+	-- sticks
+	pot_in_async <= 
+					consol(2)&consol(2)&consol(2)&consol(2)&consol(2)&consol(2)&consol(2)&consol(2) and gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable and 
+					("0000"&
+					GPIO_1_IN(27)&GPIO_1_IN(21)& -- 32/24
+					GPIO_1_IN(26)&GPIO_1_IN(29)); -- 31/34
+	pot_in0_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(0), sync=>pot_in(0));						
+	pot_in1_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(1), sync=>pot_in(1));						
+	pot_in2_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(2), sync=>pot_in(2));						
+	pot_in3_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(3), sync=>pot_in(3));							
+	pot_in4_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(4), sync=>pot_in(4));						
+	pot_in5_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(5), sync=>pot_in(5));						
+	pot_in6_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(6), sync=>pot_in(6));						
+	pot_in7_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(7), sync=>pot_in(7));								
+		
+--	porta_in_async <= 
+--					not(gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable) or 
+--					GPIO_1_IN(23)&GPIO_1_IN(20)&GPIO_1_IN(22)&GPIO_1_IN(24)& -- 27/25/23/26
+--					GPIO_1_IN(28)&GPIO_1_IN(30)&GPIO_1_IN(32)&GPIO_1_IN(34); -- 39/37/35/33
+	porta_in_async <= 
+					GPIO_1_IN(23)&GPIO_1_IN(20)&GPIO_1_IN(22)&GPIO_1_IN(24)& -- 27/25/23/26
+					GPIO_1_IN(28)&GPIO_1_IN(30)&GPIO_1_IN(32)&GPIO_1_IN(34); -- 39/37/35/33					
+	porta_in0_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(0), sync=>porta_in_gpio(0));						
+	porta_in1_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(1), sync=>porta_in_gpio(1));						
+	porta_in2_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(2), sync=>porta_in_gpio(2));						
+	porta_in3_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(3), sync=>porta_in_gpio(3));						
+	porta_in4_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(4), sync=>porta_in_gpio(4));						
+	porta_in5_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(5), sync=>porta_in_gpio(5));						
+	porta_in6_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(6), sync=>porta_in_gpio(6));						
+	porta_in7_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(7), sync=>porta_in_gpio(7));
+		
+	porta_in(7 downto 4) <= porta_in_gpio(7 downto 4);
+	porta_in(3 downto 0) <= porta_in_gpio(3 downto 0);
+		
+	trig_in_async <= (not(gpio_enable&gpio_enable&"11") or (rd5_async&"1"&GPIO_1_IN(25)&GPIO_1_IN(35)));	-- 28/40
+	trig_in0_synchronizer : synchronizer
+		port map (clk=>clk, raw=>trig_in_async(0), sync=>trig_in_sync(0));							
+	trig_in1_synchronizer : synchronizer
+		port map (clk=>clk, raw=>trig_in_async(1), sync=>trig_in_sync(1));							
+	trig_in2_synchronizer : synchronizer
+		port map (clk=>clk, raw=>trig_in_async(2), sync=>trig_in_sync(2));							
+	trig_in3_synchronizer : synchronizer
+		port map (clk=>clk, raw=>trig_in_async(3), sync=>trig_in_sync(3));		
+
+	trig_in <= trig_in_sync;
+		
+	lightpen <= trig_in_sync(0) and trig_in_sync(1); -- either joystick button				
+	
+	-- keyboard
+	keyboard_response_async <= GPIO_1_IN(7 downto 4);
+	keyboard_response1_synchronizer : synchronizer
+		port map (clk=>clk, raw=>keyboard_response_async(0), sync=>keyboard_response_gpio(0));						
+	keyboard_response2_synchronizer : synchronizer
+		port map (clk=>clk, raw=>keyboard_response_async(1), sync=>keyboard_response_gpio(1));			
+	keyboard_response3_synchronizer : synchronizer
+		port map (clk=>clk, raw=>keyboard_response_async(2), sync=>keyboard_response_gpio(2));			
+	keyboard_response4_synchronizer : synchronizer
+		port map (clk=>clk, raw=>keyboard_response_async(3), sync=>keyboard_response_gpio(3));			
+		
+	decode_kb_row : entity work.complete_address_decoder
+		generic map(width=>2)
+		port map (addr_in=>not(keyboard_scan(4 downto 3)), addr_decoded=>keyboard_row);
+
+	--keyboard_response <= keyboard_response_gpio;
+	--keyboard_response(1) <= porta_in_gpio(0) when consol(1 downto 0)="00" else '1';
+	--keyboard_response(0) <= not(or_reduce(keyboard_row(2 downto 0)&keyboard_row(3) and keyboard_response_gpio)) when consol(1 downto 0)="00" else '1'; -- if we see a 1 on the selected line
+	keyboard_response(1) <= porta_in_gpio(0) when consol(1 downto 0)="00" else '1';
+	keyboard_response(0) <= not(or_reduce(keyboard_row(0)&keyboard_row(3)&keyboard_row(2)&keyboard_row(1) and keyboard_response_gpio))  when consol(1 downto 0)="00" else '1';
+	
+	-- cartridge
+--	 1(21). S4' Chip Select--$8000 to $9FFF  A(22). RD4 ROM present--$8000 to $9FFF
+-- 2(20). A3 CPU Address bus line          B(GND). GND Ground
+-- 3(19). A2 CPU Address bus line          C(23). A4 CPU Address bus line
+-- 4(18). A1 CPU Address bus line          D(24). A5 CPU Address bus line
+-- 5(17). A0 CPU Address bus line          E(25). A6 CPU Address bus line
+-- 6(16). D4 CPU Data bus line             F(26). A7 CPU Address bus line
+-- 7(15). D5 CPU Data bus line             H(27). A8 CPU Address bus line
+-- 8(14). D2 CPU Data bus line             J(28). A9 CPU Address bus line
+-- 9(13). D1 CPU Data bus line             K(29). A12 CPU Address bus line
+--10(12). D0 CPU Data bus line             L(30). D3 CPU Data bus line
+--11(11). D6 CPU Data bus line             M(31). D7 CPU Data bus line
+--12(10). S5' Chip Select--$A000 to $BFFF  N(32). A11 CPU Address bus line
+--13(5V). +5V                              P(33). A10 CPU Address bus line
+--14(9). RD5 ROM present--$A000 to $BFFF  R(34). R/W' CPU read/write
+--15(8). CCTL' Cartridge control select   S(35). B02,Phi2 CPU Phase 2 clock
+
+	-- S4'/S5' - chip select
+	-- CTTL' - control select
+	-- R/W'
+	-- clock (not needed for rom?)
+	-- RD5 ROM present (in)
+	-- RD4 ROM present (in)
+	
+	read_write_n <= not(pbi_write_enable);
+	
+	cart_complete <= cart_request; -- TODO!
+	
+	rd4_async <= gpio_enable and GPIO_0_IN(22);
+	cart_rd4_synchronizer : synchronizer
+		port map (clk=>clk, raw=>rd4_async, sync=>rd4);							
+	rd5_async <= gpio_enable and GPIO_0_IN(9);
+	cart_rd5_synchronizer : synchronizer
+		port map (clk=>clk, raw=>rd5_async, sync=>rd5);							
+	
+	cart_data_read_async <= GPIO_0_IN(31)&GPIO_0_IN(11)&GPIO_0_IN(15)&GPIO_0_IN(16)&GPIO_0_IN(30)&GPIO_0_IN(14)&GPIO_0_IN(13)&GPIO_0_IN(12);	
+	cart_data0_synchronizer : synchronizer
+		port map (clk=>clk, raw=>cart_data_read_async(0), sync=>cart_data_read(0));							
+	cart_data1_synchronizer : synchronizer
+		port map (clk=>clk, raw=>cart_data_read_async(1), sync=>cart_data_read(1));							
+	cart_data2_synchronizer : synchronizer
+		port map (clk=>clk, raw=>cart_data_read_async(2), sync=>cart_data_read(2));							
+	cart_data3_synchronizer : synchronizer
+		port map (clk=>clk, raw=>cart_data_read_async(3), sync=>cart_data_read(3));	
+	cart_data4_synchronizer : synchronizer
+		port map (clk=>clk, raw=>cart_data_read_async(4), sync=>cart_data_read(4));							
+	cart_data5_synchronizer : synchronizer
+		port map (clk=>clk, raw=>cart_data_read_async(5), sync=>cart_data_read(5));							
+	cart_data6_synchronizer : synchronizer
+		port map (clk=>clk, raw=>cart_data_read_async(6), sync=>cart_data_read(6));							
+	cart_data7_synchronizer : synchronizer
+		port map (clk=>clk, raw=>cart_data_read_async(7), sync=>cart_data_read(7));
+		
+	--GPIO_1(25) <= GPIO_1(29);
+	
+--40	35
+--39	34
+--38	33
+--37	32
+--36	31
+--35	30
+--34	29
+--33	28
+--32	27
+--31	26
+--30	GND
+--29	3.3V
+--28	25
+--27	24
+--26	23
+--25	22
+--24	21
+--23	20
+--22	19
+--21	18
+--20	17
+--19	16
+--18	15
+--17	14
+--16	13
+--15	12
+--14	11
+--13	10
+--12	GND
+--11	5V
+--10	9
+--9	8
+--8	7
+--7	6
+--6	5
+--5	4
+--4	3
+--3	2
+--2	1
+--1	0
+
+end vhdl;
+
+
Index: de1_5200/hexdecoder.vhd
===================================================================
--- de1_5200/hexdecoder.vhd	(nonexistent)
+++ de1_5200/hexdecoder.vhd	(revision 176)
@@ -0,0 +1,75 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+ENTITY hexdecoder IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	NUMBER : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+	DIGIT : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
+);
+END hexdecoder;
+
+ARCHITECTURE vhdl OF hexdecoder IS
+	signal numinv : STD_LOGIC_VECTOR(3 downto 0);
+	signal digit_next : std_logic_vector(6 downto 0);
+	signal digit_reg : STD_LOGIC_VECTOR(6 DOWNTO 0);
+BEGIN
+	--numinv <= not(NUMBER);
+	numinv <= NUMBER;
+	process(numinv)
+	begin
+		case numinv is
+			when "0000" =>
+				digit_next <= "1111111";
+			when "0001" =>
+				digit_next <= "1111001";
+			when "0010" =>
+				digit_next <= "0100100";
+			when "0011" =>
+				digit_next <= "0110000";
+			when "0100" =>
+				digit_next <= "0011001";
+			when "0101" =>
+				digit_next <= "0010010";
+			when "0110" =>
+				digit_next <= "0000010";
+			when "0111" =>
+				digit_next <= "1111000";
+			when "1000" =>
+				digit_next <= "0000000";
+			when "1001" =>
+				digit_next <= "0011000";
+			when "1010" =>
+				digit_next <= "0001000";
+			when "1011" =>
+				digit_next <= "0000011";
+			when "1100" =>
+				digit_next <= "1000110";
+			when "1101" =>
+				digit_next <= "0100001";
+			when "1110" =>
+				digit_next <= "0000110";
+			when "1111" =>
+				digit_next <= "0001110";
+			when others =>
+				digit_next <= "1111111";
+		end case;
+	end process;
+	
+	process(clk)
+	begin
+		if (clk'event and clk='1') then
+			digit_reg <= digit_next;
+		end if;
+	end process;
+	
+	digit<=digit_reg;
+END vhdl;
\ No newline at end of file
Index: de1_5200/i2c_loader.vhd
===================================================================
--- de1_5200/i2c_loader.vhd	(nonexistent)
+++ de1_5200/i2c_loader.vhd	(revision 176)
@@ -0,0 +1,302 @@
+-- ZX Spectrum for Altera DE1
+--
+-- Copyright (c) 2009-2010 Mike Stirling
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- * Redistributions of source code must retain the above copyright notice,
+--   this list of conditions and the following disclaimer.
+--
+-- * Redistributions in synthesized form must reproduce the above copyright
+--   notice, this list of conditions and the following disclaimer in the
+--   documentation and/or other materials provided with the distribution.
+--
+-- * Neither the name of the author nor the names of other contributors may
+--   be used to endorse or promote products derived from this software without
+--   specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use IEEE.STD_LOGIC_MISC.ALL; -- for AND_REDUCE
+use IEEE.NUMERIC_STD.ALL;
+
+entity i2c_loader is
+generic (
+	-- Address of slave to be loaded
+	device_address : integer := 16#1a#;
+	-- Number of retries to allow before stopping
+	num_retries : integer := 0;
+	-- Length of clock divider in bits.  Resulting bus frequency is
+	-- CLK/2^(log2_divider + 2)
+	log2_divider : integer := 7
+);
+
+port (
+	CLK			:	in	std_logic;
+	nRESET		:	in	std_logic;
+	
+	I2C_SCL		:	inout	std_logic;
+	I2C_SDA		:	inout	std_logic;
+	
+	IS_DONE		:	out std_logic;
+	IS_ERROR	:	out	std_logic
+	);
+end i2c_loader;
+
+architecture i2c_loader_arch of i2c_loader is
+type regs is array(0 to 19) of std_logic_vector(7 downto 0);
+constant init_regs : regs := (
+	-- Left line in, 0dB, mute
+	X"00", X"97",
+	-- Right line in, 0dB, mute
+	X"02", X"97",
+	-- Left headphone out, -29dB, zero cross disabled
+	--X"04", X"58",
+	X"04", X"68",
+	-- Right headphone out, -29dB, zero cross disabled
+	--X"06", X"58",
+	X"06", X"68",
+	-- Audio path, DAC enabled, Line in, Bypass off, mic muted
+	X"08", X"12",
+	-- Digital path, Unmute, HP filter enabled
+	X"0A", X"00",
+	-- Power down mic, clkout and xtal osc, line in and adc
+	X"0C", X"67",
+	-- Format 16-bit I2S, no bit inversion or phase changes, MASTER
+	X"0E", X"42",
+	-- Sampling control, Normal mode, mclk/2 used, We should provide 12.288MHz but will provide 12.25MHz - making 96KHz notional, 97.656KHz actual 
+	X"10", X"DC",
+	-- Activate
+	X"12", X"01"
+	);
+-- Number of bursts (i.e. total number of registers)
+constant burst_length : positive := 2;
+-- Number of bytes to transfer per burst
+constant num_bursts : positive := (init_regs'length / burst_length);
+	
+type state_t is (Idle, Start, Data, Ack, Stop, Pause, Done);
+signal state : state_t;
+signal phase : std_logic_vector(1 downto 0);
+subtype nbit_t is integer range 0 to 7;
+signal nbit : nbit_t;
+subtype nbyte_t is integer range 0 to burst_length; -- +1 for address byte
+signal nbyte : nbyte_t;
+subtype thisbyte_t is integer range 0 to init_regs'length; -- +1 for "done"
+signal thisbyte : thisbyte_t;
+subtype retries_t is integer range 0 to num_retries;
+signal retries : retries_t;
+
+signal clken : std_logic;
+signal divider : std_logic_vector(log2_divider-1 downto 0);
+signal shiftreg : std_logic_vector(7 downto 0);
+signal scl_out : std_logic;
+signal sda_out : std_logic;
+signal nak : std_logic;
+begin
+	-- Create open-drain outputs for I2C bus
+	I2C_SCL <= '0' when scl_out = '0' else 'Z';
+	I2C_SDA <= '0' when sda_out = '0' else 'Z';
+	-- Status outputs are driven both ways
+	IS_DONE <= '1' when state = Done else '0';
+	IS_ERROR <= nak;
+	
+	-- Generate clock enable for desired bus speed
+	clken <= AND_REDUCE(divider);
+	process(nRESET,CLK)
+	begin
+		if nRESET = '0' then
+			divider <= (others => '0');
+		elsif falling_edge(CLK) then
+			divider <= divider + '1';
+		end if;
+	end process;
+
+	-- The I2C loader process
+	process(nRESET,CLK,clken)
+	begin
+		if nRESET = '0' then
+			scl_out <= '1';
+			sda_out <= '1';
+			state <= Idle;
+			phase <= "00";
+			nbit <= 0;
+			nbyte <= 0;
+			thisbyte <= 0;
+			shiftreg <= (others => '0');
+			nak <= '0'; -- No error
+			retries <= num_retries;
+		elsif rising_edge(CLK) and clken = '1' then
+  			-- Next phase by default
+			phase <= phase + 1;
+
+			-- STATE: IDLE
+			if state = Idle then
+				-- Start loading the device registers straight away
+				-- A 'GO' bit could be polled here if required
+				state <= Start;
+				phase <= "00";
+				scl_out <= '1';
+				sda_out <= '1';
+				
+			-- STATE: START
+			elsif state = Start then
+				-- Generate START condition
+				case phase is
+				when "00" =>
+					-- Drop SDA first
+					sda_out <= '0';
+				when "10" =>
+					-- Then drop SCL
+					scl_out <= '0';
+				when "11" =>
+					-- Advance to next state
+					-- Shift register loaded with device slave address
+					state <= Data;
+					nbit <= 7;
+					shiftreg <= std_logic_vector(to_unsigned(device_address,7)) & '0'; -- writing
+					nbyte <= burst_length;
+				when others =>
+					null;
+				end case;
+				
+			-- STATE: DATA
+			elsif state = Data then
+				-- Generate data
+				case phase is
+				when "00" =>
+					-- Drop SCL
+					scl_out <= '0';
+				when "01" =>
+					-- Output data and shift (MSb first)
+					sda_out <= shiftreg(7);
+					shiftreg <= shiftreg(6 downto 0) & '0';
+				when "10" =>
+					-- Raise SCL
+					scl_out <= '1';
+				when "11" =>
+					-- Next bit or advance to next state when done
+					if nbit = 0 then
+						state <= Ack;
+					else
+						nbit <= nbit - 1;
+					end if;
+				when others =>
+				  null;
+				end case;
+				
+			-- STATE: ACK
+			elsif state = Ack then
+				-- Generate ACK clock and check for error condition
+				case phase is
+				when "00" =>
+					-- Drop SCL
+					scl_out <= '0';
+				when "01" =>
+					-- Float data
+					sda_out <= '1';
+				when "10" =>
+					-- Sample ack bit
+					nak <= I2C_SDA;
+					if I2C_SDA = '1' then
+						-- Error
+						nbyte <= 0; -- Close this burst and skip remaining registers
+						thisbyte <= init_regs'length;
+					else
+						-- Hold ACK to avoid spurious stops - this seems to fix a
+						-- problem with the Wolfson codec which releases the ACK
+						-- right on the falling edge of the clock pulse.  It looks like
+						-- the device interprets this is a STOP condition and then fails
+						-- to acknowledge the next byte.  We can avoid this by holding the
+						-- ACK condition for a little longer.
+						sda_out <= '0';
+					end if;
+					-- Raise SCL
+					scl_out <= '1';
+				when "11" =>
+					-- Advance to next state
+					if nbyte = 0 then
+						-- No more bytes in this burst - generate a STOP
+						state <= Stop;
+					else
+						-- Generate next byte
+						state <= Data;
+						nbit <= 7;
+						shiftreg <= init_regs(thisbyte);
+						nbyte <= nbyte - 1;
+						thisbyte <= thisbyte + 1;
+					end if;
+				when others =>
+					null;
+				end case;
+				
+			-- STATE: STOP
+			elsif state = Stop then
+				-- Generate STOP condition
+				case phase is
+				when "00" =>
+					-- Drop SCL first
+					scl_out <= '0';
+				when "01" =>
+					-- Drop SDA
+					sda_out <= '0';
+				when "10" =>
+					-- Raise SCL
+					scl_out <= '1';
+				when "11" =>
+					if thisbyte = init_regs'length then
+						-- All registers done, advance to finished state.  This will
+						-- bring SDA high while SCL is still high, completing the STOP
+						-- condition
+						state <= Done;
+					else
+						-- Load the next register after a short delay
+						state <= Pause;
+					end if;
+				when others =>
+					null;
+				end case;
+				
+			-- STATE: PAUSE
+			elsif state = Pause then
+				-- Delay for one cycle of 'phase' then start the next burst
+				scl_out <= '1';
+				sda_out <= '1';
+				if phase = "11" then
+					state <= Start;
+				end if;
+				
+			-- STATE: DONE
+			else
+				-- Finished
+				scl_out <= '1';
+				sda_out <= '1';
+				
+				if nak = '1' and retries > 0 then
+					-- We can retry in the event of a NAK in case the
+					-- slave got out of sync for some reason
+					retries <= retries - 1;
+					state <= Idle;
+				end if;
+			end if;
+		end if;
+	end process;
+end i2c_loader_arch;
+
Index: de1_5200/i2sslave.vhdl
===================================================================
--- de1_5200/i2sslave.vhdl	(nonexistent)
+++ de1_5200/i2sslave.vhdl	(revision 176)
@@ -0,0 +1,86 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+ENTITY i2sslave IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	
+	BCLK : IN STD_LOGIC;
+	DACLRC : IN STD_LOGIC;
+	
+	LEFT_IN : in std_logic_vector(15 downto 0);
+	RIGHT_IN : in std_logic_vector(15 downto 0);
+	
+	MCLK_2 : OUT STD_LOGIC;
+	DACDAT : OUT STD_LOGIC
+);
+END i2sslave;
+
+ARCHITECTURE vhdl OF i2sslave IS
+	signal bclk_reg : std_logic;
+	signal bclk_last_reg : std_logic;
+	signal daclrc_reg : std_logic;
+	signal daclrc_last_reg : std_logic;
+	
+	signal shiftreg_reg : std_logic_vector(15 downto 0);
+	signal shiftreg_next : std_logic_vector(15 downto 0);
+	
+	signal CLK_FAKE : std_logic;
+BEGIN
+	MCLK_2 <= CLK_FAKE; -- bad practice, but pll out of...
+	
+	-- Data read on bclk low->high transition
+	-- daclrc is set on bclk high->low transition
+	
+	-- register inputs
+	process(clk)
+	begin
+		if (clk'event and clk='1') then
+			CLK_FAKE <= not(CLK_FAKE);
+		end if;
+	end process;
+	
+	process(CLK_FAKE)
+	begin	
+		if (CLK_FAKE'event and CLK_FAKE='1') then
+			bclk_reg <= bclk;
+			bclk_last_reg <= bclk_reg;
+			daclrc_reg <= daclrc;
+			daclrc_last_reg <= daclrc_reg;
+			shiftreg_reg <= shiftreg_next;
+		end if;
+	end process;
+	
+	-- sample on change to daclrc, shift out bit if required
+	process(daclrc_reg,daclrc_last_reg,bclk_reg,shiftreg_reg,left_in,right_in,bclk_last_reg)
+		variable reload : std_logic;
+	begin
+		reload := '0';
+		shiftreg_next <= shiftreg_reg;
+		
+		if (daclrc_reg = '1' and daclrc_last_reg = '0') then
+			shiftreg_next <= right_in;
+			reload := '1';
+		end if;
+		
+		if (daclrc_reg = '0' and daclrc_last_reg = '1') then
+			shiftreg_next <= left_in;
+			reload := '1';
+		end if;
+		
+		if (bclk_reg = '0' and bclk_last_reg = '1' and reload='0') then
+				shiftreg_next <= shiftreg_reg(14 downto 0)&'0';
+		end if;
+			
+	end process;
+	
+	DACDAT <= shiftreg_reg(15);
+END vhdl;
\ No newline at end of file
Index: de1_5200/makeqsf
===================================================================
--- de1_5200/makeqsf	(nonexistent)
+++ de1_5200/makeqsf	(revision 176)
@@ -0,0 +1,33 @@
+#!/usr/bin/perl -w
+use strict;
+
+my $qsf_in = shift @ARGV;
+my $qsf_out = $qsf_in;
+$qsf_out =~ s/.*\///;
+
+open (QSF_IN,$qsf_in) or die "Failed to open $qsf_in";
+my @qsf_base = <QSF_IN>;
+close (QSF_IN);
+
+open (QSF_OUT,">$qsf_out") or die "Failed to open $qsf_out";
+print QSF_OUT @qsf_base;
+
+foreach (@ARGV)
+{
+	my @vhdl = glob ("$_/*.vhd");
+	push @vhdl, glob ("$_/*.vhdl");
+	my @verilog = glob ("$_/*.v");
+
+	foreach (@verilog)
+	{
+		print QSF_OUT "set_global_assignment -name VERILOG_FILE $_\n";
+	}
+
+	foreach (@vhdl)
+	{
+		print QSF_OUT "set_global_assignment -name VHDL_FILE $_\n";
+	}
+}
+
+close (QSF_OUT);
+

Property changes on: de1_5200/makeqsf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: de1_5200/pll.cmp
===================================================================
--- de1_5200/pll.cmp	(nonexistent)
+++ de1_5200/pll.cmp	(revision 176)
@@ -0,0 +1,25 @@
+--Copyright (C) 1991-2012 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component pll
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+end component;
Index: de1_5200/pll.ppf
===================================================================
--- de1_5200/pll.ppf	(nonexistent)
+++ de1_5200/pll.ppf	(revision 176)
@@ -0,0 +1,12 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone II" variation_name="pll" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="c1" direction="output" scope="external" source="clock"  />
+<pin name="c2" direction="output" scope="external" source="clock"  />
+<pin name="locked" direction="output" scope="external"  />
+
+</global>
+</pinplan>
Index: de1_5200/pll.qip
===================================================================
--- de1_5200/pll.qip	(nonexistent)
+++ de1_5200/pll.qip	(revision 176)
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "12.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
Index: de1_5200/pll.vhd
===================================================================
--- de1_5200/pll.vhd	(nonexistent)
+++ de1_5200/pll.vhd	(revision 176)
@@ -0,0 +1,427 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: pll.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 12.1 Build 243 01/31/2013 SP 1.33 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2012 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pll IS
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+END pll;
+
+
+ARCHITECTURE SYN OF pll IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (5 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC ;
+	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire7_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		clk2_divide_by		: NATURAL;
+		clk2_duty_cycle		: NATURAL;
+		clk2_multiply_by		: NATURAL;
+		clk2_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		gate_lock_counter		: NATURAL;
+		gate_lock_signal		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		invalid_lock_multiplier		: NATURAL;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		valid_lock_multiplier		: NATURAL
+	);
+	PORT (
+			clk	: OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+			locked	: OUT STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire7_bv(0 DOWNTO 0) <= "0";
+	sub_wire7    <= To_stdlogicvector(sub_wire7_bv);
+	sub_wire4    <= sub_wire0(2);
+	sub_wire3    <= sub_wire0(0);
+	sub_wire1    <= sub_wire0(1);
+	c1    <= sub_wire1;
+	locked    <= sub_wire2;
+	c0    <= sub_wire3;
+	c2    <= sub_wire4;
+	sub_wire5    <= inclk0;
+	sub_wire6    <= sub_wire7(0 DOWNTO 0) & sub_wire5;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		clk0_divide_by => 10,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 23,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 20,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 23,
+		clk1_phase_shift => "0",
+		clk2_divide_by => 10,
+		clk2_duty_cycle => 50,
+		clk2_multiply_by => 23,
+		clk2_phase_shift => "-1280",
+		compensate_clock => "CLK0",
+		gate_lock_counter => 1048575,
+		gate_lock_signal => "YES",
+		inclk0_input_frequency => 20000,
+		intended_device_family => "Cyclone II",
+		invalid_lock_multiplier => 5,
+		lpm_hint => "CBX_MODULE_PREFIX=pll",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_UNUSED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_USED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_USED",
+		port_clk3 => "PORT_UNUSED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		valid_lock_multiplier => 1
+	)
+	PORT MAP (
+		inclk => sub_wire6,
+		clk => sub_wire0,
+		locked => sub_wire2
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "10"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "20"
+-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "10"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "115.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "57.500000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "115.000000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "1"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "23"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "23"
+-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "23"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "28.70000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "28.70000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "-1.28000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ns"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "10"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "23"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "20"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "23"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "10"
+-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "23"
+-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "-1280"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: GATE_LOCK_COUNTER NUMERIC "1048575"
+-- Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "YES"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
+-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
+-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
Index: de1_5200/pll_ntsc.cmp
===================================================================
--- de1_5200/pll_ntsc.cmp	(nonexistent)
+++ de1_5200/pll_ntsc.cmp	(revision 176)
@@ -0,0 +1,25 @@
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component pll_ntsc
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+end component;
Index: de1_5200/pll_ntsc.ppf
===================================================================
--- de1_5200/pll_ntsc.ppf	(nonexistent)
+++ de1_5200/pll_ntsc.ppf	(revision 176)
@@ -0,0 +1,12 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone II" variation_name="pll_ntsc" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="c1" direction="output" scope="external" source="clock"  />
+<pin name="c2" direction="output" scope="external" source="clock"  />
+<pin name="locked" direction="output" scope="external"  />
+
+</global>
+</pinplan>
Index: de1_5200/pll_ntsc.qip
===================================================================
--- de1_5200/pll_ntsc.qip	(nonexistent)
+++ de1_5200/pll_ntsc.qip	(revision 176)
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.0"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll_ntsc.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_ntsc.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_ntsc.ppf"]
Index: de1_5200/pll_ntsc.vhd
===================================================================
--- de1_5200/pll_ntsc.vhd	(nonexistent)
+++ de1_5200/pll_ntsc.vhd	(revision 176)
@@ -0,0 +1,427 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: pll_ntsc.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pll_ntsc IS
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+END pll_ntsc;
+
+
+ARCHITECTURE SYN OF pll_ntsc IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (5 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC ;
+	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire7_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		clk2_divide_by		: NATURAL;
+		clk2_duty_cycle		: NATURAL;
+		clk2_multiply_by		: NATURAL;
+		clk2_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		gate_lock_counter		: NATURAL;
+		gate_lock_signal		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		invalid_lock_multiplier		: NATURAL;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		valid_lock_multiplier		: NATURAL
+	);
+	PORT (
+			clk	: OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+			locked	: OUT STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire7_bv(0 DOWNTO 0) <= "0";
+	sub_wire7    <= To_stdlogicvector(sub_wire7_bv);
+	sub_wire4    <= sub_wire0(2);
+	sub_wire3    <= sub_wire0(0);
+	sub_wire1    <= sub_wire0(1);
+	c1    <= sub_wire1;
+	locked    <= sub_wire2;
+	c0    <= sub_wire3;
+	c2    <= sub_wire4;
+	sub_wire5    <= inclk0;
+	sub_wire6    <= sub_wire7(0 DOWNTO 0) & sub_wire5;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		clk0_divide_by => 4,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 17,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 8,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 17,
+		clk1_phase_shift => "0",
+		clk2_divide_by => 4,
+		clk2_duty_cycle => 50,
+		clk2_multiply_by => 17,
+		clk2_phase_shift => "-1280",
+		compensate_clock => "CLK0",
+		gate_lock_counter => 1048575,
+		gate_lock_signal => "YES",
+		inclk0_input_frequency => 37037,
+		intended_device_family => "Cyclone II",
+		invalid_lock_multiplier => 5,
+		lpm_hint => "CBX_MODULE_PREFIX=pll_ntsc",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_UNUSED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_USED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_USED",
+		port_clk3 => "PORT_UNUSED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		valid_lock_multiplier => 1
+	)
+	PORT MAP (
+		inclk => sub_wire6,
+		clk => sub_wire0,
+		locked => sub_wire2
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "4"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "4"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "114.750000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "57.375000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "114.750000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "1"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "17"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "17"
+-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "17"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "28.70000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "28.70000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "-1.28000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ns"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "4"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "17"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "8"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "17"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "4"
+-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "17"
+-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "-1280"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: GATE_LOCK_COUNTER NUMERIC "1048575"
+-- Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "YES"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
+-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
+-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_ntsc.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_ntsc.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_ntsc.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_ntsc.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_ntsc.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_ntsc_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
Index: de1_5200/pll_pal.cmp
===================================================================
--- de1_5200/pll_pal.cmp	(nonexistent)
+++ de1_5200/pll_pal.cmp	(revision 176)
@@ -0,0 +1,25 @@
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component pll_pal
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+end component;
Index: de1_5200/pll_pal.ppf
===================================================================
--- de1_5200/pll_pal.ppf	(nonexistent)
+++ de1_5200/pll_pal.ppf	(revision 176)
@@ -0,0 +1,12 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone II" variation_name="pll_pal" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="c1" direction="output" scope="external" source="clock"  />
+<pin name="c2" direction="output" scope="external" source="clock"  />
+<pin name="locked" direction="output" scope="external"  />
+
+</global>
+</pinplan>
Index: de1_5200/pll_pal.qip
===================================================================
--- de1_5200/pll_pal.qip	(nonexistent)
+++ de1_5200/pll_pal.qip	(revision 176)
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.0"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll_pal.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_pal.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_pal.ppf"]
Index: de1_5200/pll_pal.vhd
===================================================================
--- de1_5200/pll_pal.vhd	(nonexistent)
+++ de1_5200/pll_pal.vhd	(revision 176)
@@ -0,0 +1,427 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: pll_pal.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pll_pal IS
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+END pll_pal;
+
+
+ARCHITECTURE SYN OF pll_pal IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (5 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC ;
+	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire7_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		clk2_divide_by		: NATURAL;
+		clk2_duty_cycle		: NATURAL;
+		clk2_multiply_by		: NATURAL;
+		clk2_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		gate_lock_counter		: NATURAL;
+		gate_lock_signal		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		invalid_lock_multiplier		: NATURAL;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		valid_lock_multiplier		: NATURAL
+	);
+	PORT (
+			clk	: OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+			locked	: OUT STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire7_bv(0 DOWNTO 0) <= "0";
+	sub_wire7    <= To_stdlogicvector(sub_wire7_bv);
+	sub_wire4    <= sub_wire0(2);
+	sub_wire3    <= sub_wire0(0);
+	sub_wire1    <= sub_wire0(1);
+	c1    <= sub_wire1;
+	locked    <= sub_wire2;
+	c0    <= sub_wire3;
+	c2    <= sub_wire4;
+	sub_wire5    <= inclk0;
+	sub_wire6    <= sub_wire7(0 DOWNTO 0) & sub_wire5;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		clk0_divide_by => 5,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 21,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 10,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 21,
+		clk1_phase_shift => "0",
+		clk2_divide_by => 5,
+		clk2_duty_cycle => 50,
+		clk2_multiply_by => 21,
+		clk2_phase_shift => "-1280",
+		compensate_clock => "CLK0",
+		gate_lock_counter => 1048575,
+		gate_lock_signal => "YES",
+		inclk0_input_frequency => 37037,
+		intended_device_family => "Cyclone II",
+		invalid_lock_multiplier => 5,
+		lpm_hint => "CBX_MODULE_PREFIX=pll_pal",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_UNUSED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_USED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_USED",
+		port_clk3 => "PORT_UNUSED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		valid_lock_multiplier => 1
+	)
+	PORT MAP (
+		inclk => sub_wire6,
+		clk => sub_wire0,
+		locked => sub_wire2
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "5"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "10"
+-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "5"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "113.400002"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "56.700001"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "113.400002"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "1"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "21"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "21"
+-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "21"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "28.70000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "28.70000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "-1.28000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ns"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "21"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "10"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "21"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "5"
+-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "21"
+-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "-1280"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: GATE_LOCK_COUNTER NUMERIC "1048575"
+-- Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "YES"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
+-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
+-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
Index: de1_5200/sram.vhdl
===================================================================
--- de1_5200/sram.vhdl	(nonexistent)
+++ de1_5200/sram.vhdl	(revision 176)
@@ -0,0 +1,143 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+ENTITY sram IS
+PORT 
+( 
+	ADDRESS : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
+	DIN : IN STD_LOGIC_vector(15 downto 0);
+	WREN : IN STD_LOGIC;
+	
+	clk : in std_logic;
+	reset_n : in std_logic;
+	
+	request : in std_logic;
+	
+	width_16bit : in std_logic;
+	
+	-- SRAM interface
+	SRAM_ADDR: OUT STD_LOGIC_VECTOR(17 downto 0);
+	SRAM_CE_N: OUT STD_LOGIC;
+	SRAM_OE_N: OUT STD_LOGIC;
+	SRAM_WE_N: OUT STD_LOGIC;
+
+	SRAM_LB_N: OUT STD_LOGIC;
+	SRAM_UB_N: OUT STD_LOGIC;
+	
+	SRAM_DQ: INOUT STD_LOGIC_VECTOR(15 downto 0);
+	
+	-- Provide data to system
+	DOUT : OUT STD_LOGIC_VECTOR(15 downto 0);
+	complete : out std_logic
+);
+
+END sram;
+
+-- TODO, implement 32-bit accesses in two cycles
+
+-- first cycle, capture inputs
+-- second cycle, sram access
+ARCHITECTURE slow OF sram IS
+	signal oe_n_next : std_logic;
+	signal oe_n_reg : std_logic;
+	
+	signal we_n_next : std_logic;
+	signal we_n_reg : std_logic;	
+	
+	signal data_next : std_logic_vector(15 downto 0);
+	signal data_reg : std_logic_vector(15 downto 0);
+	
+	signal request_next : std_logic;
+	signal request_reg : std_logic;
+	
+	signal low_byte : std_logic_vector(7 downto 0);
+BEGIN
+	-- registers
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			oe_n_reg <= '1';
+			we_n_reg <= '1';
+			data_reg <= (others=>'0');
+			request_reg <= '0';
+		elsif (clk'event and clk='1') then
+			oe_n_reg <= oe_n_next;
+			we_n_reg <= we_n_next;
+			data_reg <= data_next;
+			request_reg <= request_next;
+		end if;
+	end process;
+
+	-- next state
+	process(din,wren,request,request_reg,width_16bit)
+	begin		
+		data_next <= din;
+		request_next <= '0';
+		
+		oe_n_next <= '0';
+		we_n_next <= '1';
+		
+		if (width_16bit = '0') then
+			data_next <= din(7 downto 0)&din(7 downto 0);
+		end if;
+		
+		if (request = '1') then
+			-- on second cycle do write - address/data stable by now guaranteed (normal timequest...)
+			oe_n_next <= wren;
+			we_n_next <= not(wren);		
+			request_next <= '1';
+		end if;
+	end process;
+	
+	LOW_BYTE <= SRAM_DQ(7 downto 0) when address(0)='0' else SRAM_DQ(15 downto 8);
+	
+	-- output
+	SRAM_ADDR <= address(18 downto 1);
+	SRAM_CE_N <= '0';
+	SRAM_OE_N <= oe_n_reg;
+	SRAM_WE_N <= we_n_reg;
+	SRAM_LB_N <= not(width_16bit) and address(0);
+	SRAM_UB_N <= not(width_16bit) and NOT(address(0));
+	SRAM_DQ <= data_reg when we_n_reg = '0' else (others=>'Z');
+
+	DOUT <= SRAM_DQ(15 downto 8)&LOW_BYTE;
+			
+	complete <= request_reg;		
+		
+	--GPIO <= (others=>'0');
+END slow;
+
+--ARCHITECTURE fast OF sram IS
+--	signal we_n : std_logic;
+--	signal dq : std_logic_vector(7 downto 0);
+--	
+--BEGIN
+--	we_n <= not(clk) nand WREN;
+--	dq <= SRAM_DQ(7 downto 0) when address(0)='0' else
+--		SRAM_DQ(15 downto 8);
+--		
+--	-- output
+--	SRAM_ADDR <= ADDRESS(18 downto 1);
+--	--SRAM_ADDR <= ADDRESS(17 downto 0);
+--	SRAM_CE_N <= '0';
+--	SRAM_OE_N <= WREN;
+--	SRAM_WE_N <= we_n;
+--	
+--	SRAM_LB_N <= ADDRESS(0);
+--	SRAM_UB_N <= NOT(ADDRESS(0));
+--	--SRAM_LB_N <= '0';
+--	--SRAM_UB_N <= '0';
+--		
+--	DOUT <= dq;		
+--	SRAM_DQ <= DIN&DIN when wren='1' else (others=>'Z');
+--	
+--	-- immediate completion
+--	complete <= request;
+--END fast;
\ No newline at end of file
Index: de1_5200/sync_switches.vhd
===================================================================
--- de1_5200/sync_switches.vhd	(nonexistent)
+++ de1_5200/sync_switches.vhd	(revision 176)
@@ -0,0 +1,69 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+ENTITY sync_switches IS
+PORT ( 
+	CLK : IN STD_LOGIC;
+
+	SW : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
+	KEY : IN STD_LOGIC_VECTOR(3 downto 0);
+	
+	SYNC_KEYS : out std_logic_vector(3 downto 0);
+	SYNC_SWITCHES : out std_logic_vector(9 downto 0)
+); 
+END sync_switches;
+
+ARCHITECTURE Behavior OF sync_switches IS
+	component synchronizer IS
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RAW : IN STD_LOGIC;
+		SYNC : OUT STD_LOGIC
+	);
+	END component;
+		
+	signal sw_reg : std_logic_vector(9 downto 0);
+	signal key_reg : std_logic_vector(3 downto 0);
+	
+BEGIN
+	sw9_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sw(9), sync=>sw_reg(9));	
+	sw8_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sw(8), sync=>sw_reg(8));	
+	sw7_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sw(7), sync=>sw_reg(7));	
+	sw6_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sw(6), sync=>sw_reg(6));	
+	sw5_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sw(5), sync=>sw_reg(5));			
+	sw4_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sw(4), sync=>sw_reg(4));	
+	sw3_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sw(3), sync=>sw_reg(3));	
+	sw2_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sw(2), sync=>sw_reg(2));	
+	sw1_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sw(1), sync=>sw_reg(1));	
+	sw0_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sw(0), sync=>sw_reg(0));			
+
+	key3_synchronizer : synchronizer
+		port map (clk=>clk, raw=>not(key(3)), sync=>key_reg(3));	
+	key2_synchronizer : synchronizer
+		port map (clk=>clk, raw=>not(key(2)), sync=>key_reg(2));	
+	key1_synchronizer : synchronizer
+		port map (clk=>clk, raw=>not(key(1)), sync=>key_reg(1));	
+	key0_synchronizer : synchronizer
+		port map (clk=>clk, raw=>not(key(0)), sync=>key_reg(0));			
+	
+	-- outputs
+	SYNC_KEYS <= key_reg(3)&key_reg(2)&key_reg(1)&key_reg(0);
+	SYNC_SWITCHES <= sw_reg(9)&sw_reg(8)&sw_reg(7)&sw_reg(6)&sw_reg(5)&sw_reg(4)&sw_reg(3)&sw_reg(2)&sw_reg(1)&sw_reg(0);
+END Behavior;
Index: de1_5200/zpu_rom.vhdl
===================================================================
--- de1_5200/zpu_rom.vhdl	(nonexistent)
+++ de1_5200/zpu_rom.vhdl	(revision 176)
@@ -0,0 +1,4130 @@
+
+--
+--ROMsUsingBlockRAMResources.
+--VHDLcodeforaROMwithregisteredoutput(template2)
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity zpu_rom is
+port(
+        clock:in std_logic;
+        address:in std_logic_vector(11 downto 0);
+        q:out std_logic_vector(31 downto 0)
+);
+end zpu_rom;
+
+architecture syn of zpu_rom is
+        type rom_type is array(0 to 4095) of std_logic_vector(31 downto 0);
+        signal ROM:rom_type:=
+(
+	X"0b0b0b89",
+X"ad040b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"71fd0608",
+X"72830609",
+X"81058205",
+X"832b2a83",
+X"ffff0652",
+X"04000000",
+X"00000000",
+X"00000000",
+X"71fd0608",
+X"83ffff73",
+X"83060981",
+X"05820583",
+X"2b2b0906",
+X"7383ffff",
+X"0b0b0b0b",
+X"83a70400",
+X"72098105",
+X"72057373",
+X"09060906",
+X"73097306",
+X"070a8106",
+X"53510400",
+X"00000000",
+X"00000000",
+X"72722473",
+X"732e0753",
+X"51040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"71737109",
+X"71068106",
+X"30720a10",
+X"0a720a10",
+X"0a31050a",
+X"81065151",
+X"53510400",
+X"00000000",
+X"72722673",
+X"732e0753",
+X"51040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"0b0b0b88",
+X"bc040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"720a722b",
+X"0a535104",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"72729f06",
+X"0981050b",
+X"0b0b889f",
+X"05040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"72722aff",
+X"739f062a",
+X"0974090a",
+X"8106ff05",
+X"06075351",
+X"04000000",
+X"00000000",
+X"00000000",
+X"71715351",
+X"020d0406",
+X"73830609",
+X"81058205",
+X"832b0b2b",
+X"0772fc06",
+X"0c515104",
+X"00000000",
+X"72098105",
+X"72050970",
+X"81050906",
+X"0a810653",
+X"51040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"72098105",
+X"72050970",
+X"81050906",
+X"0a098106",
+X"53510400",
+X"00000000",
+X"00000000",
+X"00000000",
+X"71098105",
+X"52040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"72720981",
+X"05055351",
+X"04000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"72097206",
+X"73730906",
+X"07535104",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"71fc0608",
+X"72830609",
+X"81058305",
+X"1010102a",
+X"81ff0652",
+X"04000000",
+X"00000000",
+X"00000000",
+X"71fc0608",
+X"0b0b80e6",
+X"c4738306",
+X"10100508",
+X"060b0b0b",
+X"88a20400",
+X"00000000",
+X"00000000",
+X"0b0b0b88",
+X"ff040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"0b0b0b88",
+X"d8040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"72097081",
+X"0509060a",
+X"8106ff05",
+X"70547106",
+X"73097274",
+X"05ff0506",
+X"07515151",
+X"04000000",
+X"72097081",
+X"0509060a",
+X"098106ff",
+X"05705471",
+X"06730972",
+X"7405ff05",
+X"06075151",
+X"51040000",
+X"05ff0504",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"810b80e9",
+X"a40c5104",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00007181",
+X"05520400",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000284",
+X"05721010",
+X"05520400",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00007171",
+X"05ff0571",
+X"5351020d",
+X"04000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"10101010",
+X"10101010",
+X"10101010",
+X"10101010",
+X"10101010",
+X"10101010",
+X"10101010",
+X"10101053",
+X"51047381",
+X"ff067383",
+X"06098105",
+X"83051010",
+X"102b0772",
+X"fc060c51",
+X"51043c04",
+X"72728072",
+X"8106ff05",
+X"09720605",
+X"71105272",
+X"0a100a53",
+X"72ed3851",
+X"51535104",
+X"83e08008",
+X"83e08408",
+X"83e08808",
+X"757580e0",
+X"f12d5050",
+X"83e08008",
+X"5683e088",
+X"0c83e084",
+X"0c83e080",
+X"0c510483",
+X"e0800883",
+X"e0840883",
+X"e0880875",
+X"7580df85",
+X"2d505083",
+X"e0800856",
+X"83e0880c",
+X"83e0840c",
+X"83e0800c",
+X"51040000",
+X"800489aa",
+X"0489aa0b",
+X"96bf0480",
+X"3d0d80ea",
+X"cc087008",
+X"810683e0",
+X"800c5182",
+X"3d0d04ff",
+X"3d0d80ea",
+X"cc087008",
+X"70fe0676",
+X"07720c52",
+X"52833d0d",
+X"04803d0d",
+X"80eacc08",
+X"70087081",
+X"2c810683",
+X"e0800c51",
+X"51823d0d",
+X"04ff3d0d",
+X"80eacc08",
+X"700870fd",
+X"06761007",
+X"720c5252",
+X"833d0d04",
+X"803d0d80",
+X"eacc0870",
+X"0870822c",
+X"bf0683e0",
+X"800c5151",
+X"823d0d04",
+X"ff3d0d80",
+X"eacc0870",
+X"0870fe83",
+X"0676822b",
+X"07720c52",
+X"52833d0d",
+X"04803d0d",
+X"80eacc08",
+X"70087088",
+X"2c870683",
+X"e0800c51",
+X"51823d0d",
+X"04ff3d0d",
+X"80eacc08",
+X"700870f1",
+X"ff067688",
+X"2b07720c",
+X"5252833d",
+X"0d04803d",
+X"0d80eacc",
+X"08700870",
+X"8b2cbf06",
+X"83e0800c",
+X"5151823d",
+X"0d04ff3d",
+X"0d80eacc",
+X"08700870",
+X"f88fff06",
+X"768b2b07",
+X"720c5252",
+X"833d0d04",
+X"803d0d80",
+X"eadc0870",
+X"0870882c",
+X"810683e0",
+X"800c5151",
+X"823d0d04",
+X"803d0d80",
+X"eadc0870",
+X"0870892c",
+X"810683e0",
+X"800c5151",
+X"823d0d04",
+X"803d0d80",
+X"eadc0870",
+X"08708a2c",
+X"810683e0",
+X"800c5151",
+X"823d0d04",
+X"803d0d80",
+X"eadc0870",
+X"08708b2c",
+X"810683e0",
+X"800c5151",
+X"823d0d04",
+X"fd3d0d75",
+X"81e62987",
+X"2a80eabc",
+X"0854730c",
+X"853d0d04",
+X"fe3d0d75",
+X"75ff1953",
+X"535370ff",
+X"2e8d3872",
+X"72708105",
+X"5434ff11",
+X"51f03984",
+X"3d0d04fe",
+X"3d0d7575",
+X"ff195353",
+X"5370ff2e",
+X"8d387272",
+X"70840554",
+X"0cff1151",
+X"f039843d",
+X"0d04fe3d",
+X"0d818080",
+X"53805288",
+X"800a51ff",
+X"b33fa080",
+X"53805282",
+X"800a51c7",
+X"3f843d0d",
+X"04803d0d",
+X"8151fccf",
+X"3f72802e",
+X"8338d33f",
+X"8151fcf1",
+X"3f8051fc",
+X"ec3f8051",
+X"fcb93f82",
+X"3d0d04fd",
+X"3d0d7552",
+X"805480ff",
+X"72258838",
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+
+);
+        signal rdata:std_logic_vector(31 downto 0);
+begin
+        rdata<=ROM(conv_integer(address));
+
+        process(clock)
+        begin
+                if(clock'event and clock='1')then
+                	q<=rdata;
+                end if;
+        end process;
+end syn;
