Index: mist_5200/pll_pal_pre.ppf
===================================================================
--- mist_5200/pll_pal_pre.ppf	(nonexistent)
+++ mist_5200/pll_pal_pre.ppf	(revision 177)
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="pll_pal_pre" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="locked" direction="output" scope="external"  />
+
+</global>
+</pinplan>
Index: mist_5200/pll_pal_pre.vhd
===================================================================
--- mist_5200/pll_pal_pre.vhd	(nonexistent)
+++ mist_5200/pll_pal_pre.vhd	(revision 177)
@@ -0,0 +1,360 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: pll_pal_pre.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pll_pal_pre IS
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+END pll_pal_pre;
+
+
+ARCHITECTURE SYN OF pll_pal_pre IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire5_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		self_reset_on_loss_lock		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+			locked	: OUT STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire5_bv(0 DOWNTO 0) <= "0";
+	sub_wire5    <= To_stdlogicvector(sub_wire5_bv);
+	sub_wire1    <= sub_wire0(0);
+	c0    <= sub_wire1;
+	locked    <= sub_wire2;
+	sub_wire3    <= inclk0;
+	sub_wire4    <= sub_wire5(0 DOWNTO 0) & sub_wire3;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "LOW",
+		clk0_divide_by => 27,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 20,
+		clk0_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 37037,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "CBX_MODULE_PREFIX=pll_pal_pre",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_UNUSED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_USED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_UNUSED",
+		port_clk2 => "PORT_UNUSED",
+		port_clk3 => "PORT_UNUSED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		self_reset_on_loss_lock => "OFF",
+		width_clock => 5
+	)
+	PORT MAP (
+		inclk => sub_wire4,
+		clk => sub_wire0,
+		locked => sub_wire2
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "1"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "20.000000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "20"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_pal_pre.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "LOW"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "20"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal_pre.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal_pre.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal_pre.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal_pre.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal_pre.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal_pre_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
Index: mist_5200/tb_data/data_io_tb.vhd
===================================================================
--- mist_5200/tb_data/data_io_tb.vhd	(nonexistent)
+++ mist_5200/tb_data/data_io_tb.vhd	(revision 177)
@@ -0,0 +1,319 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.std_logic_unsigned.all;
+  use ieee.numeric_std.all;
+  use ieee.std_logic_textio.all;
+
+library std_developerskit ; -- used for to_string
+--  use std_developerskit.std_iopak.all;
+
+entity data_io_tb is
+end;
+
+architecture rtl of data_io_tb is
+
+  constant CLK_A_PERIOD : time := 1 us / (1.79*32);
+
+  signal CLK_A : std_logic;
+
+  signal reset_n : std_logic;
+
+  signal spi_clk : std_logic;
+  signal spi_ss_io : std_logic_vector(1 downto 0);
+  signal spi_miso : std_logic;
+  signal spi_mosi : std_logic;
+
+  signal request : std_logic;
+  signal write : std_logic;
+  signal ready : std_logic;
+  signal sector : std_logic_vector(23 downto 0);
+
+  signal addr : std_logic_vector(8 downto 0);
+  signal data_out : std_logic_vector(7 downto 0);
+  signal data_in : std_logic_vector(7 downto 0);
+  signal wr_en : std_logic;
+
+  signal spi_enable : std_logic;
+  signal spi_tx_data : std_logic_vector(7 downto 0);
+  signal spi_rx_data : std_logic_vector(7 downto 0);
+  signal spi_busy : std_logic;
+
+  signal spi_addr : integer;
+
+begin
+	p_clk_gen_a : process
+	begin
+	clk_a <= '1';
+	wait for CLK_A_PERIOD/2;
+	clk_a <= '0';
+	wait for CLK_A_PERIOD - (CLK_A_PERIOD/2 );
+	end process;
+
+	reset_n <= '0', '1' after 1000ns;
+
+
+	spi_master1 : entity work.spi_master
+		generic map(slaves=>2,d_width=>8)
+		port map (clock=>clk_a,reset_n=>reset_n,enable=>spi_enable,cpol=>'0',cpha=>'0',cont=>'0',clk_div=>4,addr=>spi_addr,
+		          tx_data=>spi_tx_data, miso=>spi_miso,sclk=>spi_clk,ss_n=>spi_ss_io,mosi=>spi_mosi,
+					 rx_data=>spi_rx_data,busy=>spi_busy);
+
+	spi_fake : process
+ 	variable type_conv : std_logic_vector(8 downto 0);
+	begin
+	spi_enable <= '0';
+	spi_addr <= 0;
+	wait for 1500us;
+
+	spi_tx_data <= x"50";
+	spi_enable <= '1';
+	wait for CLK_A_PERIOD*2;
+	spi_tx_data <= x"FF";
+	spi_enable <= '0';
+	wait until spi_busy='0';
+
+	for i in 0 to 3 loop
+		spi_tx_data <= x"ff";
+		spi_enable <= '1';
+		wait for CLK_A_PERIOD*2;
+		spi_tx_data <= x"FF";
+		spi_enable <= '0';
+		wait until spi_busy='0';
+	end loop;
+
+	spi_addr <= 1;
+	spi_tx_data <= x"ff";
+	spi_enable <= '1';
+	wait for CLK_A_PERIOD*2;
+	spi_tx_data <= x"FF";
+	spi_enable <= '0';
+	wait until spi_busy='0';
+	spi_addr <= 0;
+	wait for 20us;
+
+	spi_tx_data <= x"51";
+	spi_enable <= '1';
+	wait for CLK_A_PERIOD*2;
+	spi_tx_data <= x"FF";
+	spi_enable <= '0';
+	wait until spi_busy='0';
+
+	for i in 0 to 511 loop
+		type_conv := std_logic_vector(to_unsigned(i,9));
+		spi_tx_data <= type_conv(7 downto 0);
+		spi_enable <= '1';
+		wait for CLK_A_PERIOD*4;
+		spi_tx_data <= x"FF";
+		spi_enable <= '0';
+		wait until spi_busy='0';
+	end loop;
+
+	spi_tx_data <= x"ff";
+	spi_enable <= '1';
+	wait for CLK_A_PERIOD*2;
+	spi_tx_data <= x"FF";
+	spi_enable <= '0';
+	wait until spi_busy='0';
+
+	-- NEXT
+
+	spi_addr <= 1;
+	spi_tx_data <= x"ff";
+	spi_enable <= '1';
+	wait for CLK_A_PERIOD*2;
+	spi_tx_data <= x"FF";
+	spi_enable <= '0';
+	wait until spi_busy='0';
+	spi_addr <= 0;
+	wait for 20us;
+
+	spi_tx_data <= x"50";
+	spi_enable <= '1';
+	wait for CLK_A_PERIOD*2;
+	spi_tx_data <= x"FF";
+	spi_enable <= '0';
+	wait until spi_busy='0';
+
+	for i in 0 to 3 loop
+		spi_tx_data <= x"ff";
+		spi_enable <= '1';
+		wait for CLK_A_PERIOD*2;
+		spi_tx_data <= x"FF";
+		spi_enable <= '0';
+		wait until spi_busy='0';
+	end loop;
+
+	spi_addr <= 1;
+	spi_tx_data <= x"ff";
+	spi_enable <= '1';
+	wait for CLK_A_PERIOD*2;
+	spi_tx_data <= x"FF";
+	spi_enable <= '0';
+	wait until spi_busy='0';
+	spi_addr <= 0;
+	wait for 20us;
+
+	spi_tx_data <= x"51";
+	spi_enable <= '1';
+	wait for CLK_A_PERIOD*2;
+	spi_tx_data <= x"FF";
+	spi_enable <= '0';
+	wait until spi_busy='0';
+
+	for i in 0 to 511 loop
+		type_conv := std_logic_vector(to_unsigned(511-i,9));
+		spi_tx_data <= type_conv(7 downto 0);
+		spi_enable <= '1';
+		wait for CLK_A_PERIOD*4;
+		spi_tx_data <= x"FF";
+		spi_enable <= '0';
+		wait until spi_busy='0';
+	end loop;
+
+	spi_tx_data <= x"ff";
+	spi_enable <= '1';
+	wait for CLK_A_PERIOD*2;
+	spi_tx_data <= x"FF";
+	spi_enable <= '0';
+	wait until spi_busy='0';
+
+	-- NEXT - WRITE...
+
+	spi_addr <= 1;
+	spi_tx_data <= x"ff";
+	spi_enable <= '1';
+	wait for CLK_A_PERIOD*2;
+	spi_tx_data <= x"FF";
+	spi_enable <= '0';
+	wait until spi_busy='0';
+	spi_addr <= 0;
+	wait for 20us;
+
+	spi_tx_data <= x"50";
+	spi_enable <= '1';
+	wait for CLK_A_PERIOD*2;
+	spi_tx_data <= x"FF";
+	spi_enable <= '0';
+	wait until spi_busy='0';
+
+	for i in 0 to 3 loop
+		spi_tx_data <= x"ff";
+		spi_enable <= '1';
+		wait for CLK_A_PERIOD*2;
+		spi_tx_data <= x"FF";
+		spi_enable <= '0';
+		wait until spi_busy='0';
+	end loop;
+
+	spi_addr <= 1;
+	spi_tx_data <= x"ff";
+	spi_enable <= '1';
+	wait for CLK_A_PERIOD*2;
+	spi_tx_data <= x"FF";
+	spi_enable <= '0';
+	wait until spi_busy='0';
+	spi_addr <= 0;
+	wait for 20us;
+
+	spi_tx_data <= x"52";
+	spi_enable <= '1';
+	wait for CLK_A_PERIOD*2;
+	spi_tx_data <= x"FF";
+	spi_enable <= '0';
+	wait until spi_busy='0';
+
+	for i in 0 to 511 loop
+		spi_tx_data <= x"FF";
+		spi_enable <= '1';
+		wait for CLK_A_PERIOD*4;
+		spi_tx_data <= x"FF";
+		spi_enable <= '0';
+		wait until spi_busy='0';
+	end loop;
+
+	spi_tx_data <= x"ff";
+	spi_enable <= '1';
+	wait for CLK_A_PERIOD*2;
+	spi_tx_data <= x"FF";
+	spi_enable <= '0';
+	wait until spi_busy='0';
+
+	wait for 100ms;
+	
+	end process;
+
+	spi_request : process
+	begin
+	sector <= (others=>'0');
+	request <= '0';
+	write <= '0';
+	wait for 1500us;
+
+	sector <= x"123456";
+	request <= '1';
+	wait until ready = '1';
+	request <= '0';
+	wait for CLK_A_PERIOD*20;
+	wait until ready = '0';
+
+
+	sector <= x"654321";
+	request <= '1';
+	wait until ready = '1';
+	request <= '0';
+	wait for CLK_A_PERIOD*20;
+	wait until ready = '0';
+
+	sector <= x"111111";
+	write <= '1';
+	wait until ready = '1';
+	write <= '0';
+	wait for CLK_A_PERIOD*20;
+	wait until ready = '0';
+
+	wait for 100ms;
+	end process;
+
+	ram : entity work.generic_ram_infer
+	generic map
+	(
+		ADDRESS_WIDTH => 9,
+		SPACE => 512,
+		DATA_WIDTH => 8
+	)
+   PORT map
+   (
+      clock => spi_clk,
+      data => data_out,
+      address => addr,
+      we => wr_en,
+      q => data_in
+   );
+
+	data_io : entity work.data_io
+	PORT MAP
+	(
+		CLK => spi_clk,
+		RESET_n =>reset_n,
+		
+		-- SPI connection - up to upstream to make miso 'Z' on ss_io going high
+	   SPI_CLK => spi_clk,
+	   SPI_SS_IO => spi_ss_io(0),
+	   SPI_MISO => spi_miso,
+	   SPI_MOSI => spi_mosi,
+		
+		-- Sector access request
+		read_request => request,
+		write_request => write,
+		sector => sector,
+		ready => ready,
+		
+		-- DMA to RAM
+		ADDR => addr,
+		DATA_OUT => data_out,
+		DATA_IN => data_in,
+		WR_EN => wr_en
+	 );
+
+end rtl;
+
Index: mist_5200/zpu_rom.vhdl
===================================================================
--- mist_5200/zpu_rom.vhdl	(nonexistent)
+++ mist_5200/zpu_rom.vhdl	(revision 177)
@@ -0,0 +1,4130 @@
+
+--
+--ROMsUsingBlockRAMResources.
+--VHDLcodeforaROMwithregisteredoutput(template2)
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity zpu_rom is
+port(
+        clock:in std_logic;
+        address:in std_logic_vector(11 downto 0);
+        q:out std_logic_vector(31 downto 0)
+);
+end zpu_rom;
+
+architecture syn of zpu_rom is
+        type rom_type is array(0 to 4095) of std_logic_vector(31 downto 0);
+        signal ROM:rom_type:=
+(
+	X"0b0b0b89",
+X"ad040b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"71fd0608",
+X"72830609",
+X"81058205",
+X"832b2a83",
+X"ffff0652",
+X"04000000",
+X"00000000",
+X"00000000",
+X"71fd0608",
+X"83ffff73",
+X"83060981",
+X"05820583",
+X"2b2b0906",
+X"7383ffff",
+X"0b0b0b0b",
+X"83a70400",
+X"72098105",
+X"72057373",
+X"09060906",
+X"73097306",
+X"070a8106",
+X"53510400",
+X"00000000",
+X"00000000",
+X"72722473",
+X"732e0753",
+X"51040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"71737109",
+X"71068106",
+X"30720a10",
+X"0a720a10",
+X"0a31050a",
+X"81065151",
+X"53510400",
+X"00000000",
+X"72722673",
+X"732e0753",
+X"51040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"0b0b0b88",
+X"bc040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"720a722b",
+X"0a535104",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"72729f06",
+X"0981050b",
+X"0b0b889f",
+X"05040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"72722aff",
+X"739f062a",
+X"0974090a",
+X"8106ff05",
+X"06075351",
+X"04000000",
+X"00000000",
+X"00000000",
+X"71715351",
+X"020d0406",
+X"73830609",
+X"81058205",
+X"832b0b2b",
+X"0772fc06",
+X"0c515104",
+X"00000000",
+X"72098105",
+X"72050970",
+X"81050906",
+X"0a810653",
+X"51040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"72098105",
+X"72050970",
+X"81050906",
+X"0a098106",
+X"53510400",
+X"00000000",
+X"00000000",
+X"00000000",
+X"71098105",
+X"52040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"72720981",
+X"05055351",
+X"04000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"72097206",
+X"73730906",
+X"07535104",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"71fc0608",
+X"72830609",
+X"81058305",
+X"1010102a",
+X"81ff0652",
+X"04000000",
+X"00000000",
+X"00000000",
+X"71fc0608",
+X"0b0b80de",
+X"c4738306",
+X"10100508",
+X"060b0b0b",
+X"88a20400",
+X"00000000",
+X"00000000",
+X"0b0b0b88",
+X"ff040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"0b0b0b88",
+X"d8040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"72097081",
+X"0509060a",
+X"8106ff05",
+X"70547106",
+X"73097274",
+X"05ff0506",
+X"07515151",
+X"04000000",
+X"72097081",
+X"0509060a",
+X"098106ff",
+X"05705471",
+X"06730972",
+X"7405ff05",
+X"06075151",
+X"51040000",
+X"05ff0504",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"810b80e1",
+X"a40c5104",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00007181",
+X"05520400",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000284",
+X"05721010",
+X"05520400",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00007171",
+X"05ff0571",
+X"5351020d",
+X"04000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"10101010",
+X"10101010",
+X"10101010",
+X"10101010",
+X"10101010",
+X"10101010",
+X"10101010",
+X"10101053",
+X"51047381",
+X"ff067383",
+X"06098105",
+X"83051010",
+X"102b0772",
+X"fc060c51",
+X"51043c04",
+X"72728072",
+X"8106ff05",
+X"09720605",
+X"71105272",
+X"0a100a53",
+X"72ed3851",
+X"51535104",
+X"83e08008",
+X"83e08408",
+X"83e08808",
+X"757580d8",
+X"f22d5050",
+X"83e08008",
+X"5683e088",
+X"0c83e084",
+X"0c83e080",
+X"0c510483",
+X"e0800883",
+X"e0840883",
+X"e0880875",
+X"7580d786",
+X"2d505083",
+X"e0800856",
+X"83e0880c",
+X"83e0840c",
+X"83e0800c",
+X"51040000",
+X"800489aa",
+X"0489aa0b",
+X"96bf0480",
+X"3d0d80e2",
+X"cc087008",
+X"810683e0",
+X"800c5182",
+X"3d0d04ff",
+X"3d0d80e2",
+X"cc087008",
+X"70fe0676",
+X"07720c52",
+X"52833d0d",
+X"04803d0d",
+X"80e2cc08",
+X"70087081",
+X"2c810683",
+X"e0800c51",
+X"51823d0d",
+X"04ff3d0d",
+X"80e2cc08",
+X"700870fd",
+X"06761007",
+X"720c5252",
+X"833d0d04",
+X"803d0d80",
+X"e2cc0870",
+X"0870822c",
+X"bf0683e0",
+X"800c5151",
+X"823d0d04",
+X"ff3d0d80",
+X"e2cc0870",
+X"0870fe83",
+X"0676822b",
+X"07720c52",
+X"52833d0d",
+X"04803d0d",
+X"80e2cc08",
+X"70087088",
+X"2c870683",
+X"e0800c51",
+X"51823d0d",
+X"04ff3d0d",
+X"80e2cc08",
+X"700870f1",
+X"ff067688",
+X"2b07720c",
+X"5252833d",
+X"0d04803d",
+X"0d80e2cc",
+X"08700870",
+X"8b2cbf06",
+X"83e0800c",
+X"5151823d",
+X"0d04ff3d",
+X"0d80e2cc",
+X"08700870",
+X"f88fff06",
+X"768b2b07",
+X"720c5252",
+X"833d0d04",
+X"803d0d80",
+X"e2dc0870",
+X"0870882c",
+X"810683e0",
+X"800c5151",
+X"823d0d04",
+X"803d0d80",
+X"e2dc0870",
+X"0870892c",
+X"810683e0",
+X"800c5151",
+X"823d0d04",
+X"803d0d80",
+X"e2dc0870",
+X"08708a2c",
+X"810683e0",
+X"800c5151",
+X"823d0d04",
+X"803d0d80",
+X"e2dc0870",
+X"08708b2c",
+X"810683e0",
+X"800c5151",
+X"823d0d04",
+X"fd3d0d75",
+X"81e62987",
+X"2a80e2bc",
+X"0854730c",
+X"853d0d04",
+X"fe3d0d75",
+X"75ff1953",
+X"535370ff",
+X"2e8d3872",
+X"72708105",
+X"5434ff11",
+X"51f03984",
+X"3d0d04fe",
+X"3d0d7575",
+X"ff195353",
+X"5370ff2e",
+X"8d387272",
+X"70840554",
+X"0cff1151",
+X"f039843d",
+X"0d04fe3d",
+X"0d818080",
+X"53805288",
+X"800a51ff",
+X"b33fa080",
+X"53805282",
+X"800a51c7",
+X"3f843d0d",
+X"04803d0d",
+X"8151fccf",
+X"3f72802e",
+X"8338d33f",
+X"8151fcf1",
+X"3f8051fc",
+X"ec3f8051",
+X"fcb93f82",
+X"3d0d04fd",
+X"3d0d7552",
+X"805480ff",
+X"72258838",
+X"810bff80",
+X"135354ff",
+X"bf125170",
+X"99268638",
+X"e012529e",
+X"39ff9f12",
+X"51997127",
+X"9538d012",
+X"e0137054",
+X"54518971",
+X"2788388f",
+X"73278338",
+X"80527380",
+X"2e853881",
+X"80125271",
+X"81ff0683",
+X"e0800c85",
+X"3d0d0480",
+X"3d0d84d8",
+X"c0518071",
+X"70810553",
+X"347084e0",
+X"c02e0981",
+X"06f03882",
+X"3d0d04fe",
+X"3d0d0297",
+X"053351ff",
+X"863f83e0",
+X"800881ff",
+X"0683e09c",
+X"08545280",
+X"73249b38",
+X"83e0b808",
+X"137283e0",
+X"bc080753",
+X"53717334",
+X"83e09c08",
+X"810583e0",
+X"9c0c843d",
+X"0d04fa3d",
+X"0d82800a",
+X"1b558057",
+X"883dfc05",
+X"54795374",
+X"527851a2",
+X"cf3f883d",
+X"0d04fe3d",
+X"0d83e0b0",
+X"08527451",
+X"a9e33f83",
+X"e080088c",
+X"38765375",
+X"5283e0b0",
+X"0851c73f",
+X"843d0d04",
+X"fe3d0d83",
+X"e0b00853",
+X"75527451",
+X"a3f13f83",
+X"e080088d",
+X"38775376",
+X"5283e0b0",
+X"0851ffa2",
+X"3f843d0d",
+X"04fd3d0d",
+X"83e0b408",
+X"51a2e53f",
+X"83e08008",
+X"90802e09",
+X"8106ad38",
+X"805483c1",
+X"80805383",
+X"e0800852",
+X"83e0b408",
+X"51fef33f",
+X"87c18080",
+X"143387c1",
+X"90801534",
+X"81145473",
+X"90802e09",
+X"8106e938",
+X"853d0d04",
+X"0b0b80df",
+X"940b83e0",
+X"800c04f7",
+X"3d0d805a",
+X"80598058",
+X"80705757",
+X"fde53f80",
+X"0b83e09c",
+X"0c800b83",
+X"e0bc0c0b",
+X"0b80df98",
+X"519dc73f",
+X"81800b83",
+X"e0bc0c0b",
+X"0b80df9c",
+X"519db73f",
+X"80d00b83",
+X"e09c0c75",
+X"30707707",
+X"80257087",
+X"2b83e0bc",
+X"0c5154f9",
+X"cb3f83e0",
+X"8008520b",
+X"0b80dfa4",
+X"519d8f3f",
+X"80f80b83",
+X"e09c0c75",
+X"81327030",
+X"70720780",
+X"2570872b",
+X"83e0bc0c",
+X"515555fe",
+X"fb3f83e0",
+X"8008520b",
+X"0b80dfb0",
+X"519ce33f",
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+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000"
+
+);
+        signal rdata:std_logic_vector(31 downto 0);
+begin
+        rdata<=ROM(conv_integer(address));
+
+        process(clock)
+        begin
+                if(clock'event and clock='1')then
+                	q<=rdata;
+                end if;
+        end process;
+end syn;
Index: mist_5200/atari800core.jdi
===================================================================
--- mist_5200/atari800core.jdi	(nonexistent)
+++ mist_5200/atari800core.jdi	(revision 177)
@@ -0,0 +1,62 @@
+<sld_project_info>
+  <project>
+    <hash md5_digest_80b="7d0f11bf891bc55d775e"/>
+  </project>
+  <file_info/>
+  <hub_info ir_width="8" node_count="1"/>
+  <node_info>
+    <node hpath="sld_signaltap:auto_signaltap_0" instance_id="0" mfg_id="110" node_id="0" sld_node_info="0x30006E00" version="6">
+      <parameters>
+        <parameter name="lpm_type" type="string" value="sld_signaltap"/>
+        <parameter name="sld_node_info" type="unknown" value="805334528"/>
+        <parameter name="SLD_IP_VERSION" type="dec" value="6"/>
+        <parameter name="SLD_IP_MINOR_VERSION" type="dec" value="0"/>
+        <parameter name="SLD_COMMON_IP_VERSION" type="dec" value="0"/>
+        <parameter name="sld_data_bits" type="unknown" value="119"/>
+        <parameter name="sld_trigger_bits" type="unknown" value="119"/>
+        <parameter name="SLD_NODE_CRC_BITS" type="dec" value="32"/>
+        <parameter name="sld_node_crc_hiword" type="unknown" value="37736"/>
+        <parameter name="sld_node_crc_loword" type="unknown" value="25945"/>
+        <parameter name="SLD_INCREMENTAL_ROUTING" type="dec" value="0"/>
+        <parameter name="sld_sample_depth" type="unknown" value="2048"/>
+        <parameter name="sld_segment_size" type="unknown" value="2048"/>
+        <parameter name="SLD_RAM_BLOCK_TYPE" type="string" value="AUTO"/>
+        <parameter name="sld_state_bits" type="unknown" value="11"/>
+        <parameter name="sld_buffer_full_stop" type="unknown" value="1"/>
+        <parameter name="SLD_MEM_ADDRESS_BITS" type="dec" value="7"/>
+        <parameter name="SLD_DATA_BIT_CNTR_BITS" type="dec" value="4"/>
+        <parameter name="sld_trigger_level" type="unknown" value="1"/>
+        <parameter name="sld_trigger_in_enabled" type="unknown" value="0"/>
+        <parameter name="sld_advanced_trigger_entity" type="unknown" value="basic,1,"/>
+        <parameter name="sld_trigger_level_pipeline" type="unknown" value="1"/>
+        <parameter name="sld_enable_advanced_trigger" type="unknown" value="0"/>
+        <parameter name="SLD_ADVANCED_TRIGGER_1" type="string" value="NONE"/>
+        <parameter name="SLD_ADVANCED_TRIGGER_2" type="string" value="NONE"/>
+        <parameter name="SLD_ADVANCED_TRIGGER_3" type="string" value="NONE"/>
+        <parameter name="SLD_ADVANCED_TRIGGER_4" type="string" value="NONE"/>
+        <parameter name="SLD_ADVANCED_TRIGGER_5" type="string" value="NONE"/>
+        <parameter name="SLD_ADVANCED_TRIGGER_6" type="string" value="NONE"/>
+        <parameter name="SLD_ADVANCED_TRIGGER_7" type="string" value="NONE"/>
+        <parameter name="SLD_ADVANCED_TRIGGER_8" type="string" value="NONE"/>
+        <parameter name="SLD_ADVANCED_TRIGGER_9" type="string" value="NONE"/>
+        <parameter name="SLD_ADVANCED_TRIGGER_10" type="string" value="NONE"/>
+        <parameter name="sld_inversion_mask_length" type="unknown" value="382"/>
+        <parameter name="sld_inversion_mask" type="unknown" value="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
+        <parameter name="sld_power_up_trigger" type="unknown" value="0"/>
+        <parameter name="SLD_STATE_FLOW_MGR_ENTITY" type="string" value="state_flow_mgr_entity.vhd"/>
+        <parameter name="sld_state_flow_use_generated" type="unknown" value="0"/>
+        <parameter name="sld_current_resource_width" type="unknown" value="1"/>
+        <parameter name="sld_attribute_mem_mode" type="unknown" value="OFF"/>
+        <parameter name="SLD_STORAGE_QUALIFIER_BITS" type="dec" value="1"/>
+        <parameter name="SLD_STORAGE_QUALIFIER_GAP_RECORD" type="dec" value="0"/>
+        <parameter name="SLD_STORAGE_QUALIFIER_MODE" type="string" value="OFF"/>
+        <parameter name="SLD_STORAGE_QUALIFIER_ENABLE_ADVANCED_CONDITION" type="dec" value="0"/>
+        <parameter name="sld_storage_qualifier_inversion_mask_length" type="unknown" value="0"/>
+        <parameter name="SLD_STORAGE_QUALIFIER_ADVANCED_CONDITION_ENTITY" type="string" value="basic"/>
+        <parameter name="SLD_STORAGE_QUALIFIER_PIPELINE" type="dec" value="0"/>
+      </parameters>
+      <inputs/>
+      <outputs/>
+    </node>
+  </node_info>
+</sld_project_info>
Index: mist_5200/atari800core.qpf
===================================================================
--- mist_5200/atari800core.qpf	(nonexistent)
+++ mist_5200/atari800core.qpf	(revision 177)
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2012 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Web Edition
+# Date created = 13:58:38  April 11, 2013
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "12.1"
+DATE = "13:58:38  April 11, 2013"
+
+# Revisions
+
+PROJECT_REVISION = "atari800core"
Index: mist_5200/atari800core.qsf
===================================================================
--- mist_5200/atari800core.qsf	(nonexistent)
+++ mist_5200/atari800core.qsf	(revision 177)
@@ -0,0 +1,320 @@
+# Copyright (C) 1991-2007 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+
+
+# The default values for assignments are stored in the file
+#		minimig_de1_assignment_defaults.qdf
+# If this file doesn't exist, and for assignments not listed, see file
+#		assignment_defaults.qdf
+
+# Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+
+
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE EP3C25E144C8
+set_global_assignment -name TOP_LEVEL_ENTITY atari800core_mist
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.2
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:27:29  OCTOBER 30, 2007"
+set_global_assignment -name LAST_QUARTUS_VERSION "12.1 SP1.33"
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
+set_global_assignment -name FITTER_EFFORT "AUTO FIT"
+set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name GENERATE_RBF_FILE ON
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+
+set_location_assignment PIN_7 -to LED
+set_location_assignment PIN_22 -to CLOCK_50[0]
+set_location_assignment PIN_23 -to CLOCK_50[1]
+set_location_assignment PIN_128 -to CLOCK_32[0]
+set_location_assignment PIN_129 -to CLOCK_32[1]
+set_location_assignment PIN_54 -to CLOCK_27[0]
+set_location_assignment PIN_55 -to CLOCK_27[1]
+set_location_assignment PIN_144 -to VGA_R[5]
+set_location_assignment PIN_143 -to VGA_R[4]
+set_location_assignment PIN_142 -to VGA_R[3]
+set_location_assignment PIN_141 -to VGA_R[2]
+set_location_assignment PIN_137 -to VGA_R[1]
+set_location_assignment PIN_135 -to VGA_R[0]
+set_location_assignment PIN_133 -to VGA_B[5]
+set_location_assignment PIN_132 -to VGA_B[4]
+set_location_assignment PIN_125 -to VGA_B[3]
+set_location_assignment PIN_121 -to VGA_B[2]
+set_location_assignment PIN_120 -to VGA_B[1]
+set_location_assignment PIN_115 -to VGA_B[0]
+set_location_assignment PIN_114 -to VGA_G[5]
+set_location_assignment PIN_113 -to VGA_G[4]
+set_location_assignment PIN_112 -to VGA_G[3]
+set_location_assignment PIN_111 -to VGA_G[2]
+set_location_assignment PIN_110 -to VGA_G[1]
+set_location_assignment PIN_106 -to VGA_G[0]
+set_location_assignment PIN_136 -to VGA_VS
+set_location_assignment PIN_119 -to VGA_HS
+set_location_assignment PIN_65 -to AUDIO_L
+set_location_assignment PIN_80 -to AUDIO_R
+set_location_assignment PIN_46 -to UART_TX
+set_location_assignment PIN_31 -to UART_RX
+set_location_assignment PIN_105 -to SPI_DO
+set_location_assignment PIN_88 -to SPI_DI
+set_location_assignment PIN_126 -to SPI_SCK
+set_location_assignment PIN_127 -to SPI_SS2
+set_location_assignment PIN_91 -to SPI_SS3
+set_location_assignment PIN_90 -to SPI_SS4
+set_location_assignment PIN_13 -to CONF_DATA0
+
+set_location_assignment PIN_49 -to SDRAM_A[0]
+set_location_assignment PIN_44 -to SDRAM_A[1]
+set_location_assignment PIN_42 -to SDRAM_A[2]
+set_location_assignment PIN_39 -to SDRAM_A[3]
+set_location_assignment PIN_4 -to SDRAM_A[4]
+set_location_assignment PIN_6 -to SDRAM_A[5]
+set_location_assignment PIN_8 -to SDRAM_A[6]
+set_location_assignment PIN_10 -to SDRAM_A[7]
+set_location_assignment PIN_11 -to SDRAM_A[8]
+set_location_assignment PIN_28 -to SDRAM_A[9]
+set_location_assignment PIN_50 -to SDRAM_A[10]
+set_location_assignment PIN_30 -to SDRAM_A[11]
+set_location_assignment PIN_32 -to SDRAM_A[12]
+set_location_assignment PIN_83 -to SDRAM_DQ[0]
+set_location_assignment PIN_79 -to SDRAM_DQ[1]
+set_location_assignment PIN_77 -to SDRAM_DQ[2]
+set_location_assignment PIN_76 -to SDRAM_DQ[3]
+set_location_assignment PIN_72 -to SDRAM_DQ[4]
+set_location_assignment PIN_71 -to SDRAM_DQ[5]
+set_location_assignment PIN_69 -to SDRAM_DQ[6]
+set_location_assignment PIN_68 -to SDRAM_DQ[7]
+set_location_assignment PIN_86 -to SDRAM_DQ[8]
+set_location_assignment PIN_87 -to SDRAM_DQ[9]
+set_location_assignment PIN_98 -to SDRAM_DQ[10]
+set_location_assignment PIN_99 -to SDRAM_DQ[11]
+set_location_assignment PIN_100 -to SDRAM_DQ[12]
+set_location_assignment PIN_101 -to SDRAM_DQ[13]
+set_location_assignment PIN_103 -to SDRAM_DQ[14]
+set_location_assignment PIN_104 -to SDRAM_DQ[15]
+set_location_assignment PIN_58 -to SDRAM_BA[0]
+set_location_assignment PIN_51 -to SDRAM_BA[1]
+set_location_assignment PIN_85 -to SDRAM_DQMH
+set_location_assignment PIN_67 -to SDRAM_DQML
+set_location_assignment PIN_60 -to SDRAM_nRAS
+set_location_assignment PIN_64 -to SDRAM_nCAS
+set_location_assignment PIN_66 -to SDRAM_nWE
+set_location_assignment PIN_59 -to SDRAM_nCS
+set_location_assignment PIN_33 -to SDRAM_CKE
+set_location_assignment PIN_43 -to SDRAM_CLK
+
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE BALANCED
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name ENABLE_SIGNALTAP ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
+set_global_assignment -name FMAX_REQUIREMENT "114 MHz"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name TPD_REQUIREMENT "2 ns"
+set_global_assignment -name TSU_REQUIREMENT "2 ns"
+set_global_assignment -name TCO_REQUIREMENT "2 ns"
+set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
+set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION OFF
+set_global_assignment -name AUTO_RAM_RECOGNITION ON
+set_global_assignment -name AUTO_ROM_RECOGNITION ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top
+set_global_assignment -name MISC_FILE atari800core.dpf
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA OFF
+
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY out
+set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 4.0
+set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 4.0
+set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY OFF
+
+#set_parameter -name ENABLE_RUNTIME_MOD YES -to "Minimig1:minimig|amiga_boot:BOOTROM1|altsyncram:Ram0_rtl_10"
+#set_parameter -name INSTANCE_NAME mig -to "Minimig1:minimig|amiga_boot:BOOTROM1|altsyncram:Ram0_rtl_10"
+
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+
+
+
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[0]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[1]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[2]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[3]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[4]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[5]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[6]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[7]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[8]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[9]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[10]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[11]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[12]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[13]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[14]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[15]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[0]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[1]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[2]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[3]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[4]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[5]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[6]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[7]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[8]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[9]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[10]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[11]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[12]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
+
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[0]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[1]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[2]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[3]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[4]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[5]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[6]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[7]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[8]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[9]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[10]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[11]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[12]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[13]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[14]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[15]
+
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[0]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[1]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[2]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[3]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[4]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[5]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[6]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[7]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[8]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[9]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[10]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[11]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[12]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[13]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[14]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[15]
+
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[0]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[1]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[2]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[3]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[4]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[5]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[6]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[7]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[8]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[9]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[10]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[11]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[12]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[0]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[1]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[2]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[3]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[4]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[5]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[6]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[7]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[8]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[9]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[10]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[11]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[12]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[13]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[14]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[15]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_BA[0]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_BA[1]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQML
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQMH
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nRAS
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nCAS
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nWE
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nCS
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_CKE
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_CLK
+
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[5]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[4]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[3]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[2]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[1]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[0]
+
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[5]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[4]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[3]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[2]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[1]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[0]
+
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[5]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[4]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[3]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[2]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[1]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[0]
+
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+
+set_global_assignment -name VHDL_FILE data_io.vhdl
+set_global_assignment -name VHDL_FILE zpu_rom.vhdl
+set_global_assignment -name SDC_FILE atari800core.sdc
+set_global_assignment -name QIP_FILE mist_sector_buffer.qip
+set_global_assignment -name VHDL_FILE atari800core_mist.vhd
+set_global_assignment -name VERILOG_FILE user_io.v
+set_global_assignment -name QIP_FILE pll_pal_pre.qip
+set_global_assignment -name QIP_FILE pll_pal_post.qip
+set_global_assignment -name QIP_FILE pll_ntsc.qip
+
Index: mist_5200/atari800core.qws
===================================================================
Cannot display: file marked as a binary type.
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Property changes on: mist_5200/atari800core.qws
___________________________________________________________________
Added: svn:mime-type
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+application/octet-stream
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Index: mist_5200/atari800core.sdc
===================================================================
--- mist_5200/atari800core.sdc	(nonexistent)
+++ mist_5200/atari800core.sdc	(revision 177)
@@ -0,0 +1,9 @@
+create_clock -period 27MHz [get_ports CLOCK_27[0]]
+derive_pll_clocks
+create_generated_clock -name sdclk_pin -source [get_pins {clock|altpll_component|auto_generated|pll1|clk[2]}] [get_ports {SDRAM_CLK}]
+derive_clock_uncertainty
+set_input_delay -clock sdclk_pin -max 6.4 [get_ports SDRAM_DQ*]
+set_input_delay -clock sdclk_pin -min 3.2 [get_ports SDRAM_DQ*]
+set_output_delay -clock sdclk_pin -max 1.5 [get_ports SDRAM_*]
+set_output_delay -clock sdclk_pin -min -0.8 [get_ports SDRAM_*]
+set_multicycle_path -from [get_clocks {sdclk_pin}] -to [get_clocks {clock|altpll_component|auto_generated|pll1|clk[0]}] -setup -end 2
Index: mist_5200/atari800core_mist.vhd
===================================================================
--- mist_5200/atari800core_mist.vhd	(nonexistent)
+++ mist_5200/atari800core_mist.vhd	(revision 177)
@@ -0,0 +1,741 @@
+--------------------------------------------------------------------------- -- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all; 
+use ieee.numeric_std.all;
+
+LIBRARY work;
+
+ENTITY atari800core_mist IS 
+	GENERIC
+	(
+		TV : integer;  -- 1 = PAL, 0=NTSC
+		VIDEO : integer; -- 1 = RGB, 2 = VGA
+		COMPOSITE_SYNC : integer; --0 = no, 1 = yes!
+		SCANDOUBLE : integer -- 1 = YES, 0=NO, (+ later scanlines etc)
+	);
+	PORT
+	(
+		CLOCK_27 :  IN  STD_LOGIC_VECTOR(1 downto 0);
+
+		VGA_VS :  OUT  STD_LOGIC;
+		VGA_HS :  OUT  STD_LOGIC;
+		VGA_B :  OUT  STD_LOGIC_VECTOR(5 DOWNTO 0);
+		VGA_G :  OUT  STD_LOGIC_VECTOR(5 DOWNTO 0);
+		VGA_R :  OUT  STD_LOGIC_VECTOR(5 DOWNTO 0);
+		
+		AUDIO_L : OUT std_logic;
+		AUDIO_R : OUT std_logic;
+
+		SDRAM_BA :  OUT  STD_LOGIC_VECTOR(1 downto 0);
+		SDRAM_nCS :  OUT  STD_LOGIC;
+		SDRAM_nRAS :  OUT  STD_LOGIC;
+		SDRAM_nCAS :  OUT  STD_LOGIC;
+		SDRAM_nWE :  OUT  STD_LOGIC;
+		SDRAM_DQMH :  OUT  STD_LOGIC;
+		SDRAM_DQML :  OUT  STD_LOGIC;
+		SDRAM_CLK :  OUT  STD_LOGIC;
+		SDRAM_CKE :  OUT  STD_LOGIC;
+		SDRAM_A :  OUT  STD_LOGIC_VECTOR(12 DOWNTO 0);
+		SDRAM_DQ :  INOUT  STD_LOGIC_VECTOR(15 DOWNTO 0);
+
+		LED : OUT std_logic;
+		
+		UART_TX :  OUT  STD_LOGIC;
+		UART_RX :  IN  STD_LOGIC;
+		
+		SPI_DO :  INOUT  STD_LOGIC;
+		SPI_DI :  IN  STD_LOGIC;
+		SPI_SCK :  IN  STD_LOGIC;
+		SPI_SS2 :  IN  STD_LOGIC;		
+		SPI_SS3 :  IN  STD_LOGIC;		
+		SPI_SS4 :  IN  STD_LOGIC;
+		CONF_DATA0 :  IN  STD_LOGIC -- AKA SPI_SS5
+	);
+END atari800core_mist;
+
+ARCHITECTURE vhdl OF atari800core_mist IS 
+
+component hq_dac
+port (
+  reset :in std_logic;
+  clk :in std_logic;
+  clk_ena : in std_logic;
+  pcm_in : in std_logic_vector(19 downto 0);
+  dac_out : out std_logic
+);
+end component;
+
+component user_io
+	PORT(
+	   SPI_CLK : in std_logic;
+	   SPI_SS_IO : in std_logic;
+	   SPI_MISO : out std_logic;
+	   SPI_MOSI : in std_logic;
+	   CORE_TYPE : in std_logic_vector(7 downto 0);
+		JOY0 : out std_logic_vector(5 downto 0);
+		JOY1 : out std_logic_vector(5 downto 0);
+		BUTTONS : out std_logic_vector(1 downto 0);
+		SWITCHES : out std_logic_vector(1 downto 0);
+		CLK : in std_logic;
+		PS2_CLK : out std_logic;
+		PS2_DATA : out std_logic
+	  );
+end component;
+
+  signal AUDIO_L_PCM : std_logic_vector(15 downto 0);
+  signal AUDIO_R_PCM : std_logic_vector(15 downto 0);
+
+  signal VGA_VS_RAW : std_logic;
+  signal VGA_HS_RAW : std_logic;
+
+  signal RESET_n : std_logic;
+  signal PLL_LOCKED : std_logic;
+  signal CLK : std_logic;
+  signal CLK_SDRAM : std_logic;
+
+  signal CLK_PLL1 : std_logic; -- cascaded to get better pal clock
+  signal PLL1_LOCKED : std_logic;
+
+  SIGNAL PS2_CLK : std_logic;
+  SIGNAL PS2_DAT : std_logic;
+  SIGNAL	CONSOL_OPTION_RAW :  STD_LOGIC;
+  SIGNAL	CONSOL_OPTION :  STD_LOGIC;
+  SIGNAL	CONSOL_SELECT_RAW :  STD_LOGIC;
+  SIGNAL	CONSOL_SELECT :  STD_LOGIC;
+  SIGNAL	CONSOL_START_RAW :  STD_LOGIC;
+  SIGNAL	CONSOL_START :  STD_LOGIC;
+  SIGNAL FKEYS : std_logic_vector(11 downto 0);
+
+  signal capslock_pressed : std_logic;
+  signal capsheld_next : std_logic;
+  signal capsheld_reg : std_logic;
+  
+  signal mist_sector_ready : std_logic;
+  signal mist_sector_ready_sync : std_logic;
+  signal mist_sector_request : std_logic;
+  signal mist_sector_request_sync : std_logic;
+  signal mist_sector_write : std_logic;
+  signal mist_sector_write_sync : std_logic;
+  signal mist_sector : std_logic_vector(25 downto 0);
+  signal mist_sector_sync : std_logic_vector(25 downto 0);
+  
+  		
+  signal mist_addr : std_logic_vector(8 downto 0);
+  signal mist_do : std_logic_vector(7 downto 0);
+  signal mist_di : std_logic_vector(7 downto 0);
+  signal mist_wren : std_logic;
+  
+  signal spi_miso_data : std_logic;
+  signal spi_miso_io : std_logic;
+
+  signal mist_buttons : std_logic_vector(1 downto 0);
+  signal mist_switches : std_logic_vector(1 downto 0);
+
+  signal		JOY1 :  STD_LOGIC_VECTOR(5 DOWNTO 0);
+  signal		JOY2 :  STD_LOGIC_VECTOR(5 DOWNTO 0);
+  signal		JOY1_n :  STD_LOGIC_VECTOR(4 DOWNTO 0);
+  signal		JOY2_n :  STD_LOGIC_VECTOR(4 DOWNTO 0);
+  signal joy_still : std_logic;
+
+  SIGNAL	KEYBOARD_RESPONSE :  STD_LOGIC_VECTOR(1 DOWNTO 0);
+  SIGNAL	KEYBOARD_SCAN :  STD_LOGIC_VECTOR(5 DOWNTO 0);
+
+  SIGNAL PAL : std_logic;
+  SIGNAL COMPOSITE_ON_HSYNC : std_logic;
+  SIGNAL VGA : std_logic;
+
+  signal SDRAM_REQUEST : std_logic;
+  signal SDRAM_REQUEST_COMPLETE : std_logic;
+  signal SDRAM_READ_ENABLE :  STD_LOGIC;
+  signal SDRAM_WRITE_ENABLE : std_logic;
+  signal SDRAM_ADDR : STD_LOGIC_VECTOR(22 DOWNTO 0);
+  signal SDRAM_DO : STD_LOGIC_VECTOR(31 DOWNTO 0);
+  signal SDRAM_DI : STD_LOGIC_VECTOR(31 DOWNTO 0);
+  signal SDRAM_WIDTH_8bit_ACCESS : std_logic;
+  signal SDRAM_WIDTH_16bit_ACCESS : std_logic;
+  signal SDRAM_WIDTH_32bit_ACCESS : std_logic;
+
+  signal SDRAM_REFRESH : std_logic;
+  
+  signal SDRAM_RESET_N : std_logic;
+
+	-- dma/virtual drive
+	signal DMA_ADDR_FETCH : std_logic_vector(23 downto 0);
+	signal DMA_WRITE_DATA : std_logic_vector(31 downto 0);
+	signal DMA_FETCH : std_logic;
+	signal DMA_32BIT_WRITE_ENABLE : std_logic;
+	signal DMA_16BIT_WRITE_ENABLE : std_logic;
+	signal DMA_8BIT_WRITE_ENABLE : std_logic;
+	signal DMA_READ_ENABLE : std_logic;
+	signal DMA_MEMORY_READY : std_logic;
+	signal DMA_MEMORY_DATA : std_logic_vector(31 downto 0);
+
+	signal ZPU_ADDR_ROM : std_logic_vector(15 downto 0);
+	signal ZPU_ROM_DATA :  std_logic_vector(31 downto 0);
+
+	signal ZPU_OUT1 : std_logic_vector(31 downto 0);
+	signal ZPU_OUT2 : std_logic_vector(31 downto 0);
+	signal ZPU_OUT3 : std_logic_vector(31 downto 0);
+	signal ZPU_OUT4 : std_logic_vector(31 downto 0);
+
+	signal zpu_pokey_enable : std_logic;
+	signal zpu_sio_txd : std_logic;
+	signal zpu_sio_rxd : std_logic;
+	signal zpu_sio_command : std_logic;
+
+	-- system control from zpu
+	signal ram_select : std_logic_vector(2 downto 0);
+	signal rom_select : std_logic_vector(5 downto 0);
+	signal reset_atari : std_logic;
+	signal pause_atari : std_logic;
+	SIGNAL speed_6502 : std_logic_vector(5 downto 0);
+
+	-- mist sector
+	signal ZPU_ROM_DATA_MUX :  std_logic_vector(31 downto 0);
+	signal ZPU_SECTOR_DATA :  std_logic_vector(31 downto 0);
+	signal ZPU_ROM_DO :  std_logic_vector(31 downto 0);
+	signal ZPU_ROM_WREN :  std_logic;
+
+	-- ps2
+	signal SLOW_PS2_CLK : std_logic; -- around 16KHz
+
+	-- scandoubler
+	signal half_scandouble_enable_reg : std_logic;
+	signal half_scandouble_enable_next : std_logic;
+	signal VIDEO_B : std_logic_vector(7 downto 0);
+
+BEGIN 
+pal <= '1' when tv=1 else '0';
+vga <= '1' when video=2 else '0';
+composite_on_hsync <= '1' when composite_sync=1 else '0';
+
+-- mist spi io
+mist_spi_interface : entity work.data_io 
+	PORT map
+	(
+		CLK =>spi_sck,
+		RESET_n =>reset_n,
+		
+		-- SPI connection - up to upstream to make miso 'Z' on ss_io going high
+		SPI_CLK =>spi_sck,
+		SPI_SS_IO => spi_ss2,
+		SPI_MISO => spi_miso_data,
+		SPI_MOSI => spi_di,
+		
+		-- Sector access request
+		read_request => mist_sector_request_sync,
+		write_request => mist_sector_write_sync,
+		--request => mist_sector_request_sync,
+		sector => mist_sector_sync(25 downto 0),
+		ready => mist_sector_ready,
+		
+		-- DMA to RAM
+		ADDR => mist_addr,
+		DATA_OUT => mist_do,
+		DATA_IN => mist_di,
+		WR_EN => mist_wren
+	 );
+ 
+	-- TODO, review if these are all needed when ZPU connected again...
+	select_sync : entity work.synchronizer
+	PORT MAP ( CLK => clk, raw => mist_sector_ready, sync=>mist_sector_ready_sync);
+
+	select_sync2 : entity work.synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector_request, sync=>mist_sector_request_sync);
+
+	select_sync3 : entity work.synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector_write, sync=>mist_sector_write_sync);
+
+	sector_sync0 : entity work.synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(0), sync=>mist_sector_sync(0));
+
+	sector_sync1 : entity work.synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(1), sync=>mist_sector_sync(1));
+
+	sector_sync2 : entity work.synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(2), sync=>mist_sector_sync(2));
+
+	sector_sync3 : entity work.synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(3), sync=>mist_sector_sync(3));
+
+	sector_sync4 : entity work.synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(4), sync=>mist_sector_sync(4));
+
+	sector_sync5 : entity work.synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(5), sync=>mist_sector_sync(5));
+
+	sector_sync6 : entity work.synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(6), sync=>mist_sector_sync(6));
+
+	sector_sync7 : entity work.synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(7), sync=>mist_sector_sync(7));
+
+	sector_sync8 : entity work.synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(8), sync=>mist_sector_sync(8));
+
+	sector_sync9 : entity work.synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(9), sync=>mist_sector_sync(9));
+
+	sector_sync10 : entity work.synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(10), sync=>mist_sector_sync(10));
+
+	sector_sync11 : entity work.synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(11), sync=>mist_sector_sync(11));
+
+	sector_sync12 : entity work.synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(12), sync=>mist_sector_sync(12));
+
+	sector_sync13 : entity work.synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(13), sync=>mist_sector_sync(13));
+
+	sector_sync14 : entity work.synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(14), sync=>mist_sector_sync(14));
+
+	sector_sync15 : entity work.synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(15), sync=>mist_sector_sync(15));
+
+	sector_sync16 : entity work.synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(16), sync=>mist_sector_sync(16));
+
+	sector_sync17 : entity work.synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(17), sync=>mist_sector_sync(17));
+
+	sector_sync18 : entity work.synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(18), sync=>mist_sector_sync(18));
+
+	sector_sync19 : entity work.synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(19), sync=>mist_sector_sync(19));
+
+	sector_sync20 : entity work.synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(20), sync=>mist_sector_sync(20));
+
+	sector_sync21 : entity work.synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(21), sync=>mist_sector_sync(21));
+
+	sector_sync22 : entity work.synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(22), sync=>mist_sector_sync(22));
+
+	sector_sync23 : entity work.synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(23), sync=>mist_sector_sync(23));
+
+	sector_sync24 : entity work.synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(24), sync=>mist_sector_sync(24));
+
+	sector_sync25 : entity work.synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(25), sync=>mist_sector_sync(25));
+	
+	
+	spi_do <= spi_miso_io when CONF_DATA0 ='0' else spi_miso_data when spi_SS2='0' else 'Z';
+
+mist_sector_buffer1 : entity work.mist_sector_buffer
+	PORT map
+	(
+		address_a		=> mist_addr,
+		address_b		=> zpu_addr_rom(8 downto 2),
+		clock_a		=> spi_sck,
+		clock_b		=> clk,
+		data_a		=> mist_do,
+		data_b		=> dma_write_data(7 downto 0)&dma_write_data(15 downto 8)&dma_write_data(23 downto 16)&dma_write_data(31 downto 24),
+		wren_a		=> mist_wren,
+		wren_b		=> zpu_rom_wren, 
+		q_a		=> mist_di,
+		q_b		=> zpu_sector_data
+	);
+	
+my_user_io : user_io
+	PORT map(
+	   SPI_CLK => SPI_SCK,
+	   SPI_SS_IO => CONF_DATA0,
+	   SPI_MISO => SPI_miso_io,
+	   SPI_MOSI => SPI_DI,
+	   CORE_TYPE => x"A4",
+		JOY0 => joy2,
+		JOY1 => joy1,
+		BUTTONS => mist_buttons,
+		SWITCHES => mist_switches,
+		CLK => SLOW_PS2_CLK,
+		PS2_CLK => ps2_clk,
+		PS2_DATA => ps2_dat
+	  );
+	  
+	 joy1_n <= not(joy1(4 downto 0));
+	 joy2_n <= not(joy2(4 downto 0));
+
+-- PS2 to pokey
+keyboard_map1 : entity work.ps2_to_atari800
+	PORT MAP
+	( 
+		CLK => clk,
+		RESET_N => reset_n,
+		PS2_CLK => ps2_clk,
+		PS2_DAT => ps2_dat,
+		
+		KEYBOARD_SCAN => KEYBOARD_SCAN,
+		KEYBOARD_RESPONSE => KEYBOARD_RESPONSE,
+
+		CONSOL_START => CONSOL_START_RAW,
+		CONSOL_SELECT => CONSOL_SELECT_RAW,
+		CONSOL_OPTION => CONSOL_OPTION_RAW,
+		
+		FKEYS => FKEYS
+	);
+
+CONSOL_START <= CONSOL_START_RAW or (mist_buttons(1) and not(joy1_n(4)));
+joy_still <= joy1_n(3) and joy1_n(2) and joy1_n(1) and joy1_n(0);
+CONSOL_SELECT <= CONSOL_SELECT_RAW or (mist_buttons(1) and joy1_n(4) and not(joy_still));
+CONSOL_OPTION <= CONSOL_OPTION_RAW or (mist_buttons(1) and joy1_n(4) and joy_still);
+	 
+dac_left : hq_dac
+port map
+(
+  reset => not(reset_n),
+  clk => clk,
+  clk_ena => '1',
+  pcm_in => AUDIO_L_PCM&"0000",
+  dac_out => audio_l
+);
+
+dac_right : hq_dac
+port map
+(
+  reset => not(reset_n),
+  clk => clk,
+  clk_ena => '1',
+  pcm_in => AUDIO_R_PCM&"0000",
+  dac_out => audio_r
+);
+
+gen_ntsc_pll : if tv=0 generate
+mist_pll : entity work.pll_ntsc
+PORT MAP(inclk0 => CLOCK_27(0),
+		 c0 => CLK_SDRAM,
+		 c1 => CLK,
+		 c2 => SDRAM_CLK,
+		 c3 => SLOW_PS2_CLK,
+		 locked => PLL_LOCKED);
+end generate;
+
+gen_pal_pll : if tv=1 generate
+mist_pll : entity work.pll_pal_pre
+PORT MAP(inclk0 => CLOCK_27(0),
+		 c0 => CLK_PLL1,
+		 locked => PLL1_LOCKED);
+mist_pll2 : entity work.pll_pal_post
+PORT MAP(inclk0 => CLK_PLL1,
+		 c0 => CLK_SDRAM,
+		 c1 => CLK,
+		 c2 => SDRAM_CLK,
+		 c3 => SLOW_PS2_CLK,
+		 areset => not(PLL1_LOCKED),
+		 locked => PLL_LOCKED);
+end generate;
+
+reset_n <= PLL_LOCKED;
+
+atari5200_test : entity work.atari5200core_simplesdram
+	GENERIC MAP
+	(
+		cycle_length => 32,
+		--internal_rom => 4, --5200 rom...
+		internal_rom => 0, --5200 rom...
+		internal_ram => 0, -- only 1 option for 5200...
+		video_bits => 8,
+		palette => 0
+	)
+	PORT MAP
+	(
+		CLK => CLK,
+		RESET_N => RESET_N and SDRAM_RESET_N and not(reset_atari),
+
+		VIDEO_VS => VGA_VS_RAW,
+		VIDEO_HS => VGA_HS_RAW,
+		VIDEO_B => VIDEO_B,
+		VIDEO_G => open,
+		VIDEO_R => open,
+
+		AUDIO_L => AUDIO_L_PCM,
+		AUDIO_R => AUDIO_R_PCM,
+
+		SDRAM_REQUEST => SDRAM_REQUEST,
+		SDRAM_REQUEST_COMPLETE => SDRAM_REQUEST_COMPLETE,
+		SDRAM_READ_ENABLE => SDRAM_READ_ENABLE,
+		SDRAM_WRITE_ENABLE => SDRAM_WRITE_ENABLE,
+		SDRAM_ADDR => SDRAM_ADDR,
+		SDRAM_DO => SDRAM_DO,
+		SDRAM_DI => SDRAM_DI,
+		SDRAM_32BIT_WRITE_ENABLE => SDRAM_WIDTH_32bit_ACCESS,
+		SDRAM_16BIT_WRITE_ENABLE => SDRAM_WIDTH_16bit_ACCESS,
+		SDRAM_8BIT_WRITE_ENABLE => SDRAM_WIDTH_8bit_ACCESS,
+		SDRAM_REFRESH => SDRAM_REFRESH,
+
+		DMA_FETCH => dma_fetch,
+		DMA_READ_ENABLE => dma_read_enable,
+		DMA_32BIT_WRITE_ENABLE => dma_32bit_write_enable,
+		DMA_16BIT_WRITE_ENABLE => dma_16bit_write_enable,
+		DMA_8BIT_WRITE_ENABLE => dma_8bit_write_enable,
+		DMA_ADDR => dma_addr_fetch,
+		DMA_WRITE_DATA => dma_write_data,
+		MEMORY_READY_DMA => dma_memory_ready,
+		DMA_MEMORY_DATA => dma_memory_data, 
+
+		THROTTLE_COUNT_6502 => speed_6502,
+		HALT => pause_atari
+
+		-- JOYSTICK
+		--JOY1_n : IN std_logic_vector(4 downto 0); -- FRLDU, 0=pressed
+		--JOY2_n : IN std_logic_vector(4 downto 0); -- FRLDU, 0=pressed
+
+		-- KEYBOARD
+		--PS2_CLK : IN STD_LOGIC;
+		--PS2_DAT : IN STD_LOGIC;
+	);
+
+--atarixl_simple_sdram1 : entity work.atari800core_simple_sdram
+--	GENERIC MAP
+--	(
+--		cycle_length => 32,
+--		internal_rom => 0,
+--		internal_ram => 0,
+--		video_bits => 8,
+--		palette => 0
+--	)
+--	PORT MAP
+--	(
+--		CLK => CLK,
+--		RESET_N => RESET_N and SDRAM_RESET_N and not(reset_atari),
+--
+--		VIDEO_VS => VGA_VS_RAW,
+--		VIDEO_HS => VGA_HS_RAW,
+--		VIDEO_B => VIDEO_B,
+--		VIDEO_G => open,
+--		VIDEO_R => open,
+--
+--		AUDIO_L => AUDIO_L_PCM,
+--		AUDIO_R => AUDIO_R_PCM,
+--
+--		JOY1_n => JOY1_n(4)&JOY1_n(0)&JOY1_n(1)&JOY1_n(2)&JOY1_n(3),
+--		JOY2_n => JOY2_n(4)&JOY2_n(0)&JOY2_n(1)&JOY2_n(2)&JOY2_n(3),
+--
+--		KEYBOARD_RESPONSE => KEYBOARD_RESPONSE,
+--		KEYBOARD_SCAN => KEYBOARD_SCAN,
+--
+--		SIO_COMMAND => zpu_sio_command,
+--		SIO_RXD => zpu_sio_txd,
+--		SIO_TXD => zpu_sio_rxd,
+--
+--		CONSOL_OPTION => CONSOL_OPTION,
+--		CONSOL_SELECT => CONSOL_SELECT,
+--		CONSOL_START => CONSOL_START,
+--
+--		SDRAM_REQUEST => SDRAM_REQUEST,
+--		SDRAM_REQUEST_COMPLETE => SDRAM_REQUEST_COMPLETE,
+--		SDRAM_READ_ENABLE => SDRAM_READ_ENABLE,
+--		SDRAM_WRITE_ENABLE => SDRAM_WRITE_ENABLE,
+--		SDRAM_ADDR => SDRAM_ADDR,
+--		SDRAM_DO => SDRAM_DO,
+--		SDRAM_DI => SDRAM_DI,
+--		SDRAM_32BIT_WRITE_ENABLE => SDRAM_WIDTH_32bit_ACCESS,
+--		SDRAM_16BIT_WRITE_ENABLE => SDRAM_WIDTH_16bit_ACCESS,
+--		SDRAM_8BIT_WRITE_ENABLE => SDRAM_WIDTH_8bit_ACCESS,
+--		SDRAM_REFRESH => SDRAM_REFRESH,
+--
+--		DMA_FETCH => dma_fetch,
+--		DMA_READ_ENABLE => dma_read_enable,
+--		DMA_32BIT_WRITE_ENABLE => dma_32bit_write_enable,
+--		DMA_16BIT_WRITE_ENABLE => dma_16bit_write_enable,
+--		DMA_8BIT_WRITE_ENABLE => dma_8bit_write_enable,
+--		DMA_ADDR => dma_addr_fetch,
+--		DMA_WRITE_DATA => dma_write_data,
+--		MEMORY_READY_DMA => dma_memory_ready,
+--		DMA_MEMORY_DATA => dma_memory_data, 
+--
+--   		RAM_SELECT => ram_select,
+--    		ROM_SELECT => rom_select,
+--		PAL => PAL,
+--		HALT => pause_atari,
+--		THROTTLE_COUNT_6502 => speed_6502
+--	);
+
+sdram_adaptor : entity work.sdram_statemachine
+GENERIC MAP(ADDRESS_WIDTH => 22,
+			AP_BIT => 10,
+			COLUMN_WIDTH => 8,
+			ROW_WIDTH => 12
+			)
+PORT MAP(CLK_SYSTEM => CLK,
+		 CLK_SDRAM => CLK_SDRAM,
+		 RESET_N =>  RESET_N,
+		 READ_EN => SDRAM_READ_ENABLE,
+		 WRITE_EN => SDRAM_WRITE_ENABLE,
+		 REQUEST => SDRAM_REQUEST,
+		 BYTE_ACCESS => SDRAM_WIDTH_8BIT_ACCESS,
+		 WORD_ACCESS => SDRAM_WIDTH_16BIT_ACCESS,
+		 LONGWORD_ACCESS => SDRAM_WIDTH_32BIT_ACCESS,
+		 REFRESH => SDRAM_REFRESH,
+		 ADDRESS_IN => SDRAM_ADDR,
+		 DATA_IN => SDRAM_DI,
+		 SDRAM_DQ => SDRAM_DQ,
+		 COMPLETE => SDRAM_REQUEST_COMPLETE,
+		 SDRAM_BA0 => SDRAM_BA(0),
+		 SDRAM_BA1 => SDRAM_BA(1),
+		 SDRAM_CKE => SDRAM_CKE,
+		 SDRAM_CS_N => SDRAM_nCS,
+		 SDRAM_RAS_N => SDRAM_nRAS,
+		 SDRAM_CAS_N => SDRAM_nCAS,
+		 SDRAM_WE_N => SDRAM_nWE,
+		 SDRAM_ldqm => SDRAM_DQML,
+		 SDRAM_udqm => SDRAM_DQMH,
+		 DATA_OUT => SDRAM_DO,
+		 SDRAM_ADDR => SDRAM_A(11 downto 0),
+		 reset_client_n => SDRAM_RESET_N
+		 );
+		 
+SDRAM_A(12) <= '0';
+--SDRAM_REFRESH <= '0'; -- TODO
+
+-- Until SDRAM enabled... TODO
+--SDRAM_nCS <= '1';
+--SDRAM_DQ <= (others=>'Z');
+
+--SDRAM_CKE <= '1';		 
+LED <= zpu_sio_rxd;
+
+--VGA_HS <= not(VGA_HS_RAW xor VGA_VS_RAW);
+--VGA_VS <= not(VGA_VS_RAW);
+
+	process(clk,RESET_N,SDRAM_RESET_N,reset_atari)
+	begin
+		if ((RESET_N and SDRAM_RESET_N and not(reset_atari))='0') then
+			half_scandouble_enable_reg <= '0';
+		elsif (clk'event and clk='1') then
+			half_scandouble_enable_reg <= half_scandouble_enable_next;
+		end if;
+	end process;
+
+	half_scandouble_enable_next <= not(half_scandouble_enable_reg);
+
+	scandoubler1: entity work.scandoubler
+	GENERIC MAP
+	(
+		video_bits=>6
+	)
+	PORT MAP
+	( 
+		CLK => CLK,
+		RESET_N => RESET_N and SDRAM_RESET_N and not(reset_atari),
+		
+		VGA => vga,
+		COMPOSITE_ON_HSYNC => composite_on_hsync,
+
+		colour_enable => half_scandouble_enable_reg,
+		doubled_enable => '1',
+		scanlines_on => mist_switches(1),
+		
+		-- GTIA interface
+		colour_in => VIDEO_B,
+		vsync_in => VGA_VS_RAW,
+		hsync_in => VGA_HS_RAW,
+		
+		-- TO TV...
+		R => VGA_R,
+		G => VGA_G,
+		B => VGA_B,
+		
+		VSYNC => VGA_VS,
+		HSYNC => VGA_HS
+	);
+
+zpu: entity work.zpucore
+	GENERIC MAP
+	(
+		platform => 1,
+		spi_clock_div => 1 -- 28MHz/2. Max for SD cards is 25MHz...
+	)
+	PORT MAP
+	(
+		-- standard...
+		CLK => CLK,
+		RESET_N => RESET_N and sdram_reset_n,
+
+		-- dma bus master (with many waitstates...)
+		ZPU_ADDR_FETCH => dma_addr_fetch,
+		ZPU_DATA_OUT => dma_write_data,
+		ZPU_FETCH => dma_fetch,
+		ZPU_32BIT_WRITE_ENABLE => dma_32bit_write_enable,
+		ZPU_16BIT_WRITE_ENABLE => dma_16bit_write_enable,
+		ZPU_8BIT_WRITE_ENABLE => dma_8bit_write_enable,
+		ZPU_READ_ENABLE => dma_read_enable,
+		ZPU_MEMORY_READY => dma_memory_ready,
+		ZPU_MEMORY_DATA => dma_memory_data, 
+
+		-- rom bus master
+		-- data on next cycle after addr
+		ZPU_ADDR_ROM => zpu_addr_rom,
+		ZPU_ROM_DATA => zpu_rom_data_mux,
+	
+		ZPU_ROM_WREN => zpu_rom_wren, -- special for mist...
+
+		-- spi master
+		-- not used for mist...
+		ZPU_SD_DAT0 => '0',
+		ZPU_SD_CLK => open,
+		ZPU_SD_CMD => open,
+		ZPU_SD_DAT3 => open,
+
+		-- SIO
+		-- Ditto for speaking to Atari, we have a built in Pokey
+		ZPU_POKEY_ENABLE => zpu_pokey_enable,
+		ZPU_SIO_TXD => zpu_sio_txd,
+		ZPU_SIO_RXD => zpu_sio_rxd,
+		ZPU_SIO_COMMAND => zpu_sio_command,
+
+		-- external control
+		-- switches etc. sector DMA blah blah.
+		ZPU_IN1 => X"00000"&(FKEYS(11) or (mist_buttons(0) and not(joy1_n(4))))&(FKEYS(10) or (mist_buttons(0) and joy1_n(4) and joy_still))&(FKEYS(9) or (mist_buttons(0) and joy1_n(4) and not(joy_still)))&FKEYS(8 downto 0),
+		ZPU_IN2 => X"00000000",
+		ZPU_IN3 => X"00000000",
+		ZPU_IN4 => X"000000"&"0000000"&mist_sector_ready_sync,
+
+		-- ouputs - e.g. Atari system control, halt, throttle, rom select
+		ZPU_OUT1 => zpu_out1,
+		ZPU_OUT2 => zpu_out2,
+		ZPU_OUT3 => zpu_out3,
+		ZPU_OUT4 => zpu_out4
+	);
+
+	mist_sector <= zpu_out4(25 downto 0);
+	mist_sector_request <= zpu_out4(26);
+	mist_sector_write <= zpu_out4(27);
+
+	pause_atari <= zpu_out1(0);
+	reset_atari <= zpu_out1(1);
+	speed_6502 <= zpu_out1(7 downto 2);
+	ram_select <= zpu_out1(10 downto 8);
+	rom_select <= zpu_out1(16 downto 11);
+
+zpu_rom1: entity work.zpu_rom
+	port map(
+	        clock => clk,
+	        address => zpu_addr_rom(13 downto 2),
+	        q => zpu_rom_data
+	);
+
+process(zpu_addr_rom, zpu_rom_data, zpu_sector_data)
+begin
+	zpu_rom_data_mux <= zpu_rom_data;
+	if (zpu_addr_rom(15 downto 14) = "01") then
+		zpu_rom_data_mux <= zpu_sector_data(7 downto 0)&zpu_sector_data(15 downto 8)&zpu_sector_data(23 downto 16)&zpu_sector_data(31 downto 24);
+	end if;
+end process;
+
+enable_179_clock_div_zpu_pokey : entity work.enable_divider
+	generic map (COUNT=>32) -- cycle_length
+	port map(clk=>clk,reset_n=>reset_n,enable_in=>'1',enable_out=>zpu_pokey_enable);
+
+END vhdl;
Index: mist_5200/build.sh
===================================================================
--- mist_5200/build.sh	(nonexistent)
+++ mist_5200/build.sh	(revision 177)
@@ -0,0 +1,105 @@
+#!/usr/bin/perl -w
+use strict;
+
+my $wanted_variant = shift @ARGV;
+
+#variants...
+my $PAL = 1;
+my $NTSC = 0;
+
+my $RGB = 1; # i.e. not scandoubled
+my $VGA = 2;
+
+#Added like this to the generated qsf
+#set_parameter -name TV 1
+
+my %variants = 
+(
+	"PAL_RGB" => 
+	{
+		"TV" => $PAL,
+		"SCANDOUBLE" => 0,
+		"VIDEO" => $RGB,
+		"COMPOSITE_SYNC" => 1
+	},
+	"PAL_VGA" =>
+	{
+		"TV" => $PAL,
+		"SCANDOUBLE" => 1,
+		"VIDEO" => $VGA,
+		"COMPOSITE_SYNC" => 0
+	},
+	"PAL_VGA_CS" =>
+	{
+		"TV" => $PAL,
+		"SCANDOUBLE" => 1,
+		"VIDEO" => $VGA,
+		"COMPOSITE_SYNC" => 1
+	},
+	"NTSC_RGB" =>
+	{
+		"TV" => $NTSC,
+		"SCANDOUBLE" => 0,
+		"VIDEO" => $RGB, 
+		"COMPOSITE_SYNC" => 1
+	},
+	"NTSC_VGA" => 
+	{
+		"TV" => $NTSC,
+		"SCANDOUBLE" => 1,
+		"VIDEO" => $VGA,
+		"COMPOSITE_SYNC" => 0
+	},
+	"NTSC_VGA_CS" => 
+	{
+		"TV" => $NTSC,
+		"SCANDOUBLE" => 1,
+		"VIDEO" => $VGA,
+		"COMPOSITE_SYNC" => 1
+	}
+);
+
+if (not defined $wanted_variant or (not exists $variants{$wanted_variant} and $wanted_variant ne "ALL"))
+{
+	die "Provide variant of ALL or ".join ",",sort keys %variants;
+}
+
+foreach my $variant (sort keys %variants)
+{
+	next if ($wanted_variant ne $variant and $wanted_variant ne "ALL");
+	print "Building $variant\n";
+
+	my $dir = "build_$variant";
+	`rm -rf $dir`;
+	mkdir $dir;
+	`cp atari800core_mist.vhd $dir`;
+	`cp *pll*.* $dir`;
+	`cp *mist_sector*.* $dir`;
+	`cp *.v $dir`;
+	`cp *.vhdl $dir`;
+	`cp zpu_rom.vhdl $dir`;
+	`cp atari800core.sdc $dir`;
+	`mkdir $dir/common`;
+	`mkdir $dir/common/a8core`;
+	`mkdir $dir/common/components`;
+	`mkdir $dir/common/zpu`;
+	`cp ../common/a8core/* ./$dir/common/a8core`;
+	`cp ../common/components/* ./$dir/common/components`;
+	`cp ../common/zpu/* ./$dir/common/zpu`;
+
+	chdir $dir;
+	`../makeqsf ../atari800core.qsf ./common/a8core ./common/components ./common/zpu`;
+
+	foreach my $key (sort keys %{$variants{$variant}})
+	{
+		my $val = $variants{$variant}->{$key};
+		`echo set_parameter -name $key $val >> atari800core.qsf`;
+	}
+
+	`quartus_sh --flow compile atari800core > build.log 2> build.err`;
+
+	`quartus_cpf --convert ../output_file.cof`;
+	
+	chdir "..";
+}
+

Property changes on: mist_5200/build.sh
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: mist_5200/data_io.cmd
===================================================================
--- mist_5200/data_io.cmd	(nonexistent)
+++ mist_5200/data_io.cmd	(revision 177)
@@ -0,0 +1,6 @@
+#onerror {resume}
+# GAME
+#=====================
+#run 18871970 ns
+#isim force add {/replay_tb/uut/tpp2/cpu/dd_s} 11111111 -radix bin -cancel 250 ns 
+#run 200 ms
Index: mist_5200/data_io.vhdl
===================================================================
--- mist_5200/data_io.vhdl	(nonexistent)
+++ mist_5200/data_io.vhdl	(revision 177)
@@ -0,0 +1,236 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all; 
+use ieee.numeric_std.all;
+
+LIBRARY work;
+
+ENTITY data_io IS 
+	PORT
+	(
+		CLK : in std_logic;
+		RESET_n : in std_logic;
+		
+		-- SPI connection - up to upstream to make miso 'Z' on ss_io going high
+	   SPI_CLK : in std_logic;
+	   SPI_SS_IO : in std_logic;
+	   SPI_MISO: out std_logic;
+	   SPI_MOSI : in std_logic;
+		
+		-- Sector access read_request
+		read_request : in std_logic;
+		write_request : in std_logic;
+		sector : in std_logic_vector(25 downto 0);
+		ready : out std_logic;
+		
+		-- DMA to RAM
+		ADDR: out std_logic_vector(8 downto 0);
+		DATA_OUT : out std_logic_vector(7 downto 0);
+		DATA_IN : in std_logic_vector(7 downto 0);
+		WR_EN : out std_logic
+	 );
+end data_io;
+
+architecture vhdl of data_io is
+
+
+   signal sbuf_next : std_logic_vector(6 downto 0);
+	signal sbuf_reg : std_logic_vector(6 downto 0);
+	
+   signal cmd_next : std_logic_vector(7 downto 0);
+	signal cmd_reg : std_logic_vector(7 downto 0);
+	
+	signal cnt_next : std_logic_vector(15 downto 0);
+	signal cnt_reg : std_logic_vector(15 downto 0);
+
+	signal data_in_next : std_logic_vector(7 downto 0);
+	signal data_in_reg : std_logic_vector(7 downto 0);
+
+	signal data_out_next : std_logic_vector(7 downto 0);
+	signal data_out_reg : std_logic_vector(7 downto 0);
+
+	signal addr_next : std_logic_vector(8 downto 0);
+	signal addr_reg : std_logic_vector(8 downto 0);
+
+	signal wren_next : std_logic;
+	signal wren_reg : std_logic;
+
+	signal ready_next : std_logic;
+	signal ready_reg : std_logic;
+	
+	signal transmit_next : std_logic_vector(7 downto 0);
+	signal transmit_reg : std_logic_vector(7 downto 0);
+	
+	signal sector_next : std_logic_vector(25 downto 0);
+	signal sector_reg : std_logic_vector(25 downto 0);
+	
+	signal read_request_next : std_logic;
+	signal read_request_reg : std_logic;
+	
+	signal write_request_next : std_logic;
+	signal write_request_reg : std_logic;
+
+	signal clk2 : std_logic;
+begin	 
+	clk2 <= clk or spi_ss_io;
+
+	process(clk2,reset_n,spi_ss_io)
+	begin
+		if (spi_ss_io = '1') then
+			cnt_reg <= (others=>'0');
+			cmd_reg <= (others=>'0');
+			wren_reg <= '0';
+		elsif (reset_n = '0') then
+			cnt_reg <= (others=>'0');
+			cmd_reg <= (others=>'0');
+			sbuf_reg <= (others=>'0');
+			
+			addr_reg <= (others => '0');
+			data_in_reg <= (others => '0');
+			data_out_reg <= (others => '0');
+			wren_reg <= '0';			
+			
+			ready_reg <= '0';
+			
+			transmit_reg <= (others=>'0');
+			
+			read_request_reg <= '0';
+			write_request_reg <= '0';
+			sector_reg <=(others=>'0');
+		elsif (clk2'event and clk2='1') then
+			cnt_reg <= cnt_next;
+			cmd_reg <= cmd_next;
+			sbuf_reg <= sbuf_next;			
+			
+			addr_reg <= addr_next;
+			data_in_reg <= data_in_next;
+			data_out_reg <= data_out_next;
+			wren_reg <= wren_next;
+			
+			ready_reg <= ready_next;
+		
+			transmit_reg <= transmit_next;
+
+			read_request_reg <= read_request_next;
+			write_request_reg <= write_request_next;
+			sector_reg <= sector_next;			
+		end if;
+	end process;	
+	
+--	clk_sync : synchronizer
+--	PORT MAP ( CLK => clk, raw => spi_clk, sync=>spi_clk_next);
+--spi_clk_next <= spi_clk;
+
+--	input_sync : synchronizer
+--	PORT MAP ( CLK => clk, raw => spi_mosi, sync=>spi_mosi_next);
+
+--	select_sync : synchronizer
+--	PORT MAP ( CLK => clk, raw => spi_ss_io, sync=>spi_ss_next);
+
+	data_in_next <= data_in;
+
+	process(spi_ss_io,cnt_reg, sbuf_reg, transmit_reg, spi_mosi, addr_reg, cmd_reg, sector_reg, write_request_reg, read_request_reg, ready_reg,read_request,write_request,sector,data_in_reg)
+	begin
+		cnt_next <= cnt_reg;
+		sbuf_next <= sbuf_reg;
+		cmd_next <= cmd_reg;
+		ready_next <= ready_reg and (read_request or write_request); -- stay ready until read_request cleared (received by other end)
+		
+		transmit_next <= transmit_reg;
+		
+		wren_next <= '0';
+		data_out_next <= (others=>'0');		
+		addr_next <= addr_reg;
+		
+		sector_next <= sector_reg;
+		read_request_next <= read_request_reg;		
+		write_request_next <= write_request_reg;		
+		
+--- It polls get_status 10 times a second
+--- it uses SPI_SS2 for this
+--- it sends command code 0x50
+--- reads 4 bytes afterwards
+
+--- it reports whenever the returned value is different then the one from previous get_status
+
+--- if the lowest byte of the status (the last transmitted of the four) is 0xa5:
+--- a sector is read from sd card with the sector no being the upper/first three bytes transmitted
+--- if the sector could be read
+--- SPI_SS2 is activated
+--- command byte 0x51 is sent
+--- all 512 sector bytes are sent
+		
+		--if (spi_clk_reg = '1' and spi_clk_next = '0') then
+		transmit_next(7 downto 1) <= transmit_reg(6 downto 0);
+		transmit_next(0) <= '0';
+
+		cnt_next <= std_logic_vector(unsigned(cnt_reg) + 1);		
+		
+		sbuf_next(6 downto 1) <= sbuf_reg(5 downto 0);
+		sbuf_next(0) <= SPI_MOSI;
+
+		if (cnt_reg = X"0000") then
+			addr_next <= (others=>'0');
+		end if;
+			
+		if (cnt_reg = X"0007") then
+			cmd_next(7 downto 1) <= sbuf_reg;
+			cmd_next(0) <= SPI_MOSI;
+			
+			sector_next <= sector;
+			read_request_next <= read_request;		
+			write_request_next <= write_request;		
+		end if;
+			
+		--end if;
+		
+		case cmd_reg is
+		when X"50" => --get status
+			case cnt_reg is 
+			when X"0008" =>
+				transmit_next <= sector_reg(25 downto 18);
+			when X"0010" =>
+				transmit_next <= sector_reg(17 downto 10);
+			when X"0018" =>
+				transmit_next <= sector_reg(9 downto 2);				
+			when X"0020" =>
+				transmit_next <= sector_reg(1 downto 0)&"1010"&write_request_reg&read_request_reg; --read read_request
+			when others =>
+				-- nothing
+			end case;
+		when X"51" => --sector read from sd, write it...
+			if (cnt_reg = X"0008") then
+				addr_next <= (others=>'1');
+			end if;
+			if (cnt_reg(2 downto 0) = "111") then
+				addr_next <= std_logic_vector(unsigned(addr_reg) + 1);
+				data_out_next(7 downto 1) <= sbuf_reg;
+				data_out_next(0) <= SPI_MOSI;
+				wren_next <= read_request;
+				
+				if (cnt_reg(12) = '1')then
+					ready_next <= '1';
+				end if;
+			end if;
+		when X"52" => -- read from write, write to sd
+			if (cnt_reg(2 downto 0) = "000") then
+				addr_next <= std_logic_vector(unsigned(addr_reg) + 1);
+				transmit_next <= data_in_reg;
+				
+				if (cnt_reg(12) = '1')then
+					ready_next <= '1';
+				end if;
+			end if;
+		when others =>
+			-- nop
+		end case;
+	end process;
+
+	-- outputs
+	addr <= addr_next;
+	data_out <= data_out_next;
+	wr_en <= wren_next;
+	
+	ready <= ready_reg;
+
+	spi_miso <= transmit_next(7);
+end vhdl;
Index: mist_5200/data_io.wcfg
===================================================================
--- mist_5200/data_io.wcfg	(nonexistent)
+++ mist_5200/data_io.wcfg	(revision 177)
@@ -0,0 +1,103 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="data_io.wdb" id="1" type="auto">
+         <top_modules>
+            <top_module name="data_io_tb" />
+            <top_module name="numeric_std" />
+            <top_module name="std_logic_1164" />
+            <top_module name="std_logic_arith" />
+            <top_module name="std_logic_textio" />
+            <top_module name="std_logic_unsigned" />
+            <top_module name="textio" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <WVObjectSize size="19" />
+   <wvobject fp_name="/data_io_tb/reset_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">reset_n</obj_property>
+      <obj_property name="ObjectShortName">reset_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/data_io_tb/request" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">request</obj_property>
+      <obj_property name="ObjectShortName">request</obj_property>
+   </wvobject>
+   <wvobject fp_name="/data_io_tb/write" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">write</obj_property>
+      <obj_property name="ObjectShortName">write</obj_property>
+   </wvobject>
+   <wvobject fp_name="/data_io_tb/ready" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">ready</obj_property>
+      <obj_property name="ObjectShortName">ready</obj_property>
+   </wvobject>
+   <wvobject fp_name="/data_io_tb/spi_miso" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">spi_miso</obj_property>
+      <obj_property name="ObjectShortName">spi_miso</obj_property>
+   </wvobject>
+   <wvobject fp_name="/data_io_tb/spi_mosi" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">spi_mosi</obj_property>
+      <obj_property name="ObjectShortName">spi_mosi</obj_property>
+   </wvobject>
+   <wvobject fp_name="/data_io_tb/spi_clk" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">spi_clk</obj_property>
+      <obj_property name="ObjectShortName">spi_clk</obj_property>
+   </wvobject>
+   <wvobject fp_name="/data_io_tb/spi_tx_data" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">spi_tx_data[7:0]</obj_property>
+      <obj_property name="ObjectShortName">spi_tx_data[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/data_io_tb/spi_rx_data" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">spi_rx_data[7:0]</obj_property>
+      <obj_property name="ObjectShortName">spi_rx_data[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/data_io_tb/spi_busy" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">spi_busy</obj_property>
+      <obj_property name="ObjectShortName">spi_busy</obj_property>
+   </wvobject>
+   <wvobject fp_name="/data_io_tb/spi_enable" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">spi_enable</obj_property>
+      <obj_property name="ObjectShortName">spi_enable</obj_property>
+   </wvobject>
+   <wvobject fp_name="/data_io_tb/data_io/cmd_reg" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">cmd_reg[7:0]</obj_property>
+      <obj_property name="ObjectShortName">cmd_reg[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/data_io_tb/data_io/cnt_reg" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">cnt_reg[15:0]</obj_property>
+      <obj_property name="ObjectShortName">cnt_reg[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/data_io_tb/data_io/sbuf_reg" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">sbuf_reg[6:0]</obj_property>
+      <obj_property name="ObjectShortName">sbuf_reg[6:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/data_io_tb/addr" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">addr[8:0]</obj_property>
+      <obj_property name="ObjectShortName">addr[8:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/data_io_tb/data_out" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">data_out[7:0]</obj_property>
+      <obj_property name="ObjectShortName">data_out[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/data_io_tb/data_in" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">data_in[7:0]</obj_property>
+      <obj_property name="ObjectShortName">data_in[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/data_io_tb/wr_en" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">wr_en</obj_property>
+      <obj_property name="ObjectShortName">wr_en</obj_property>
+   </wvobject>
+   <wvobject fp_name="/data_io_tb/spi_ss_io" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">spi_ss_io[1:0]</obj_property>
+      <obj_property name="ObjectShortName">spi_ss_io[1:0]</obj_property>
+   </wvobject>
+</wave_config>
Index: mist_5200/keyboard.JPG
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: mist_5200/keyboard.JPG
___________________________________________________________________
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: mist_5200/makeqsf
===================================================================
--- mist_5200/makeqsf	(nonexistent)
+++ mist_5200/makeqsf	(revision 177)
@@ -0,0 +1,39 @@
+#!/usr/bin/perl -w
+use strict;
+
+my $qsf_in = shift @ARGV;
+my $qsf_out = $qsf_in;
+$qsf_out =~ s/.*\///;
+
+open (QSF_IN,$qsf_in) or die "Failed to open $qsf_in";
+my @qsf_base = <QSF_IN>;
+close (QSF_IN);
+
+open (QSF_OUT,">$qsf_out") or die "Failed to open $qsf_out";
+print QSF_OUT @qsf_base;
+
+foreach (@ARGV)
+{
+	my @vhdl = glob ("$_/*.vhd");
+	push @vhdl, glob ("$_/*.vhdl");
+	my @verilog = glob ("$_/*.v");
+	my @qip = glob ("$_/*.qip");
+
+	foreach (@verilog)
+	{
+		print QSF_OUT "set_global_assignment -name VERILOG_FILE $_\n";
+	}
+
+	foreach (@vhdl)
+	{
+		print QSF_OUT "set_global_assignment -name VHDL_FILE $_\n";
+	}
+
+	foreach (@qip)
+	{
+		print QSF_OUT "set_global_assignment -name QIP_FILE $_\n";
+	}
+}
+
+close (QSF_OUT);
+

Property changes on: mist_5200/makeqsf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: mist_5200/mist_sector_buffer.cmp
===================================================================
--- mist_5200/mist_sector_buffer.cmp	(nonexistent)
+++ mist_5200/mist_sector_buffer.cmp	(revision 177)
@@ -0,0 +1,30 @@
+--Copyright (C) 1991-2012 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component mist_sector_buffer
+	PORT
+	(
+		address_a		: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
+		address_b		: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
+		clock_a		: IN STD_LOGIC  := '1';
+		clock_b		: IN STD_LOGIC ;
+		data_a		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data_b		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		wren_a		: IN STD_LOGIC  := '0';
+		wren_b		: IN STD_LOGIC  := '0';
+		q_a		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+		q_b		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+end component;
Index: mist_5200/mist_sector_buffer.qip
===================================================================
--- mist_5200/mist_sector_buffer.qip	(nonexistent)
+++ mist_5200/mist_sector_buffer.qip	(revision 177)
@@ -0,0 +1,4 @@
+set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
+set_global_assignment -name IP_TOOL_VERSION "12.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "mist_sector_buffer.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "mist_sector_buffer.cmp"]
Index: mist_5200/mist_sector_buffer.vhd
===================================================================
--- mist_5200/mist_sector_buffer.vhd	(nonexistent)
+++ mist_5200/mist_sector_buffer.vhd	(revision 177)
@@ -0,0 +1,270 @@
+-- megafunction wizard: %RAM: 2-PORT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram 
+
+-- ============================================================
+-- File Name: mist_sector_buffer.vhd
+-- Megafunction Name(s):
+-- 			altsyncram
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 12.1 Build 243 01/31/2013 SP 1.33 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2012 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY mist_sector_buffer IS
+	PORT
+	(
+		address_a		: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
+		address_b		: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
+		clock_a		: IN STD_LOGIC  := '1';
+		clock_b		: IN STD_LOGIC ;
+		data_a		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data_b		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		wren_a		: IN STD_LOGIC  := '0';
+		wren_b		: IN STD_LOGIC  := '0';
+		q_a		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+		q_b		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+END mist_sector_buffer;
+
+
+ARCHITECTURE SYN OF mist_sector_buffer IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (31 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		address_reg_b		: STRING;
+		clock_enable_input_a		: STRING;
+		clock_enable_input_b		: STRING;
+		clock_enable_output_a		: STRING;
+		clock_enable_output_b		: STRING;
+		indata_reg_b		: STRING;
+		intended_device_family		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		numwords_b		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_aclr_b		: STRING;
+		outdata_reg_a		: STRING;
+		outdata_reg_b		: STRING;
+		power_up_uninitialized		: STRING;
+		read_during_write_mode_port_a		: STRING;
+		read_during_write_mode_port_b		: STRING;
+		widthad_a		: NATURAL;
+		widthad_b		: NATURAL;
+		width_a		: NATURAL;
+		width_b		: NATURAL;
+		width_byteena_a		: NATURAL;
+		width_byteena_b		: NATURAL;
+		wrcontrol_wraddress_reg_b		: STRING
+	);
+	PORT (
+			clock0	: IN STD_LOGIC ;
+			wren_a	: IN STD_LOGIC ;
+			address_b	: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
+			clock1	: IN STD_LOGIC ;
+			data_b	: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+			q_a	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+			wren_b	: IN STD_LOGIC ;
+			address_a	: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
+			data_a	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+			q_b	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q_a    <= sub_wire0(7 DOWNTO 0);
+	q_b    <= sub_wire1(31 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_reg_b => "CLOCK1",
+		clock_enable_input_a => "BYPASS",
+		clock_enable_input_b => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		clock_enable_output_b => "BYPASS",
+		indata_reg_b => "CLOCK1",
+		intended_device_family => "Cyclone III",
+		lpm_type => "altsyncram",
+		numwords_a => 512,
+		numwords_b => 128,
+		operation_mode => "BIDIR_DUAL_PORT",
+		outdata_aclr_a => "NONE",
+		outdata_aclr_b => "NONE",
+		outdata_reg_a => "UNREGISTERED",
+		outdata_reg_b => "UNREGISTERED",
+		power_up_uninitialized => "FALSE",
+		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
+		read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
+		widthad_a => 9,
+		widthad_b => 7,
+		width_a => 8,
+		width_b => 32,
+		width_byteena_a => 1,
+		width_byteena_b => 1,
+		wrcontrol_wraddress_reg_b => "CLOCK1"
+	)
+	PORT MAP (
+		clock0 => clock_a,
+		wren_a => wren_a,
+		address_b => address_b,
+		clock1 => clock_b,
+		data_b => data_b,
+		wren_b => wren_b,
+		address_a => address_a,
+		data_a => data_a,
+		q_a => sub_wire0,
+		q_b => sub_wire1
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock NUMERIC "5"
+-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "4096"
+-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING ""
+-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
+-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
+-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
+-- Retrieval info: PRIVATE: REGq NUMERIC "0"
+-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
+-- Retrieval info: PRIVATE: REGrren NUMERIC "0"
+-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+-- Retrieval info: PRIVATE: VarWidth NUMERIC "1"
+-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
+-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
+-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
+-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
+-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
+-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: enable NUMERIC "0"
+-- Retrieval info: PRIVATE: rden NUMERIC "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
+-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
+-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "128"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
+-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
+-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
+-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
+-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "7"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
+-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
+-- Retrieval info: USED_PORT: address_a 0 0 9 0 INPUT NODEFVAL "address_a[8..0]"
+-- Retrieval info: USED_PORT: address_b 0 0 7 0 INPUT NODEFVAL "address_b[6..0]"
+-- Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a"
+-- Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b"
+-- Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL "data_a[7..0]"
+-- Retrieval info: USED_PORT: data_b 0 0 32 0 INPUT NODEFVAL "data_b[31..0]"
+-- Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL "q_a[7..0]"
+-- Retrieval info: USED_PORT: q_b 0 0 32 0 OUTPUT NODEFVAL "q_b[31..0]"
+-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
+-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
+-- Retrieval info: CONNECT: @address_a 0 0 9 0 address_a 0 0 9 0
+-- Retrieval info: CONNECT: @address_b 0 0 7 0 address_b 0 0 7 0
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
+-- Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
+-- Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0
+-- Retrieval info: CONNECT: @data_b 0 0 32 0 data_b 0 0 32 0
+-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
+-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
+-- Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0
+-- Retrieval info: CONNECT: q_b 0 0 32 0 @q_b 0 0 32 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL mist_sector_buffer.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL mist_sector_buffer.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL mist_sector_buffer.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL mist_sector_buffer.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL mist_sector_buffer_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
Index: mist_5200/output_file.cof
===================================================================
--- mist_5200/output_file.cof	(nonexistent)
+++ mist_5200/output_file.cof	(revision 177)
@@ -0,0 +1,19 @@
+<?xml version="1.0" encoding="US-ASCII" standalone="yes"?>
+<cof>
+	<eprom_name>CFI_128Mb</eprom_name>
+	<output_filename>output_files/atari800core.rbf</output_filename>
+	<n_pages>1</n_pages>
+	<width>1</width>
+	<mode>0</mode>
+	<sof_data>
+		<user_name>Page_0</user_name>
+		<page_flags>1</page_flags>
+		<bit0>
+			<sof_filename>output_files/atari800core.sof<compress_bitstream>1</compress_bitstream></sof_filename>
+		</bit0>
+	</sof_data>
+	<version>5</version>
+	<create_cvp_file>0</create_cvp_file>
+	<options>
+	</options>
+</cof>
Index: mist_5200/pll_ntsc.cmp
===================================================================
--- mist_5200/pll_ntsc.cmp	(nonexistent)
+++ mist_5200/pll_ntsc.cmp	(revision 177)
@@ -0,0 +1,26 @@
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component pll_ntsc
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		c3		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+end component;
Index: mist_5200/pll_ntsc.ppf
===================================================================
--- mist_5200/pll_ntsc.ppf	(nonexistent)
+++ mist_5200/pll_ntsc.ppf	(revision 177)
@@ -0,0 +1,13 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="pll_ntsc" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="c1" direction="output" scope="external" source="clock"  />
+<pin name="c2" direction="output" scope="external" source="clock"  />
+<pin name="c3" direction="output" scope="external" source="clock"  />
+<pin name="locked" direction="output" scope="external"  />
+
+</global>
+</pinplan>
Index: mist_5200/pll_ntsc.qip
===================================================================
--- mist_5200/pll_ntsc.qip	(nonexistent)
+++ mist_5200/pll_ntsc.qip	(revision 177)
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.0"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll_ntsc.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_ntsc.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_ntsc.ppf"]
Index: mist_5200/pll_ntsc.vhd
===================================================================
--- mist_5200/pll_ntsc.vhd	(nonexistent)
+++ mist_5200/pll_ntsc.vhd	(revision 177)
@@ -0,0 +1,456 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: pll_ntsc.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pll_ntsc IS
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		c3		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+END pll_ntsc;
+
+
+ARCHITECTURE SYN OF pll_ntsc IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC ;
+	SIGNAL sub_wire6	: STD_LOGIC ;
+	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire8_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire8	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		clk2_divide_by		: NATURAL;
+		clk2_duty_cycle		: NATURAL;
+		clk2_multiply_by		: NATURAL;
+		clk2_phase_shift		: STRING;
+		clk3_divide_by		: NATURAL;
+		clk3_duty_cycle		: NATURAL;
+		clk3_multiply_by		: NATURAL;
+		clk3_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		self_reset_on_loss_lock		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+			locked	: OUT STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire8_bv(0 DOWNTO 0) <= "0";
+	sub_wire8    <= To_stdlogicvector(sub_wire8_bv);
+	sub_wire5    <= sub_wire0(2);
+	sub_wire4    <= sub_wire0(0);
+	sub_wire2    <= sub_wire0(3);
+	sub_wire1    <= sub_wire0(1);
+	c1    <= sub_wire1;
+	c3    <= sub_wire2;
+	locked    <= sub_wire3;
+	c0    <= sub_wire4;
+	c2    <= sub_wire5;
+	sub_wire6    <= inclk0;
+	sub_wire7    <= sub_wire8(0 DOWNTO 0) & sub_wire6;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 33,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 140,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 33,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 70,
+		clk1_phase_shift => "0",
+		clk2_divide_by => 33,
+		clk2_duty_cycle => 50,
+		clk2_multiply_by => 140,
+		clk2_phase_shift => "-2400",
+		clk3_divide_by => 270,
+		clk3_duty_cycle => 50,
+		clk3_multiply_by => 1,
+		clk3_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 37037,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "CBX_MODULE_PREFIX=pll_ntsc",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_UNUSED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_USED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_USED",
+		port_clk3 => "PORT_USED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		self_reset_on_loss_lock => "OFF",
+		width_clock => 5
+	)
+	PORT MAP (
+		inclk => sub_wire7,
+		clk => sub_wire0,
+		locked => sub_wire3
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "33"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "33"
+-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "33"
+-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "32768"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "114.545456"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "57.272728"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "114.545456"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "0.100000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "1"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "140"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "70"
+-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "140"
+-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "23"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "57.40000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "57.50000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "57.50000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "0.10000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "-2.40000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ns"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "33"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "140"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "33"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "70"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "33"
+-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "140"
+-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "-2400"
+-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "270"
+-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_ntsc.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_ntsc.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_ntsc.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_ntsc.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_ntsc.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_ntsc_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
Index: mist_5200/pll_pal_post.cmp
===================================================================
--- mist_5200/pll_pal_post.cmp	(nonexistent)
+++ mist_5200/pll_pal_post.cmp	(revision 177)
@@ -0,0 +1,27 @@
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component pll_pal_post
+	PORT
+	(
+		areset		: IN STD_LOGIC  := '0';
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		c3		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+end component;
Index: mist_5200/pll_pal_post.ppf
===================================================================
--- mist_5200/pll_pal_post.ppf	(nonexistent)
+++ mist_5200/pll_pal_post.ppf	(revision 177)
@@ -0,0 +1,14 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="pll_pal_post" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="areset" direction="input" scope="external"  />
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="c1" direction="output" scope="external" source="clock"  />
+<pin name="c2" direction="output" scope="external" source="clock"  />
+<pin name="c3" direction="output" scope="external" source="clock"  />
+<pin name="locked" direction="output" scope="external"  />
+
+</global>
+</pinplan>
Index: mist_5200/pll_pal_post.qip
===================================================================
--- mist_5200/pll_pal_post.qip	(nonexistent)
+++ mist_5200/pll_pal_post.qip	(revision 177)
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.0"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll_pal_post.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_pal_post.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_pal_post.ppf"]
Index: mist_5200/pll_pal_post.vhd
===================================================================
--- mist_5200/pll_pal_post.vhd	(nonexistent)
+++ mist_5200/pll_pal_post.vhd	(revision 177)
@@ -0,0 +1,461 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: pll_pal_post.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pll_pal_post IS
+	PORT
+	(
+		areset		: IN STD_LOGIC  := '0';
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		c3		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+END pll_pal_post;
+
+
+ARCHITECTURE SYN OF pll_pal_post IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC ;
+	SIGNAL sub_wire6	: STD_LOGIC ;
+	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire8_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire8	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		clk2_divide_by		: NATURAL;
+		clk2_duty_cycle		: NATURAL;
+		clk2_multiply_by		: NATURAL;
+		clk2_phase_shift		: STRING;
+		clk3_divide_by		: NATURAL;
+		clk3_duty_cycle		: NATURAL;
+		clk3_multiply_by		: NATURAL;
+		clk3_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		self_reset_on_loss_lock		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			areset	: IN STD_LOGIC ;
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+			locked	: OUT STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire8_bv(0 DOWNTO 0) <= "0";
+	sub_wire8    <= To_stdlogicvector(sub_wire8_bv);
+	sub_wire5    <= sub_wire0(2);
+	sub_wire4    <= sub_wire0(0);
+	sub_wire2    <= sub_wire0(3);
+	sub_wire1    <= sub_wire0(1);
+	c1    <= sub_wire1;
+	c3    <= sub_wire2;
+	locked    <= sub_wire3;
+	c0    <= sub_wire4;
+	c2    <= sub_wire5;
+	sub_wire6    <= inclk0;
+	sub_wire7    <= sub_wire8(0 DOWNTO 0) & sub_wire6;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "HIGH",
+		clk0_divide_by => 40,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 227,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 80,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 227,
+		clk1_phase_shift => "0",
+		clk2_divide_by => 40,
+		clk2_duty_cycle => 50,
+		clk2_multiply_by => 227,
+		clk2_phase_shift => "-2400",
+		clk3_divide_by => 200,
+		clk3_duty_cycle => 50,
+		clk3_multiply_by => 1,
+		clk3_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 50000,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "CBX_MODULE_PREFIX=pll_pal_post",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_USED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_USED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_USED",
+		port_clk3 => "PORT_USED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		self_reset_on_loss_lock => "OFF",
+		width_clock => 5
+	)
+	PORT MAP (
+		areset => areset,
+		inclk => sub_wire7,
+		clk => sub_wire0,
+		locked => sub_wire3
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "High"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "1"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "40"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "80"
+-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "40"
+-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "51600"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "113.500000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "56.750000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "113.500000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "0.100000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "20.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "deg"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "227"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "227"
+-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "227"
+-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "227"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "0.10000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "-2.40000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ns"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_pal_post.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "HIGH"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "40"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "227"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "80"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "227"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "40"
+-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "227"
+-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "-2400"
+-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "200"
+-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "50000"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal_post.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal_post.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal_post.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal_post.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal_post.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal_post_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
Index: mist_5200/pll_pal_pre.cmp
===================================================================
--- mist_5200/pll_pal_pre.cmp	(nonexistent)
+++ mist_5200/pll_pal_pre.cmp	(revision 177)
@@ -0,0 +1,23 @@
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component pll_pal_pre
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+end component;
Index: mist_5200/pll_pal_pre.qip
===================================================================
--- mist_5200/pll_pal_pre.qip	(nonexistent)
+++ mist_5200/pll_pal_pre.qip	(revision 177)
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.0"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll_pal_pre.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_pal_pre.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_pal_pre.ppf"]
Index: mist_5200/simulate_data_io.sh
===================================================================
--- mist_5200/simulate_data_io.sh	(nonexistent)
+++ mist_5200/simulate_data_io.sh	(revision 177)
@@ -0,0 +1,65 @@
+#!/bin/bash
+
+echo "---------------------------------------------------------"
+echo "Use 'simulate -run' to skip compilation stage."
+echo "Use 'simulate -view' to show previous simulation results."
+echo "---------------------------------------------------------"
+
+name=data_io
+
+
+
+. /home/markw/fpga/xilinx/14.7/ISE_DS/settings64.sh
+
+mkdir -p sim
+pushd sim
+
+# if we have a WDB file, we can view it if requested (otherwise we remove it)
+if [ ! -e $name.wdb -o "$1" != "-view" ]; then
+
+    rm -f $name.wdb
+
+    # if we have a EXE, we can run it if requested (otherwise we remove it)
+    if [ ! -e $name.exe -o "$1" != "-run" ]; then
+
+        rm -f $name.exe
+
+        # copy testbench files
+        cp -p ../tb_data/* .
+
+        # copy source files
+	cp ../data_io.vhdl .
+	cp ../../common/components/spi_master.vhd .
+	cp ../../common/components/generic_ram_infer.vhdl .
+
+        # set up project definition file
+	ls *.v | perl -e 'while (<>){s/(.*)/verilog work $1/;print $_;}' | cat > $name.prj
+	ls *.vhd* | perl -e 'while (<>){s/(.*)/vhdl work $1/;print $_;}' | cat >> $name.prj
+	echo NumericStdNoWarnings = 1 >> xilinxsim.ini
+
+        # verbose & no multthreading - fallback in case of problems
+        # fuse -v 1 -mt off -incremental -prj %name%.prj -o %name%.exe -t %name%
+
+        fuse -timeprecision_vhdl 1fs -incremental -prj $name.prj -o $name.exe -t ${name}_tb || exit 1
+        # fuse --mt off -prj %name%.prj -o %name%.exe -t %name%_tb
+
+        # Check for the EXE again, independent of the errorlevel of fuse...
+        [ -e $name.exe ] || echo "No simulation executable created"
+
+
+    fi
+
+    # Open the iSIM GUI and run the simulation
+    ./$name.exe -gui -f ../$name.cmd -wdb $name.wdb -log $name.log -view ../$name.wcfg || exit 1
+    #strace ./$name.exe -gui -f ../$name.cmd -wdb $name.wdb -log $name.log -view ../$name.wcfg >& out
+    #./$name.exe -h -log $name.log 
+
+
+else
+
+    # Only start the viewer on an existing wave configuration (from an old simulation)
+    isimgui -view ../$name.wcfg || exit 1
+
+fi
+
+popd

Property changes on: mist_5200/simulate_data_io.sh
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: mist_5200/user_io.v
===================================================================
--- mist_5200/user_io.v	(nonexistent)
+++ mist_5200/user_io.v	(revision 177)
@@ -0,0 +1,153 @@
+// MiST user_io
+
+module user_io(
+	input      		SPI_CLK,
+	input      		SPI_SS_IO,
+	output     		reg SPI_MISO,
+	input      		SPI_MOSI,
+	
+	input [7:0] 	CORE_TYPE,
+	
+	output [5:0] 	JOY0,
+	output [5:0] 	JOY1,
+	output [1:0] 	BUTTONS,
+	output [1:0] 	SWITCHES,
+	
+	input 	  		clk,
+	output	 		ps2_clk,
+	output reg 		ps2_data
+);
+
+reg [6:0]         sbuf;
+reg [7:0]         cmd;
+reg [4:0] 	      cnt;
+reg [5:0]         joystick0;
+reg [5:0]         joystick1;
+reg [3:0] 	      but_sw;
+
+assign JOY0 = joystick0;
+assign JOY1 = joystick1;
+assign BUTTONS = but_sw[1:0];
+assign SWITCHES = but_sw[3:2];
+   
+// drive MISO only when transmitting core id
+always@(negedge SPI_CLK or posedge SPI_SS_IO) begin
+	if(SPI_SS_IO == 1) begin
+	   SPI_MISO <= 1'bZ;
+	end else begin
+      if(cnt < 8) begin
+		  SPI_MISO <= CORE_TYPE[7-cnt];
+		end else begin
+	     SPI_MISO <= 1'bZ;
+		end
+   end
+end
+
+// 8 byte fifo to store ps2 bytes
+localparam PS2_FIFO_BITS = 3;
+reg [7:0] ps2_fifo [(2**PS2_FIFO_BITS)-1:0];
+reg [PS2_FIFO_BITS-1:0] ps2_wptr;
+reg [PS2_FIFO_BITS-1:0] ps2_rptr;
+
+// ps2 transmitter state machine
+reg [3:0] ps2_tx_state;
+reg [7:0] ps2_tx_byte;
+reg ps2_parity;
+
+assign ps2_clk = clk || (ps2_tx_state == 0);
+
+
+// ps2 transmitter
+// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
+reg ps2_r_inc;
+always@(posedge clk) begin
+	ps2_r_inc <= 1'b0;
+	
+	if(ps2_r_inc)
+		ps2_rptr <= ps2_rptr + 1;
+
+	// transmitter is idle?
+	if(ps2_tx_state == 0) begin
+		// data in fifo present?
+		if(ps2_wptr != ps2_rptr) begin
+			// load tx register from fifo
+			ps2_tx_byte <= ps2_fifo[ps2_rptr];
+			ps2_r_inc <= 1'b1;
+			
+			// reset parity
+			ps2_parity <= 1'b1;
+			
+			// start transmitter
+			ps2_tx_state <= 4'd1;
+
+			// put start bit on data line
+			ps2_data <= 1'b0;			// start bit is 0
+		end
+	end else begin
+	
+		// transmission of 8 data bits
+		if((ps2_tx_state >= 1)&&(ps2_tx_state < 9)) begin
+			ps2_data <= ps2_tx_byte[0];			  // data bits
+			ps2_tx_byte[6:0] <= ps2_tx_byte[7:1]; // shift down
+			if(ps2_tx_byte[0]) 
+				ps2_parity <= !ps2_parity;
+		end
+
+		// transmission of parity
+		if(ps2_tx_state == 9)
+			ps2_data <= ps2_parity;
+			
+		// transmission of stop bit
+		if(ps2_tx_state == 10)
+			ps2_data <= 1'b1;			// stop bit is 1
+
+		// advance state machine
+		if(ps2_tx_state < 11)
+			ps2_tx_state <= ps2_tx_state + 4'd1;
+		else	
+			ps2_tx_state <= 4'd0;
+	
+	end
+end
+
+// SPI receiver
+//reg ps2_w_inc;
+always@(posedge SPI_CLK or posedge SPI_SS_IO) begin
+//	ps2_w_inc <= 1'b0;
+//	if(ps2_w_inc)
+//		ps2_wptr <= ps2_wptr + 1;
+
+	if(SPI_SS_IO == 1) begin
+	   cnt <= 1'b0;
+	end else begin
+		sbuf[6:0] <= { sbuf[5:0], SPI_MOSI };
+		// counter counts 0-7, 8-15, 8-15 ...
+		// 0-7 is command, 8-15 is payload
+		if(cnt != 15)  cnt <= cnt + 4'd1;
+		else				cnt <= 4'd8;
+
+		// finished reading command byte
+      if(cnt == 7)
+		   cmd <= { sbuf, SPI_MOSI};
+
+      if(cnt == 15) begin
+		   if(cmd == 1)
+				but_sw <= { sbuf[2:0], SPI_MOSI }; 
+
+			if(cmd == 2)
+				joystick0 <= { sbuf[4:0], SPI_MOSI };
+				 
+			if(cmd == 3)
+				joystick1 <= { sbuf[4:0], SPI_MOSI };
+				 
+		   if(cmd == 5) begin
+				// store incoming keyboard bytes in 
+				ps2_fifo[ps2_wptr] <= { sbuf, SPI_MOSI }; 
+				ps2_wptr <= ps2_wptr + 1;
+			end
+				
+		end	
+	end
+end
+   
+endmodule
