Revision 22
Added by markw over 11 years ago
sdram_statemachine.vhdl | ||
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SDRAM_WE_N : out std_logic;
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SDRAM_ldqm : out std_logic; -- low enable, high disable - for byte addressing - NB, cas latency applies to reads
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SDRAM_udqm : out std_logic
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SDRAM_udqm : out std_logic;
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reset_client_n : out std_logic
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);
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END sdram_statemachine;
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... | ... | |
signal sdram_request_reg : std_logic;
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signal sdram_request_next : std_logic;
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signal reset_client_n_reg : std_logic;
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signal reset_client_n_next : std_logic;
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BEGIN
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-- register
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process(CLK_SDRAM,reset_n)
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... | ... | |
reply_sreg <= '0';
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sdram_request_reg <= '0';
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reset_client_n_reg <= '0';
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elsif (CLK_SYSTEM'event and CLK_SYSTEM='1') then
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data_in_sreg <= data_in_snext;
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address_in_sreg <= address_in_snext;
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... | ... | |
reply_sreg <= reply_snext;
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sdram_request_reg <= sdram_request_next;
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reset_client_n_reg <= reset_client_n_next;
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end if;
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end process;
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... | ... | |
end process;
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--
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process(sdram_state_reg,delay_reg, idle_priority, data_out_reg, read_en_sreg, write_en_sreg, address_in_sreg, data_in_sreg, reply_reg, require_refresh, dq_in_next, dqm_mask_sreg, request_sreg)
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process(reset_client_n_reg,sdram_state_reg,delay_reg, idle_priority, data_out_reg, read_en_sreg, write_en_sreg, address_in_sreg, data_in_sreg, reply_reg, require_refresh, dq_in_next, dqm_mask_sreg, request_sreg)
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begin
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idle_priority <= (others=>'0');
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refreshing_now <= '0';
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reset_client_n_next <= reset_client_n_reg;
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sdram_state_next <= sdram_state_reg;
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command_next <= sdram_command_no_operation;
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... | ... | |
-- nop
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end case;
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when sdram_state_idle =>
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reset_client_n_next <= '1';
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delay_next <= (others=>'0');
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idle_priority <= (request_sreg xor reply_reg)&require_refresh&write_en_sreg&read_en_sreg;
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... | ... | |
COMPLETE <= (reply_sreg xnor sdram_request_reg) and not(request);
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sdram_request_next <= sdram_request_reg xor request;
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reset_client_n <= reset_client_n_reg;
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END vhdl;
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Connected up SDRAM. Make 800XL core wait for SDRAM reset to complete. Also had to adjust phase offset to make it work - need to get a proper setup for mist